A multi-channel high-speed analog signal polling acquisition control method based on FPGA

Abstract

This invention belongs to the field of high-speed data acquisition technology and discloses a multi-channel high-speed analog signal polling acquisition control method based on FPGA. This method configures a high-speed analog switch with break-before-make and disable functions to control channel selection and disable pins to form an N:1 multiplexed channel. The FPGA sequentially selects each channel according to the polling order and starts a preset or dynamically adjustable wait counter after switching to match the switch switching and signal establishment time. After the wait is completed, the ADC conversion is triggered immediately, the data is read and bound to the channel identifier for storage, and the full-channel polling is completed cyclically. This invention utilizes the break-before-make characteristic to eliminate switching glitches, balances signal establishment time and sampling efficiency through a dynamic wait counter, and combines multi-level switch cascading and a four-state polling state machine to achieve polling acquisition of multi-channel analog signals up to 1MHz, significantly improving the accuracy, efficiency, and reliability of multi-channel high-speed acquisition. It is suitable for industrial testing, scientific research experiments, and other scenarios.

Description

Technical Field

[0001] This invention belongs to the field of high-speed data acquisition technology, specifically relating to an FPGA-based multi-channel high-speed analog signal polling acquisition and control method, which is particularly suitable for low-cost, high-precision, multi-channel analog signal polling acquisition scenarios, such as industrial automation testing, scientific research experiments, and equipment status monitoring. Background Technology

[0002] With the development of intelligent manufacturing, industrial automation, and scientific research, the requirements for the density, accuracy, and real-time performance of multi-channel analog signal acquisition are constantly increasing. Existing acquisition architectures are divided into two categories: parallel acquisition with multiple ADCs and polling acquisition with a single ADC and an analog multiplexer. Parallel acquisition offers excellent performance but has high hardware costs; polling acquisition has low costs and strong channel scalability, making it more suitable for batch applications.

[0003] Existing polling acquisition technology has obvious drawbacks: ordinary analog switch switching is prone to glitches and lacks the characteristic of breaking before making; relay switching is slow and cannot meet the requirements of high-frequency acquisition; signal establishment time mostly uses fixed delay, which cannot dynamically balance sampling accuracy and efficiency; channel expansion methods are limited and do not enable flexible reconfiguration of analog switches with disable functions; FPGA control logic is simple and lacks fine-grained state management and adaptive adjustment capabilities.

[0004] Therefore, there is an urgent need for a high-precision, high-efficiency, and highly flexible multi-channel high-speed analog signal polling acquisition and control method. Summary of the Invention

[0005] To address the aforementioned issues, this invention aims to provide a multi-channel high-speed analog signal polling acquisition and control method based on FPGA, thereby resolving problems such as channel switching glitches, difficulty in balancing signal setup time and acquisition efficiency, inconvenience of analog switch cascading reconstruction, and coarse granularity of polling state management in existing technologies.

[0006] A multi-channel high-speed analog signal polling acquisition and control method and system based on FPGA, comprising the following steps:

[0007] S1: Configure at least one high-speed analog switch chip with break-before-make characteristic and disable output function. By controlling its channel selection pin and disable pin, multiple analog switches can be cascaded or a single analog switch can be reconfigured to form an N:1 multiplexed channel structure.

[0008] S2: The FPGA generates channel selection control signals according to the preset polling order, and sequentially selects each analog input channel;

[0009] S3: After the channel switching control signal is issued, the FPGA automatically starts a preset or dynamically adjustable wait counter. The count value of the counter matches the switching time of the analog switch and the establishment time of the signal link, forming a wait state.

[0010] S4: After the waiting state ends, the FPGA immediately sends a conversion start signal to the ADC, triggering the ADC to perform one or more consecutive conversions on the currently selected analog input channel;

[0011] S5: The FPGA reads the digital data obtained by the ADC conversion, associates the data with the currently selected channel identifier and stores it, and repeats steps S2 to S5 to complete the polling acquisition of all channels.

[0012] Furthermore, the count value of the wait counter in S3 is dynamically adjustable and is adjusted in real time by the FPGA according to the preset sampling rate of the ADC and the rate of change of the signal amplitude; when the amplitude deviation of two consecutive acquisitions is less than the preset threshold, the count value is shortened, and when it is greater than the threshold, the count value is extended, so as to dynamically balance the signal establishment time and acquisition efficiency.

[0013] Furthermore, the analog switch chip is a dual-channel 2:1 analog switch with two built-in independent 2:1 channels and each channel having a disable pin; the FPGA can cascade the two 2:1 channels into a 4:1 multiplexer or configure them as two independent 2:1 multiplexers by controlling the enable and disable pins.

[0014] Furthermore, when there are multiple analog switches, a master-slave cascade structure is adopted, with the common output terminal of at least one first-stage switch connected to one of the input terminals of the second-stage switch.

[0015] Furthermore, in step S2, while generating the analog switch control signal, the FPGA also generates a synchronization signal for controlling the ADC sampling clock, thereby aligning the channel switching with the ADC sampling clock.

[0016] Furthermore, the FPGA contains a polling state machine, which includes at least four states: "channel switching state", "signal establishment waiting state", "acquisition trigger state" and "data reading state", and the above states are cyclically transferred through state encoding.

[0017] Furthermore, after reading the ADC conversion result, the FPGA performs a data validity judgment on the read digital data, including comparing it with a preset noise threshold and with the historical data change rate. When the data is determined to be invalid, the data is marked and a resampling is requested.

[0018] Furthermore, in step S5, the associated storage involves the FPGA writing the digital data of each channel into the corresponding dedicated FIFO buffer. Each channel's FIFO is independent of the others and is read by the FPGA according to channel priority.

[0019] This invention employs a high-speed analog switch with break-before-make characteristics, combined with precise FPGA control, which can prevent two signals from conducting simultaneously during channel switching, eliminating switching glitches and voltage spikes at the source and significantly improving sampling accuracy.

[0020] This invention employs a presettable and dynamically adjustable wait counter, which can adaptively adjust the signal establishment time according to the signal change rate: shorten the waiting time when the signal change is slow to improve the acquisition efficiency, and extend the waiting time when the signal change is drastic to ensure the establishment accuracy, thus achieving the optimal balance between measurement accuracy and system efficiency.

[0021] This invention utilizes a dual-channel 2:1 analog switch with a disable function. By controlling the combination of enable and disable pins through an FPGA, a single chip can be flexibly configured as a 4:1 multiplexer or two independent 2:1 multiplexers, improving hardware utilization and system integration.

[0022] This invention implements a four-state polling state machine inside the FPGA, which sequentially completes channel switching, signal establishment waiting, acquisition triggering and data reading, realizing fine-grained control of the polling process. The control accuracy and adjustability are significantly better than traditional fixed delay solutions. Attached Figure Description

[0023] Figure 1 This is a block diagram of the overall system architecture of the present invention.

[0024] Figure 2 This is the state transition diagram of the polling state machine described in this invention.

[0025] Figure 3 This is a timing diagram of the polling acquisition control described in this invention, showing the time relationship between channel switching, signal establishment, sampling triggering, and data reading.

[0026] Figure 4 This is a flowchart of the polling acquisition control method with dynamic waiting adjustment described in this invention. Detailed Implementation

[0027] To make the above features and application scenarios of the present invention clearer and easier to understand, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Implementation Case 1.

[0029] like Figure 1The diagram shown is a system architecture block diagram of the present invention, which is a multi-channel high-speed analog signal polling acquisition and control method based on FPGA.

[0030] The hardware circuit consists of an analog switch cascade system and an ADC acquisition system.

[0031] The switch cascade system uses multiple high-speed analog switch chips AD8182 with break-before-make characteristics and disable function to form a two-level tree cascade structure.

[0032] Level 1: Several switches are each configured as a 4:1 multiplexer and connected to a set of analog signals.

[0033] Second stage: A switch re-multiplexes the outputs of the switches in the first stage, forming an N:1 total multiplexed channel.

[0034] The FPGA controls the selection and high-impedance state of each switch through independent channel selection signals and enable signals, so that any analog signal can be selected to the subsequent stage.

[0035] The ADC acquisition module uses a single high-speed, high-precision ADC chip, AD9269-80, and this embodiment only uses one channel. The analog input of the ADC is connected to the final output of the analog switch cascade network, its conversion start pin is connected to the control pin of the FPGA, and its digital data output pin is connected to the data input pin of the FPGA.

[0036] The FPGA core control module consists of a data processing unit, a state machine, a counter, and other modules.

[0037] Polling state machine: Sequential transitions between four states: channel switching, waiting, triggering, and reading.

[0038] Dynamic wait counter: Generates a programmable or adaptively adjustable signal setup wait time, with the count value dynamically changing according to the rate of change of the previously acquired signal.

[0039] ADC interface unit: responsible for sending conversion start pulse and latching the digital data returned by the ADC.

[0040] Data storage FIFO: An independent FIFO buffer is allocated to each channel to temporarily store the acquired data.

[0041] The host computer is mainly used for displaying system-acquired data and sending control commands.

[0042] Implementation Case 2.

[0043] like Figure 2 The diagram shown is the state transition diagram of the polling state machine of the present invention. The state machine contains five states and one decision branch, and the states and transition conditions are as follows:

[0044] S0 is the idle state, entered after the system powers on or completes a round of data acquisition, waiting for the host computer to issue a data acquisition start command. Transfer condition: Upon receiving the start command, the system jumps to S1.

[0045] In channel switching state S1, the FPGA outputs the strobe and enable signals for the current channel, controlling the analog switch to switch to the target channel. Transfer condition: Automatically jumps to S2 after the control signal stabilizes.

[0046] Signal S2 establishes a waiting state. The FPGA starts a dynamic wait counter, waiting for the analog switch output signal to fully establish to the accuracy required by the ADC. The count value can be dynamically adjusted according to the signal change rate. Transfer condition: The counter reaches full and jumps to S3.

[0047] S3 acquires the trigger state, and the FPGA sends a conversion start pulse to the ADC to initiate an analog-to-digital conversion. Transfer condition: Wait for the ADC conversion to complete before jumping to S4.

[0048] In S4 data read mode, the FPGA reads the digital data output by the ADC, associates it with the current channel identifier, and stores it in the corresponding FIFO. Transfer condition: After data reading is complete, the system checks "Is there another channel?".

[0049] If there are still uncollected channels, return to S1 and switch to the next channel. If all channels have been collected, return to the S0 idle state and wait for the next start command or to end.

[0050] In the diagram, each state is represented by a rounded rectangle, and the trigger condition is labeled next to the transition arrow. This invention achieves fine-grained management of the polling acquisition process and precise insertion of dynamic waiting time through this five-state cyclic control.

[0051] Implementation Case 3.

[0052] like Figure 3 The diagram shown is a timing diagram of the polling acquisition control described in this invention, illustrating the time relationship between channel switching, signal establishment, sampling triggering, and data reading.

[0053] The following signals are included from top to bottom in the diagram:

[0054] CLK: FPGA system clock (80 MHz in this example, period 12.5 ns)

[0055] Rst_n: System reset signal, active low, enters working state after initial reset.

[0056] MUX_en: Analog switch output enable signal, active high, controls whether the switch output drives the bus.

[0057] T_cnt: Dynamic wait counter, the count value represents the number of wait cycles required for the signal to be established.

[0058] CH_SEL: Channel selection bus (e.g., 3 bits, corresponding to 8 channels: CH0, CH1, …, CH7).

[0059] Conv_Start: ADC conversion start pulse, valid on rising edge.

[0060] Data_Valid: Data valid flag. A high level indicates that the ADC output data is stable and readable.

[0061] Sample_Data: The sampling data bus outputs the conversion results of each channel in parallel.

[0062] Initial state: After Rst_n changes from low to high, the system enters the polling preparation state. MUX_en is high, CH_SEL points to CH0, and T_cnt is cleared.

[0063] Channel switching and establishment waiting: At time T0, CH_SEL switches from CH0 to CH1, while MUX_en remains unchanged (or is controlled by the FPGA as needed). At this time, the analog switch enters the "break-then-make" process, and a new signal is established after a brief period of high impedance at the output.

[0064] The FPGA synchronously starts a dynamic wait counter T_cnt, the count value of which is dynamically set according to the previous signal change rate of this channel. When T_cnt is full, it indicates that the signal has been sufficiently established to the accuracy required by the ADC.

[0065] Triggering ADC conversion: At time T1, the FPGA sends a Conv_Start pulse to start the ADC to perform a conversion on the current channel.

[0066] Conversion and Data Reading: During ADC conversion, Data_Valid remains low. After conversion, the ADC output data stabilizes, Data_Valid goes high, and the FPGA latches Sample_Data on the next clock edge.

[0067] Data_Valid then returns to a low level, preparing for the next channel.

[0068] Polling the next channel: After the data reading is complete, CH_SEL switches to the next channel (CH2), and the above switching → waiting → triggering → reading process is repeated. In the figure, ellipses indicate the polling of subsequent channels (CH2…CH(N-1)), and finally returns to CH0 to start a new cycle.

[0069] The diagram specifically highlights the "dynamic wait counter," whose count value can be adjusted in real time according to the signal change rate: when the signal changes slowly, the T_cnt value decreases, shortening the wait time; when the signal changes drastically, the T_cnt value increases, extending the wait time to ensure accuracy. This adaptive mechanism is a key innovation of this invention.

[0070] Implementation Case 4.

[0071] like Figure 4 The diagram shown is a flowchart of the polling acquisition control method with dynamic waiting adjustment described in this invention.

[0072] It should be noted that the signal settling time after analog switch switching is mainly determined by the RC time constant formed by the switch's on-resistance and the subsequent load capacitance, and is not directly related to the signal amplitude change rate. However, when there is a large deviation between two adjacent acquisition results that cannot be explained by the actual change in the input signal, it usually indicates that the waiting time is insufficient and the signal has not stabilized to reach the measurement accuracy required by the ADC. Therefore, this invention uses the deviation between two adjacent acquisition data as feedback to dynamically adjust the value of the waiting counter, which can ensure sampling accuracy while avoiding the decrease in acquisition efficiency caused by fixed delay.

[0073] First, after the system powers on, the FPGA internal registers are initialized, setting the total number of polling channels N, the current channel index i=0, the default wait time, the wait time dynamic adjustment threshold THD, and the wait time increment. and reduction and minimum waiting time .

[0074] After initialization, the FPGA outputs the corresponding channel selection signal CH_SEL and enable signal EN according to the current channel index i, controlling the analog switch cascade network to switch to the target channel.

[0075] After switching channels, the FPGA starts a wait counter, with the count value set to the dynamic wait time t of the current channel. The counter begins counting, during which the signal output from the analog switch gradually builds up to the accuracy required by the ADC.

[0076] If the count is not full, continue waiting; if the count is full, proceed with ADC conversion.

[0077] Once the counter reaches full, it is reset to zero. Then, the FPGA sends a conversion start pulse Conv_Start to the ADC to initiate an analog-to-digital conversion.

[0078] Then wait for the ADC conversion to complete and read the digital data. And store it in the FIFO buffer corresponding to channel i.

[0079] And the collected values Compared with the last collected value of this channel Compare them.

[0080] Calculate the relative deviation between two adjacent acquisition results FSR is the full-scale range, and this deviation is used as the basis for judging whether the signal is sufficiently established.

[0081] like > If the signal changes drastically and requires a longer setup time, then execute: (But must not exceed the preset maximum value) ).

[0082] like ≤ This indicates that the signal change is gradual, which can shorten the setup time and improve polling efficiency. Therefore, execute: .

[0083] make , pointing to the next channel to be collected.

[0084] If no stop command is received from the host computer, return to step S2 and start the acquisition of the next channel; if a stop command is received, end the current acquisition process.

[0085] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-channel high-speed analog signal polling acquisition control method based on FPGA, characterized in that, Includes the following steps: S1: Configure at least one high-speed analog switch chip with break-before-make characteristic and disable output function. By controlling its channel selection pin and disable pin, multiple analog switches can be cascaded or a single analog switch can be reconfigured to form an N:1 multiplexed channel structure. S2: The FPGA generates channel selection control signals according to the preset polling order, and sequentially selects each analog input channel; S3: After the channel switching control signal is issued, the FPGA automatically starts a preset or dynamically adjustable wait counter. The count value of the counter matches the switching time of the analog switch and the establishment time of the signal link, forming a wait state. S4: After the waiting state ends, the FPGA immediately sends a conversion start signal to the ADC, triggering the ADC to perform one or more consecutive conversions on the currently selected analog input channel; S5: The FPGA reads the digital data of each channel obtained by the ADC conversion, associates the data with the identifier of the currently selected channel and stores it, and returns to step S2 to poll all channels in turn to complete one or more rounds of acquisition.

2. The method of claim 1, wherein, The count value of the wait counter in S3 is dynamically adjustable and is adjusted in real time by the FPGA according to the preset sampling rate of the ADC and the rate of change of the signal amplitude. When the amplitude deviation of two consecutive acquisitions is less than the preset threshold, the count value is shortened; when it is greater than the threshold, the count value is extended, so as to dynamically balance the signal establishment time and acquisition efficiency.

3. The method of claim 1, wherein, The analog switch chip is a dual-channel 2:1 analog switch with two built-in independent 2:1 channels, each with a disable pin. The FPGA can cascade the two 2:1 channels into a 4:1 multiplexer or configure them as two independent 2:1 multiplexers by controlling the enable and disable pins.

4. The method of claim 1, wherein, When there are multiple analog switches, a master-slave cascade structure is adopted, and the common output terminal of at least one first-stage switch is connected to one of the input terminals of the second-stage switch.

5. The method of claim 1, wherein, In step S2, while generating the analog switch control signal, the FPGA also generates a synchronization signal to control the ADC sampling clock, thereby aligning the channel switching with the ADC sampling clock.

6. The method of claim 1, wherein, The FPGA contains a polling state machine, which includes at least four states: "channel switching state", "signal establishment waiting state", "acquisition trigger state" and "data reading state", and the above states are cyclically transferred through state encoding.

7. The method of claim 1, wherein, After reading the ADC conversion result, the FPGA performs a data validity check on the read digital data, including comparing it with a preset noise threshold and with the historical data change rate. If the data is determined to be invalid, it is marked.

8. The method of claim 1, wherein, The associated storage in step S5 involves the FPGA writing the digital data of each channel into the corresponding dedicated FIFO buffer, or the FIFO of each channel being independent of each other and being read by the FPGA according to the channel priority.

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