An encoding method, a decoding method, a communication device, and a communication system.

Abstract

This application provides an encoding method, a decoding method, a communication device, and a communication system to improve the high throughput performance of LDPC codes. The method includes: extracting an information bit sequence; encoding the information bit sequence according to a basis matrix; wherein the basis matrix includes a first region E2; the columns of the first region E2 include columns kb+M+1 to X1+kb of the basis matrix; row P of the basis matrix is ​​the row that first satisfies a first relation with the first M rows of the basis matrix, and row X1 of the basis matrix is ​​the last row of row P; the rows of the first region E2 include rows X1+1 to the last row of the basis matrix; at least one row from row 1 to row x of the first region E2 includes elements of the first type; the elements included in rows x+1 to the last row of the first region E2 are all elements of the second type, and the number w of rows x+1 to the last row is greater than 1; wherein, elements of the first type correspond to non-zero elements, and elements of the second type correspond to zero elements.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0002] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5G communication. Mainstream LDPC codes employ a quasi-cyclic (QC) structure, which avoids poor structures such as short cycles and improves code distance by adjusting the shift of each block.

[0003] How to further enhance the performance of LDPC codes in the next-generation standards under development, or in future communication systems, is a hot topic of research. Summary of the Invention

[0004] This application provides an encoding method, a decoding method, a communication device, and a communication system, with the aim of improving the high throughput performance of LDPC codes.

[0005] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.) or a component in the communication device (e.g., a processor, a chip, or a chip system, etc.). Alternatively, the encoding method described in the first aspect can also be implemented by a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: taking an information bit sequence; encoding the information bit sequence according to a basis matrix to obtain an encoded output bit sequence; wherein, the basis matrix includes a first region E2; the columns of the first region E2 include columns kb+M+1 to X1+kb of the basis matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5, or 6; row P of the basis matrix is ​​the row that first satisfies a first relation with the first M rows of the basis matrix, and row X1 of the basis matrix is ​​the last row of row P, where P is a positive integer; wherein, one row of row P is the first target row in the first relation, and one row of the first M rows is the second target row in the first relation; the first relation is: the column index in the first column interval of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in column y, then ,or, This holds true for any value of y. This is the row number of the first target row. This is the row number of the second target row. t is a positive integer; the first column interval is the 1st column to the kb+Mth column of the base matrix; the rows of the first region E2 include the (X1+1)th row to the last row of the base matrix; at least one row from the 1st row to the xth row of the first region E2 includes the first type of element, where x is an integer greater than 1; the elements included in the (X+1)th row to the last row of the first region E2 are all second type of elements, and the number of rows w from the (X+1)th row to the last row is greater than 1; where the first type of element corresponds to a non-zero element, and the second type of element corresponds to a zero element.

[0006] This application, by dividing the E2 region and designing features within it, can maximize the benefits of split LDPC in the matrix, improving decoding performance in both high and low bitrate ranges. Furthermore, the feature design within the E2 region allows for flexible bitrate support on the encoding side, reducing the complexity of control logic and encoding implementation. Additionally, designing features within the E2 region enhances the orthogonality of the basis matrix, contributing to improved encoding and decoding efficiency in high-throughput scenarios.

[0007] A larger w value results in better matrix orthogonality. This application uses a larger w value (i.e., w greater than 1) to help reduce decoding latency and improve throughput. A larger w value ensures that the E region from x+1 to the last row is completely orthogonal. This part can be encoded in parallel, meaning that the parity code with the larger row index in this region does not depend on the parity bit with the smaller row index, which helps improve the parallelism of encoding and reduce encoding latency.

[0008] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, etc.) or a component within that communication device (e.g., a processor, a chip, or a chip system, etc.). Alternatively, the decoding method described in the second aspect can also be implemented by a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: acquiring information to be decoded; decoding the information to be decoded according to a base matrix to obtain a decoded output bit sequence; wherein, the base matrix includes a first region E2; the columns of the first region E2 include columns kb+M+1 to X1+kb of the base matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5, or 6; the P rows in the base matrix are the rows that first satisfy a first relation with the first M rows of the base matrix, the X1 row of the base matrix is ​​the last row of the P rows, and P is a positive integer; wherein, one row in the P rows is the first target row in the first relation, and one row in the first M rows is the second target row in the first relation; the first relation is: the column index in the first column interval of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in column y, then ,or, This holds true for any value of y. This is the row number of the first target row. This is the row number of the second target row. t is a positive integer; the first column interval is from the kb+M+1th column to the last column of the base matrix; the rows of the first region E2 include from the X1+1th row to the last row of the base matrix; at least one row from the 1st row to the xth row of the first region E2 includes the first type of element, where x is an integer greater than 1; the elements included from the x+1th row to the last row of the first region E2 are all second type of elements, and the number of rows w from the x+1th row to the last row is greater than 1; where the first type of element corresponds to a non-zero element, and the second type of element corresponds to a zero element.

[0009] Based on the first and second aspects mentioned above, the following implementation methods are available: As one possible implementation, the first row set from row 1 to row x of the first region E2 includes all elements of the first type, and the first row set includes xt rows, where t = 0, 1, 2, or 3; the second row set from row 1 to row x of the first region E2 includes all elements of the second type, and the second row set includes the remaining rows from row 1 to row x of the first region E2 excluding the first row set.

[0010] This method ensures that the split-extended check columns have a weight of at least 2 in the decoding matrix and are associated with the core rows. Increasing the weight of these columns helps improve the overall reliability of the core matrix, offering performance benefits in high-throughput, low-complexity scenarios and resulting in faster decoding speeds. Furthermore, it can further reduce the complexity of the encoding control logic at low bit rates and further improve encoding and decoding efficiency in high-throughput scenarios.

[0011] As one possible implementation, rows in the first region E2 with row numbers less than the first row number include elements of the first type; rows in the first region E2 with row numbers greater than or equal to the first row number include elements of the second type. This method, by dividing the E2 region using a row number, can reduce the complexity of the encoding implementation.

[0012] As one possible implementation, the row corresponding to the first row number in the base matrix and the first extended check row satisfy the first relationship; wherein, the row corresponding to the first row number in the base matrix is ​​the first target row in the first relationship, and the first extended check row is the second target row in the first relationship. This approach can increase the reliability of the check column associated with the core row at low bit rates and improve convergence speed. Furthermore, it can further reduce the complexity of the control logic on the encoding side at low bit rates and further improve encoding and decoding efficiency in high-throughput scenarios.

[0013] As one possible implementation, the first row number is the last row in the base matrix that satisfies the first relationship with either the extended check row or the first M rows of the base matrix. This approach can increase the reliability of the check columns associated with all core rows at low bit rates and improve convergence speed. Furthermore, it can further reduce the complexity of the control logic on the encoding side at low bit rates and further improve encoding and decoding efficiency in high-throughput scenarios.

[0014] As one possible implementation, row t1 in the second row set and row t2 in the base matrix satisfy the first relationship. Row t1 in the second row set is any row in the second row set, row t2 in the base matrix is ​​the extended check row, and the row index of row t2 in the base matrix is ​​less than the row index of row t1 in the second row set. Wherein, row t1 in the base matrix is ​​the first target row in the first relationship, row t2 in the base matrix is ​​the second target row in the first relationship, t1 is a positive integer less than or equal to t, and t2 is a positive integer. This approach helps to avoid splitting and expanding core rows in low-bitrate scenarios, thus improving performance under reverse decoding scheduling (rows updated in the early stages of iteration have less row weight). Furthermore, it can further reduce the complexity of the control logic on the encoding side in low-bitrate scenarios and further improve the encoding and decoding efficiency in high-throughput scenarios.

[0015] As one possible implementation, the t2th row in the base matrix is ​​one of the t extended check rows in the first X1 rows of the base matrix, ordered by row weight from largest to smallest. This method, by splitting and expanding rows with large row weights, ensures that the row weight correction after splitting and expanding is more in line with the optimal degree distribution of density evolution theory, which helps improve decoding performance and also improves coding efficiency on the encoding side.

[0016] As one possible implementation, the number of elements of the first type in a row of the first row set is 1, 2, or 3. The more elements of the first type, the more significant the effect of improving the column weight of the split verification column; however, it will also increase the density of these columns too much, which may reduce the orthogonality of the matrix. Therefore, in practice, a trade-off must be made based on the needs of the scenario and the hardware implementation, prioritizing performance over implementation simplicity. 1 to 3 can all show a good trade-off.

[0017] As one possible implementation, w can be 2, 3, 4, 5, or 6.

[0018] As one possible implementation, the base matrix further includes a second region E1; the columns of the second region E1 include columns kb+M+1 to X1+kb of the base matrix; the rows of the second region E1 include rows M+1 to X1 of the base matrix; wherein the elements in the i1th row and j1th column of the second region E1 are all elements of the second type, where kb+M < j1 < kb+i1, and i1 is greater than M and less than or equal to X1. This design can improve the reliability of the check columns associated with all core rows under high bitrates and also improve the convergence speed. Furthermore, it can further reduce the complexity of the control logic on the encoding side under high bitrates and further improve the encoding and decoding efficiency in high-throughput scenarios.

[0019] As one possible implementation, the base matrix further includes a second region E1; the columns of the second region E1 include columns kb+M+1 to X1+kb of the base matrix; the rows of the second region E1 include rows M+1 to X1 of the base matrix; the column weight of the first target column in the base matrix is ​​greater than or equal to 2; wherein the index of the first target column in the second region E1 is the same as the index of row P in the second region E1. This design can improve the reliability of the check columns associated with all core rows under high bitrates and also improve the convergence speed. Furthermore, it can further reduce the complexity of the control logic on the encoding side under high bitrates and further improve the encoding and decoding efficiency in high-throughput scenarios.

[0020] As a possible implementation, the base matrix further includes Q rows, which satisfy the first relationship with the P rows and / or the first M rows. One row in the Q rows is the first target row in the first relationship, and one row in the P rows and / or the first M rows is the second target row in the first relationship. Q is equal to the number of rows in the P rows and / or the first M rows. The Q rows are separated from the P rows by Y rows, where Y is a positive integer. The elements in the i2th row and j2th column of the first region E2 include the first type of elements, where kb+M < j2 < kb+i2, and the row number of the i2th row is the same as the row number of one row in the Y rows. This design improves the early convergence speed of decoding. Furthermore, it reduces the complexity of the control logic on the encoding side and further improves encoding and decoding efficiency in high-throughput scenarios.

[0021] As one possible implementation, the base matrix further includes Q rows, which satisfy the first relationship with the P rows and / or the first M rows. One row in the Q rows is the first target row in the first relationship, and one row in the P rows and / or the first M rows is the second target row in the first relationship. Q is equal to the number of rows in the P rows and / or the first M rows. The elements in the i3th row and j3th column of the first region E2 are both elements of the second type, where kb+M < j3 < kb+i3, and the row number of the i3th row is the same as the row number of one row in the Q rows. This approach reduces the complexity of the encoding implementation and improves the orthogonality of the base matrix, which helps improve encoding and decoding efficiency in high-throughput scenarios.

[0022] As one possible implementation, the base matrix further includes Q rows, which satisfy the first relationship with the P rows and / or the first M rows. One row in the Q rows is the first target row in the first relationship, and one row in the P rows and / or the first M rows is the second target row in the first relationship. Q is equal to the number of rows in the P rows and / or the first M rows. The column weight of the second target column in the base matrix is ​​greater than or equal to 2. The index of the second target column in the first region E2 is the same as the index of the Q rows in the first region E2. This design improves the early convergence speed of decoding. Furthermore, it reduces the complexity of the control logic on the encoding side and further improves encoding and decoding efficiency in high-throughput scenarios.

[0023] Thirdly, this application provides a communication device that has the functions involved in any of the implementation methods of the first aspect described above. For example, the communication device includes modules, units, or means corresponding to the operations involved in any of the implementation methods of the first aspect described above. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0024] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in any implementation method of the first aspect described above.

[0025] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions involved in any implementation of the first aspect described above. The processor may execute the computer programs or instructions stored in the memory, such that when the computer programs or instructions are executed, the communication device implements any implementation of the first aspect described above.

[0026] In one possible design, the communication device includes a processor and a memory, the memory of which can store necessary computer programs or instructions for implementing the functions involved in any implementation method of the first aspect described above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement any implementation method of the first aspect described above.

[0027] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute any implementation of the first aspect described above.

[0028] Understandably, the processor in the third aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0029] Fourthly, this application provides a communication device that has the functions involved in any of the implementation methods of the second aspect described above. For example, the communication device includes modules, units, or means corresponding to the operations involved in any of the implementation methods of the second aspect described above. The functions, units, or means can be implemented by software, or by hardware, or by hardware executing corresponding software.

[0030] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in any implementation method of the second aspect described above.

[0031] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions involved in any implementation of the second aspect described above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement any implementation of the second aspect described above when the computer programs or instructions are executed.

[0032] In one possible design, the communication device includes a processor and a memory, the memory of which can store necessary computer programs or instructions for implementing the functions involved in any implementation method of the second aspect described above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement any implementation method of the second aspect described above.

[0033] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is used to communicate with other devices through the interface circuit and to execute any implementation of the second aspect described above.

[0034] Understandably, the processor in the fourth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or they can be set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0035] Fifthly, this application provides a communication device that has the functions of the first aspect described above. For example, the communication device includes modules, units, or means that perform the operations involved in the first aspect. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0036] Sixthly, this application provides a communication device that has the functions of the second aspect above. For example, the communication device includes modules, units, or means that perform the operations involved in the second aspect above. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0037] In a seventh aspect, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to execute any implementation method of the first aspect, and the second communication device is used to execute any implementation method of the second aspect.

[0038] Eighthly, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which any of the implementation methods of the first to second aspects are executed when a computer reads and executes some or all of the computer-readable instructions.

[0039] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0040] Ninthly, this application provides a computer program product that, when read and executed by a computer, causes any implementation of the first to second aspects described above to be executed.

[0041] In a tenth aspect, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any implementation method of the first to second aspects described above is executed. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the embodiments of this application; Figure 2 A schematic diagram illustrating a processing flow between the information source and the information sink; Figure 3 4 A schematic diagram of a 4-bit cyclic shift matrix; Figure 4 This is a schematic diagram of the structure of a base graph or parity check matrix; Figure 5 This is a schematic diagram of a double-diagonal coding structure; Figure 6 Example diagram for splitting extension; Figure 7 A flowchart illustrating the encoding and decoding methods provided in the embodiments of this application; Figures 8 to 14 A schematic diagram of the region partitioning for the basis matrix; Figure 15 An example diagram of a base map provided in an embodiment of this application; Figure 16 A schematic diagram of a basis matrix provided in an embodiment of this application; Figure 17 An exemplary block diagram of a communication device provided in an embodiment of this application; Figure 18 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0043] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0044] The technical solutions of this application can be applied to various wireless communication systems, such as wireless local area networks (WLANs), short-range wireless communication systems (e.g., sidelinks, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, frequency division duplex (FDD) systems, time division duplex (TDD) systems, 5th generation (5G) mobile communication systems (e.g., new radio (NR) systems), 6G communication systems, future communication systems, or other similar communication systems, without limitation. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0045] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1 The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0046] (1) Network equipment

[0047] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network in 3GPP, such as 5G or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), a virtualized RAN (vRAN), an artificial intelligence radio access network (AI RAN), a wireless fidelity (WiFi) system, or a communication network combining two or more of these.

[0048] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system (such as an aNB), or an access node in a WiFi system, etc.

[0049] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) protocol and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (such as...) Figure 1 (e.g., 110a), or it can be a micro base station or an indoor station (such as...) Figure 1 The node in question (110b) can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0050] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0051] (2) Terminal equipment

[0052] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, onboard units (OBUs) or telematics boxes (T-BOXs), etc.), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0053] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0054] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0055] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0056] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0057] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0058] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0059] (1) Channel coding and channel decoding

[0060] Figure 2 This is a schematic diagram illustrating a processing flow between the information source and the information sink. For example... Figure 2As shown, the transmitting end obtains the bit sequence to be encoded through source coding and then performs channel coding on the bit sequence to obtain the encoded bit sequence. Correspondingly, after the receiving end obtains the sequence to be decoded, it performs channel decoding on the sequence to be decoded to obtain the decoding result, and then performs source recovery on the decoding result to obtain useful information.

[0061] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0062] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with sparse parity-check matrices, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0063] (2) Modulation and demodulation

[0064] See Figure 2 The transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then send the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and then demodulate it to obtain the symbol sequence to be decoded.

[0065] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0066] (3) Information bit sequence

[0067] An information bit sequence refers to a sequence of multiple information bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, the resulting information bit sequence is 10101100101. This information bit sequence consists of K information bits, where K is a positive integer. This information bit sequence can be a transport block (TB), a bit sequence resulting from a transport block concatenated with a TB-CRC sequence, a code block (CB), or a bit sequence resulting from a code block concatenated with a CB-CRC sequence and / or padding bits. A transport block can be divided into multiple code blocks. CRC is short for Cyclic Redundancy Check. TB and CB can also be referred to as payload bit sequences.

[0068] (4) Information length, code length and code rate

[0069] The information length is the length of the information bit sequence, which can be represented by K or K'. This length can be the length of the payload information bits, the length of the payload information bits after adding cyclic redundancy check (CRC) bits, or the length of the payload information bits after adding CRC bits and shortening bits. In this application, the information length is the length of the information bit sequence after code block segmentation. The CRC bits in this application may include transport block-cyclic redundancy check (TB-CRC), or include TB-CRC and code block-cyclic redundancy check (CB-CRC). The shortening bits refer to known bits (such as 0, null, padding bits, or other values).

[0070] In one possible approach, the length K of the information bit sequence can be determined as follows: Let B be the length of the input bit sequence for code block segmentation (e.g., B is the length of the payload information bits after adding TB-CRC bits of length L, or the length after adding probabilistic shaping padding bits). If B is greater than the maximum code block size K corresponding to the base map, ... cb The input bit sequence is then segmented to obtain C code blocks (C≥1, numbered starting from 1). When C is greater than 1, a CB-CRC bit of length L' is appended to each code block. For example, K... cb The values ​​are 8448, 16896, or 3840. For example, L = 16 or 24, L' = 24.

[0071] In some embodiments, the code length can refer to the length of the encoded bit sequence obtained through encoding, and can be represented by N. Generally, this code length also refers to the code length before rate matching. In some embodiments, the code length can refer to the length of the transmitted bit sequence or the length of the bit sequence to be transmitted, and can be represented by E. Generally, this code length can also refer to the code length after rate matching. In some embodiments, the code length can also be the number of transmitted bits corresponding to the modulated symbol.

[0072] The code rate can refer to the ratio of the length of the bit sequence of information to be transmitted to the code length, and is generally represented by R. For example, R equals K / E. Another example is R equaling K / N.

[0073] Optionally, the information length, code length, or code rate can be pre-configured / indicated by higher-layer signaling, media / medium access control (MAC) layer, or physical layer signaling, or it can be obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, or modulation scheme of the encoded and transmitted information bit sequence; the code rate can be obtained through the modulation and coding scheme (MCS).

[0074] (5) LDPC code

[0075] LDPC codes are a channel coding scheme very close to the Shannon limit, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes have a QC structure, which avoids bad structures such as short loops and improves code distance by setting the shift amount of each block.

[0076] LDPC codes are typically defined by an LDPC matrix H, which can be defined using a base graph. The base graph can be represented as an m x n matrix, containing m × n elements (or entries). Each element in the base graph indicates a submatrix of the LDPC matrix H. The base graph includes two types of elements; this application uses zero elements and non-zero elements as examples. Zero elements indicate a matrix of all zeros, and non-zero elements indicate a cyclic permutation matrix. Optionally, the zero elements in the base graph are represented by a first value, and the non-zero elements by a second value. As an example, the first value is 0, and the second value is 1.

[0077] Each zero element in the base graph represents a zero matrix of size Z × Z in the LDPC matrix H. That is, this zero element can be replaced by a zero matrix of size Z × Z. Here, Z is a positive integer, and Z represents the lifting size, sometimes also called the lifting factor, expansion factor, expansion value, expansion coefficient, etc. Each non-zero element in the base graph represents a circulant permutation matrix of size Z × Z in the LDPC matrix H. That is, this non-zero element can be replaced by a circulant permutation matrix of size Z × Z.

[0078] The position of each element in the base graph is defined by its row index i and column index j. In other words, an element can be identified by its row index i and column index j. The non-zero element (i, j) at row i and column j in the base graph corresponds to the cyclic shift value P. i,j P i,j The integer is greater than or equal to 0. The non-zero element (i, j) in row i and column j represents the Z×Z cyclic permutation matrix corresponding to Pi,j, which can be obtained by cyclically shifting the Z×Z identity matrix Pi,j times to the right or left. For example, for 4 The matrix obtained by circularly shifting the identity matrix of 4 to the right by 1, 2, 3, and 0 times respectively is as follows: Figure 3 As shown, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0079] In a base graph, the positions of non-zero elements indicate that the remaining elements in the base graph are zero elements, and vice versa. Therefore, a base graph can also be defined by the positions of its non-zero or zero elements.

[0080] There is a correspondence between the base graph and the LDPC matrix H. In one implementation, the LDPC matrix H can be obtained based on the base graph and the boosting value as follows: If the element in row i, column j of the base graph has a value of 0 (i.e., the element is zero), then the element is replaced with a Z×Z matrix of all zeros; if the element in row i, column j of the base graph has a value of 1 (i.e., the element is non-zero), then the element is replaced with a Z×Z cyclic permutation matrix I(P). i,j The cyclic permutation matrix I(P) i,j By cyclically shifting the Z×Z identity matrix to the right or left by P i,j This is obtained the next time. Among them, P... i,j is an integer greater than or equal to 0. For an m-row, n-column base graph, the size of its corresponding LDPC matrix H is (m×Z) ×(n×Z).

[0081] P corresponding to the non-zero element in row i and column j of the base graph i,j It can be derived based on Z. For the same non-zero element at the same position, different Z values ​​may result in different P values. i,j For example, P i,j The offset value is modulo Z. If the element in row i and column j of the base graph is non-zero, then its offset value can be expressed as V. i,j P i,j For example, P can be satisfied. i,j =mod(V i,j , Z), where mod represents modulo.

[0082] In some possible implementations, it can be based on P i,j or V i,j The encoding or decoding effect constrained by the Z×Z cyclic permutation matrix can be achieved by cyclically shifting the Z bits to be encoded or decoded (e.g., using a feedback shift register or cyclic shift network circuit).

[0083] The LDPC matrix H can also be defined by an m-row, n-column base matrix corresponding to the base graph. The base matrix is ​​sometimes also called the offset matrix, offset value matrix, cyclic shift matrix, or cyclic shift value matrix of the base graph. Each element in the base matrix corresponds one-to-one with the position of each element in the base graph. Specifically, the base matrix includes zero elements and non-zero elements. The zero elements in the base graph remain in their positions in the base matrix and can be represented by a first preset value, such as -1, null, or other values. The non-zero element in the i-th row, i-th column, j-th column of the base graph remains in its position in the base matrix and can be represented by a second preset value, such as P. i,j V i,j Or other values. Each element in the base matrix corresponds one-to-one with the position of each element in the base graph. This can also be understood as the base matrix including elements (or entries) indicating different values. The element in the base matrix corresponding to the zero element in the base graph indicates a first preset value, such as -1, null, or other values; the element in the base matrix corresponding to the non-zero element in row i and column j of the base graph indicates a second preset value, such as P. i,j V i,j Or other values.

[0084] In a basis matrix, the positions of the remaining positions corresponding to the non-zero elements (or, in other words, the positions corresponding to the first preset value) can be used to determine if they correspond to zero elements. Therefore, a basis matrix can also be determined by the second preset value (e.g., P) corresponding to the non-zero elements. i,j V i,j Defined by (or other values) and their positions.

[0085] In this application, for a base graph or base matrix with m rows and n columns, its row index i and column index j satisfy 0 ≤ i ≤ m-1, 0 ≤ j ≤ n-1. That is, both row and column numbers start from 0. Column 0 represents the first column of the matrix, column 1 represents the second column, row 0 represents the first row, row 1 represents the second row, and so on. Alternatively, the row and column numbers can start from other values. For example, starting from 1, the corresponding row and column numbers are increased by 1 based on the row and column numbers shown in this application. For instance, if the row and column numbers start from 1, then column 1 represents the first column, column 2 represents the second column, row 1 represents the first row, row 2 represents the second row, and so on.

[0086] (6) The basis graph of LDPC code

[0087] The columns of an LDPC base matrix (or base graph, check matrix) consist of information columns and check columns.

[0088] Information column: Corresponds to information bits (or information bits, system bits, etc.), and the number of information columns is denoted as kb.

[0089] Check column: Corresponds to the check bit (or check digit, etc.), and can include the core check column and the extended check column.

[0090] Figure 4 This is a schematic diagram of a base graph or parity check matrix structure. For example... Figure 4 As shown in (a), the base map may include a high rate region (also known as the core region or core matrix), an all-zero region, an incremental redundancy region, and a raptor-like region.

[0091] The high bitrate region (core matrix, where high bitrate can be 0.926, or 11 / 12, 44 / 47, 44 / 49, 44 / 50) can include Figure 4 The diagram shows parts A and B. Part A corresponds to information bits (or system bits, information bits, system bits, etc.), and the information columns of the base map are the columns corresponding to parts A. Part B is a square matrix and corresponds to core check bits (or core check bits), and the core check columns of the base map are the columns corresponding to parts B. Part B is characterized by the fact that the column weight of each column in part B is greater than 1 (i.e., each column in part B contains at least 2 non-zero elements in the row corresponding to part B), and the number of rows in part B can be 3, 4, 5, or 6. As an example, part B corresponds to 4... The submatrix region of 4, in this 4 In the submatrix region of 4, all column weights are greater than 1. More specifically, part B can be a non-lower triangular coding part (i.e., the values ​​above the diagonal are not all 0, i.e., it includes at least one 1 element). For example, part B can be a double-diagonal matrix structure. For instance, the column weights of a double-diagonal coding structure include 2 and 3, and the number of columns with a weight of 3 is 1 or 2. When part B consists of 3 rows and 3 columns, the column weights corresponding to the 3 columns in part B can be 3, 2, and 2 respectively, such as... Figure 5 As shown in (a); when part B consists of 4 rows and 4 columns, the column weights of the 4 columns in part B can be 3, 2, 2, 2, respectively, as shown in (a). Figure 5 As shown in (b); when part B consists of 6 rows and 6 columns, the column weights corresponding to the 6 columns in part B can be 3, 2, 2, 3, 2, 2, or 3, 2, 2, 2, 2, 2 (the column weights are not distinguished by order, only the column weight values ​​are limited).

[0092] Core rows are rows in the core matrix, or rows corresponding to parts A, B, or C. Non-core rows are all rows remaining in the LDPC basis matrix except for the core rows. For example, core rows have significantly higher row weights than non-core rows, or the row weight of core rows is greater than 15, 20, 25, or 30, or the row weight of core rows is greater than the sum of the maximum non-core row weight and a row weight threshold, such as 10, 15, or 20.

[0093] Core columns can include all information columns and all core verification columns. In other words, core columns are columns of the core matrix, or columns corresponding to part A plus part B.

[0094] The all-zero region can correspond to Figure 4 The C part of (b) is an all-zero matrix, and the extended check column of the base map is the column corresponding to the C part.

[0095] Incremental redundancy regions can correspond to Figure 4 In part D of (b), the rows in region D correspond to the incremental redundancy (IR) check relation (i.e. check equation) in non-peak bit rate scenarios.

[0096] The Laputa-like region can correspond to Figure 4The E part of (b) can be an identity matrix, corresponding to the parity bits of the low-rate extension. The extended parity column of the base map is the column corresponding to the E part. Both the B and E parts are parity parts. The E part is defined as the extended parity region, and its characteristics can be a lower triangular matrix (i.e., all values ​​above the diagonal are 0) or an identity matrix. Since the values ​​on the diagonal of the E region are always 1, the correspondence between the extended parity row and the extended parity column can be represented by the row number i and column number j of the diagonal, where i and j satisfy the condition j = i + kb. The extended parity column j is said to be the parity column corresponding to the extended parity row i, or the parity column corresponding to the extended parity row is the last column associated with this row.

[0097] For example, the extended check region of the NR LDPC code adopts a "raptor-like" structure, which can be gradually extended from high-rate regions to low-rate regions. In practical use, such as... Figure 4 As shown in (a), X rows and X columns can be added to the high bit rate region. As the bit rate decreases, X gradually increases, and the matrix region used also gradually expands. Another possible implementation is that the encoding side can not perform the process of filtering the matrix from the largest base matrix, but instead encode according to the lowest bit rate (or the maximum code length), and then send the corresponding encoded bits according to the target bit rate.

[0098] It is understandable that the partitioning method of the basis matrix is ​​similar to that of the basis graph. The parity check matrix can be represented by the LDPC basis matrix. Therefore, the partitioning method of the parity check matrix is ​​similar to that of the LDPC basis matrix, and will not be elaborated here.

[0099] (7) LDPC rate matching

[0100] Rate matching refers to the process of removing some bits from the encoded bit sequence or repeating the transmission of some bits to meet the actual transmission rate. The methods of rate matching are further explained below in three categories.

[0101] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the decoder can set the LLR of the corresponding bit to 0.

[0102] Shortening: This makes certain bit positions in the encoded bit sequence fixed values ​​and do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are equivalent to being known at the receiving end (usually 0), the decoding end can set the LLR of the corresponding bit to infinity.

[0103] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0104] (8) Traditional expansion and split expansion

[0105] Figure 4 The LDPC matrix with flexible code rate shown in (a) is only an example. Figure 4 (a) can be seen as a traditional extension of the LDPC matrix.

[0106] For example, another approach is to support LDPC matrices with flexible code rates through splitting. This is characterized by a first split relationship between rows with larger row indices and rows with smaller row indices. This first split relationship can be used to perform elimination between rows with larger row indices (e.g., child rows, or child nodes, rows used for elimination) and rows with smaller row indices (e.g., parent rows, or parent nodes, rows being eliminated), resulting in new check equations that maintain both sparsity and the error-correcting capability of the LDPC code. LDPC codes that satisfy this characteristic can be called split LDPC codes.

[0107] The first split relation refers to: Sub-row (referred to as row) In the set of column indexes corresponding to non-zero elements, the column indexes other than the X column indexes are properly contained in the parent row (called row X). The set of column indices corresponding to non-zero elements in the parent row, and if the child row and the parent row are in the same column (called column indexes) If all elements in the array have non-zero elements, then we have: or and The difference is a fixed value, that is... This holds true for any column j. Here, t is any given integer; the value of t can be the same or different for different rows, which is not restricted in this scheme. X takes the value 1 or 2; X must be at least 1 because the extended check column corresponding to the child row is not included in the set of associated column indices of the parent row, i.e., the base graph... OK The column takes a value of 1, but... OK The column takes a value of 0.

[0108] The following example illustrates a splitting expansion method for an LDPC matrix. For example, Figure 6 Here's an example of splitting a basis matrix, which can be denoted as matrix 1 for ease of description. In this matrix, the values ​​of elements other than -1 represent the shift values ​​at that position, and the elements with a value of -1 correspond to the zero element, representing the Zc value in the parity check matrix. A matrix of all zeros in Zc, or an element that can be represented by Zc. The all-zero matrix replacement of Zc is not a translation of -1 at this position.

[0109] Figure 6 Matrix 1 shown in (a) has 4 rows and 48 columns, where columns 1 to 44 are information columns and columns 45 to 48 are verification columns.

[0110] The first row of matrix 1 is {112 186 190 13 180 185 139 73 168 50 163 59 103 10 110 124 114 181 54 136 190 49 1 136 27 144 -1 -1 -1 -1 -1 -1 33 49 3 122 8 150 133 169 169 10 161 150 0 0 -1 -1}. The second row of matrix 1 is {16 78 36 65 126 28 15 149 49 81 147 149 96 123 174 122 69 112 58 84 -1 -1 -1 -1 -1 -1 -1 The first matrix has the following data: 191 129 60 43 181 819 32 65 51 122 25 180 99 123 35 25 15 1 0 0 -1}. The third row of matrix 1 contains: {64 12 185 183 165 7 25 138 149 109 25 158 118 97 106 95 81 84 18 26 159 137 159 42 164 58 120 130 163 86 139 150 152 178 92 75 190 167 -1 -1 -1 -1 -1 -1 -1 -1 0 0}. The fourth row of matrix 1 contains: {136 15 6 149 191 129 60 43 181 819 32 65 51 122 25 180 99 123 35 25 15 1 0 0 -1}. 14 116 112 14 8 92 17 133 21 121 141 104 182 34 13371 45 180 17 60 96 169 136 44 141 132 162 11 -1 -1 -1 -1 -1 -1 71 11 63 49188 67 0 -1 -1 0}.

[0111] As can be seen, matrix 1 is applicable to high bitrate ranges (without puncturing, the bitrate is 44 / 48≈0.917). Furthermore, matrix 1 has a large number of non-zero elements in each row, resulting in a high edge density, which allows for high convergence speed at high bitrates. The edge density can be understood as the number of edges in the BG (Block Graph), corresponding to the number of non-zero elements in the base matrix.

[0112] The matrix 2 shown below includes matrix 1 as the core matrix, and also includes an extended checksum for lower bitrates (row 5 in matrix 2). The row weight of row 5 in matrix 2 is approximately 0.5 times the total number of columns in matrix 2 (49 / 0.5). It can be seen that matrix 2 has 5 rows and 49 columns, with one additional checksum column compared to matrix 1, thus supporting a lower bitrate (without puncturing, the bitrate is 44 / 49≈0.898).

[0113] Figure 6The first row of matrix 2 shown in (b) is {112 186 190 13 180 185 139 73 168 50 16359 103 10 110 124 114 181 54 136 190 49 1 136 27 144 -1 -1 -1 -1 -1 -1 33 493 122 8 150 133 169 169 10 161 150 0 0 -1 -1 -1}, and the second row of matrix 2 is {16 78 36 65126 28 15 149 49 81 147 149 96 123 174 122 69 112 58 84 -1 -1 -1}. -1 -1 -1 191129 60 43 181 81 9 32 65 51 122 25 180 99 123 35 25 15 1 0 0 -1 -1}, the third row of matrix 2 is {64 12 185 183 165 7 25 138 149 109 25 158 118 97 106 95 81 84 18 26 159137 159 42 164 58 120 130 163 86 139 150 152 178 92 75 190 167 -1 -1 -1 -1 -1 -1 -1 -1 0 0 The fourth row of matrix 2 is {136 15 6 149 14 116 112 14 8 92 17 133 21 121141 104 182 34 133 71 45 180 17 60 96 169 136 44 141 132 162 11 -1 -1 -1 -1 -1 -1 71 11 63 49 188 67 0 -1 -1 0 -1}. The fifth row of matrix 2 is {-1 -1 185 183 -1 -1 25138 149 109 25 158 118 97 -1 -1 -1 -1 -1 -1 -1 -1 -1 159 42 -1 -1 120 130}. -1 -1-1 -1 152 178 92 75 190 167 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0}.

[0114] It can be seen that the 5th row and the 3rd row of matrix 2 satisfy the first split relationship. Therefore, the 5th row and the 3rd row of matrix 2 can be eliminated (the Zc row corresponding to the improved parity check matrix of the 5th row of matrix 2 is eliminated with the Zc row corresponding to the improved 3rd row), resulting in a new parity check equation, as shown in the 3rd row of matrix 3 below (the 3rd row is a row in the basis matrix corresponding to the eliminated Zc row). The 3rd row of matrix 3 is obtained by eliminating the 5th row and the 3rd row of matrix 2. In this application, elimination can be understood as an XOR operation in the binary field. The matrix after elimination can be used for low code rate decoding. Since the matrix after elimination has a more regular row redistribution, it is more in line with the row redistribution condition of the density evolution theory for decoding threshold optimization, and will have better decoding performance.

[0115] Figure 6The first row of matrix 3 after elimination, as shown in (c), is {112 186 190 13 180 185 139 73168 50 163 59 103 10 110 124 114 181 54 136 190 49 1 136 27 144 -1 -1 -1 -1 -1 -1 33 49 3 122 8 150 133 169 169 10 161 150 0 0 -1 -1 -1}. The second row of matrix 3 is {16 78 36 65 126 28 15 149 49 81 147 149 96 123 174 122 69 112 58 84 -1}. The third row of matrix 3 is {64 12 -1 -1 165 7 -1 -1 -1 -1 -1 -1 -1 -1 -1 106 95 81 8418 26 159 137 -1 -1 164 58 -1 -1 163 86 139 150 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 0}. The fourth row of matrix 3 is {136 15 6 149 14 116 112 14 8}. The fifth row of matrix 3 is {-1 -1 185 183 -1 -125 138 149 109 25 158 118 97 -1 -1 -1 -1 -1 -1 -1 -1 159 42 -1 -1 120 130 -1 -1 -1 -1 152 178 92 75 190 167 -1 -1 -1 -1}. -1 -1 -1 -1 -1 -1 0}.

[0116] Since elimination does not change the parity check relationship, the sending end can skip elimination and directly encode the bit sequence to be encoded based on the matrix before elimination (e.g., matrix 2) or the matrix after elimination (e.g., matrix 3). This application does not limit this approach; the example described is based on the sending end using the matrix before elimination. The matrix after elimination scheme can also be derived accordingly. In actual implementation, both the sending and receiving ends may omit elimination and instead store each matrix that changes due to elimination (e.g., matrix 2 and matrix 3), selecting the matrix for encoding / decoding based on the code rate.

[0117] Optionally, a categorical expansion sequence (split sequence) can be defined. This is used to indicate elimination relations. elements in It is a special character (such as -1) or less than ,sequence The length is equal to the total number of parity columns in the LDPC matrix. Indicates the first line and number The rows satisfy the first split relation, and the second split relation needs to be used during decoding. Line and number The verification equation is used to perform elimination. It can be seen as The parent node, It can be seen as child nodes, Indicates the first The line number is not less than the line number. Any row of the sequence satisfies the first split relation. For example, in the example shown above, the sequence... It is (-1 -1 -1 -1 2).

[0118] In the above sequence, -1 is a special character. express It does not correspond to any row index. If the row index starts from 1, other values ​​can be used as special characters, such as... wait.

[0119] For example, in a split scenario, encoding can be done using either the matrix before or after elimination, resulting in identical parity bits, i.e., H1. x=0 is equivalent to H2 x=0, where H1 is the matrix before elimination and H2 is the matrix after elimination.

[0120] (9) Selection of basis matrix

[0121] For example, if A is less than or equal to 292, or A is less than or equal to 3824 and R is less than or equal to 0.67, or R is less than or equal to 0.25, then 5G BG2 is selected; otherwise, 5G BG1 is selected. Here, A is the length of the payload bit sequence, and R is the payload code rate.

[0122] Currently, LDPC codes still have room for improvement in performance and convergence speed under high-throughput scenarios. Furthermore, high-code-rate matrices may appear as submatrices in low-code-rate scenarios, resulting in dense core regions persisting even at low code-rate levels, leading to poor overall orthogonality and high decoding latency. For split-extended matrices, the numerous locations of the split-extends make it difficult to specifically enhance decoding performance.

[0123] Therefore, the embodiments of this application design the characteristics of each region of the base matrix to ensure that the matrix can obtain the benefits of split expansion, with excellent performance in both high and low bit rate ranges, while being simple to implement and requiring no complex control logic.

[0124] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.) or a component within that communication device (e.g., a processor, a chip, or a chip system, etc.). Alternatively, the method executed by the first communication device in this application can also be implemented by a logic module or software capable of implementing all or part of the functions of the communication device. The term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.) or a component within that communication device (e.g., a processor, a chip, or a chip system, etc.). Alternatively, the method executed by the second communication device in this application can also be implemented by a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0125] In this application, the first type of element corresponds to a non-zero element, and the second type of element corresponds to a zero element. In one example, the first type of element is a non-zero element, and the second type of element is a zero element. In another example, the first type of element is represented by a second preset value, such as P. i,j V i,jOr other values, the position of the first type of element in the basis matrix is ​​the same as the position of the non-zero element in the basis graph; the second type of element is represented by the first preset value, such as -1 or the null value or other values, and the position of the second type of element in the basis matrix is ​​the same as the position of the zero element in the basis graph.

[0126] Figure 7 This is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps: S1001, the first communication device acquires the information bit sequence.

[0127] This information bit sequence consists of K information bits, where K is a positive integer. For details on this information bit sequence, please refer to the relevant description in the terminology introduction (3) above. A transport block can be divided into multiple code blocks.

[0128] S1002, the first communication device encodes the information bit sequence according to the base matrix to obtain the encoded output bit sequence.

[0129] Alternatively, this method can also be described as follows: the first communication device encodes the information bit sequence according to the base map (or information of the base map).

[0130] In one possible implementation, the first communication device is capable of storing a complete or partial basis matrix / base map in matrix form, or storing all or part of the parameters of the basis matrix / base map. The first communication device encodes an information bit sequence based on the basis matrix / base map, including: the first communication device encodes the information bit sequence based on a partial or complete basis matrix / base map, or the first communication device encodes the information bit sequence based on all or part of the parameters of the basis matrix / base map. For example, the first communication device can perform P on the Z bits corresponding to the non-zero element positions in the information bit sequence based on some or all of the parameters of the basis matrix / base map. i,j The next cyclic shift is performed, and the shifted bits are encoded (e.g., XORed) to determine the encoded output bit sequence.

[0131] In one possible implementation, the first communication device encodes the information bit sequence according to the LDPC matrix H to obtain the encoded output bit sequence.

[0132] In one implementation of the LDPC matrix H, it can be obtained by expanding the basis matrix / basis graph according to the lift value Z, that is, by expanding the non-zero elements to Z. The cyclic permutation matrix of Z, with zero elements extended to Z The all-zero matrix of Z.

[0133] In one implementation of the LDPC matrix H, during encoding, the offset value or cyclic shift value corresponding to the non-zero element can be obtained based on the position of the non-zero element corresponding to the information bit, and the non-zero element can be replaced with the corresponding cyclic permutation matrix. This eliminates the need to expand the complete LDPC matrix H all at once, thereby reducing storage overhead and implementation complexity.

[0134] In one implementation of the LDPC matrix H, the LDPC matrix H is not directly expanded during the encoding process. Instead, the connection relationship between the rows and columns of the matrix is ​​determined based on the offset value or the cyclic shift value, and the bits in the information bit sequence are processed.

[0135] It is understood that in the above encoding process, encoding can be based on the complete base matrix, base graph, or LDPC matrix H, or it can be based on a part of the base matrix, base graph, or LDPC matrix H.

[0136] For example, encoding can be based on a complete base matrix, a base graph, or an LDPC matrix H to obtain as many parity bits as possible. In subsequent processing, the information bits and parity bits to be transmitted are determined from the output sequence generated by the encoder.

[0137] For example, encoding can be based on a portion of the complete base matrix, base graph, or LDPC matrix H, including a portion of rows, columns, or a subset of rows and columns. The appropriate rows and / or columns can be selected from the complete base matrix, base graph, or LDPC matrix H for encoding based on factors such as the code rate.

[0138] Optionally, the first communication device may output an encoded bit sequence, such as modulating the output bit sequence to output a modulated signal.

[0139] S1003, the second communication device acquires the information to be decoded.

[0140] The information to be decoded can be obtained by demodulating the received sequence, or by demodulation and rate matching. This application does not limit the method for obtaining the information to be decoded.

[0141] S1004, the second communication device decodes the information to be decoded according to the basis matrix to obtain the decoded output bit sequence.

[0142] Alternatively, this method can also be described as follows: the second communication device encodes the information bit sequence according to the base map (or information of the base map).

[0143] In one possible implementation, the second communication device is capable of storing a complete or partial basis matrix / base map in matrix form, or storing all or part of the parameters of the basis matrix / base map. The second communication device decodes the information bit sequence based on the basis matrix / base map, including: the second communication device decoding the information bit sequence based on a partial or complete basis matrix / base map, or the second communication device decoding the information bit sequence based on all or part of the parameters of the basis matrix / base map. For example, the second communication device can perform P on the Z bits corresponding to the non-zero element positions in the information bit sequence based on some or all of the parameters of the basis matrix / base map. i,j The next cyclic shift is performed, and the shifted bits are then decoded (e.g., XORed) to determine the decoded output bit sequence.

[0144] In one possible implementation, the second communication device decodes the information bit sequence according to the LDPC matrix H to obtain the decoded output bit sequence.

[0145] In one implementation of the LDPC matrix H, it can be obtained by expanding the basis matrix / basis graph according to the lift value Z, that is, by expanding the non-zero elements to Z. The cyclic permutation matrix of Z, with zero elements extended to Z The all-zero matrix of Z.

[0146] In one implementation of the LDPC matrix H, during decoding, the offset or cyclic shift value corresponding to the non-zero element can be obtained based on the position of the non-zero element corresponding to the information bit, and the non-zero element can be replaced with the corresponding cyclic permutation matrix. This eliminates the need to expand the complete LDPC matrix H all at once, thereby reducing storage overhead and implementation complexity.

[0147] In one implementation of the LDPC matrix H, the LDPC matrix H is not directly expanded during the decoding process. Instead, the connection relationship between the rows and columns of the matrix is ​​determined based on the offset value or the cyclic shift value, and the bits in the information bit sequence are processed.

[0148] It is understandable that in the above decoding process, decoding can be performed based on the complete basis matrix, basis graph, or LDPC matrix H, or it can be performed based on a part of the basis matrix, basis graph, or LDPC matrix H.

[0149] For example, decoding can be based on a complete basis matrix, a basis graph, or an LDPC matrix H to obtain as many parity bits as possible. In subsequent processing, the information bits and parity bits to be transmitted are determined from the output sequence generated by the decoder.

[0150] For example, decoding can be performed based on a portion of the complete base matrix, base graph, or LDPC matrix H, including a portion of rows, columns, or a subset of rows and columns. The appropriate rows and / or columns can be selected from the complete base matrix, base graph, or LDPC matrix H for decoding based on factors such as the code rate.

[0151] In this embodiment of the application, the base matrix may include a first region (also called the E2 region, or simply E2). For example, the location of the E2 region may be as follows: Figure 8 As shown.

[0152] Before introducing the location / range of the E2 region, let's first introduce row P in the base matrix. This row P in the base matrix is ​​the first row that satisfies the first relation with the first M rows of the base matrix. Specifically, one row in this row P is the first target row in the first relation, and one row in the first M rows of the base matrix is ​​the second target row in the first relation. P is a positive integer, specifically, P can be less than or equal to M. Taking row i (where i can be understood as the row number) in the first M rows of the base matrix as an example, the row that first satisfies the first relation with row i in the first M rows of the base matrix can be understood as the row with the smallest row number in row j that satisfies the following condition: j>i and satisfies the first relation with row i, and j>i. Alternatively, in the context of split-expansion sequences... In the scheme, the split extension sequence The first occurrence of row i in the sequence is the position of the sequence. For example, if the sequence is 0 0 0 0 3 2 1, then row 5 is the first row that satisfies the first relation with row 3.

[0153] The first relation can be understood as the first split relation in the terminology introduction (8) above, the first target row can be understood as the child row in the terminology introduction above, and the second target row can be understood as the parent row in the terminology introduction above.

[0154] That is, the first relation is: the column indices within the first column range of the column index set corresponding to the first type of elements in the first target row are properly contained in the column index set corresponding to the first type of elements in the second target row, and if both the first and second target rows have first type elements in the column with column index y, then... or and The difference is a fixed value, that is... This holds true for any value of y. The row index for the first target row. The row index for the second target row. t is a positive integer.

[0155] The first column interval mentioned above is the 1st to the kb+Mth column of the base matrix, which is the information column (i.e., the 1st to the kbth column of the base matrix) and the core check column (i.e., the kb+1th to the kb+Mth column of the base matrix). The information column and the core check column can be referred to the relevant descriptions in the terminology introduction (6) above.

[0156] In one example, the region corresponding to the first M rows and information columns of the basis matrix can be called the core information column region (also known as region A, or simply A), and the region corresponding to the first M rows and core check columns of the basis matrix can be called the core check region (also known as region B, or simply B). Figure 9 As shown. Among them, the relevant explanations for regions A and B can be found in the terminology introduction (6) above. The union of regions A and B will be referred to as the core region below.

[0157] The last row of the P rows of the basis matrix is ​​the X1 row of the basis matrix. In one example, the M+1 row to the X1 row of the basis matrix includes at least one row that first satisfies the first relation with the first M rows of the basis matrix. This at least one row is the aforementioned P rows, where P is less than or equal to X1-M.

[0158] In this context, rows P can be consecutive from row M+1 to row X1 of the base matrix. This approach helps reduce row weight, improves the reliability of the verification equation, and thus enhances performance under low complexity, especially in high-throughput scenarios.

[0159] Alternatively, the aforementioned rows P can also be discrete from row M+1 to row X1 of the base matrix. This approach helps to balance reducing matrix row weight and increasing matrix column weight, resulting in more stable performance and supporting a wider range of scenarios.

[0160] In one example, the region (or submatrix) corresponding to the interval from the (M+1)th row to the first column of the (X1)th row of the base matrix can be called the first incremental redundancy region (also known as the D1 region, or simply D1), such as... Figure 10 As shown. Based on Figure 10 The above row P can belong to the row interval of region D1. In the example, the column interval of region D1 is the union of the column intervals of region A and region B. The first row of region D1 is the row following the last row of region A.

[0161] Optionally, the last row in region D1 is the last row that satisfies the following condition: it is the first row to satisfy the first relation with the first M rows of the base matrix. Here, "last" means the last row in ascending order of row index. The lower boundary of the row interval of region D1 can be determined by this last row that satisfies the above condition, thereby determining the range of region D1.

[0162] Based on this, the location / range of region E2 is as follows: the columns of region E2 include columns kb+M+1 to X1+kb of the base matrix, that is, the column interval of region E2 is from column kb+M+1 to X1+kb of the base matrix. kb is the number of information columns, and M is 3, 4, 5, or 6. M can also be understood / replaced as the number of core rows. X1 is greater than M; specifically, the X1 row of the base matrix is ​​the last row of that P row in the base matrix.

[0163] The rows of region E2 include the X1+1th row of the base matrix to the last row, that is, the row interval of region E2 is the X1+1th row of the base matrix to the last row.

[0164] The location / range of region E2 has been described above. The characteristics of region E2 will be described below.

[0165] like Figure 11 As shown, in this application, the E2 region is divided into two parts: the upper part includes the first row to the xth row of the E2 region (assumed to be the X1+1th row to the X2th row of the base matrix), and the lower part includes the x+1th row to the last row of the E2 region (assumed to be the X2+1th row to the last row of the base matrix).

[0166] In one example, the region (or submatrix) corresponding to the interval from row X1+1 to the first column of row X2 of the base matrix can be called the second incremental redundancy region (also known as the D2 region, or simply D2). The region (or submatrix) corresponding to the interval from row X2+1 to the first column of the last row of the base matrix can be called the third incremental redundancy region (also known as the D3 region, or simply D3), such as... Figure 12 As shown.

[0167] In this example, the row intervals of region D2 are the same as the upper half of region E2, and the row intervals of region D3 are the same as the lower half of region E2. The column intervals of regions D2 and D3 are the same as the column intervals of region D1.

[0168] This can be understood as, in Figure 4 Based on the partitioning structure of the basis matrix shown, further... Figure 4 The D region is divided into D1, D2 and D3 regions.

[0169] For the upper part, i.e., rows 1 to x of region E2: at least one row in region E2 contains elements of type I, where x is an integer greater than 1. This can also be understood as at least one row in region D2 containing elements of type I in region E2. Alternatively, it can be understood as the column index j of the element of type I being the parity column index corresponding to row i in region D1 that satisfies the split relationship, i.e., i + kb = j. Through this method, the split parity column has a column weight of at least 2 in the decoding matrix and is associated with the core row. Increasing the column weight of this part helps improve the overall reliability of the core matrix, offering performance benefits in high-throughput, low-complexity scenarios and resulting in faster decoding speeds.

[0170] For example, rows xt from row 1 to row x in region E2 (hereinafter referred to as the first row set) all contain elements of type I, where t = 0, 1, 2, or 3. The remaining rows t from row 1 to row x in region E2, excluding the aforementioned xt rows (hereinafter referred to as the second row set), contain elements of type II. For instance, a single row (e.g., each row) in the first row set from row 1 to row x in region E2 may contain 1, 2, or 3 elements of type I. This can also be understood as most rows in region D2 containing elements of type I in region E2.

[0171] In this method, most rows in the E2 region contribute to increasing the column weight of the split check column, which can specifically enhance the reliability of the decoding bottleneck node, thus achieving a good decoding threshold and convergence speed. The smaller the value of t, the more significant the effect of increasing column weight; therefore, t is set to some small values.

[0172] The more elements of the first category there are, the more significant the effect of increasing the column weight of the split verification column will be; however, at the same time, too much density will be added to this part of the column, which may reduce the orthogonality of the matrix. Therefore, in practice, a trade-off must be made based on the needs of the scenario and the hardware implementation method, whether to focus more on performance or more on implementation simplicity. 1 to 3 can all show a good trade-off.

[0173] As an optional approach (hereinafter referred to as Approach A), the t1-th row in the second row set and the t2-th row in the base matrix satisfy the first relation, where the t1-th row in the second row set is a row in the second row set, the t2-th row in the base matrix is ​​an extended verification row, and the row index of the t2-th row in the base matrix is ​​less than the row index of the t1-th row in the base matrix. The t1-th row in the second row set is the first target row in the first relation, and the t2-th row in the base matrix is ​​the second target row in the first relation. t1 is a positive integer less than or equal to t, and t2 is a positive integer.

[0174] In one example, each row in the second set can satisfy the above method A.

[0175] This approach helps to avoid splitting core lines in low-bitrate scenarios, resulting in better performance under reverse decoding scheduling (the updated lines in the early stages of iteration have less line weight).

[0176] As an alternative approach (hereinafter referred to as Approach B), the t3rd row of the second row set and the t4th row of the base matrix satisfy the first relation, where the t3th row of the second row set is a row in the second row set, and the t4th row of the base matrix is ​​the core row. The t3th row of the second row set is the first target row in the first relation, and the t4th row of the base matrix is ​​the second target row in the first relation. T3 is a positive integer less than or equal to t, and t4 is a positive integer.

[0177] In one example, some rows in the second set satisfy method A above, while the remaining rows satisfy method B above. For instance, if row t3 in the second set satisfies method B above, then every remaining row in the second set except row t3 satisfies the above method.

[0178] The core line typically has a large line weight, which may still be large after one split. In this case, continuing to split the core line will further improve the reliability of the parity check equation at low bit rates and increase the convergence speed.

[0179] For example, the t2th row in the base matrix can be one of the first t extended check rows in the first X1 rows of the base matrix, ordered by row weight from largest to smallest. In this method, the row weight correction of the split matrix has better performance.

[0180] Optionally, rows 1 to x of region E2 can be divided into a first set of rows and a second set of rows based on whether the rows of region D2 are the first target rows that satisfy the first relation.

[0181] For example, for a row with row index g in region D2, if the row with row index g is the first target row satisfying the first relation, then the row with row index g belongs to the aforementioned first row set. Optionally, the row with row index g includes elements of the first type in region E2, and the column index corresponding to the position of the first type element is... The column; or, the row with row index g contains elements of type 2 in the E2 area.

[0182] If the row with index g is not the first target row satisfying the first relation, then the row with index g belongs to the second set of rows mentioned above. Optionally, the row with index g includes elements of the first type in the E2 area, and the position of the elements of the first type can correspond to any column in the E2 area.

[0183] In one example, taking kb=44, and considering that region D2 includes rows 9 to 25 of the base matrix, and region D3 includes rows 26 to the last row of the base matrix, this example illustrates the number of first target rows satisfying the first relation in region D2. It should be understood that this example uses rows 9 to 25 of the base matrix as the row interval of region D2. In practice, the row interval of region D2 is a subset of this interval (i.e., rows 9 to 25 of the base matrix) (e.g., rows d1 to d2 of the base matrix, where d1 is greater than or equal to 9, and d2 is less than or equal to 25). If the row interval of region D2 is a subset of this interval (i.e., rows 9 to 25), the possibility of realizing row intervals not in region D2 can be eliminated in the following scheme. For example, in the scheme below where the number of first target rows satisfying the first relation in region D2 is 1, the position of this first target row satisfying the first relation is one of rows d1 to d2 of the base matrix. For example, in the scheme where the number of first target rows satisfying the first relation in region D2 below is 2, the values ​​9~d1-1 and d2+1~25 can be removed from the first set and the second set.

[0184] 1) The number of first target rows satisfying the first relation in region D2 is 0, that is, there are no first target rows satisfying the first relation in region D2.

[0185] 2) The number of first target rows satisfying the first relation in region D2 is 1. The position of the first target row satisfying the first relation is one row from row 9 to row 25 of the basis matrix. Optionally, all elements in this row in region E2 are of type II.

[0186] Specifically, in the E2 area, rows whose row index is less than the row index of the current row include elements of the first type, while elements in rows whose row index is greater than or equal to the row index of the current row are all elements of the second type.

[0187] Optionally, if M=3, the position range of the second target row corresponding to the first target row that satisfies the first relation is the 1st to 3rd row or the 4th to 8th row in the base matrix.

[0188] If M=4, the position range of the second target row corresponding to the first target row that satisfies the first relation is rows 1-4 or rows 5-8 in the base matrix.

[0189] If M=5, the position range of the second target row corresponding to the first target row that satisfies the first relation is row 1~5 or row 6~8 in the basis matrix.

[0190] 3) The number of first target rows satisfying the first relation in region D2 is 2. Any row satisfying the first relation is a row from row 9 to row 25 of the basis matrix. Specifically, one first target row satisfying the first relation is row b1 of the basis matrix, and the other is row b2 of the basis matrix. b1 is the x-th value in the first set, b2 is the x-th value in the second set, and x is a positive integer. The first set includes {9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13 ... ,14,14,14,14,14,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15,15,15,15,16,16,16,16,16,16,16,16,16,16,16,16,17,17,17,17,17,17,17,17,17,18,18,18,18,18,18,18,19,19,19,19,19,20,20,20,20,20,21,21,21,21,21,22,22,22,23,23,24}; The second set includes {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19, 20, 21, 22,} 23, 24, 25, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 17, 18, 19, 20, 21, 22, 23, 24, 25, 18, 19, 20, 21, 22, 23, 24, 25, 19, 20, 21, 22, 23, 24, 25, 20, 21, 22, 23, 24, 25, 21, 22, 23, 24, 25, 22, 23, 24, 25, 23, 24, 25, 24, 25, 25}.

[0191] Optionally, if M=3, the second target rows corresponding to the two first target rows that satisfy the first relation are two rows from rows 4 to 8 of the basis matrix, and the row indices of the second target rows corresponding to the two first target rows that satisfy the first relation are different. Alternatively, the second target rows corresponding to the two first target rows that satisfy the first relation are two rows from rows 1 to 3 of the basis matrix, and the row indices of the second target rows corresponding to the two first target rows that satisfy the first relation are different. Alternatively, the second target row corresponding to one first target row that satisfies the first relation is one row from rows 4 to 8 of the basis matrix, and the second target row corresponding to the other first target row that satisfies the first relation is one row from rows 1 to 3 of the basis matrix.

[0192] If M=4, the second target rows corresponding to the two first target rows that satisfy the first relation are two rows from rows 5 to 8 of the basis matrix, and the row indices of the second target rows corresponding to the two first target rows that satisfy the first relation are different. Alternatively, the second target rows corresponding to the two first target rows that satisfy the first relation are two rows from rows 1 to 4 of the basis matrix, and the row indices of the second target rows corresponding to the two first target rows that satisfy the first relation are different. Or, one first target row that satisfies the first relation has a second target row corresponding to a row from rows 5 to 8 of the basis matrix, and the other first target row that satisfies the first relation has a second target row corresponding to a row from rows 1 to 4 of the basis matrix.

[0193] If M=5, the second target rows corresponding to the two first target rows that satisfy the first relation are located in rows 6-8 of the basis matrix, and the row indices of the second target rows corresponding to these two first target rows are different. Alternatively, the second target rows corresponding to the two first target rows that satisfy the first relation are located in rows 1-5 of the basis matrix, and the row indices of the second target rows corresponding to these two first target rows are different. Or, one first target row that satisfies the first relation has a second target row located in rows 6-8 of the basis matrix, and the other first target row that satisfies the first relation has a second target row located in rows 1-5 of the basis matrix.

[0194] For the lower half of region E2, from row x+1 to the last row: all elements in row x+1 to the last row of region E2 are elements of the second category, and the row number w in row x+1 to the last row of region E2 is greater than 1. For example, w can be 2, 3, 4, 5, or 6. This can also be understood as all rows in region D3 not containing elements of the first category in region E2, meaning all rows in region D3 contain elements of the second column in region E2. Alternatively, it can be understood as all rows in region D3 not satisfying the first condition mentioned above.

[0195] A larger w value results in better matrix orthogonality, which helps reduce decoding latency and improve throughput; a smaller x value results in greater column weight in the split parity column, leading to better performance. In practice, the values ​​of w and x can be weighed according to the scenario. A larger w value ensures that the E region from x+1 to the last row is completely orthogonal. This part can be encoded in parallel, meaning that the parity encoding with larger row indices in this region does not depend on the parity bits with smaller row indices, which helps improve the parallelism of encoding and reduce encoding latency.

[0196] The following describes one possible way to divide the upper and lower parts of the E2 region.

[0197] Optionally, the E2 region can be divided into an upper and lower half based on a row index.

[0198] For example, the E2 region can be divided into an upper and lower half based on the first row index. Rows in the E2 region with row indices less than the first row index include elements of type I; rows with row indices greater than or equal to the first row index include elements of type II. That is, the first row set includes rows in the E2 region with row indices less than the first row index; the second row set includes rows in the E2 region with row indices greater than or equal to the first row index. Rows with smaller row numbers include elements of type I in the E2 region, which helps improve the performance of decoding bottleneck nodes; rows with larger row numbers do not need to include elements of type I to maintain good performance, improving encoding and decoding parallelism and reducing latency.

[0199] Optionally, the row corresponding to the first row index in the base matrix and the first extended verification row satisfy a first relationship; wherein, the row corresponding to the first row index in the base matrix is ​​the first target row in the first relationship, and the first extended verification row is the second target row in the first relationship.

[0200] In one example, the first row index can be the last row in the base matrix that satisfies the aforementioned first relation with either the extended check row or the first M rows of the base matrix. This first row index can be used to divide the E2 region into an upper and lower half.

[0201] This application, by dividing the E2 region and designing features within that region, can maximize the benefits of split LDPC in the matrix, improving decoding performance in both high and low bitrate ranges. Furthermore, the feature design within the E2 region allows for flexible bitrate support on the encoding side, reducing the complexity of control logic and implementation. Additionally, designing features within the E2 region enhances the orthogonality of the basis matrix, contributing to improved encoding and decoding efficiency in high-throughput scenarios.

[0202] In a specific example, region D1 consists of rows 1 to x1 in region D, region D2 consists of rows x1+1 to x2 in region D, and region D3 consists of rows x2+1 to the last row in region D. The value range of x1 is 1 to 8, and the value range of x2 is 10 to 19.

[0203] For example, region D1 consists of rows 4 to 11 of the base matrix (taking M=3 and x1=8 as an example), region D2 consists of rows 12 to 14 of the base matrix (taking x2=11 as an example), and region D3 consists of rows 15 to the last row of the base matrix.

[0204] Alternatively, region D1 can be rows 5-12 of the base matrix (for example, M=4, x1=8), region D2 can be rows 13-15 of the base matrix (for example, x2=11), and region D3 can be rows 16-the last row of the base matrix.

[0205] Alternatively, region D1 can be rows 6-13 of the base matrix (for example, M=5, x1=8), region D2 can be rows 14-16 of the base matrix (for example, x2=11), and region D3 can be rows 17-the last row of the base matrix.

[0206] Alternatively, region D1 can be rows 7-14 of the base matrix (for example, M=6, x1=8), region D2 can be rows 15-17 of the base matrix (for example, x2=11), and region D3 can be rows 18 to the last row of the base matrix.

[0207] As one implementation method, a split extension sequence can also be used in the embodiments of this application. This indicates whether a row in the basis matrix satisfies a first relation with other rows. Specifically, the basis matrix corresponds to a splitting and expanding sequence. This splitting extension sequence Expanded by Q splitting sequence numbers Composition, where Q is the row number of the basis matrix, that is, the split expansion index corresponding to the p-th row of the basis matrix is... p = 1, 2, ..., Z.

[0208] Based on this method, the characteristics of the aforementioned basis matrix can also be described as partially... For rows with values ​​greater than 0, the column weight of the extended validation column must be greater than or equal to 2. All others... The corresponding extended check columns all have a column weight of 1 in the base matrix. Specifically, The value is the core row (i.e. ), or The value is a child node of the core row (i.e. or In the case of recursion (e.g., when the corresponding extended check column has a column weight greater than or equal to 2 in the base matrix), otherwise the column weight of the extended check column in the base matrix is ​​0 (even if...). ).

[0209] Most rows in region D2 have a split expansion index of 0. At least one row t in region D2 has a split expansion index greater than 0, and the corresponding split expansion index of that row is 0. Furthermore, none of these rows t are core rows (i.e., the first M rows of the base matrix). For example, consider a row in region D2 (row index r). ,and Furthermore, this bank is not a core bank.

[0210] Optionally, the basis matrix can be as follows: Figure 13 As shown, the base matrix can also include a second region (also called the E1 region, or simply E1). The column range of the E1 region is the same as that of the E2 region; that is, the columns of the E1 region include columns kb+M+1 to X1+kb of the base matrix. The row range of the E1 region is the same as that of the D1 region; that is, the rows of the E1 region include rows M+1 to X1 of the base matrix. In other words, the first row of the E1 region is the first extended check row in the base matrix. The first row of the E2 region is the row following the last row of the E1 region.

[0211] The characteristics of region E1 are explained below in conjunction with the three possible row numbers of region D1.

[0212] Example 1: The number of rows in region D1 is equal to the number of rows in the core region.

[0213] In this example, rows in region D1 correspond one-to-one with rows in the core region, and the corresponding rows satisfy the first relationship described above. Specifically, rows in region D1 are the first target rows (child nodes), and rows in the core region are the second target rows (parent nodes). Optionally, in this example, the number of rows in region D1 (X1-M) = M = P, i.e., X1 = 2M, and the row interval of region D1 is from row M+1 to row 2M of the base matrix.

[0214] In this example, the elements in the i1th row and j1st column of region E1 are both second-class elements, where kb+M<j1<kb+i1, and i1 is greater than M and less than or equal to 2M.

[0215] The above method splits each row of the core region by using rows of the D1 region, and only splits them once. This makes the hardware implementation on the encoding side relatively simple (the i-th row of the D1 region corresponds to the i-th row of the core region, making the hardware the simplest). Furthermore, since each row in the core region is split once, good decoding performance can be maintained even at low bitrates (especially in low iteration scenarios and high throughput scenarios).

[0216] In schemes based on split-expansion sequences, the above method can also be described as follows: For the permutations from 1 to M, more specifically, right Established.

[0217] Example 2: The number of rows in region D1 is less than the number of rows in the core region.

[0218] In this example, rows in region D1 correspond one-to-one with some rows in the core region, and the corresponding rows satisfy the first relationship mentioned above. Specifically, rows in region D1 are the first target rows (i.e., child nodes), and rows in the core region are the second target rows (i.e., parent nodes). Optionally, in this example, the number of rows in region D1 (X1-M) = P, where P is less than M, i.e., X1 = M+P. The row interval of region D1 is from row M+1 to row M+P of the base matrix.

[0219] In this example, the elements in the i1th row and j1st column of region E1 are both second-class elements, where kb+M<j1<kb+i1, and i1 is greater than M and less than or equal to M+P.

[0220] Each row in region D1 is split once by each row in the core region, and there are unsplit rows in the core region. In this case, the core region can support non-regular line overlap, resulting in better performance at high bitrates. Furthermore, the hardware implementation on the encoding side is relatively simple (the i-th row of region D1 corresponds to the i-th row of the core region, making the hardware the simplest).

[0221] In schemes based on split-expansion sequences, the above method can also be described as follows: For the permutation of a subset from 1 to M, more specifically, right Established.

[0222] Example 3: The number of rows in region D1 is greater than the number of rows in the core region.

[0223] In this method, some rows in region D1 (i.e., row P mentioned earlier) can correspond one-to-one with rows in the core region. The corresponding rows satisfy the first relationship mentioned above. Among them, the rows in region D1 are the first target rows, i.e., child nodes, and the rows in the core region are the second target rows, i.e., parent nodes. Optionally, in this example, the number of rows in region D1 (X1-M) is greater than P, P=M, that is, X1 is greater than 2M.

[0224] In one possible approach (hereinafter referred to as Approach 1), the preceding P row represents the first M rows of region D1. That is, the first M rows of region D1 correspond one-to-one with the M rows of the core region, and the corresponding rows satisfy the first relationship described above. Here, the row in region D1 is the first target row (i.e., the child node), and the row in the core region is the second target row (i.e., the parent node). In this example, the elements in the i1th row and j1th column of region E1 are both elements of the second type, where kb+M < j1 < kb+i1, and i1 is greater than M and less than or equal to 2M.

[0225] In schemes based on split-expansion sequences, the above method can also be described as follows: right Established.

[0226] In another possible approach (hereinafter referred to as Approach Two), rows P in the preceding text are from row M+a (a > M and < P) to row 2M+a in region D1. That is, the first a rows of region D1 and the rows of the core region do not satisfy the aforementioned first relationship. Rows M+a (a > 0 and < M) to row 2M+a correspond one-to-one with row M of the core region, and the corresponding rows satisfy the aforementioned first relationship. Here, the rows in region D1 are the first target rows (child nodes), and the rows in the core region are the second target rows (parent nodes). In this example, the elements in row i1 and column j1 of region E1 are both second-type elements, where kb+M < j1 < kb+i1, and i1 is greater than M+a and less than or equal to 2M+a. This approach can first perform an extension (i.e., extend a rows after the core rows), increasing the column weight of the extended rows (i.e., these a rows), and then perform a split.

[0227] Alternatively, rows P in the preceding text represent rows M+1 to M+f1 (f1 < p) and rows M+f2 (f2 > f1) to 2M+f2-f1 in region D1. That is, rows f2-f1 in the middle of region D1 and the rows in the core region do not satisfy the first relationship mentioned above. Rows M+1 to M+f1 and rows M+f2 (f2 > f1) to 2M+f2-f1 correspond one-to-one with rows M in the core region, and these corresponding rows satisfy the first relationship mentioned above. In this case, rows in region D1 are the first target rows (i.e., child nodes), and rows in the core region are the second target rows (i.e., parent nodes). This method can first split a portion of the rows in the core region (i.e., split row f1), then extend (i.e., extend rows f2-f1), increasing the column weight of the extended rows (i.e., row a), and then split the remaining rows in the core region.

[0228] In schemes based on split-expansion sequences, the above method can also be described as follows: right Established; right Established.

[0229] Optionally, the elements in the i4th row and j4th column of region E1 are all elements of the second type, where kb+M<j4<kb+i4, and i4 is greater than M and less than or equal to M+a.

[0230] In Example 3, each row of the core region is split using rows from region D1, and only once. This simplifies the hardware implementation on the encoding side (the i-th row of region D1 corresponds to the i-th row of the core region, making the hardware the simplest). Furthermore, since each row in the core region is split only once, good decoding performance can be maintained even at low bitrates (especially in low-iteration, high-throughput scenarios).

[0231] Optionally, in Example 3 above, the column weight of the first target column in the base matrix is ​​greater than or equal to 2; wherein, the index of the first target column in the E1 region is the same as the index of the above-mentioned row P of the base matrix in the E1 region.

[0232] For example, in Method 1 above, the P rows of the base matrix are rows M+1 to 2M of the base matrix, which correspond to the first M rows of the E1 region (i.e., indices 1 to M in the E1 region). Therefore, the first target column is the first M columns of the E1 region (i.e., indices 1 to M in the E1 region). As another example, in Method 2 above, the P rows of the base matrix are rows M+a (a is greater than M and less than P) to 2M+a of the base matrix, which correspond to rows a to a+M of the E1 region (i.e., indices a to a+M in the E1 region). Therefore, the first target column is columns a to a+M of the E1 region (i.e., indices a to a+M in the E1 region).

[0233] Optionally, the column weight of each column in the E1 area ∪ E2 area is greater than or equal to 2.

[0234] Furthermore, the basis matrix may also include Q rows, which satisfy a first relation with the aforementioned P rows and / or the first M rows of the basis matrix. Here, one row in the Q rows is the first target row in the first relation, and one row in the aforementioned P rows and / or the first M rows is the second target row in the first relation. Q equals the number of rows in the P rows and / or the first M rows. That is, if the Q rows of the basis matrix satisfy the first relation with the aforementioned P rows, then Q equals P; if the Q rows of the basis matrix satisfy the first relation with the first M rows, then Q = M; if the Q rows of the basis matrix satisfy the first relation with (the aforementioned P rows of the basis matrix ∪ the first M rows of the basis matrix), then Q = P + M, where ∪ represents the union. In one example, the Q rows may belong to the row interval of region D2.

[0235] In one possible approach, the Q row of the basis matrix can be consecutive to the P rows of the basis matrix, meaning that the first row of the Q row of the basis matrix is ​​the row following the last row of the P rows of the basis matrix, i.e., the Q row of the basis matrix is ​​the X1+1th row to the X1+Qth row of the basis matrix.

[0236] Taking the Q row of the basis matrix as an example, which represents the (M+1)th to 2Mth rows of the basis matrix, the above method can also be described as follows in the scheme based on the split expansion sequence: right Established; right It is true. If M=3, the sequence is 000 (corresponding to the 3rd row of the core region, i.e. the first 3 rows of the base matrix) 123 (corresponding to the first 3 rows of the D1 region, i.e. the above P row) 123456 (corresponding to the first 6 rows of the D2 region, i.e. the above Q row).

[0237] Taking the Q row of the basis matrix as an example, from the M+a to the 2M+a rows of the basis matrix, in the scheme based on the split expansion sequence, the above method can also be described as follows: right Established, substitution, such as If M=3 and a=2, the sequence is 000 (corresponding to the 3rd row of the core region, i.e. the first 3 rows of the base matrix) 00 (corresponding to the first 2 rows of the D1 region, i.e. the above row a) 123 (corresponding to the 3rd to 5th rows of the D1 region, i.e. the above row P) 123678 (corresponding to the first 6 rows of the D2 region, i.e. the previous row Q).

[0238] In this method, the elements in the i3rd row and j3rd column of region E2 can both be elements of the second type, where kb+M < j3 < kb+i3. The row index of the i3rd row in region E2 is the same as the row index of a row in row Q. That is, the row index of the i3rd row in region E1 and region E2 belongs to the row index of a row from row X1+1 to row X1+Q of the base matrix. In other words, the row index of row X1+1 of the base matrix ≤ the row index of the i3rd row in region E2 ≤ the row index of row X1+Q of the base matrix.

[0239] In another possible approach, the Q row of the basis matrix can also be discontinuous with the aforementioned P rows of the basis matrix. For example, the Q row of the basis matrix can also be separated from the aforementioned P rows of the basis matrix by a distance of Y rows, that is, the first row of the Q row of the basis matrix is ​​the X1+Yth row of the basis matrix.

[0240] Taking the Q row of the basis matrix as an example, which represents the (M+1)th to 2Mth rows of the basis matrix, the above method can also be described as follows in the scheme based on the split expansion sequence: right Established, right If true, such as when M=3 and Y=2, the sequence is 000 (corresponding to the 3rd row of the core region, i.e. the first 3 rows of the base matrix) 123 (corresponding to the first 3 rows of the D1 region, i.e. the above P row) 00 (corresponding to the first 2 rows of the D2 region, i.e. the above Y row) 123456 (corresponding to the 3rd to 8th rows of the D2 region, i.e. the above Q row).

[0241] Taking the Q row of the basis matrix as an example, from the M+a to the 2M+a rows of the basis matrix, in the scheme based on the split expansion sequence, the above method can also be described as follows: right Established, substitution, such as For example, if M=3 and a=2, the sequence is 000 (corresponding to the 3rd row of the core region, i.e. the first 3 rows of the base matrix) 00 (corresponding to the first 2 rows of the D1 region, i.e. the above row a) 123 (corresponding to the 3rd to 5th rows of the D1 region, i.e. the above row P) 00 (corresponding to the first 2 rows of the D2 region, i.e. the above row Y) 123456 (corresponding to the 3rd to 8th rows of the D2 region, i.e. the above row Q).

[0242] In this method, the elements in the i3rd row and j3rd column of region E2 can both be elements of the second type, where kb+M < j3 < kb+i3. The row index of the i3rd row in region E2 is the same as the row index of a row in row Q. That is, the row index of the i3rd row in region E1 and region E2 belongs to the row index of a row from row X1+1 to row X1+Q of the base matrix. In other words, the row index of row X1+1 of the base matrix ≤ the row index of the i3rd row in region E2 ≤ the row index of row X1+Q of the base matrix.

[0243] In this approach, the elements in the i2th row and j2th column of region E2 can include elements of the first type, where kb+M < j2 < kb+i2, and the row index of the i2th row is the same as the row index of one row in the aforementioned Y rows. This method increases column weighting in the split rows corresponding to the aforementioned P rows, improving the convergence speed of early decoding information and resulting in better performance.

[0244] Optionally, the column weight of the second target column in the base matrix is ​​greater than or equal to 2; wherein the index of the second target column in the E2 region is the same as the index of row Q in the E2 region. For example, if the aforementioned Q rows of the base matrix are rows X1+1 to X1+Q, that is, the aforementioned Q rows of the base matrix correspond to the first Q rows of the E2 region (i.e., the indices in the E2 region are 1 to Q), then the second target column is the first Q columns of the E2 region (i.e., the indices in the E2 region are 1 to Q). As another example, if the aforementioned Q rows of the base matrix are rows X1+Y to X1+Y+Q, that is, the aforementioned Q rows of the base matrix correspond to rows Y to Y+Q of the E2 region (i.e., the indices in the E1 region are Y to Y+Q), then the second target column is the columns Y to Y+Q of the E2 region (i.e., the indices in the E1 region are Y to Y+Q).

[0245] In addition, such as Figure 14 As shown, the basis matrix may also include at least one of the following regions: the third region (also known as the E3 region, or simply E3), the fourth region (also known as the E4 region, or simply E4), and the all-zero region (also known as the C region, or simply C).

[0246] In this region, the column interval of region E3 is from the (kb+X1+1)th column to the last column of the base matrix, and the first column of region E3 is the column following the last column of region E2. The row interval of region E3 is the same as that of region E2. Optionally, E3 can be an identity matrix.

[0247] The column range of region E4 is the same as that of region E3. The row range of region E4 is the same as that of region E1. Optionally, all elements in region E4 can be of type II.

[0248] The column intervals of region C are the union of the column intervals of regions E1 and E4. The row intervals of region C are the same as those of region A. Optionally, all elements in region C can be of the second type.

[0249] This can be understood as, in Figure 4 Based on the partitioning structure of the basis matrix shown, further... Figure 4 The E region is divided into E1, E2, E3 and E4 regions.

[0250] Regarding the row and column relationships between regions A, B, C, D, and E, please refer to the previous section on... Figure 4 The detailed description is omitted here.

[0251] The following is combined Figure 15 and Figure 16 The example shown illustrates this. Figure 15 This is an example of a base map partitioning region. Figure 16 Is with Figure 15 The corresponding basis matrix, where, due to display limitations, Figure 16 The basis matrix is ​​shown in two parts. Figure 16 (a) and Figure 16 The concatenation of (b) forms the basis matrix, which is... Figure 16 The last column of (a) is concatenated Figure 16 The first column in (b). In this example, 22 The base graph of 66 is divided into sections of size 4. Region A of size 44 Region B, size 4 Region C of size 18, with a size of 5 The D1 region of size 48 has a size of 11. The D2 region of size 48 is 3. The D3 region of size 48 The E1 region is 4, and its size is 14. The E2 region is 4, and its size is 14. The E3 region of size 14 and a size of 4 The E4 region of 14.

[0252] The following example illustrates how row and column numbers can both start from 0. Of course, in practical applications, they can also start from 1.

[0253] Figure 15 Taking region D3 as the last 3 rows of the base map, region D1 as rows 4-8 of the base map, and region D2 as rows 9-19 of the base map as an example, the corresponding splitting and expansion sequence of the base map can be [0, 0, 0, 0, 2, 0, 3, 1, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0].

[0254] The row index i and column index j corresponding to the position of the first type of element in the base graph are: i=0,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 , 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45; i=1,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46; i=2,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46; i=3,j=26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,46,47; i=4,j=3,4,7,9,10,11,14,19,21,22,23,24,27,30,31,36,38,40,43,44,45,46,48; i=5,j=37,38,39,40,41,42,43,44,45,48,49; i=6,j=1,2,4,5,9,10,11,16,18,20,23,25,27,28,29,31,32,33,36,38,40,41,42,50; i=7,j=13,21,26,28,29,30,32,34,35,36,38,39,40,41,44,45,51; i=8,j=36,39,40,41,42,43,44,51,52; i=9,j=38,41,42,43,44,50,51,53; i=10,j=28,29,31,33,35,38,41,42,43,44,54; i=11,j=13,32,33,34,35,42,43,44,51,55; i=12,j=27,44,45,46,48,50,56; i=13,j=43,45,46,48,50,57; i=14,j=31,45,48,50,51,58; i=15,j=24,25,37,46,50,51,59; i=16,j=22,23,33,34,35,36,51,60; i=17,j=18,19,20,21,37,45,50,51,61; i=18, j=15, 16, 17, 32, 42, 50, 51, 62; i=19, j=14, 40, 43, 44, 45, 46, 63; i=20, j=11, 12, 13, 33, 34, 42, 64; i=21, j=35, 36, 38, 39, 43, 44, 65; Correspondingly, Figure 16 It shows Figure 15 The corresponding basis matrix. Specifically, the correspondence between the first type of elements in the basis graph and the offset values ​​in the basis matrix is ​​as follows: i=0,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 , 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45; V i，j The values ​​are 16, 19, 47, 12, 1, 31, 5, 13, 28, 24, 10, 34, 24, 24, 36, 37, 41, 37, 45, 27, 28, 47, 2, 5, 19, 38, 35, 23, 11, 20, 24, 25, 39, 5, 19, 4, 22, 43, 40, 24, 17, 44, 22, 35, 0, 0; i=1,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,2 4, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46; V i，j The values ​​are 88, 181, 7, 55, 29, 65, 68, 183, 151, 158, 90, 107, 16, 60, 149, 155, 139, 185, 102, 82, 122, 111, 109, 2, 18, 41, 89, 129, 98, 105, 189, 106, 35, 162, 120, 168, 130, 57, 33, 47, 59, 74, 89, 160, 1, 0, 0; i=2,j=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 , 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 46; V i，j The values ​​are 172, 40, 9, 147, 54, 72, 114, 0, 47, 182, 87, 17, 44, 61, 165, 115, 15, 127, 145, 71, 78, 37, 28, 172, 180, 179, 94, 63, 115, 38, 174, 20, 115, 37, 7, 86, 165, 22, 152, 177, 176, 42, 37, 140, 0, 0; i=3, j=26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 46, 47; V i，j The values ​​are 4, 80, 179, 183, 82, 89, 81, 33, 79, 120, 74, 45, 161, 164, 100, 4, 75, 38, 132, 45, 0; i=4,j=3,4,7,9,10,11,14,19,21,22,23,24,27,30,31,36,38,40,43,44,45,46,48; V i，j The values ​​are 55, 29, 183, 158, 90, 107, 149, 82, 111, 109, 2, 18, 129, 189, 106, 130, 33, 59, 160, 1, 0, 0, 0; i=5, j=37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49; V i，j The values ​​are 19, 5, 6, 44, 47, 95, 85, 71, 31, 41, and 0, respectively. i=6,j=1,2,4,5,9,10,11,16,18,20,23,25,27,28,29,31,32,33,36,38,40,41,42,50; V i，j The values ​​are 40, 9, 54, 72, 182, 87, 17, 15, 145, 78, 172, 179, 63, 115, 38, 20, 115, 37, 165, 152, 176, 42, 37, 0; i=7, j=13, 21, 26, 28, 29, 30, 32, 34, 35, 36, 38, 39, 40, 41, 44, 45, 51; Vi，j The values ​​are 24, 47, 35, 11, 20, 24, 39, 19, 4, 22, 40, 24, 17, 44, 0, 0, 0; i=8, j=36, 39, 40, 41, 42, 43, 44, 51, 52; V i，j The values ​​are 79, 14, 42, 25, 83, 19, 19, 91, and 0, respectively. i=9, j=38, 41, 42, 43, 44, 50, 51, 53; V i，j The values ​​are 47, 94, 19, 22, 34, 59, 11, and 0, respectively. i=10, j=28, 29, 31, 33, 35, 38, 41, 42, 43, 44, 54; V i，j The values ​​are 179, 183, 89, 33, 120, 161, 4, 75, 38, 132, and 0, respectively. i=11, j=13, 32, 33, 34, 35, 42, 43, 44, 51, 55; V i，j The values ​​are 47, 22, 80, 51, 68, 79, 64, 51, 10, and 0, respectively. i=12, j=27, 44, 45, 46, 48, 50, 56; V i，j The values ​​are 19, 17, 54, 28, 67, 34, and 0 respectively. i=13, j=43, 45, 46, 48, 50, 57; V i，j The values ​​are 59, 83, 67, 44, 53, and 0 respectively. i=14, j=31, 45, 48, 50, 51, 58; V i，j The values ​​are 87, 31, 94, 90, 82, and 0, respectively. i=15, j=24, 25, 37, 46, 50, 51, 59; V i，j The values ​​are 73, 74, 51, 68, 77, 68, and 0, respectively. i=16, j=22, 23, 33, 34, 35, 36, 51, 60; V i，j The values ​​are 74, 42, 67, 78, 73, 91, 86, and 0, respectively. i=17, j=18, 19, 20, 21, 37, 45, 50, 51, 61; V i，j The values ​​are 59, 8, 14, 72, 84, 23, 36, 48, and 0, respectively. i=18, j=15, 16, 17, 32, 42, 50, 51, 62; V i，j The values ​​are 72, 91, 32, 16, 25, 61, 38, and 0, respectively. i=19, j=14, 40, 43, 44, 45, 46, 63; V i，j The values ​​are 40, 25, 21, 66, 50, 87, and 0, respectively. i=20, j=11, 12, 13, 33, 34, 42, 64; Vi ，j The values ​​are 193, 17, 76, 82, 76, 94, and 0, respectively. i=21, j=35, 36, 38, 39, 43, 44, 65; V i，j The values ​​are 62, 73, 94, 87, 91, 90, and 0, respectively. In this application, the number of information columns (kb) can be 22, 33, 44, or other values. High bitrates benefit from a large number of information columns, which can support peak bitrates without the need for puncturing, resulting in high throughput and good low-iteration performance. In this application, the maximum lift value can be 192 or 384 or other values, corresponding to 8 sets of lift values, that is, 8 sets of translation values.

[0255] In this application, the maximum code block size (CBS) can be the product of the maximum lift value and the number of information columns. For example, with a maximum lift value of 192 and a number of information columns of 44, CBS = 192. 44 = 8448.

[0256] In this application, the density of the expanded graph of the basis matrix can be less than 2^10. 384; the number of 1s in the basis matrix does not exceed 512.

[0257] In this application, the core row number of the basis matrix can be 3 or 4, that is, a 3-row double-diagonal coding matrix or a 4-row double-diagonal matrix. The main characteristic of a double-diagonal matrix is ​​3. 3, 4 A matrix of size 4 consists of one triple column and the rest are double columns, and has a coupled structure (it cannot be divided into two independent short codes by changing the order of rows and columns); in terms of translation value characteristics, the two translation values ​​of the double column are the same, and the three translation values ​​of the triple column have two identical values ​​and the third value is different from these two values. Since the properties of the code do not change when the entire row and column of the matrix are increased or decreased by a fixed value, the description here applies to all matrices after row and column transformations.

[0258] In this application, the number of rows in the base matrix can be 11 to 12, and the number of columns can be 33 to 34 (for information columns 22); or the number of rows can be 17 to 18, and the number of columns can be 50 to 51 (for information columns 33); or the number of rows can be 22 to 23, and the number of columns can be 66 to 67 (for information columns 44).

[0259] In this application, the row weight of the basis matrix can be less than or equal to 48, that is, the number of first-class elements in each row is at most 48.

[0260] In this application, the E region of the basis matrix can be a lower triangular matrix, that is, the area below the diagonal (row i, column j, i>j) includes at least one first-class elegant and vulgar.

[0261] In this application, the fixed number of punctures in the base matrix can be 0, 1, or other values. Furthermore, the fixed number of puncture bits can not exceed 192.

[0262] In this application, the basis matrix can be interleaved using row and column interleaving under high-order modulation.

[0263] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0264] When using integrated units, Figure 17 A possible exemplary block diagram of the apparatus involved in an embodiment of this application is shown. For example... Figure 17 As shown, device 1600 may include a processing unit 1602 and a communication unit 1603. The processing unit 1602 is used to control and manage the operation of device 1600. The communication unit 1603 is used to support communication between device 1600 and other devices. Optionally, the communication unit 1603, also called a transceiver unit, may include a receiving unit and / or a transmitting unit, respectively used to perform receiving and transmitting operations. Device 1600 may also include a storage unit 1601 for storing program code and / or data of device 1600.

[0265] The device 1600 can be the first communication device in the above embodiments. The processing unit 1602 can support the device 1600 in performing the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1602 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1603 can support communication between the device 1600 and other devices.

[0266] For example, in one embodiment, processing unit 1602 is used to acquire an information bit sequence; encode the information bit sequence according to a basis matrix to obtain an encoded output bit sequence; wherein, the basis matrix includes a first region E2; the columns of the first region E2 include columns kb+M+1 to X1+kb of the basis matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5, or 6; row P of the basis matrix is ​​the row that first satisfies a first relation with the first M rows of the basis matrix, and row X1 of the basis matrix is ​​the last row of row P, where P is a positive integer; wherein, one row of row P is the first target row in the first relation, and one row of the first M rows is the second target row in the first relation; the first relation is: the column index in the first column interval of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in column y, then ,or, This holds true for any value of y; the first column interval is from the 1st column to the kb+Mth column of the base matrix; the rows of the first region E2 include the (X1+1)th row to the last row of the base matrix; at least one row from the 1st row to the xth row of the first region E2 includes the first type of element, where x is an integer greater than 1; the elements included from the (X+1)th row to the last row of the first region E2 are all second type of elements, and the number of rows w from the (X+1)th row to the last row is greater than 1; wherein, the first type of element corresponds to a non-zero element, and the second type of element corresponds to a zero element.

[0267] The device 1600 can be the second communication device in the above embodiments. The processing unit 1602 can support the device 1600 in performing the operations of the second communication device in the above method embodiments. Alternatively, the processing unit 1602 mainly performs the internal operations of the second communication device in the method embodiments, and the communication unit 1603 can support communication between the device 1600 and other devices.

[0268] For example, in one embodiment, processing unit 1602 is used to acquire information to be decoded; decode the information to be decoded according to a base matrix to obtain a decoded output bit sequence; wherein, the base matrix includes a first region E2; the columns of the first region E2 include columns kb+M+1 to X1+kb of the base matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5, or 6; the P rows in the base matrix are the rows that first satisfy a first relation with the first M rows of the base matrix, the X1 row of the base matrix is ​​the last row of the P rows, and P is a positive integer; wherein, one row in the P rows is the first target row in the first relation, and one row in the first M rows is the second target row in the first relation; the first relation is: the column index in the first column interval of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in column y, then ,or, This holds true for any value of y; the first column interval is from the 1st column to the kb+Mth column of the base matrix; the rows of the first region E2 include the (X1+1)th row to the last row of the base matrix; at least one row from the 1st row to the xth row of the first region E2 includes the first type of element, where x is an integer greater than 1; the elements included from the (X+1)th row to the last row of the first region E2 are all second type of elements, and the number of rows w from the (X+1)th row to the last row is greater than 1; wherein, the first type of element corresponds to a non-zero element, and the second type of element corresponds to a zero element.

[0269] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0270] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0271] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0272] Based on the same technical concept, embodiments of this application also provide a communication device, which is used to implement the functions of the first or second communication device in the above embodiments. For example... Figure 18 As shown, the device can be a communication device or a component within a communication device (e.g., a processor, chip, or chip system). The device includes a processor 1701 and a communication interface 1702, and optionally, a memory 1703. The memory 1703 can be independent of the processor 1701 or integrated into the processor 1701; no specific limitation is made. It is understood that... Figure 18 Only the main components of the communication device are shown. Furthermore, the communication device may further include input / output devices (not shown in the figure).

[0273] The processor 1701 is used to execute the program code stored in the memory 1703, specifically to perform the actions of the aforementioned processing unit 1602, which will not be described in detail here. The communication interface 1702 is specifically used to perform the actions of the aforementioned communication unit 1603, which will not be described in detail here.

[0274] Processor 1701 can be a CPU, a digital processing unit, etc. Processor 1701 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1702 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1701 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of the present invention do not limit the specific implementation of the above-mentioned devices.

[0275] The communication interface 1702 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1702 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used for receiving user input data and outputting data to the user.

[0276] Memory 1703 is used to store programs executed by processor 1701. Memory 1703 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1703 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0277] When the communication device is powered on, the processor 1701 can read the software program in the memory 1703, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1701 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1701. The processor 1701 converts the baseband signal into data and processes the data.

[0278] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0279] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be: (1) An independent integrated circuit (IC), or chip, or chip system or subsystem; (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions; (3) Application-specific integrated circuit (ASIC), such as modem; (4) Modules that can be embedded in other devices; (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.; (6) Others, etc.

[0280] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0281] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0282] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0283] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0284] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0285] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1The steps of the function specified in one or more boxes.

Claims

1. An encoding method characterized by comprising: The method includes: Obtain the information bit sequence; The information bit sequence is encoded according to the basis matrix to obtain the encoded output bit sequence; The basis matrix includes a first region E2; The columns of the first region E2 include columns kb+M+1 to X1+kb of the base matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5 or 6. The P rows in the base matrix are the rows that first satisfy the first relation with the first M rows of the base matrix, and the X1 row of the base matrix is ​​the last row of the P rows, where P is a positive integer; wherein, one row in the P rows is the first target row in the first relation, and one row in the first M rows is the second target row in the first relation; The first relationship is as follows: the column index within the first column range of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in the column with column index y, then ,or, This holds true for any value of y; where, This is the row index of the first target row. This is the row index of the second target row. is a positive integer, t is a positive integer; the first column interval is from the 1st column to the (kb+Mth)th column of the basis matrix; The rows of the first region E2 include the (X1+1)th row to the last row of the basis matrix; At least one row from row 1 to row x in the first region E2 includes elements of the first type, where x is an integer greater than 1; The elements in the first region E2 from the (x+1)th row to the last row are all of the second type, and the number of rows w from the (x+1)th row to the last row is greater than 1; Among them, the first type of element corresponds to non-zero elements, and the second type of element corresponds to zero elements.

2. The method of claim 1, wherein, The first row set from row 1 to row x in the first region E2 all include the first type of elements, and the first row set includes xt rows, where t = 0, 1, 2 or 3. The elements in the second set of rows 1 to x in the first region E2 are all elements of the second type. The second set of rows includes the remaining rows in rows 1 to x of the first region E2 excluding the first set of rows.

3. The method of claim 2, wherein, The rows in the first region E2 whose row index is less than the first row index include the first type of elements; In the first region E2, all rows whose row index is greater than or equal to the first row index include elements of the second type.

4. The method of claim 3, wherein, The row corresponding to the first row index in the base matrix and the first extended verification row satisfy the first relationship; wherein, the row corresponding to the first row index in the base matrix is ​​the first target row in the first relationship, and the first extended verification row is the second target row in the first relationship.

5. The method of claim 3 or 4, wherein, The first row index is the last row in the base matrix that satisfies the first relationship with either the extended check row or the first M rows of the base matrix.

6. The method according to any one of claims 2 to 5, wherein, The t1-th row in the second row set and the t2-th row in the base matrix satisfy the first relationship. The t1-th row in the second row set is any row in the second row set, and the t2-th row in the base matrix is ​​an extended verification row. The row index of the t2-th row in the base matrix is ​​less than the row index of the t1-th row in the second row set. The t1-th row in the base matrix is ​​the first target row in the first relationship, and the t2-th row in the base matrix is ​​the second target row in the first relationship. t1 is a positive integer less than or equal to t, and t2 is a positive integer.

7. The method of claim 6, wherein, The t2th row in the base matrix is ​​one of the first t extended check rows in the first X1 rows of the base matrix, ordered by row weight from largest to smallest.

8. The method according to any one of claims 2 to 7, wherein, The number of the first type of elements in a row of the xt line in the first region E2 is 1, 2 or 3.

9. The method according to any one of claims 1-8, characterized in that, w can be 2, 3, 4, 5, or 6.

10. The method of any one of claims 1-9, wherein, The base matrix further includes a second region E1; the columns of the second region E1 include the kb+M+1th column to the X1+kbth column of the base matrix; the rows of the second region E1 include the M+1th row to the X1st row of the base matrix. In the second region E1, the elements in the i1th row and j1th column are all elements of the second type, where kb+M<j1<kb+i1, and i1 is greater than M and less than or equal to X1.

11. The method of any one of claims 1-10, wherein, The base matrix further includes a second region E1; the columns of the second region E1 include the kb+M+1th column to the X1+kbth column of the base matrix; the rows of the second region E1 include the M+1th row to the X1st row of the base matrix. The column weight of the first target column in the base matrix is ​​greater than or equal to 2; Wherein, the index of the first target column in the second region E1 is the same as the index of the P row in the second region E1.

12. The method of any one of claims 1-11, wherein, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. The Q row is spaced Y rows apart from the P row, where Y is a positive integer; The elements in the i2th row and j2th column of the first region E2 include the first type of elements, where kb+M<j2<kb+i2, and the row index of the i2th row is the same as the row index of a row in the Y row.

13. The method of any one of claims 1-12, wherein, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. In the first region E2, the elements in the i3th row and j3rd column are both elements of the second type, where kb+M<j3<kb+i3, and the row index of the i3th row is the same as the row index of a row in the Q row.

14. The method of any one of claims 1-13, wherein, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. The column weight of the second target column in the base matrix is ​​greater than or equal to 2; The index of the second target column in the first region E2 is the same as the index of the Q row in the first region E2.

15. A decoding method, comprising: The method includes: Obtain the information to be decoded; The information to be decoded is decoded according to the basis matrix to obtain the decoded output bit sequence; The basis matrix includes a first region E2; The columns of the first region E2 include columns kb+M+1 to X1+kb of the base matrix; X1 is greater than M, kb is the number of information columns, and M is 3, 4, 5 or 6. Row P in the base matrix is ​​the first row that satisfies a first relation with the first M rows of the base matrix, and row X1 of the base matrix is ​​the last row of row P, where P is a positive integer; wherein, one row in row P is the first target row in the first relation, and one row in the first M rows is the second target row in the first relation; the first relation is: the column index within the first column interval of the column index set corresponding to the first type of element in the first target row is properly contained in the column index set corresponding to the first type of element in the second target row, and if both the first target row and the second target row have non-zero elements in the column with column index y, then ,or, This holds true for any value of y; where, This is the row index of the first target row. This is the row index of the second target row. is a positive integer, t is a positive integer; the first column interval is from the 1st column to the (kb+Mth)th column of the basis matrix; The rows of the first region E2 include the (X1+1)th row to the last row of the base matrix; At least one row from row 1 to row x in the first region E2 includes elements of the first type, where x is an integer greater than 1; The elements in the first region E2 from the (x+1)th row to the last row are all of the second type, and the number of rows w from the (x+1)th row to the last row is greater than 1; Among them, the first type of element corresponds to non-zero elements, and the second type of element corresponds to zero elements.

16. The method of claim 15, wherein, The first row set from row 1 to row x in the first region E2 all include the first type of elements, and the first row set includes xt rows, where t = 0, 1, 2 or 3. The elements in the second set of rows 1 to x in the first region E2 are all elements of the second type. The second set of rows includes the remaining rows in rows 1 to x of the first region E2 excluding the first set of rows.

17. The method of claim 16, wherein, The rows in the first region E2 whose row index is less than the first row index include the first type of elements; In the first region E2, all rows whose row index is greater than or equal to the first row index include elements of the second type.

18. The method of claim 17, wherein, The row corresponding to the first row index in the base matrix and the first extended verification row satisfy the first relationship; wherein, the row corresponding to the first row index in the base matrix is ​​the first target row in the first relationship, and the first extended verification row is the second target row in the first relationship.

19. The method of claim 17 or 18, wherein, The first row index is the last row in the base matrix that satisfies the first relationship with either the extended check row or the first M rows of the base matrix.

20. The method of any one of claims 16-19, wherein, The t1 row in the second row set and the t2 row in the base matrix satisfy the first relationship. The t1 row in the second row set is any row in the second row set, and the t2 row in the base matrix is ​​an extended verification row. The row index of the t2 row in the base matrix is ​​less than the row index of the t1 row in the second row set. The t1 row in the base matrix is ​​the first target row in the first relationship, and the t2 row in the base matrix is ​​the second target row in the first relationship.

21. The method of claim 20, wherein, The t2th row in the base matrix is ​​one of the first t extended check rows in the first X1 rows of the base matrix, ordered by row weight from largest to smallest.

22. The method of any one of claims 16-21, wherein, The number of the first type of elements in a row of the xt line in the first region E2 is 1, 2 or 3.

23. The method of any one of claims 15-22, wherein, w can be 2, 3, 4, 5, or 6.

24. The method of any one of claims 15-23, wherein, The base matrix further includes a second region E1; the columns of the second region E1 include the kb+M+1th column to the X1+kbth column of the base matrix; the rows of the second region E1 include the M+1th row to the X1st row of the base matrix. In the second region E1, the elements in the i1th row and j1th column are all elements of the second type, where kb+M<j1<kb+i1, and i1 is greater than M and less than or equal to X1.

25. The method of any one of claims 15-24, wherein, The base matrix further includes a second region E1; the columns of the second region E1 include the kb+M+1th column to the X1+kbth column of the base matrix; the rows of the second region E1 include the M+1th row to the X1st row of the base matrix. The column weight of the first target column in the base matrix is ​​greater than or equal to 2; Wherein, the index of the first target column in the second region E1 is the same as the index of the P row in the second region E1.

26. The method according to any one of claims 15-25, characterized in that, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. The Q row is spaced Y rows apart from the P row, where Y is a positive integer; The elements in the i2th row and j2th column of the first region E2 include the first type of elements, where kb+M<j2<kb+i2, and the row index of the i2th row is the same as the row index of a row in the Y row.

27. The method according to any one of claims 15-26, characterized in that, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. In the first region E2, the elements in the i3th row and j3rd column are both elements of the second type, where kb+M<j3<kb+i3, and the row index of the i3th row is the same as the row index of a row in the Q row.

28. The method of any one of claims 15-27, wherein, The base matrix further includes Q rows, which satisfy the first relation with the P rows and / or the first M rows, wherein one row in the Q rows is the first target row in the first relation, and one row in the P rows and / or the first M rows is the second target row in the first relation; Q is equal to the number of rows in the P rows and / or the first M rows. The column weight of the second target column in the base matrix is ​​greater than or equal to 2; The index of the second target column in the first region E2 is the same as the index of the Q row in the first region E2.

29. A communications device, characterized by The device includes a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory to implement the method of any one of claims 1 to 14, or to implement the method of any one of claims 15 to 28.

30. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a communication device, implement the method of any one of claims 1 to 14, or the method of any one of claims 15 to 28.

31. A computer program product, characterised in that, It includes a computer program or instructions that, when executed by a communication device, implement the method of any one of claims 1 to 14, or the method of any one of claims 15 to 28.

32. A communication system, characterized by The communication system includes a first communication device and a second communication device; wherein the first communication device is used to perform the method as described in any one of claims 1 to 14, and the second communication device is used to perform the method as described in any one of claims 15 to 28.

33. A chip, characterized by The chip includes a processor for implementing the method of any one of claims 1 to 14, or the method of any one of claims 15 to 28.

Images