A low complexity hardware implementation method for polar code fast serial successive cancellation list decoding

Abstract

A low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes, belonging to the field of digital communication technology, solves the problem of excessive network resource overhead in existing Rate-1 and SPC node hardware decoding schemes. The method includes: sorting the log-likelihood ratio vectors of L paths by absolute value, and obtaining hard decision codewords based on the sign bit; within each clock cycle, a branch metric selection unit outputs the current minimum branch metric increment and flip mask in partial order based on a set of partial order relations constructed from the first few minimum absolute values ​​after sorting and their combinations, thereby generating two sets of candidate path metrics and candidate codewords; selecting L surviving paths through a filter; terminating the iteration when all paths are dead or a preset number of outputs is reached; finally, writing the selected minimum path metric value and corresponding codeword into memory. This invention is applicable to decoding Rate-1 nodes or SPC nodes.

Description

Technical Field

[0001] This application relates to the field of digital communication technology, and in particular to polar code decoding. Background Technology

[0002] Polar code encoding and decoding is an efficient encoding and decoding method in the field of channel coding technology. Compared with traditional linear block codes or other coding methods, polar codes have for the first time proven that they can achieve the channel capacity derived by Shannon in binary erased channels with infinite code length. [1] .

[0003] In order to reduce the delay of serial cancellation list decoding, Reference [2] proposed a simplified serial cancellation decoding algorithm. By identifying special node types such as Rate-0, Rate-1, REP and SPC in the decoding binary tree, multi-bit parallel decision is used instead of bit-by-bit traversal, which effectively reduces the number of time steps required for decoding. On this basis, Reference [3] further proposed the minimum combination set theory, proving that in the list decoding process of Rate-1 nodes, only a limited number of flip combinations need to be considered to ensure that the decoding performance is not lost, which provides an algorithmic optimization basis for subsequent hardware implementation. However, the above methods focus on the algorithmic reduction of candidate paths, and still face the problem of excessive consumption of sorting network resources in hardware implementation. Reference [4] proposed a partitioned sorting network scheme, which reduces the size of the sorter through a two-level sorting structure. However, this scheme introduces a decoding performance loss of about 0.05 to 0.1 dB in the pre-pruning process of candidate paths, and the sorter still needs more comparison and exchange units when the list size is large. It fails to fundamentally eliminate the contradiction between hardware overhead and performance loss caused by large-scale sorting networks. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problem of excessive sorting network resource overhead in existing Rate-1 and SPC node hardware decoding schemes, and to provide a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes.

[0005] The technical solution adopted by this invention to solve the above problems is: a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes, the method comprising:

[0006] Step 1: Sort the LLR vectors of the L input decoding paths in ascending order according to the absolute value of LLR and retain the original bit position index after sorting. Obtain the hard decision codeword of each path according to the LLR sign bit. Perform parity check on the hard decision codeword of each path to obtain the parity check result.

[0007] The sorted LLR absolute value sequence and position index are latched into the minimum branch metric selector, and all L-bit path liveness status registers are initialized to liveness status. When the current node type is SPC, the parity check result is used to determine the calculation rule of the branch metric increment. When the current node type is Rate-1, the parity check result is ignored.

[0008] Step 2: Based on the sorted LLR absolute value sequence, a minimum branch metric selector is used to automatically output the current minimum branch metric increment and the corresponding flip mask in each clock cycle; two sets of common values ​​are generated by the path metric calculation unit. Each candidate path metric and candidate codeword is fed into a path metric value filtering unit to select the path metric with the smallest value. Each candidate path is selected as a surviving path, and the path survival status register is updated according to the source path index corresponding to the eliminated candidate path. This iterative process is repeated until all bits in the path survival status register are zero, or the cumulative output count of the minimum branch metric selector reaches a certain number. The iteration is terminated and the process proceeds to step 3.

[0009] The set of branch metric increments maintained internally by the minimum branch metric selector consists of the sum of the first few minimum values ​​and their combinations in the sorted LLR absolute value sequence.

[0010] The branch metric increments satisfy the partial order relation based on subset inclusion and the numerical partial order relation based on LLR absolute value sorting. This partial order relation is organized into a binary tree structure: the flipped combination corresponding to the parent node is a proper subset of the flipped combination corresponding to the child node, and the branch metric increment of the parent node is not greater than the branch metric increment of the child node.

[0011] Step 3: Store the L smallest path metrics that have been finally selected into the path metric memory, update the decoding bit sequence of each path according to the corresponding candidate codeword, and trigger the partial sum update network to perform subsequent calculations to complete the decoding of the current node.

[0012] Furthermore, in step 1, for the i-th path, Its LLR vector is denoted as Nv is the length of the current node;

[0013] The sorted LLR absolute value sequence satisfies The corresponding original bit position index vector is ,in, This represents the bit position of the k-th smallest LLR absolute value in the original vector, used to determine the bits that need to be flipped when generating candidate codewords.

[0014] Further, in step 1, obtaining the hard decision codewords for each path based on the LLR sign bit, and performing parity check calculations on the hard decision codewords for each path to obtain the parity check result, specifically includes:

[0015] according to or The hard decision codewords are obtained, forming a hard decision codeword vector. This vector is simultaneously fed into subsequent parity check calculations and path metric calculations;

[0016] Parity check result by Calculate, where, Indicates the length of the simplified node. This indicates a modulo-2 addition operation.

[0017] Furthermore, the minimum branch metric selector in step 2 contains a status register, which is initially all zeros to indicate that all increments have not yet been output; a ready signal generation network is used to generate ready signals according to the parent-child partial order relationship. A node enters the ready state only when its parent node has output and it has not yet output; the minimum value is selected from all ready nodes every clock cycle and marked as output, until the cumulative number of outputs reaches L-1 and the status register is automatically reset.

[0018] Furthermore, in step 2, the iterative process specifically includes:

[0019] In each iteration, the path metric calculation unit receives the current minimum branch metric increment output by the minimum branch metric selection unit. and its flip mask Generate two sets of 2L post-selection path metrics and their candidate codewords; denoted as the first... The initial path metric for the path is The hard judgment code is ,but:

[0020] The metric for the first group of candidate paths was equal to [value] in the first iteration. The corresponding candidate codeword is In subsequent iterations, the first group of candidate path metrics reuses the L smallest candidate path metrics output by the path metric value filtering unit from the previous round. , The corresponding candidate codewords are the surviving codewords that were saved during the previous round of screening. ;

[0021] The second set of candidate path metrics is determined in each iteration by... calculate, The corresponding candidate codewords are Generate, where This is a bitwise XOR operation.

[0022] Furthermore, the path liveness status register in step 2 Initialize to all 1s at the start of decoding at each node; after each iteration, set the set of source path indices corresponding to the eliminated candidates as follows: The state is then updated to , of which Logical AND, Logical NOT; when the global liveness indicator signal is... At that time, all bits in the path liveness status register are zero, where Represents a continuous logical OR operation.

[0023] Furthermore, the path metric filtering unit in step 2 is the original pruned bitone sorting network in the serial cancellation list decoder.

[0024] Secondly, the present invention provides a low-complexity hardware implementation apparatus for fast serial cancellation list decoding of polar codes, used to execute a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes as described above, the apparatus comprising:

[0025] The LLR storage unit is used to store the L LLR vectors corresponding to the current decoding node;

[0026] The LLR sorting unit is used to sort each LLR vector in ascending order by absolute value and retain the original bit position index, and to generate hard decision codewords based on the sign bit.

[0027] The parity check unit is used to perform modulo-2 summation on the hard decision codewords of each path to obtain the parity check result.

[0028] The minimum branch metric selection unit internally maintains a set of branch metric increments consisting of the sum of the first few minimum values ​​and their combinations in the sorted LLR absolute value sequence. Each increment has a fixed partial order relationship based on subset inclusion and numerical size and is organized into a binary tree structure. Internally, it contains a status register and a ready signal generation network that correspond one-to-one with the binary tree nodes. It is used to automatically select the current minimum branch metric increment from up to 3 ready nodes in each clock cycle and output the corresponding flip mask.

[0029] The path metric calculation unit is used to receive the minimum branch metric increment and flip mask in each clock cycle, and generate a first group of L candidate path metrics and a second group of L candidate path metrics, for a total of 2L candidate path metrics and corresponding candidate codewords.

[0030] The path metric filtering unit is used to select the L paths with the smallest path metric values ​​from 2L candidate path metrics as surviving paths and output the index of the eliminated paths.

[0031] The path survival status management unit is used to maintain an L-bit path survival status register, update the survival flag of each path according to the index of the eliminated path, and output a termination signal when all paths die.

[0032] The path metric storage unit is used to store the L smallest path metrics that are finally selected.

[0033] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, it executes the steps of a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes as described above.

[0034] Fourthly, the present invention provides a computer-readable storage medium for storing a computer program that executes a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes as described above.

[0035] The beneficial effects of this invention are:

[0036] This invention replaces the traditional fully expanded sorting network by outputting the branch metric increment step by step through a minimum branch metric selector based on a partial order relation, and completes path selection with a reusable filter.

[0037] (1) Extremely low hardware resource overhead. Taking a list size L=8 and a length Nv=4 as an example, this invention only requires adding a 3-to-1 comparator and a 9-bit status register as additional hardware for Rate-1 and SPC nodes, while the candidate path selection process completely reuses the original serial cancellation list decoder. select Filter. Compared to the traditional fully parallel scheme that requires hundreds to thousands of comparison and switching units, and the partition sorting network scheme in reference [4] with about 180 comparison and switching units at L=8, the additional hardware overhead of this invention is reduced to the order of several logic gates.

[0038] (2) Decoding performance is completely lossless. The minimum branch metric selection method of the present invention is based on the minimum combination set theory in reference [3]. By utilizing the partial order relationship between candidate branch metrics, it ensures that the incremental sequence of branch metrics output step by step is completely equivalent to the full expansion scheme. No approximation or pruning is performed on the candidate path during the entire iteration process. The decoding result is strictly consistent with the traditional full expansion scheme in mathematics, and there is no loss of bit error rate performance.

[0039] (3) High iteration efficiency. Through the early termination mechanism of the path survival state management unit, combined with the minimum branch metric selection unit... With the secondary output threshold, the number of iterations required in actual decoding by this invention is much smaller than the theoretical maximum in most cases, effectively reducing dynamic power consumption and average decoding delay.

[0040] This invention is applicable to the decoding process of Rate-1 nodes or Single Parity Check (SPC) nodes. Attached Figure Description

[0041] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a channel coding and decoding system.

[0043] Figure 2 A schematic diagram of special node types and node message passing structure in fast serial cancellation list decoding.

[0044] Figure 3 This is a hardware architecture block diagram of the method in an embodiment of the present invention.

[0045] Figure 4 A schematic diagram of the binary tree partial order structure within the unit for selecting the minimum branch metric (L=8, Nv=4).

[0046] Figure 5 This is a diagram illustrating the activation status of each module under state A.

[0047] Figure 6 This is a diagram illustrating the activation status of each module under state B.

[0048] Figure 7 This is a diagram illustrating the activation status of each module under state C.

[0049] Figure 8 This is a schematic diagram of the sorted network structure of non-simplified nodes after pruning (L=4).

[0050] Figure 9 A simplified diagram of the fully parallel sorting network structure for Rate-1 and SPC nodes (L=4).

[0051] Figure 10 A schematic diagram of the sorting network structure after applying the method of this invention to the simplified nodes of Rate-1 and SPC (L=4). Detailed Implementation

[0052] The specific implementation method of this embodiment, a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes, includes:

[0053] To address the path expansion and filtering process of Rate-1 and SPC nodes in fast list decoding, a minimum branch metric selection unit based on the partial order relationship of a binary tree is designed. Utilizing the fixed partial order characteristic between candidate branch metrics, a state machine outputs the current minimum branch metric increment clock cycle, and compares it with the original state of the decoder. The filter works collaboratively in a pipelined reuse manner, thereby replacing the large-scale sorting network required in traditional fully parallel schemes. While ensuring completely lossless decoding performance, it solves the problem of balancing resource consumption and decoding performance in existing schemes with extremely low additional hardware overhead.

[0054] This embodiment provides a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes, used for decoding Rate-1 nodes or SPC nodes. The method is based on a hardware architecture including an LLR sorting unit, a parity check unit, a minimum branch metric selection unit, a path metric calculation unit, a path metric filtering unit, and a path liveness state management unit. Under the unified scheduling of the decoding control state machine, the decoding process is completed collaboratively according to the following states A to C:

[0055] State A (Initialization and LLR Sorting): The decoding control state machine sets all path liveness registers to 1, indicating that all L paths are initially in a live state. The LLR sorting unit reads the L LLR vectors corresponding to the current decoding node from the LLR memory unit. For the... Path ( Its input LLR vector is denoted as:

[0056]

[0057] Where Nv is the length of the current Rate-1 or SPC node. This unit obtains the hard decision codeword vector based on the sign bit of the LLR value:

[0058]

[0059] The resulting hard decision codeword vector is denoted as Meanwhile, the absolute values ​​of each element of the LLR vector are... Sort in ascending order to obtain the sorted sequence of absolute values:

[0060]

[0061] And record the corresponding original bit position index vector. The sorted LLR absolute value sequence and position index are fed into the minimum branch metric selection unit latch. The parity check unit performs modulo-2 summation on the hard decision codewords of each path to obtain the parity check result:

[0062]

[0063] This is for use by the minimum branch metric selection unit under the SPC node. In this state, the M bit of the internal status register of the minimum branch metric selection unit is zero, indicating that it is ready.

[0064] State B (Iterative Candidate Selection): This state is the core process of this implementation. The minimum branch metric selection unit, based on the sorted LLR absolute value sequence, automatically outputs the current minimum branch metric increment and its corresponding flip mask in each clock cycle. Internally, this unit maintains a set of branch metric increments with a fixed partial order, obtained by summing the first few minimum values ​​of the sorted LLR absolute values ​​and their combinations.

[0065] Taking a set with L=8 and Nv=4 containing 9 branch metric increments as an example, the set of branch metric increments consists of the sum of the top 4 minimum absolute values ​​of the sorted LLR and their combinations, and is defined as:

[0066]

[0067] These nine values ​​satisfy a partial order relationship based on subset inclusion and LLR absolute value sorting, and can be organized into a binary tree structure, ensuring that the total number of nodes in the ready state does not exceed three in each clock cycle. Only one at most 3-to-1 comparator is needed to select the current minimum branch metric increment. This unit uses a 9-bit status register. The ready signal generation network controls each increment to be output sequentially in a partial order until the cumulative number of outputs reaches L-1 bits.

[0068] Each branch metric increment corresponds to a specific Nv bit flip mask. Bits that are 1 indicate the bit positions that need to be flipped relative to the hard decision codeword, and bits that are 0 indicate that the original decision is maintained. In the binary tree structure, the flip combination corresponding to the parent node is a proper subset of the flip combination corresponding to its child node and there are no other flip combinations between the two. The root node is the global minimum.

[0069] In each iteration, the path metric calculation unit receives the current minimum branch metric increment output by the minimum branch metric selection unit. and its flip mask Two sets of post-selection path metrics and their candidate codewords are generated, totaling 2L. Let the first set be... The initial path metric for the path is The hard judgment code is ,but:

[0070] First group of candidates ( (Location): In the first iteration, the candidate path metric is equal to the initial path metric value, and the candidate codeword is a hard-decision codeword; in subsequent iterations, the candidate path metric reuses the L smallest candidate path metric values ​​output by the path metric value filtering unit in the previous round. ( The candidate codewords are the surviving codewords saved in the previous round.

[0071] First group of candidates ( (Location): In each iteration, the candidate path metric is obtained by adding the initial path metric value to the current minimum branch metric increment:

[0072]

[0073] The corresponding candidate codeword is generated by bitwise XORing the hard-decision codeword with the current flip mask:

[0074]

[0075] The path metric filtering unit selects the smallest L from the above 2L path metrics as the surviving path in this round, and sends the index of the eliminated path to the path survival status management unit. The path survival status management unit maintains an L-bit survival status register. The initial value is all 1s. After each iteration, let the set of indices of the eliminated paths be . The status is then updated to:

[0076]

[0077] When the global survival indicator signal When the value is zero, all paths are dead, the iteration is terminated early and the state is transitioned to C.

[0078] State C (Result Storage): The control state machine will ultimately select the... The minimum path metric value and the corresponding decoded codeword are written into the path metric value storage unit and the decoded bit storage unit, and the partial and updated network is triggered to perform subsequent calculations to complete the decoding of the current node.

[0079] In this implementation, when decoding Rate-1 and SPC nodes, the log-likelihood ratio vectors of L paths are first sorted by absolute value. Hard decision codewords are obtained based on the sign bit, and parity check results are provided to the SPC nodes. Then, an iterative candidate selection phase begins. Within each clock cycle, the branch metric selection unit, based on a set of partial order relations constructed from the first few minimum absolute values ​​after sorting and their combinations, outputs the current minimum branch metric increment and flip mask in partial order. The path metric calculation unit generates two sets of candidate path metrics and candidate codewords accordingly. The original 2L-to-L filter selects L surviving paths, and the path survival status register is updated based on the selection results. Iteration terminates when all paths die or the preset number of outputs is reached. Finally, the selected minimum path metric value and corresponding codeword are written to memory. This invention replaces the large-scale sorting network in traditional fully parallel schemes with a small number of comparators and status registers, significantly reducing hardware resource consumption without sacrificing decoding accuracy. Specific Implementation

[0080] A low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes is proposed. For the path expansion and filtering process of Rate-1 and single parity check (SPC) nodes in fast list decoding, a minimum branch metric selector based on the partial order relationship of a binary tree is designed. This method utilizes the fixed partial order characteristic between candidate branch metrics, outputting the current minimum branch metric value clock-cycle through a state machine. It works in conjunction with the decoder's original filter to complete the candidate path filtering in a pipelined multiplexing manner, thus replacing the large-scale sorting network required in traditional fully parallel schemes. While ensuring completely lossless decoding performance, it significantly reduces the number of hardware comparison and switching units and the overall implementation area.

[0081] like Figure 1 As shown, the channel encoding and decoding process is as follows: K bits of information to be transmitted are encoded using polar codes to form a codeword sequence of length N. After appropriate modulation, u is transmitted to the designated channel. The channel itself can negatively impact the transmitted signal; for example, the channel may be a binary additive white Gaussian noise channel. Polar code decoding recovers the transmitted information sequence y from the received vector y at the receiving end, thus obtaining its estimated vector. .

[0082] The fast serial cancellation list decoding algorithm for polar codes can be simply divided into two parts: message passing in the decoding binary tree and decoding by the external code decoder. The serial cancellation decoding of polar codes can itself be viewed as a process at a depth of... The message passing process involves depth-first traversal within a decoded binary tree. Assuming the communication channel is additive white Gaussian noise, the noise variance is obtained by combining the channel estimation results. The likelihood value corresponding to the received vector y can be calculated. The likelihood value is passed as a message in the binary tree through a specific calculation rule. When the fast serial cancellation list decoding algorithm traverses to the known outer code structure, the corresponding decoder needs to calculate multiple possible codewords and select the L most reliable ones as outputs, while providing the corresponding likelihood value sequence.

[0083] like Figure 2 The diagram illustrates the types of special nodes and their message passing structures in fast serial cancellation list decoding. In the decoding binary tree, based on the distribution of information bits and frozen bits within a node, four types of special nodes can be identified: Rate-0 nodes consist entirely of frozen bits, allowing direct output of all-zero codewords without path splitting; Rate-1 nodes consist entirely of information bits, requiring path splitting to generate candidate codewords; REP nodes retain only one information bit on their rightmost side, with the remaining positions being frozen bits; and SPC nodes retain only one frozen bit on their leftmost side, with the remaining positions being information bits. For Rate-1 and SPC nodes, this invention designs a dedicated low-overhead candidate filtering unit.

[0084] In terms of message passing, each decoding node receives a soft information vector from its parent node. The inputs to the left and right child nodes are calculated using the f and g functions, respectively. and and receive the corresponding hard decision results from the child nodes. and The binary output of the current node is generated after the combination operation. And return to the parent node. For the four special types of nodes mentioned above, the Fast-SSCL decoding algorithm does not need to perform recursive traversal, but instead utilizes... Direct parallel computation of candidate codewords And the corresponding path metrics.

[0085] like Figure 3 The diagram shown is a hardware architecture block diagram of the method in an embodiment of the present invention. The Rate-1, SPC node decoder includes an LLR storage unit (LLR_Mem), an LLR sorting unit (LLR_SortUnit), a parity check unit (Parity), a minimum branch metric selection unit (MinBM_selector), a path metric calculation unit (PM_Calculate), a path metric filtering unit (PM_Mux), a path liveness management unit (Path_Liveness), and a path metric storage unit (PM_Mem).

[0086] LLR sorting unit: Reads L LLR vectors corresponding to the current decoding node from the external LLR storage unit. For the l-th path (l = 0, 1, …, L-1), its input LLR vector is denoted as:

[0087]

[0088] Where Nv is the length of the current Rate-1 or SPC node. This unit performs the following two operations:

[0089] Operation 1: Hard decision codeword generation. Obtain the hard decision codeword based on the sign bit of each LLR value. :

[0090]

[0091] The resulting hard decision codeword vector is denoted as The vector is simultaneously fed into the parity check unit and the path metric calculation unit.

[0092] Operation 2: LLR Absolute Value Sort and Index Records. Sort the absolute values ​​of each element in the LLR vector. Sort in ascending order to obtain the sorted sequence of absolute values:

[0093]

[0094] Simultaneously record the original bit position index vector corresponding to each element after sorting:

[0095]

[0096] in express In the original LLR vector The bit position in the code. Taking Nv = 4 as an example, The LLR value with the smallest absolute value has the original position index as: ; The LLR value with the largest absolute value has the corresponding original position index as: The sorted LLR absolute value sequence and the corresponding position index vector It is fed into the minimum branch metric selector to determine the specific bit that needs to be flipped when generating candidate codewords based on the position index.

[0097] Parity Check Unit: Receives the hard-decision codeword vectors for each path from the LLR sorting unit and performs parity check calculations independently for each path. For the l-th path, its hard-decision codeword vector is denoted as:

[0098]

[0099] The parity check unit performs a modulo-2 summation on all bits of the vector to obtain the parity check result:

[0100]

[0101] in This indicates a modulo-2 addition operation. This indicates that the hard-decision codeword satisfies the even parity constraint. This indicates that the even parity constraint is not satisfied. The parity results of the L paths form a vector:

[0102]

[0103] This vector is fed into the minimum branch metric selection unit to determine the calculation rules for the branch metric values ​​under the SPC node. Specifically, when When the minimum branch metric selection unit is selected, the branch metric calculation method is adopted when even parity passes; when When even parity fails, the branch metric calculation method is adopted, that is, an additional penalty value corresponding to the least reliable bit is added to the penalty term.

[0104] It should be noted that when the current decoding node type is a Rate-1 node, since Rate-1 nodes do not have parity check constraints, the output of this unit does not affect subsequent processing. In this case, the decoding control state machine can... The value can be forced to zero, or the minimum branch metric selection unit can be made to directly adopt the fixed branch metric calculation rule corresponding to the Rate-1 node by using the selection signal.

[0105] The minimum branch metric selection unit is the core innovative unit of this invention. This unit receives the LLR absolute value sequence after sorting by the LLR sorting unit and the corresponding original bit position index, as well as the parity check result vector from the parity check unit. In each clock cycle, it automatically outputs the current minimum branch metric value and its corresponding flip mask, thereby replacing the large-scale sorting network required in the traditional fully parallel scheme and completing the selection of candidate paths with extremely low hardware overhead.

[0106] The minimum branch metric selection method proposed in this invention is theoretically based on the minimum combination set theory proposed in reference [3]. Reference [3] points out that in the Rate-1 node decoding process of fast serial cancellation list decoding, the generation of candidate paths can be reduced to flipping several bits of the maximum likelihood codeword, and the path metric values ​​corresponding to different flipping combinations satisfy a specific partial order relationship. Specifically, as can be seen from the part of the LLR sorting unit, for a simplified node of length Nv, the sorted LLR absolute value ascending sequence is:

[0107]

[0108] The corresponding original bit position index is For each flip combination, The increment of the corresponding candidate path metric, the likelihood path metric (i.e., the branch metric), is:

[0109]

[0110] Reference [3] proves that, under the constraint of list size L, only those “minimum combinations” that meet specific conditions can win in path filtering; the remaining combinations can be discarded in advance because their branch metric value must be greater than at least L other candidates. This theory provides a set of basic partial order constraints for the hardware implementation of this invention. Specifically, the partial order constraints include the following two levels of properties.

[0111] Property 1 (based on the partial order relation of subset inclusion): If two flipped combinations satisfy... ,Right now yes If a set is a proper subset of another set, then it must have the following:

[0112]

[0113] This is because It includes All flipped bits and at least one more flipped bit, with each bit corresponding to a branch metric increment. All are non-negative values, therefore The branch metric increment is not less than This property guarantees the existence of partial order relations, but it is not enough to uniquely determine the order between any two candidates (for example, when two flipped combinations do not contain each other, it is not possible to directly determine the relationship between their branch metric increments).

[0114] Property 2 (Numerical Partial Order Based on LLR Absolute Value Sort): Since the LLR vectors are already sorted in ascending order of absolute value, all single-bit flip branch metric increments based on the sorted index satisfy:

[0115]

[0116] Therefore, for any two single-bit flip combinations and ,like Then there must be Furthermore, for multi-bit flip combinations, the branch metric increment can be expressed as the sum of several single-bit branch metric increments, thus allowing the numerical magnitude relationship of single bits to be transferred to the multi-bit case. For example, if And the flip combination and Only in the corresponding first and the There is a difference in each bit (i.e.) Including the Bits without the first Bit, Conversely, the same conclusion can be drawn. The conclusion.

[0117] The two properties mentioned above work together to establish a complete partial order relation network among all candidate branch metrics in the minimal combination set determined by reference [3]. The partial order relation determined by the two properties mentioned above can naturally organize the set of branch metric increments into a binary tree: each node in the tree corresponds to a branch metric increment, where the parent node and child node satisfy both the proper subset inclusion relationship and the numerical size relationship, thus ensuring that the branch metric increment of any parent node is less than or equal to the branch metric increments of all its child nodes.

[0118] The connection rule between parent and child nodes is as follows: the flipped combination corresponding to the parent node is a proper subset of the flipped combination corresponding to the child node, and they satisfy a numerical order. Under this structure, the branch metric increment of the parent node is necessarily no greater than that of all its child nodes, and the root node is the global minimum.

[0119] The following section uses a typical configuration with list size L=8 and node length Nv=4 as an example to elaborate on the internal structure and working mechanism of the minimum branch metric selection unit. It should be understood that this structure can be expanded accordingly based on the actual list size and node length.

[0120] When Nv=4, for any path, its sorted LLR absolute value sequence contains 4 elements, satisfying:

[0121]

[0122] Based on the minimal combination set analysis in reference [3], at most 9 flip combinations need to be considered under this configuration, corresponding to 9 branch metric increments, denoted as follows: ,Right now:

[0123]

[0124] As can be seen above, the increments of these nine branches are not arranged in a total order, but rather satisfy a fixed partially ordered relationship. For example, according to property two, we know... According to property one, we know , , By combining these two properties, we can determine all the partial order associations among the nine branch metric increments in this example. This partial order relation can be naturally expressed as a binary tree using sets, such as... Figure 4 As shown.

[0125] Figure 4The binary tree partial order structure inside the minimum branch metric selection unit in this invention, with L=8 and Nv=4, is depicted. In this tree, each node corresponds to a branch metric increment, and the root node is... This means that only the branch metric increment corresponding to the least reliable bit is flipped, which is the global minimum. The connection between parent and child nodes follows this rule: if the flipped combination corresponding to node A is a proper subset of the flipped combination corresponding to node B, and there is no third candidate node whose flipped combination lies between the two, then A is the parent node of B, and B is the child node of A. Under this construction, the branch metric increment of the parent node must be less than or equal to the branch metric increment of the child node. For example, the root node represents flipping only the least reliable bit, and its child node represents flipping one more second least reliable bit on top of that, and so on. This construction ensures that the partial order relationship is completely preserved in the tree structure: only after any parent node outputs can its child node be output (i.e., "ready"); and nodes that are not yet ready cannot participate in the comparison because their parent node has not output. This design ensures that the total number of nodes in the "ready" state does not exceed 3 in each clock cycle. Therefore, this unit only needs to be configured with a comparator of at most 3 to 1 to complete the selection of the current minimum branch metric increment, which greatly reduces the hardware overhead of the comparison logic.

[0126] The minimum branch metric selection unit contains a 9-bit status register. Each digit corresponds to a node in the binary tree, with an initial value. Indicates the first The branch metric increment has not yet been output. The ready signal generation network calculates the ready state of each node in real time based on the partial order relationship of the binary tree. Its combinational logic can be expressed as:

[0127]

[0128] in Indicates to Take the logical NOT. This represents a logical AND operation. It can be seen that a node only enters the ready state if its parent node has already output and it itself has not yet output anything.

[0129] Each clock cycle, this unit from all Select the node with the smallest branch metric increment from the ready nodes (at most 3), and output the smallest increment. and the corresponding flip mask Simultaneously, the status register is updated on the rising edge of the clock. The bit corresponding to this node Set it to 1 to mark it as output. This process repeats until the status register is updated. The cumulative number of bits with a middle 1 has reached (by For example, after accumulating 7 branch metric increments, the control logic determines that the candidate selection for the current node has been fully completed and automatically resets. The new LLR sorting result is then latched to prepare for the processing of the next decoding node. It should be noted that only... The reason for this output is that the list size is... At most, only The minimum branch metric increment is sufficient to guarantee obtaining the optimal result. There are 10 candidate paths; continuing to output subsequent increments will not change the path selection result, so early termination can further save clock cycles and dynamic power consumption.

[0130] Through the aforementioned binary tree-guided state machine design, the minimum branch metric selection unit of this invention consumes only a 3-to-1 comparator, a 9-bit state register, and a small amount of combinational logic, replacing the large-scale sorting network composed of hundreds of comparison and exchange units in the traditional fully parallel scheme with extremely low hardware cost. This scheme fully utilizes the partial order pattern among candidate branch metrics, achieving a significant reduction in hardware area while ensuring completely lossless decoding performance. The minimum branch metric increment and flip mask output by this selection unit are directly fed into the path metric calculation unit to participate in subsequent path metric updates and candidate selection.

[0131] The path metric calculation unit receives data from the path metric storage unit. The current path metric value and the current minimum branch metric increment from the minimum branch metric selection unit. and its flip mask And the hard decision codewords from each path from the LLR sorting unit. This unit generates two sets of common codewords in parallel within each clock cycle. Each candidate path metric and its corresponding candidate codeword is used by the subsequent path metric selection unit for selection. It should be noted that the following description uses a Rate-1 node as an example to give the specific formula for candidate generation; for SPC nodes, the calculation method for candidate path metrics and candidate codewords is completely consistent with that of Rate-1 nodes, the only difference being the minimum branch metric selection unit. The value of needs to be adjusted accordingly based on the parity check unit's check result, while the addition and XOR logic inside the path metric calculation unit remains unchanged.

[0132] First group of candidates ( Location): In the first iteration, the candidate path metrics are directly derived from the current path metric value read from the path metric value storage unit, denoted as... ,Right now:

[0133]

[0134] The corresponding candidate codewords are the hard decision codewords:

[0135]

[0136] In subsequent iterations, this group of candidate path metrics directly reuses the output of the path metric filtering unit from the previous round. The smallest candidate path metric, denoted as ( Indicates the first Round iteration), that is:

[0137]

[0138] The corresponding candidate codeword is the path metric value selected by the previous round of filtering unit. The candidate codewords saved along with the minimum candidate path metric are denoted as follows: ,Right now:

[0139]

[0140] Second group of candidates ( Location): In each iteration, the metric for this group of candidate paths is obtained by adding the initial path metric to the current minimum branch metric increment, i.e.:

[0141]

[0142] The corresponding candidate codeword is generated by bitwise XORing the hard-decision codeword with the current flip mask:

[0143]

[0144] The above two sets of candidate path metrics total Each value and its corresponding candidate codeword After being processed by the register, the data is sent in parallel to the path metric filtering unit. The path metric filtering unit selects the path with the smallest path metric value. The candidate paths are selected, and their corresponding path metrics are used as the first set of candidate path metrics in the next iteration. Feedback is sent to this unit, and the corresponding candidate codeword is then used as... This is used by the first set of candidates in the next iteration. This closed-loop structure enables a compact pipeline iteration between this unit and the minimum branch metric selection unit and the path metric filtering unit, eliminating the need to read data from the path metric storage unit again in each iteration, thus significantly reducing storage access overhead.

[0145] The path metric filtering unit receives data from the path metric calculation unit. Given a set of candidate path metrics and their corresponding candidate codewords, select the path metric with the smallest value. Each candidate path is selected as a surviving path in this iteration. In traditional fully parallel Rate-1 / SPC node decoding schemes, since all candidate paths are expanded within a single clock cycle, a large-scale [structure / mechanism] is required. Large-scale filters and a The secondary filter's hardware overhead increases exponentially with the list size. The partition sorting network proposed in reference [4] reduces the size of the secondary filter to approximately [size missing] through a two-level sorting structure. However, this scheme introduces approximately [a certain amount of] [problem] during the candidate path pre-pruning process. The decoding performance loss, and its second-level sorter in While still requiring the processing of dozens of candidates, this approach fails to fundamentally eliminate the need for large-scale ranking networks. In contrast, this invention, through the pipelined cooperation of the minimum branch metric selection unit and the path metric calculation unit, strictly controls the candidate size in each iteration to a minimum. The only requirement is to reuse the existing serial offset list decoder. The filter can complete the path selection. Since the filter is a regular module of the decoder, this scheme does not introduce any additional large-scale sorting hardware, and all candidates in the iteration process are generated and compared based on accurate branch metric increments. The decoding result is completely equivalent to the traditional full expansion scheme, and there is no performance loss.

[0146] The path survival status management unit maintains a path index based on the path metric filtering unit's output elimination path index. Bit liveness status register At the start of decoding at each Rate-1 / SPC node, all bits are initialized to 0. This indicates that all paths are alive. After each iteration, let the eliminated paths be... The set of source path indices corresponding to each candidate is The state update rule is as follows:

[0147]

[0148] That is, for any path eliminated in the current round of selection, its corresponding survival flag is cleared to zero. The unit also outputs a global survival indication signal:

[0149]

[0150] in Represents a continuous logical OR operation. When (i.e., all) When the current node's iteration process ends prematurely, the control state machine immediately terminates the iteration process of the current node and jumps to the result storage state; otherwise, it continues to the next iteration.

[0151] The structure and function of each component in the hardware architecture of this invention have been described in detail above with reference to the accompanying drawings. Based on the above system architecture, the overall execution flow of the low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes provided by this invention will be further elaborated below. It should be noted that the LLR sorting unit, parity check unit, minimum branch metric selection unit, path metric calculation unit, path metric filtering unit, and path liveness state management unit in the above hardware architecture, under the unified scheduling of the decoding control state machine, collaboratively complete the decoding process of a Rate-1 node or SPC node according to states A to C. Figure 5-7 This diagram illustrates the activation status of each module in State AC. Red indicates the module is active in the current state, while black indicates it is inactive. The repeated appearance of the same module in different state diagrams indicates that the hardware unit is time-division multiplexed across different clock cycles or rounds, and does not correspond to multiple independent hardware instances.

[0152] State A: Initialization and LLR Sorting. The decoding control state machine first sets all path liveness registers to 1, indicating that all L paths are initially in a live state. The LLR sorting unit reads the L LLR vectors corresponding to the current decoding node from the LLR storage unit, sorts the elements of each vector in ascending order of absolute value and retains the original bit position index, and generates hard decision codewords for each path based on the sign bit. These hard decision codewords are latched by the parity check unit and the path metric calculation unit, respectively. The parity check unit calculates the parity check result for each path, which is used by the minimum branch metric selection unit. At this stage, the minimum branch metric selection unit latches the sorted LLR absolute value sequence and position index, and resets its internal state register to zero, completing the readiness process.

[0153] State B: Iterative Candidate Selection. This stage is the core process of this invention. In each iteration, the minimum branch metric selection unit outputs the current minimum branch metric increment and the corresponding flip mask on the rising edge of the clock; within the same clock cycle, the path metric calculation unit performs addition and XOR operations on it with the latched initial path metric and hard decision codeword to generate 2L candidate path metrics and candidate codewords, which are then sent to the path metric selection unit; the path metric selection unit selects the smallest L candidates and sends the index of the eliminated path to the path survival status management unit to update the survival status register. This iterative process continues until any of the following termination conditions are met: the path survival status management unit detects that all paths are dead ( (This occurs when) the cumulative output count of the minimum branch metric selection unit reaches L−1. At this point, the control state machine exits the iteration loop and transitions to state C.

[0154] State C: Result Storage. The control state machine writes the L smallest path metrics and their corresponding decoded codewords to the path metric storage unit and the decoded bit storage unit, and triggers the partial sum update network to perform subsequent calculations, completing the decoding of the current node. Then, the state machine releases the control signals of each unit, preparing to proceed to the next decoding node.

[0155] The following uses the number of Compare And Select Units (CASUs) to measure hardware resource consumption, denoted by symbols. This is represented as follows. For non-simplified nodes, due to the inherent partial order relationship in their internal path metrics, the corresponding sorting network can be pruned to eliminate redundant CASUs. The sorting network structure after pruning at L=4 is shown below. Figure 8 As shown, the formulas for calculating the number of CASUs before and after pruning are given below:

[0156]

[0157]

[0158] Rate-1, SPC simplified fully parallel sorting network with L=4 nodes, such as Figure 9 As shown, the formula for calculating the number of CASUs is as follows:

[0159]

[0160] When Rate-1 and SPC simplified node L=4, the pruned sorting network of this invention is as follows: Figure 10 As shown, the formula for calculating the number of CASUs before and after pruning is as follows:

[0161]

[0162]

[0163] definition The additional CASUs added for semi-parallelism (different from ordinary nodes except for whether pruning is performed in the first layer, the rest are the same, so they can be reused), when L takes 2-64, the number of CASUs for different types of sorting networks is shown in Table 1:

[0164] Table 1

[0165]

[0166] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art will understand from the foregoing description that other embodiments are conceivable within the scope of the invention described herein. The disclosure of the invention is illustrative and not restrictive, and the scope of the invention is defined by the appended claims.

[0167] The references cited in this invention are as follows:

[0168] [1] Arikan, Erdal. "Channel polarization: A method for constructingcapacity-achieving codes for symmetric binary-input memoryless channels." IEEE Transactions on information Theory 55.7 (2009): 3051-3073.

[0169] [2] Alamdar-Yazdi, Amin, and Frank R. Kschischang. "A simplifiedsuccessive-cancellation decoder for polar codes." IEEE Communications Letters15.12 (2011): 1378-1380.

[0170] [3] Zhao, Yanlong, Zhendong Yin, Zhilu Wu, and Mingdong Xu. "Minimum-combinations set-based rate-1 decoder for fast list decoding of polar codes." IEEE Communications Letters 25.10 (2021): 3185-3189.

[0171] [4] Lee, Yongje, Jae Hong Roh, Useok Lee, and Myung Hoon Sunwoo. "Alow-complexity sorting network for a fast list polar decoder." IEEE Access 11(2023): 1107-1116.

Claims

1. A low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes, characterized in that, The method includes: Step 1: Sort the LLR vectors of the L input decoding paths in ascending order according to the absolute value of LLR and retain the original bit position index after sorting. Obtain the hard decision codeword of each path according to the LLR sign bit. Perform parity check on the hard decision codeword of each path to obtain the parity check result. The sorted LLR absolute value sequence and position index are latched into the minimum branch metric selector, and all L-bit path liveness status registers are initialized to liveness status. When the current node type is SPC, the parity check result is used to determine the calculation rule of the branch metric increment. When the current node type is Rate-1, the parity check result is ignored. Step 2: Based on the sorted LLR absolute value sequence, a minimum branch metric selector is used to automatically output the current minimum branch metric increment and the corresponding flip mask in each clock cycle; two sets of common values ​​are generated by the path metric calculation unit. Each candidate path metric and candidate codeword is fed into a path metric value filtering unit to select the path metric with the smallest value. Each candidate path is selected as a surviving path, and the path survival status register is updated according to the source path index corresponding to the eliminated candidate path. This iterative process is repeated until all bits in the path survival status register are zero, or the cumulative output count of the minimum branch metric selector reaches a certain number. The iteration is terminated and the process proceeds to step 3. The set of branch metric increments maintained internally by the minimum branch metric selector consists of the sum of the first few minimum values ​​and their combinations in the sorted LLR absolute value sequence. The branch metric increments satisfy the partial order relation based on subset inclusion and the numerical partial order relation based on LLR absolute value sorting. This partial order relation is organized into a binary tree structure: the flipped combination corresponding to the parent node is a proper subset of the flipped combination corresponding to the child node, and the branch metric increment of the parent node is not greater than the branch metric increment of the child node. Step 3: Store the L smallest path metrics that have been finally selected into the path metric memory, update the decoding bit sequence of each path according to the corresponding candidate codeword, and trigger the partial sum update network to perform subsequent calculations to complete the decoding of the current node.

2. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 1, characterized in that: In step 1, for the i-th path, Its LLR vector is denoted as Nv is the length of the current node; The sorted LLR absolute value sequence satisfies The corresponding original bit position index vector is ,in, This represents the bit position of the k-th smallest LLR absolute value in the original vector, used to determine the bits that need to be flipped when generating candidate codewords.

3. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 2, characterized in that: In step 1, obtaining the hard decision codewords for each path based on the LLR sign bit, and performing parity check calculations on the hard decision codewords for each path to obtain the parity check result, specifically includes: according to or The hard decision codewords are obtained, forming a hard decision codeword vector. This vector is simultaneously fed into subsequent parity check calculations and path metric calculations; Parity check result by Calculate, where, Indicates the length of the simplified node. This indicates a modulo-2 addition operation.

4. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 1, characterized in that: The minimum branch metric selector in step 2 contains a status register. Initially, all zeros indicate that all increments have not yet been output. A ready signal generation network is used to generate ready signals according to the parent-child partial order relationship. A node enters the ready state only when its parent node has output and it has not yet output. Every clock cycle, the minimum value is selected from all ready nodes and marked as output. The status register is automatically reset after the cumulative number of outputs reaches L-1.

5. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 1, characterized in that: Step 2, the iterative process specifically includes: In each iteration, the path metric calculation unit receives the current minimum branch metric increment output by the minimum branch metric selection unit. and its flip mask Generate two sets of 2L post-selection path metrics and their candidate codewords; denoted as the first... The initial path metric for the path is The hard judgment code is ,but: The metric for the first group of candidate paths was equal to [value] in the first iteration. The corresponding candidate codeword is In subsequent iterations, the first group of candidate path metrics reuses the L smallest candidate path metrics output by the path metric value filtering unit from the previous round. , The corresponding candidate codewords are the surviving codewords that were saved during the previous round of screening. ; The second set of candidate path metrics is determined in each iteration by... calculate, The corresponding candidate codewords are Generate, where This is a bitwise XOR operation.

6. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 1, characterized in that: Path liveness status register in step 2 Initialize to all 1s at the start of decoding at each node; after each iteration, set the set of source path indices corresponding to the eliminated candidates as follows: The state is then updated to , of which Logical AND, Logical NOT; when the global liveness indicator signal is... At that time, all bits in the path liveness status register are zero, where Represents a continuous logical OR operation.

7. The low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to claim 1, characterized in that: The path metric filtering unit in step 2 is the original pruned bitone sorting network in the serial cancellation list decoder.

8. A low-complexity hardware implementation apparatus for fast serial cancellation list decoding of polar codes, used to execute the method of any one of claims 1 to 7, characterized in that, The device includes: The LLR storage unit is used to store the L LLR vectors corresponding to the current decoding node; The LLR sorting unit is used to sort each LLR vector in ascending order by absolute value and retain the original bit position index, and to generate hard decision codewords based on the sign bit. The parity check unit is used to perform modulo-2 summation on the hard decision codewords of each path to obtain the parity check result. The minimum branch metric selection unit internally maintains a set of branch metric increments consisting of the sum of the first few minimum values ​​and their combinations in the sorted LLR absolute value sequence. Each increment has a fixed partial order relationship based on subset inclusion and numerical size and is organized into a binary tree structure. Internally, it contains a status register and a ready signal generation network that correspond one-to-one with the binary tree nodes. It is used to automatically select the current minimum branch metric increment from up to 3 ready nodes in each clock cycle and output the corresponding flip mask. The path metric calculation unit is used to receive the minimum branch metric increment and flip mask in each clock cycle, and generate a first group of L candidate path metrics and a second group of L candidate path metrics, for a total of 2L candidate path metrics and corresponding candidate codewords. The path metric filtering unit is used to select the L paths with the smallest path metric values ​​from 2L candidate path metrics as surviving paths and output the index of the eliminated paths. The path survival status management unit is used to maintain an L-bit path survival status register, update the survival flag of each path according to the index of the eliminated path, and output a termination signal when all paths die. The path metric storage unit is used to store the L smallest path metrics that are finally selected.

9. A computer device, characterized in that: The method includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, it performs the steps of a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The storage medium is used to store a computer program that executes a low-complexity hardware implementation method for fast serial cancellation list decoding of polar codes according to any one of claims 1-7.

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