A method and device for parallel processing of viterbi for multi-core processors

Abstract

This application provides a Viterbi parallel processing method and apparatus for multi-core processors, applicable to the field of communication technology. The method includes: determining the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding; dividing the information sequence into multiple sub-code blocks according to the partitioning window and overlap length; each sub-code block including an effective decoding region and an overlap region that overlaps with adjacent sub-code blocks; allocating the multiple sub-code blocks to multiple processing units of a multi-core processor for parallel Viterbi decoding processing to obtain the local decoding results of each sub-code block; extracting the bit sequence of the corresponding effective decoding region from the local decoding results of each sub-code block; and concatenating the bit sequences of each sub-code block into the Viterbi decoding result of the information sequence according to their position order in the information sequence, which can solve the problem of high decoding latency in traditional Viterbi decoding methods.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a Viterbi parallel processing method and apparatus for multi-core processors. Background Technology

[0002] Viterbi decoding is a commonly used sequence decoding method, widely applied in communication decoding and other scenarios. In related technologies, Viterbi decoding typically performs serial processing according to the order of the information sequence, that is, sequentially completing the path metric calculation, surviving path selection, and backtracking decoding processes.

[0003] As the volume of communication data and the requirements for processing speed increase, the length of the information sequence to be decoded continues to increase. Serial decoding requires processing segment by segment, resulting in high overall decoding latency, which makes it difficult to meet the real-time processing requirements in high-speed communication scenarios.

[0004] Therefore, there is an urgent need for a Viterbi parallel processing method and device for multi-core processors to solve the problem of high decoding latency in traditional Viterbi decoding methods. Summary of the Invention

[0005] The purpose of this application is to provide a Viterbi parallel processing method and apparatus for multi-core processors to solve the problem of high decoding latency in traditional Viterbi decoding methods.

[0006] In a first aspect, embodiments of this application provide a Viterbi parallel processing method for multi-core processors. The method includes: determining the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding; dividing the information sequence into multiple sub-code blocks according to the partitioning window and the overlap length; each sub-code block including an effective decoding region and an overlap region overlapping with adjacent sub-code blocks; allocating the multiple sub-code blocks to multiple processing units of the multi-core processor for parallel Viterbi decoding processing to obtain local decoding results for each sub-code block; extracting the bit sequence of the corresponding effective decoding region from the local decoding results of each sub-code block; and concatenating the bit sequences of each sub-code block into a Viterbi decoding result of the information sequence according to the positional order of each sub-code block in the information sequence.

[0007] The Viterbi decoding method provided in this application determines the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding. Then, according to the partitioning window and overlap length, the information sequence is divided into multiple sub-code blocks. Furthermore, these multiple sub-code blocks are distributed to multiple processing units of a multi-core processor for parallel compilation, reducing the overhead required by traditional serial decoding and improving decoding throughput and processing efficiency. Finally, by extracting the effective decoding bit sequences of each sub-code block and concatenating them in their original order, duplicate output of overlapping areas can be avoided, ensuring the continuity and accuracy of the decoding results.

[0008] One possible implementation involves determining the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding. This includes: determining the overlap length between adjacent partitioning windows based on the backtracking depth; and determining the partitioning length of the partitioning window based on a preset effective decoding length and the overlap length.

[0009] One possible implementation involves extracting the bit sequence of the corresponding effective decoding region from the local decoding results of each sub-code block. This includes: for any sub-code block, determining the effective output range of the sub-code block in the local decoding results based on the position of the effective decoding region within that sub-code block; and extracting the decoded bits corresponding to the effective output range from the local decoding results to obtain the bit sequence of the corresponding effective decoding region of the sub-code block.

[0010] One possible implementation involves distributing multiple sub-code blocks to multiple processing units of a multi-core processor for parallel Viterbi decoding to obtain the local decoding results of each sub-code block. This includes: obtaining the position identifier corresponding to each sub-code block; writing each sub-code block into the decoding buffer of its corresponding processing unit based on the position identifier; controlling multiple processing units to perform Viterbi decoding on the sub-code blocks in their respective decoding buffers to obtain the decoded data output by each processing unit; and associating the decoded data output by each processing unit with the position identifier of the corresponding sub-code block to obtain the local decoding result of each sub-code block.

[0011] One possible implementation involves controlling multiple processing units to perform Viterbi decoding on sub-code blocks in their respective decoding buffers. This includes: for any given sub-code block, calculating a path metric based on the information sequence within that sub-code block to obtain the path metric value corresponding to each state in the information sequence; determining the surviving path for each state based on the path metric value; after determining the surviving paths for all states in the sub-code block, performing backtracking processing on the surviving paths based on the backtracking depth to obtain the backtracking processing result for that sub-code block; and generating the local decoding result corresponding to that sub-code block based on the backtracking processing result.

[0012] One possible implementation involves concatenating the bit sequences of each sub-code block according to their position order in the information sequence to obtain the Viterbi decoding result of the information sequence. This includes: obtaining the position identifier corresponding to each sub-code block; determining the order of each sub-code block in the information sequence based on its position identifier; and concatenating the bit sequences corresponding to each sub-code block in the order to obtain the Viterbi decoding result of the information sequence.

[0013] Secondly, embodiments of this application provide a Viterbi parallel processing device for multi-core processors, the device comprising: a determination module, a partitioning module, a processing module, and a splicing module.

[0014] The determining module is used to determine the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding.

[0015] The partitioning module is used to divide the information sequence into multiple sub-code blocks according to the partitioning window and overlap length. Each sub-code block includes a valid decoding area and an overlap area that overlaps with adjacent sub-code blocks.

[0016] The processing module is used to distribute multiple sub-code blocks to multiple processing units of a multi-core processor for parallel Viterbi decoding processing, and obtain the local decoding results of each sub-code block.

[0017] The extraction module is used to extract the bit sequence of the corresponding valid decoding region from the local decoding results of each sub-code block.

[0018] The splicing module is used to splice the bit sequences of each sub-code block into the Viterbi decoding result of the information sequence according to the position order of each sub-code block in the information sequence.

[0019] Thirdly, embodiments of this application provide a Viterbi parallel processing device for multi-core processors. This device has the functionality to implement the Viterbi parallel processing method for multi-core processors as described in the first aspect or any possible implementation thereof. This functionality can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functionality.

[0020] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a computer, enable the computer to perform the Viterbi parallel processing method for multi-core processors described in the first aspect or any possible implementation thereof.

[0021] Fifthly, embodiments of this application provide a computer program product containing instructions that, when run on a computer, enable the computer to execute the Viterbi parallel processing method for multi-core processors described in the first aspect or any possible implementation thereof.

[0022] The technical effects of any of the design methods in aspects two through five can be found in aspect one or in different possible implementations of aspect one, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a conventional Viterbi decoding method provided in an embodiment of this application; Figure 2 A schematic diagram of the structure of a communication device provided in an embodiment of this application; Figure 3 A schematic diagram of the structure of a communication system provided in an embodiment of this application; Figure 4 A flowchart of a Viterbi parallel processing method for multi-core processors provided in this application embodiment; Figure 5 A specific example diagram of a Viterbi parallel processing method for multi-core processors provided in this application embodiment; Figure 6 A specific example diagram of a Viterbi parallel processing method for multi-core processors provided in this application embodiment; Figure 7 A schematic diagram of a Viterbi parallel processing device for multi-core processors provided in this application embodiment; Figure 8 Another system architecture diagram of a Viterbi parallel processing system for multi-core processors provided in this application embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] Traditional Viterbi decoding is a serial decoding process, such as... Figure 1 As shown, the process first initializes the Viterbi decoder, then sequentially inputs the log-likelihood ratio (LLR) to calculate the metric for each branch, updates the metric, selects the surviving path for the current state, and continuously increments to complete all LLR processing. Finally, backtracking decoding is performed based on the path memory, and the information bit sequence is output in reverse according to the transitions in the backtracking process, thus completing the decoding process.

[0028] However, as the amount of communication data and the processing rate requirements increase, the length of the information sequence to be decoded continues to increase. Serial decoding requires processing segment by segment, resulting in high overall decoding latency, which makes it difficult to meet the real-time processing requirements in high-speed communication scenarios.

[0029] Based on this, embodiments of this application provide a Viterbi parallel processing method for multi-core processors. The method includes: determining the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding; dividing the information sequence into multiple sub-code blocks according to the partitioning window and the overlap length; each sub-code block including an effective decoding region and an overlap region that overlaps with adjacent sub-code blocks; allocating the multiple sub-code blocks to multiple processing units of the multi-core processor for parallel Viterbi decoding processing to obtain the local decoding results of each sub-code block; extracting the bit sequence of the corresponding effective decoding region from the local decoding results of each sub-code block; and concatenating the bit sequences of each sub-code block into the Viterbi decoding result of the information sequence according to the positional order of each sub-code block in the information sequence.

[0030] The Viterbi decoding method provided in this application determines the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding. Then, according to the partitioning window and overlap length, the information sequence is divided into multiple sub-code blocks. Furthermore, these multiple sub-code blocks are distributed to multiple processing units of a multi-core processor for parallel compilation, reducing the overhead required by traditional serial decoding and improving decoding throughput and processing efficiency. Finally, by extracting the effective decoding bit sequences of each sub-code block and concatenating them in their original order, duplicate output of overlapping areas can be avoided, ensuring the continuity and accuracy of the decoding results.

[0031] The methods provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0032] On the one hand, embodiments of this application provide a communication device. For example... Figure 2 As shown, the communication device 20 includes a Viterbi decoder 200. The Viterbi decoder 200 can be installed in the channel decoding module of the communication device 20. After completing signal synchronization, demodulation, and soft decision calculation, the receiving end inputs the obtained information sequence into the Viterbi decoder 200. The Viterbi decoder 200 includes: an input unit 201, a sub-code block division unit 202, a task scheduling unit 203, multiple Viterbi decoding units 204, and an output unit 205.

[0033] The input unit 201 is used to receive and buffer the information sequence to be decoded input by the communication device. This information sequence can be a soft decision information sequence obtained after demodulation by the receiving end 20, such as a sequence composed of multiple log-likelihood ratios (LLRs). The input buffer unit 210 can store each soft decision information in the receiving order and record the position of each soft decision information in the information sequence.

[0034] The sub-code block partitioning unit 202 is used to determine the partitioning window of the information sequence and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding, and to read soft decision information within the corresponding position range from the input buffer unit 201 according to the partitioning window and the overlap length to form multiple sub-code blocks. Each sub-code block includes an effective decoding area and an overlap area that overlaps with adjacent sub-code blocks. The overlap area is used to provide historical path information for backtracking decoding at the boundary of the sub-code block.

[0035] The task scheduling unit 203 is used to allocate multiple sub-code blocks to multiple Viterbi decoding units 204, so that the multiple Viterbi decoding units 204 can perform parallel decoding on different sub-code blocks respectively. The task scheduling unit 203 can also configure a corresponding position identifier for each sub-code block so that the decoding results can be organized in the order of the original information sequence.

[0036] There are multiple Viterbi decoding units 204. Each Viterbi decoding unit 204 performs Viterbi decoding processing on the received sub-code block, generates and outputs the local decoding result corresponding to the sub-code block. During this process, multiple Viterbi decoding units 204 can perform the Viterbi processing on the received sub-code block simultaneously, and the individual Viterbi decoding units 204 do not affect each other.

[0037] Output unit 205 is used to receive the local decoding results output by multiple Viterbi decoding units 204, and extract the sequence of valid decoding regions from the local decoding results according to the position of the valid decoding region corresponding to each sub-code block. Then, according to the position identifier of each sub-code block, the bit sequences of multiple valid decoding regions are concatenated in the order of the information sequence to obtain the Viterbi decoding result corresponding to the information sequence received by communication device 200.

[0038] It should be noted that the above Figure 2 The communication device 20 and the Viterbi decoder 200 shown are merely illustrative examples of the application scenarios of this application and are not intended to limit the application scenarios of this application.

[0039] On the one hand, embodiments of this application provide a communication system. For example... Figure 3 As shown, the communication system 300 may include a transmitting device 301 and a receiving device 302. The transmitting device 301 and the receiving device 302 are connected via a communication channel. The receiving device 302 may be the communication device 20 in the above embodiments, or it may be a device including the Viterbi decoder 200 in the above embodiments.

[0040] The transmitting device 301 performs channel coding on the original bit sequence to be transmitted to obtain a coded bit sequence, modulates the coded bit sequence, and then transmits the modulated communication signal to the receiving device 302 through a communication channel. The channel coding process may include convolutional coding, and the communication channel may include a wireless channel, a wired channel, a satellite communication channel, or other communication channels capable of transmitting modulated signals. For example, the transmitting device 301 may be a base station, a terminal device, a satellite communication transmitter, a broadcast transmitter, or other device with channel coding and signal transmission functions. This application does not limit the specific type of the transmitting device 301.

[0041] The receiving device 302 receives the communication signal sent by the transmitting device 301, and performs signal synchronization, demodulation, and calculation on the received communication signal to obtain the information sequence to be decoded. Then, the Viterbi decoding processor 200 provided in this embodiment processes the information sequence to generate a Viterbi decoding result corresponding to the information sequence. The receiving device 302 can be a terminal device, a base station, a satellite communication receiving device, a vehicle-mounted communication device, an IoT communication device, or other devices with signal reception and channel decoding functions. This application does not limit the specific type of the receiving device 302.

[0042] It should be noted that the above Figure 3 The communication system shown is merely an example illustrating the application scenario of the solution in this application and is not intended to limit the application scenario of the solution in this application. In some embodiments, the communication system may also include relay devices, gateway devices, core network devices, signal processing devices, or other communication processing nodes; as long as the receiving side uses the Viterbi decoder 200 described above for decoding processing, the technical solution provided in the embodiments of this application can be applied.

[0043] On one hand, embodiments of this application provide a Viterbi parallel processing method for multi-core processors, which can be implemented by... Figure 2 The communication device 20 shown is used for execution. This Viterbi parallel processing method for multi-core processors can also be implemented by... Figure 3 The communication system shown is executed. (As...) Figure 4 As shown, the method may include the following steps.

[0044] S401, based on the backtracking depth of Viterbi decoding, determine the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows.

[0045] The backtracking depth is used to represent the length of the historical path that needs to be backtracked to determine the decoded bits during the Viterbi decoding process.

[0046] One possible implementation involves determining the overlap length between adjacent partition windows based on the backtracking depth. The partition length of the partition window is then determined based on a preset effective decoding length and the overlap length.

[0047] Specifically, the backtracking depth used for surviving path backtracking during Viterbi decoding is obtained. Based on this backtracking depth, the overlap length between adjacent partition windows is determined so that the information repeatedly contained between adjacent partition windows can meet the requirements of backtracking decoding at the sub-block boundaries for historical path information.

[0048] For example, the overlap length between adjacent partitioned windows can be denoted as I, and the backtracking depth of Viterbi decoding can be denoted as D. The overlap length I is determined based on the backtracking depth D. Setting the overlap length I to be the same as the backtracking depth D, i.e., I=D, ensures that the overlap information length between adjacent partitioned windows covers the backtracking range of Viterbi decoding. This backtracking depth D can be determined based on the constraint length K of the convolutional code. Here, K represents the constraint length of the convolutional code, and K-1 represents the memory length during the convolutional encoding process. The backtracking depth D can be determined based on the reliability requirements of decoding and the computational resources available in the current communication scenario.

[0049] For example, in scenarios with low signal-to-noise ratio or high bit error rate requirements, the backtracking depth D can be set to 10 times the length of the convolutional code memory, and the overlap length I between adjacent partition windows can be set to the same as the backtracking depth D. In this scenario, I=D=10(K-1).

[0050] In scenarios where computational resources are limited, the backtracking depth D can be set to 5 times the length of the convolutional code memory, and the overlap length I between adjacent partition windows can be set to the same as the backtracking depth D. In this scenario, I=D=5(K-1).

[0051] After determining the overlap length between adjacent partitioned windows, the partition length of the partitioned window can be determined based on the preset effective decoding length and the overlap length. The preset effective decoding length represents the length of the effective decoding region that ultimately participates in the splicing output in each sub-code block, and the overlap length represents the length of information repeatedly included between adjacent partitioned windows.

[0052] For example, the preset effective decoding length can be denoted as G, and the overlap length can be denoted as I. Then, the partition length of the window can be determined as L = G + I. Here, G >> I, to avoid excessive overlap and reduced parallel decoding efficiency. Each partition window can include an effective decoding region of length G and an overlap region of length I. In two adjacent partition windows, the last I pieces of information of the preceding partition window are the same as the first I pieces of information of the following partition window.

[0053] Taking a convolutional code with a convolutional code rate of 1 / 2, generator polynomials of 133 and 171, and constraint length of K=7 as an example, the receiving device is operating in a low signal-to-noise ratio (SNR) scenario. After completing signal synchronization, demodulation, and soft-decision calculation, the receiving device inputs the information sequence, i.e., the soft-value LLR sequence. Where N represents the length of the information sequence before decoding. This represents the (N-1)th soft decision information to be decoded.

[0054] Since its constraint length K=7, the memory length of the convolutional sequence in the convolutional coding process can be determined to be K-1=6. Furthermore, the backtracking depth D of Viterbi decoding and the overlap length I between adjacent partition windows can be determined to be I=D=10(K-1)=60. That is to say, adjacent partition windows can repeatedly contain 60 soft-decision information.

[0055] S402 divides the information sequence into multiple sub-code blocks according to the partition window and overlap length.

[0056] The sub-code block includes: the effective decoding area, and the overlapping area that overlaps with the adjacent sub-code block.

[0057] Specifically, based on the segmentation length of the segmentation window, multiple segments are sequentially extracted from the information sequence to be decoded, and each segment is treated as a sub-code block. Adjacent segments retain the same information sequence segment according to the overlap length, ensuring that the tail of the preceding sub-code block overlaps with the head of the following sub-code block within the corresponding length range.

[0058] For example, the communication device can use a window length of L=G+I as a sliding step to sequentially extract partition windows of length L=G+I from the information sequence to be decoded, thereby obtaining multiple sub-code blocks. That is, the first sub-code block may include the 0th to the G+I-1th soft decision information in the information sequence, the second sub-code block may include the Lth to the 2G+I-1th soft decision information in the information sequence, and so on.

[0059] For example, the information sequence to be decoded is After partitioning, the m-th sub-code block can contain the following: .

[0060] At this point, the I LLRs at the tail of the (n-2)th sub-block can be used as the I LLRs at the head of the (n-1)th sub-block. Thus, the input sequence y is divided into multiple sub-blocks that overlap in time, each sub-block including an effective decoding region for output and an overlapping region for supporting backtracking decoding at the boundary.

[0061] Furthermore, when the number of LLRs corresponding to the last sub-code block is less than a complete partition window, the communication device can form the last sub-code block based on the remaining LLRs; or, the last sub-code block can be padded to ensure that the last sub-code block meets the corresponding partition window length. This application embodiment does not specifically limit this.

[0062] S403 distributes multiple sub-code blocks to multiple processing units of a multi-core processor for parallel Viterbi decoding processing, obtaining the local decoding results of each sub-code block.

[0063] One possible implementation involves obtaining the position identifiers corresponding to each sub-code block. Based on these position identifiers, each sub-code block is written into the decoding buffer of its corresponding processing unit. Multiple processing units are then controlled to perform Viterbi decoding on the sub-code blocks in their respective decoding buffers, yielding the decoded data output by each unit. The decoded data output by each processing unit is then associated with the position identifiers of the corresponding sub-code blocks to obtain the local decoding results for each sub-code block.

[0064] Specifically, after obtaining multiple sub-code blocks, a corresponding position identifier is configured for each sub-code block. This position identifier can be used to indicate the order of the corresponding sub-code block in the original information sequence. For example, the position identifiers of each sub-code block can be recorded as 0, 1, ..., n-1 according to their order in the information sequence.

[0065] Based on the position identifiers of each sub-code block, multiple sub-code blocks are written into the decoding buffer of the corresponding processing unit in the multi-core processor. Each processing unit can act as an independent Viterbi decoding thread, performing Viterbi decoding on the sub-code blocks written into its decoding buffer. Since each sub-code block carries an overlapping area for boundary backtracking, multiple processing units can perform parallel decoding on different sub-code blocks to obtain the local decoding results corresponding to each sub-code block.

[0066] For example, for any sub-code block, the sub-code block can be input into the decoding buffer of the corresponding processing unit, and the soft value LLR sequence in the sub-code block can be denoted as described above. Correspondingly, the encoder state set corresponding to this processing unit can be denoted as... Where M represents the total number of states in the processing unit. For a convolutional code with a constraint length of K, the total number of states is... The actual index of the grid diagram can be denoted as... .

[0067] One possible implementation involves controlling multiple processing units to perform Viterbi decoding on sub-code blocks in their respective decoding buffers. This may include: for any sub-code block, calculating a path metric based on the information sequence within that sub-code block to obtain the path metric value corresponding to each state in the information sequence; determining the surviving path for each state based on the path metric value; after determining the surviving paths for all states in the sub-code block, performing backtracking processing on the surviving paths based on the backtracking depth to obtain the backtracking processing result for the sub-code block; and generating the local decoding result corresponding to the sub-code block based on the backtracking processing result.

[0068] Specifically, when performing Viterbi decoding on the sub-code block, the processing unit can first initialize the path metric for all states corresponding to the thread, and then store the received LLR sequence in the input buffer in order.

[0069] The processing unit inputs the LLR soft value corresponding to the current time step and obtains the current state. Transition to the target state Theoretically, this corresponds to the number of encoded bits. For a 1 / 2 code rate convolutional code, each state transition can correspond to a 2-bit encoded output. At this time, the processing unit can read the 2-bit LLR soft value corresponding to the current time step and determine the theoretical 2-bit encoded output corresponding to the state transition.

[0070] The processing unit then calculates the state based on the LLR soft value corresponding to the current time step and the theoretical encoded output. Transition to state The corresponding transition metric. This transition metric can be used to represent the degree of difference between the received LLR soft value and the theoretical coded output. For example, the transition metric can be determined based on the Euclidean distance between the received LLR soft value and the theoretical coded output; alternatively, it can be determined using the XOR calculation method in the disclosure document. The transition metric for this state transition can be denoted as: .Should This indicates that at time step t, from state Transition to state Branching metric.

[0071] At time t+1, the processing unit checks all states that can be changed from the previous state. Transition to state The path is determined, and candidate path metrics are calculated based on the path metric from the previous time step and the transition metric from the current time step. The candidate path metric can be expressed as:

[0072] in, Represents the state at time t The corresponding path metric.

[0073] The processing unit processes all arriving target states. Select the minimum value from the candidate path metrics and assign this minimum value to the target state at time t+1. Corresponding path metrics Simultaneously, the processing unit records the predecessor state corresponding to this minimum path metric. .

[0074] After updating the path metrics and recording the predecessor state for each state at time t+1, the processing unit enters the next time step and continues to execute the above steps of transition metric calculation, candidate path metric calculation, surviving path selection and predecessor state recording until all LLRs in the sub-code block are processed.

[0075] After completing the forward scan of all time steps, the processing unit can find the final state with the smallest path metric among the states corresponding to the final time t=L-1. The processing unit moves from this final state. Starting from the beginning, the optimal path is reconstructed in reverse order based on the predecessor state information saved during the forward scan, and the decoded bit sequence is output sequentially according to the state transition relationship during the backtracking process to obtain the local decoding result corresponding to the sub-code block. The local decoding result corresponding to the sub-code block can be denoted as... .

[0076] It should be noted that other processing units can perform the same decoding process in parallel on other sub-code blocks and output the local decoding results of the corresponding sub-code blocks respectively. This application will not elaborate on this.

[0077] After multiple processing units output local decoding results, the communication device can associate the decoding data output by each processing unit with the position identifier of the corresponding sub-code block to obtain the local decoding result of each sub-code block.

[0078] S404 extracts the bit sequence of the corresponding effective decoding region from the local decoding results of each sub-code block.

[0079] One possible implementation involves determining the effective output range of any sub-code block based on the location of the effective decoding region within that sub-code block, using the local decoding result. The decoded bits corresponding to the effective output range are then extracted from the local decoding result to obtain the bit sequence of the effective decoding region corresponding to that sub-code block.

[0080] Specifically, for any sub-code block, the location of the effective decoding region corresponding to that sub-code block can be obtained first. The location of the effective decoding region can be determined based on the sub-code block's partitioning window and the location of the overlapping region.

[0081] For example, with a convolutional code rate of 1 / 2, every two soft decision information pieces correspond to one decoding bit. If each sub-block has a length of L, and L = G + I, where G is the effective decoding length and I is the overlap length, then after performing Viterbi decoding on the sub-block, a local decoding result of length L / 2 can be obtained. Here, the G soft decision information pieces contained in the sub-block correspond to G / 2 decoding bits, and the I overlapping soft decision information pieces correspond to I / 2 decoding bits. When extracting the effective output of the sub-block, G / 2 decoding bits corresponding to the G soft decision information pieces can be extracted from the local decoding result as the effective decoding region bit sequence used for concatenation of the sub-block. The decoding bits corresponding to the overlapping region are not used as the final output of the sub-block.

[0082] For example, the local decoding result of the sub-code block output by any processing unit is as follows: Therefore, the first G / 2 decoded bits corresponding to the effective decoded region in the local decoding result can be determined as the effective output of the sub-code block, i.e. .

[0083] After performing the above-described valid output extraction process on all processing units, the communication device can obtain the valid decoding bit sequences corresponding to multiple sub-code blocks. .

[0084] S405, according to the position order of each sub-code block in the information sequence, concatenate the bit sequences of each sub-code block into the Viterbi decoding result of the information sequence.

[0085] One possible implementation involves obtaining the position identifiers corresponding to each sub-code block. Based on these position identifiers, the order of each sub-code block within the information sequence is determined. The bit sequences corresponding to each sub-code block are then concatenated in this order to obtain the Viterbi decoding result of the information sequence.

[0086] Specifically, the communication device can obtain the position identifier corresponding to each sub-code block. This position identifier can be used to indicate the order of each sub-code block in the original information sequence. For example, according to the division order, the position identifiers of each sub-code block can be recorded as 0, 1, ..., n-1.

[0087] Based on the position identifiers of each sub-code block, the order of each sub-code block in the information sequence is determined. Following this order, the effective decoding bit sequences corresponding to each sub-code block are concatenated to obtain the Viterbi decoding result of the information sequence. For example, the effective decoding bit sequences corresponding to multiple sub-code blocks are as follows: Following the ascending order of the sub-code block positions, the bit sequence of the effective decoding region is concatenated to obtain the overall decoding result. c represents the Viterbi decoding result corresponding to the information sequence to be decoded.

[0088] In this way, the communication device can remove the overlapping output parts in each sub-code block after multiple processing units complete local decoding in parallel, and then sequentially splice the bits based only on the effective decoding bit sequence of each sub-code block to obtain the complete decoded bit sequence.

[0089] After determining the target decoding bits, the communication device can update the decoding bits at the boundary between the first and second sub-code blocks based on the target decoding bits, obtaining the updated local decoding results for the first and second sub-code blocks. The communication device can then continue to extract and concatenate the effective decoding region bit sequence based on the updated local decoding results.

[0090] By using the above method, the decoding continuity at the partition boundary can be judged by using the decoding results in the overlapping area of ​​adjacent sub-code blocks on the basis of parallel decoding, and the path metric results can be combined to update when the boundary decoding is discontinuous, thereby improving the reliability of the decoding results near the partition boundary.

[0091] The Viterbi parallel processing method for multi-core processors proposed in this application was simulated and verified using a server with an Intel Xeon E5-2650 v3 @ 2.30GHz processor, 4 cores, and 4 threads. The decoding efficiency of serial decoding and parallel decoding was compared as follows: Figure 5 As shown, it can be seen that as the number of threads increases, the throughput of parallel decoding increases exponentially compared to serial decoding, while maintaining a bit error rate almost identical to that of serial decoding.

[0092] To further verify the error performance of parallel decoding, this application embodiment simulates the error comparison between parallel decoding (4 threads) and serial decoding under Eb / N0 (0~5dB) scenarios. Figure 6 As shown, it can be seen that the error curves of parallel decoding under different Eb / N0 are basically the same as those of serial decoding. In other words, with almost no loss in error performance, the Viterbi parallel processing method for multi-core processors proposed in this application can significantly improve the decoding efficiency.

[0093] The above primarily describes the solutions provided in the embodiments of this application from the perspective of the device's working principle. It is understood that, in order to achieve the above functions, the Viterbi parallel processing device for multi-core processors includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] This application embodiment can divide the Viterbi parallel processing device for multi-core processors into functional modules according to the above method example. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module.

[0095] It should be noted that the module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. When dividing functional modules according to their respective functions, Figure 7 A schematic diagram of a possible configuration of the Viterbi parallel processing device for multi-core processors involved in the above and embodiments is shown. Figure 7 As shown, the Viterbi parallel processing device 700 for multi-core processors may include: a determination module 701, a partitioning module 702, a processing module 703, an extraction module 704, and a splicing module 705.

[0096] The determination module 701 is used to support the execution of the Viterbi parallel processing device 700 for multi-core processors. Figure 4 S401 in the illustrated Viterbi parallel processing method for multi-core processors.

[0097] Partitioning module 702 is used to support the execution of Viterbi parallel processing device 700 for multi-core processors. Figure 4 S402 in the illustrated Viterbi parallel processing method for multi-core processors.

[0098] Processing module 703 is used to support the execution of Viterbi parallel processing device 700 for multi-core processors. Figure 4 S403 in the illustrated Viterbi parallel processing method for multi-core processors.

[0099] Extraction module 704 is used to support the execution of Viterbi parallel processing device 700 for multi-core processors. Figure 4 S404 is illustrated in the Viterbi parallel processing method for multi-core processors.

[0100] The splicing module 705 is used to support the execution of the Viterbi parallel processing device 700 for multi-core processors. Figure 4 S405 is illustrated in the Viterbi parallel processing method for multi-core processors.

[0101] One possible implementation is that when the determining module is used to determine the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding, it is specifically used to: determine the overlap length between adjacent partitioning windows based on the backtracking depth; and determine the partitioning length of the partitioning window based on the preset effective decoding length and the overlap length.

[0102] One possible implementation is that, when extracting the bit sequence of the corresponding effective decoding region from the local decoding results of each of the sub-code blocks, the specific steps are as follows: for any sub-code block, based on the position of the effective decoding region in the effective decoding region of the sub-code block, determine the effective output range of the sub-code block in the local decoding results; extract the decoding bits corresponding to the effective output range from the local decoding results to obtain the bit sequence of the effective decoding region corresponding to the sub-code block.

[0103] One possible implementation involves allocating multiple sub-code blocks to multiple processing units of the multi-core processor for parallel Viterbi decoding processing to obtain local decoding results for each sub-code block. This includes: obtaining a position identifier corresponding to each sub-code block; writing each sub-code block into a decoding buffer of the corresponding processing unit based on the position identifier; controlling multiple processing units to perform Viterbi decoding processing on the sub-code blocks in their respective decoding buffers to obtain decoding data output by each processing unit; and associating the decoding data output by each processing unit with the position identifier of the corresponding sub-code block to obtain the local decoding result for each sub-code block.

[0104] One possible implementation is that the control of multiple processing units to perform Viterbi decoding processing on sub-code blocks in their respective decoding buffers includes: for any given sub-code block, calculating a path metric based on the information sequence in the sub-code block to obtain the path metric value corresponding to each state in the information sequence of the sub-code block; and determining the surviving path corresponding to each state based on the path metric value. After determining the surviving paths of all states in the sub-code block, the surviving paths are backtracked according to the backtracking depth to obtain the backtracking result of the sub-code block; based on the backtracking result, the local decoding result corresponding to the sub-code block is generated.

[0105] One possible implementation involves concatenating the bit sequences of each sub-code block according to their position order in the information sequence to obtain the Viterbi decoding result of the information sequence, including: obtaining the position identifier corresponding to each sub-code block; determining the order of each sub-code block in the information sequence based on the position identifier; and concatenating the bit sequences corresponding to each sub-code block according to the order to obtain the Viterbi decoding result of the information sequence.

[0106] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0107] The Viterbi parallel processing device 700 for multi-core processors provided in this application embodiment is used to execute the above-described... Figure 4 The Viterbi parallel processing method shown is designed for multi-core processors and therefore achieves the same effect as the Viterbi parallel processing method for multi-core processors described above.

[0108] This application also provides a Viterbi parallel processing device for multi-core processors, which can execute the Viterbi parallel processing method and related steps for multi-core processors described in the above method embodiments.

[0109] This application also provides a computer-readable storage medium storing instructions that, when executed, perform the Viterbi parallel processing method and related steps for multi-core processors described in the above method embodiments.

[0110] This application also provides a computer program product that, when run on a computer, causes the computer to execute the Viterbi parallel processing method and related steps for multi-core processors described in the above method embodiments.

[0111] In some embodiments, the methods shown in this application can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0112] This application also provides a Viterbi parallel processing system 800 for multi-core processors, such as... Figure 8 As shown, the Viterbi parallel processing system 800 for multi-core processors includes at least one processor 801 and at least one interface circuit 802.

[0113] As an example, when the Viterbi parallel processing system 800 for multi-core processors includes a processor and an interface circuit, the processor can be... Figure 8 The processor 801 shown in the solid box (or the processor 801 shown in the dashed box) can be an interface circuit. Figure 8 The interface circuit 802 is shown in either the solid or dashed box. When the Viterbi parallel processing system 800 for multi-core processors includes two processors and two interface circuits, then the two processors include... Figure 8 The processor 801 shown in the solid box and the processor 801 shown in the dashed box, these two interface circuits include Figure 8 Interface circuit 802 is shown in both solid and dashed boxes. No limitations are imposed on this.

[0114] Processor 801 and interface circuit 802 can be interconnected via a line. For example, interface circuit 802 can be used to receive signals. Alternatively, interface circuit 802 can be used to send signals to other devices (e.g., processor 801). For instance, interface circuit 802 can read computer instructions stored in memory and send those instructions to processor 801. Processor 801 executes the instructions and, in conjunction with input / output devices, implements the various steps in the above embodiments, such as implementing... Figures 4-6 The steps performed in the illustrated method embodiment are shown. Of course, this Viterbi parallel processing system for multi-core processors may also include other discrete components, and this application embodiment does not specifically limit this.

[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to it, or all or part of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for parallel processing of Viterbi for a multi-core processor, the method comprising: The method includes: Based on the backtracking depth of Viterbi decoding, determine the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows; The information sequence is divided into multiple sub-code blocks according to the division window and the overlap length; each sub-code block includes: an effective decoding area and an overlap area that overlaps with adjacent sub-code blocks; The multiple sub-code blocks are assigned to multiple processing units of a multi-core processor for parallel Viterbi decoding to obtain the local decoding results of each sub-code block; Extract the bit sequence of the corresponding effective decoding region from the local decoding results of each of the sub-code blocks; Based on the positional order of each sub-code block in the information sequence, the bit sequences of each sub-code block are concatenated to form the Viterbi decoding result of the information sequence.

2. The method of claim 1, wherein, The step of determining the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding includes: Based on the backtracking depth, determine the overlap length between adjacent partitioning windows; The division length of the partitioning window is determined based on the preset effective decoding length and the overlap length.

3. The method of claim 1, wherein, Extracting the bit sequence corresponding to the effective decoding region from the local decoding results of each of the sub-code blocks includes: For any of the sub-code blocks, the effective output range of the sub-code block is determined in the local decoding result based on the effective decoding region position of the effective decoding region in the sub-code block. Extract the decoded bits corresponding to the effective output range from the local decoding result to obtain the bit sequence of the effective decoding region corresponding to the sub-code block.

4. The method of claim 1, wherein, The step of allocating multiple sub-code blocks to multiple processing units of the multi-core processor for parallel Viterbi decoding processing to obtain the local decoding results of each sub-code block includes: Obtain the position identifier corresponding to each of the sub-code blocks; According to the location identifier, each sub-code block is written into the decoding buffer of the corresponding processing unit; Multiple processing units are controlled to perform Viterbi decoding on the sub-code blocks in their respective decoding buffers to obtain the decoded data output by each processing unit. The decoded data output by each processing unit is associated with the position identifier of the corresponding sub-code block to obtain the local decoding result of each sub-code block.

5. The method of claim 4, wherein, The control of multiple processing units to perform Viterbi decoding processing on sub-code blocks in their respective decoding buffers includes: For any of the sub-code blocks, a path metric is calculated based on the information sequence in the sub-code block to obtain the path metric value corresponding to each state in the information sequence of the sub-code block. Based on the path metric, determine the survival path corresponding to each state; After determining the surviving paths of all states in the sub-code block, the surviving paths are backtracked according to the backtracking depth to obtain the backtracking result of the sub-code block. Based on the backtracking result, the local decoding result corresponding to the sub-code block is generated.

6. The method of claim 1, wherein, The step of concatenating the bit sequences of each sub-code block according to their position order in the information sequence to obtain the Viterbi decoding result of the information sequence includes: Obtain the position identifier corresponding to each of the sub-code blocks; The order of each sub-code block in the information sequence is determined based on the position identifier of each sub-code block; By concatenating the bit sequences corresponding to each of the sub-code blocks in the aforementioned order, the Viterbi decoding result of the information sequence is obtained.

7. A Viterbi parallel processing device for a multi-core processor, characterized by comprising: The device includes: The determination module is used to determine the partitioning window of the information sequence to be decoded and the overlap length between adjacent partitioning windows based on the backtracking depth of Viterbi decoding. The partitioning module is used to divide the information sequence into multiple sub-code blocks according to the partitioning window and the overlap length; the sub-code block includes: an effective decoding area and an overlap area that overlaps with adjacent sub-code blocks; The processing module is used to distribute the multiple sub-code blocks to multiple processing units of a multi-core processor for parallel Viterbi decoding processing to obtain the local decoding results of each sub-code block. The extraction module is used to extract the bit sequence of the corresponding effective decoding region from the local decoding results of each of the sub-code blocks; The splicing module is used to splice the bit sequences of each of the sub-code blocks into a Viterbi decoding result of the information sequence according to the position order of each sub-code block in the information sequence.

8. The apparatus of claim 7, wherein, The processing module is specifically used to obtain the position identifier corresponding to each of the sub-code blocks; write each sub-code block into the decoding buffer of the corresponding processing unit according to the position identifier; control multiple processing units to perform Viterbi decoding processing on the sub-code blocks in their respective decoding buffers to obtain the decoding data output by each processing unit; and associate the decoding data output by each processing unit with the position identifier of the corresponding sub-code block to obtain the local decoding result of each sub-code block.

9. A parallel processing device for Viterbi processing oriented to a multi-core processor, characterized by, The Viterbi parallel processing device for multi-core processors includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the Viterbi parallel processing method for multi-core processors as described in any one of claims 1 to 6.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the Viterbi parallel processing method for multi-core processors as described in any one of claims 1 to 6.

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