A multi-channel device for acquiring WIFI6E and WIFI7 signals

Abstract

This invention provides a multi-channel device for acquiring Wi-Fi 6E and Wi-Fi 7 signals, belonging to the field of signal processing technology. The multi-channel device for acquiring Wi-Fi 6E and Wi-Fi 7 signals includes: multiple signal acquisition branches, each including a directional antenna and a down-conversion channel connected to the directional antenna; a local oscillator module connected to the down-conversion channel in the multiple signal acquisition branches, used to provide a local oscillator signal to each down-conversion channel; and a baseband module connected to the multiple signal acquisition branches, used to receive the bandwidth signal output from each down-conversion channel. The down-conversion channel includes a first bandpass filter, a second bandpass filter, and a mixer. This solves the bottleneck of hardware processing performance; the second bandpass filter further purifies the converted signal, enabling accurate capture and storage of Wi-Fi 6E and Wi-Fi 7 signals in complex outdoor environments, providing real-world test data support for subsequent improvements in wearable device performance.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a multi-channel device for acquiring WIFI6E and WIFI7 signals. Background Technology

[0002] In real-world environments, WiFi signals are severely affected by reflections, multipath propagation, obstruction, and dynamic interference, impacting the performance of wearable devices.

[0003] To verify the actual performance of wearable devices, they need to be tested in a real-world environment.

[0004] However, if each verification of the actual performance of a wearable device requires placing it in a real environment for testing, and the wearable device needs to be moved around, this testing method is time-consuming and labor-intensive, and cannot meet the current need for frequent verification. Summary of the Invention

[0005] This invention provides a multi-channel device for acquiring WIFI6E and WIFI7 signals, which solves the problem of time-consuming and labor-intensive testing of wearable devices in real-world environments in the prior art, and enables portable verification of the actual performance of wearable devices, thereby reducing the cost of verification.

[0006] This invention provides a multi-channel device for acquiring WIFI6E and WIFI7 signals, comprising the following modules: Multiple signal acquisition branches, each of which includes a directional antenna and a down-conversion channel connected to the directional antenna; The local oscillator module is connected to the down-conversion channel in the multiple signal acquisition branches and is used to provide a local oscillator signal to each of the down-conversion channels. The baseband module is connected to multiple signal acquisition branches and is used to receive the bandwidth signal output by each of the downconversion channels. The downconversion channel includes a first bandpass filter, a second bandpass filter, and a mixer. The mixer performs mixing processing based on the local oscillator signal and the bandwidth signal filtered by the first bandpass filter, and sends the mixed bandwidth signal to the second bandpass filter for storage by the baseband module.

[0007] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the passband frequency of the first bandpass filter is between 5925 MHz and 7125 MHz; and the second bandpass filter is a bandpass filter with a center frequency of 1.1 GHz and a bandwidth of less than or equal to 500 MHz.

[0008] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein each of the down-conversion channels further includes: The first gain adjustment module is located between the output of the first bandpass filter and the input of the mixer, and is used to adjust the power value of the bandwidth signal after being filtered by the first bandpass filter.

[0009] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein each of the down-conversion channels further includes: The second gain adjustment module is located between the output of the mixer and the input of the second bandpass filter, and is used to perform gain processing on the bandwidth signal after mixing.

[0010] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the baseband module includes: Multiple analog-to-digital converters are provided, with multiple input terminals of the multiple analog-to-digital converters connected one-to-one with the output terminals of the multiple signal acquisition branches. These converters are used to sample the bandwidth signal output by the down-conversion channel based on the working clock signal to obtain the target bandwidth signal. The programmable logic chip is connected to the output of multiple analog-to-digital converters; A storage chip, connected to the programmable logic chip; The programmable logic chip is used to store the target bandwidth signal in the memory chip.

[0011] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein each of the analog-to-digital converters includes a digitally controlled oscillator, the digitally controlled oscillator generating a waveform signal of a first frequency based on the operating clock signal; The analog-to-digital converter performs frequency mixing processing based on the waveform signal of the first frequency and the bandwidth signal output by the down-conversion channel to obtain the target bandwidth signal.

[0012] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the multi-channel device for acquiring WIFI6E and WIFI7 signals further includes: Reference clock source, used to generate a reference clock signal; A frequency synthesizer, connected to the reference clock source, is used to output the working clock signal based on the reference clock signal; The baseband module also includes: A clock generation module is connected to the programmable logic chip and the plurality of analog-to-digital converters respectively, and is used to receive the working clock signal and send the working clock signal to the programmable logic chip and the analog-to-digital converters.

[0013] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the multi-channel device for acquiring WIFI6E and WIFI7 signals further includes: A high-speed bus is connected to the programmable logic chip; A storage module, connected to the high-speed bus, is used to store the target bandwidth signal via the high-speed bus.

[0014] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the frequency of the local oscillator signal is greater than or equal to 4.825 GHz and less than or equal to 6.025 GHz.

[0015] According to the present invention, a multi-channel device for acquiring WIFI6E and WIFI7 signals is provided, wherein the target bandwidth signals corresponding to multiple signal acquisition branches are ping-pong stored in the storage chip.

[0016] This invention provides a multi-channel device for acquiring WiFi 6E and WiFi 7 signals. By incorporating two-stage bandpass filters in the down-conversion channel in conjunction with a mixer, it achieves a processing flow of filtering, down-converting, and then finely filtering high-frequency WiFi signals. The first bandpass filter effectively suppresses complex out-of-band interference, ensuring the purity of the mixed input signal. The mixer, combined with the local oscillator signal, converts high-frequency signals that cannot be directly acquired into intermediate frequency signals, overcoming the bottleneck of hardware processing performance. The second bandpass filter further purifies the converted signal, ensuring that the data ultimately stored in the baseband module is a high-quality, low-noise measured signal. This architecture enables the device to accurately capture and store WiFi 6E and WiFi 7 signals in complex outdoor environments with low cost and high integration, providing real-world test data support for subsequent improvements in wearable device performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1This is one of the schematic block diagrams of a multi-channel device for acquiring WIFI6E and WIFI7 signals provided by the present invention.

[0019] Figure 2 This is the second schematic block diagram of the multi-channel device for WIFI6E and WIFI7 signal acquisition provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the topology of the downconversion channel provided by the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the multi-channel device for WIFI6E and WIFI7 signal acquisition provided by the present invention.

[0022] Figure label: 10: Signal acquisition branch; 101: Directional antenna; 102: Down-conversion channel; 1021: First bandpass filter; 1022: Second bandpass filter; 1023: Mixer; 1024: First gain adjustment module; 1025: Second gain adjustment module; 20: Local oscillator module; 30: Baseband module; 301: Analog-to-digital converter; 302: Programmable logic chip; 303: Memory chip; 304: Clock generation module; 40: Reference clock source; 50: Frequency synthesizer; 60: High-speed bus; 70: Memory module. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] The present invention provides a multi-channel device for acquiring WIFI6E and WIFI7 signals. The main body executing the entire signal acquisition, down-conversion processing and data storage process can be the multi-channel device for acquiring WIFI6E and WIFI7 signals itself, or a control chip integrated inside the device.

[0025] The following is combined Figures 1 to 4 This invention describes a multi-channel device for acquiring WIFI6E and WIFI7 signals.

[0026] Figure 1 This is one of the schematic block diagrams of a multi-channel device for acquiring WIFI6E and WIFI7 signals provided by the present invention. Figure 2This is the second schematic block diagram of the multi-channel device for WIFI6E and WIFI7 signal acquisition provided by the present invention. Figure 3 This is a schematic diagram of the topology of the downconversion channel provided by the present invention, as shown below. Figure 1 , Figure 2 and Figure 3 As shown, the multi-channel device for acquiring WIFI6E and WIFI7 signals includes the following modules: Multiple signal acquisition branches 10, each signal acquisition branch 10 includes a directional antenna 101 and a down-conversion channel 102 connected to the directional antenna 101; The local oscillator module 20 is connected to the down-conversion channel 102 in the multiple signal acquisition branches 10, and is used to provide local oscillator signals to each down-conversion channel 102; The baseband module 30 is connected to multiple signal acquisition branches 10 and is used to receive the bandwidth signal output by each downconversion channel 102. The downconversion channel 102 includes a first bandpass filter 1021, a second bandpass filter 1022, and a mixer 1023. The mixer 1023 performs mixing processing based on the local oscillator signal and the bandwidth signal after filtering by the first bandpass filter 1021, and sends the mixed bandwidth signal to the second bandpass filter 1022 for storage by the baseband module 30.

[0027] The local oscillator module 20, or local oscillator module, is responsible for generating a stable and accurate local oscillator signal. In this embodiment, the local oscillator module 20 is connected to the down-conversion channels 102 in the multiple signal acquisition branches 10. To ensure the consistency and synchronization of multi-channel acquisition, the device adopts a common local oscillator scheme, that is, the same local oscillator signal generated by the same local oscillator module 20 is simultaneously provided to four or more down-conversion channels 102, ensuring that each channel operates synchronously at the same frequency.

[0028] Specifically, the high-frequency bandwidth signal (e.g., the 6GHz band signal corresponding to WIFI 6E or WIFI 7) captured by the directional antenna 101 enters the down-conversion channel 102. Due to the complex electromagnetic background in the acquisition environment (e.g., an outdoor field), the signal is first filtered by the first bandpass filter 1021. The function of the first bandpass filter 1021 is to filter out spurious signals and interference outside this frequency band, ensuring that the signal input to subsequent circuits is clean and free of out-of-band noise.

[0029] Next, the filtered bandwidth signal enters mixer 1023. Mixer 1023 is a non-linear frequency conversion element that receives two input signals: one is the filtered bandwidth signal from the first bandpass filter 1021, and the other is the local oscillator signal from the local oscillator module 20. Mixer 1023 performs physical mixing (i.e., signal multiplication) based on these two signals, shifting the high-frequency radio frequency signal to a lower frequency range according to the frequency difference principle, thus achieving down-conversion. Since high-frequency signals such as 6GHz are too high to be directly sampled with high precision, this down-conversion process converts the signal to an intermediate frequency range that is easily processed by the baseband module 30.

[0030] Finally, the signal generated by the mixing process enters the second bandpass filter 1022. The second bandpass filter 1022 is used to further filter out the sum frequency components, image frequencies and other unwanted harmonics generated during the mixing process, retaining only the target intermediate frequency bandwidth signal, and sending this signal to the baseband module 30 for subsequent digital processing and data storage.

[0031] In this embodiment, by setting two-stage bandpass filters in the down-conversion channel 102 and cooperating with mixer 1023, a processing flow of filtering, down-converting, and then finely filtering high-frequency WiFi signals is realized. The first bandpass filter 1021 effectively suppresses complex out-of-band interference, ensuring the purity of the mixing input signal; the mixer 1023, combined with the local oscillator signal, converts the high-frequency signal that cannot be directly sampled into an intermediate frequency signal, solving the bottleneck of hardware processing performance; while the second bandpass filter 1022 further purifies the signal after frequency conversion, ensuring that the data finally stored in the baseband module 30 is a high-quality, low-noise measured signal. This architecture enables the device to accurately capture and store WiFi 6E and WiFi 7 signals in complex outdoor environments with low cost and high integration, providing real measured data support for subsequent improvements in wearable device performance.

[0032] In some embodiments, the frequency of the local oscillator signal can be set by the host computer.

[0033] In some embodiments, the passband frequency of the first bandpass filter 1021 is between 5925MHz and 7125MHz; the second bandpass filter 1022 is a bandpass filter with a center frequency of 1.1GHz and a bandwidth of less than or equal to 500MHz.

[0034] The passband frequency refers to the specific frequency range that the filter allows signals to pass through. This filter extracts useful signals within a target frequency window of 5925MHz to 7125MHz from the full-spectrum electromagnetic environment received from the antenna, while suppressing signals outside this range. For example, through the precise directional interception of this filter, classic WiFi interference in the low-frequency bands of 2.4GHz and 5GHz, as well as other unrelated licensed frequency band signals in the high-frequency bands, can be effectively filtered out, thus ensuring that the radio frequency signal entering the mixer 1023 is a clean 6GHz signal conforming to the definitions of WiFi 6E and WiFi 7 standards.

[0035] After down-conversion by mixer 1023, the signal is shifted to the intermediate frequency range. At this point, the second bandpass filter 1022 comes into play, configured as a bandpass filter with a center frequency of 1.1 GHz and a bandwidth of less than or equal to 500 MHz.

[0036] The center frequency refers to the frequency position corresponding to the center of the filter passband. 1.1GHz was chosen as the intermediate frequency to avoid low-frequency flicker noise interference while remaining within the optimal frequency range that the high-performance baseband module 30 can handle.

[0037] Bandwidth refers to the range of signal frequencies that a filter allows to pass through. Setting the bandwidth to less than or equal to 500MHz (e.g., setting it to 500MHz) is to fully cover the signal acquisition requirements of the Wi-Fi 7 protocol, which has a maximum bandwidth of 320MHz. In actual acquisition, even if the Wi-Fi 7 signal occupies a very wide spectrum under multi-link operation, this 500MHz bandwidth window can ensure that the spectral characteristics of the signal are not truncated, thus guaranteeing data integrity.

[0038] In this embodiment, by strictly limiting the passband of the first bandpass filter 1021 to 5925MHz to 7125MHz, the target WiFi frequency band is accurately locked in the first step of the analog front-end process, effectively preventing strong interference signals from causing saturation or intermodulation distortion in the mixer 1023. By matching a second bandpass filter 1022 with a bandwidth of 500MHz centered at 1.1GHz, the waveform details of the ultra-wide bandwidth WiFi 7 signal are fully preserved while filtering out mixing spurious components. The coordinated parameters of these two filter stages ensure that the acquisition device can adapt to the task of acquiring massive amounts of high-speed 6GHz band signals from the source of data processing.

[0039] In some embodiments, the second bandpass filter 1022 is a bandpass filter with a center frequency of 1.1 GHz and a bandwidth of less than or equal to 250 MHz.

[0040] In some embodiments, each downconversion channel 102 further includes: The first gain adjustment module 1024 is located between the output of the first bandpass filter 1021 and the input of the mixer 1023, and is used to adjust the power value of the bandwidth signal after being filtered by the first bandpass filter 1021.

[0041] The first gain adjustment module 1024 is a circuit component capable of controlled adjustment of the amplitude of an analog radio frequency signal. It may contain one or more of a low-noise amplifier, a variable gain amplifier, or an adjustable attenuator. The core function of this module is to adjust the power value, that is, to adjust the power of the input signal to the optimal linear range for the mixer 1023 based on the strength of the input signal.

[0042] Specifically, the bandwidth signal captured by the directional antenna 101 (such as a WiFi 6E / 7 signal with a frequency range between 5925MHz and 7125MHz) is filtered out for out-of-band interference by the first bandpass filter 1021 and then output to the first gain adjustment module 1024. Next, the first gain adjustment module 1024 performs power detection and gain allocation on the filtered bandwidth signal. In actual field acquisition scenarios, the signal strength received by the directional antenna 101 may vary significantly due to differences in the distance between the wearable device and the acquisition device, as well as the presence of obstructions. If the received signal is too weak, the first gain adjustment module 1024 will activate an amplification compensation mechanism (such as gain processing through a low-noise amplifier) ​​to increase the signal amplitude and prevent the signal from being overwhelmed by the noise floor of the subsequent mixer 1023. If the received signal is too strong due to the close proximity, the first gain adjustment module 1024 will perform attenuation processing to reduce the signal power and prevent the mixer 1023 from entering saturation due to excessive input power, thereby generating nonlinear distortion or harmonic interference.

[0043] After being processed by the first gain adjustment module 1024, the bandwidth signal with a suitable power value enters the mixer 1023 and is mixed with the local oscillator signal.

[0044] By introducing a first gain adjustment module 1024 between the first bandpass filter 1021 and the mixer 1023, precise dynamic control of the RF front-end signal power is achieved. This feature, in conjunction with the filtering effect of the first bandpass filter 1021, ensures that the signal entering the mixer 1023 is both pure and of moderate strength. From a data processing perspective, this combination effectively expands the dynamic range of the system and solves the problem of acquisition distortion caused by varying external signal strength. The first gain adjustment module 1024, by locking the signal power within the optimal linear operating range of the mixer 1023, works in conjunction with the down-conversion function of the mixer 1023 to preserve the phase and amplitude characteristics of the original WiFi signal to the greatest extent possible. This ensures that the measured data ultimately stored in the baseband module 30 has extremely high fidelity, providing a reliable guarantee for subsequent accurate analysis of the physical layer characteristics of the WiFi 7 signal.

[0045] In some embodiments, each downconversion channel 102 further includes: The second gain adjustment module 1025 is located between the output of the mixer 1023 and the input of the second bandpass filter 1022, and is used to perform gain processing on the bandwidth signal after mixing.

[0046] The second gain adjustment module 1025 refers to an electronic component located at the rear end of the mixer 1023, used for amplitude control of the frequency-converted intermediate frequency signal. It is typically composed of a variable gain amplifier or an adjustable attenuator, or a combination of both. In the physical link, the second gain adjustment module 1025 is located between the output of the mixer 1023 and the input of the second bandpass filter 1022.

[0047] Specifically, the bandwidth signal output by mixer 1023 (which has now been converted from a high-frequency radio frequency signal to an intermediate frequency signal) first enters the second gain adjustment module 1025. The execution unit (such as the control circuit of the device) drives the second gain adjustment module 1025 to perform gain processing on the mixed bandwidth signal according to the current signal strength. This gain processing includes amplification or attenuation.

[0048] Because the mixer 1023 typically incurs conversion loss during the frequency conversion process, and the strength of the externally input WiFi signal fluctuates greatly in real-world environments, directly sending the mixed signal into the filter may result in a signal that is too weak and overwhelmed by noise, or a signal that is too strong and causes saturation and distortion in subsequent circuits. Therefore, the second gain adjustment module 1025 performs real-time power compensation or suppression on the signal.

[0049] In practice, the second gain adjustment module 1025 adjusts the signal to a preset ideal power envelope. The signal after gain processing is then output to the second bandpass filter 1022. For example, if the second bandpass filter 1022 is a filter with a center frequency of 1.1 GHz and a bandwidth of 500 MHz, the adjustment by the second gain adjustment module 1025 ensures that the signal entering the 1.1 GHz filter has the best signal-to-noise ratio, and that its amplitude can be adapted to the quantization range of the analog-to-digital converter in the subsequent baseband module 30.

[0050] In this embodiment, by introducing a second gain adjustment module 1025 between the mixer 1023 and the second bandpass filter 1022, precise amplitude control can be achieved for the 1.1GHz intermediate frequency signal generated after frequency conversion. In the data processing flow, this module plays a power matching role: it not only compensates for the signal loss caused by the mixer 1023, but also ensures that the signal output to the second bandpass filter 1022 is always within the linear operating range by dynamically adjusting the signal power. This feature, combined with the preceding and following filters, effectively prevents nonlinear distortion of the signal during filtering and transmission, thereby significantly improving the data accuracy ultimately acquired by the baseband module 30 and ensuring that the characteristics of the original signal are completely and accurately preserved when collecting massive amounts of WiFi data.

[0051] In some embodiments, such as Figure 4 As shown, the baseband module 30 includes: Multiple analog-to-digital converters 301 are provided, with multiple input terminals of the multiple analog-to-digital converters 301 connected one-to-one with the output terminals of multiple signal acquisition branches 10. These are used to sample the bandwidth signal output by the down-conversion channel 102 based on the working clock signal to obtain the target bandwidth signal. The programmable logic chip 302 is connected to the output terminals of multiple analog-to-digital converters 301; The memory chip 303 is connected to the programmable logic chip 302; The programmable logic chip 302 is used to store the target bandwidth signal in the memory chip 303.

[0052] The analog-to-digital converter (ADC) 301 serves as a bridge connecting the analog and digital domains. In this embodiment, multiple input terminals of the multiple ADCs 301 are connected one-to-one with the aforementioned multiple signal acquisition branches 10 (i.e., the output terminals of the down-conversion channel 102). This point-to-point connection ensures that the four intermediate frequency signals can be independently converted into digital sequences without interference, thus maintaining the independence of multi-channel acquisition.

[0053] The operating clock signal is a high-speed, stable pulse sequence provided by the system clock distribution network. The operation of the analog-to-digital converter 301 is based on the operating clock signal; that is, the ADC instantaneously samples the analog bandwidth signal output by the down-conversion channel 102 at each trigger cycle of the clock signal. In order to capture high-speed signals such as WiFi 7, which can reach 320MHz or 500MHz, the frequency of this operating clock signal typically needs to reach the order of several GHz to ensure that the sampled target bandwidth signal can completely and undistortedly reproduce the waveform characteristics of the original signal.

[0054] The target bandwidth signal refers to the digital bitstream obtained after ADC quantization processing. These bitstreams carry all the protocol information and physical layer characteristics of the original WiFi signal and are data sets existing in discrete numerical form.

[0055] In some embodiments, the programmable logic chip 302 may be a field-programmable gate array or a logic processing unit integrated within the chip. This chip is connected to the output of the analog-to-digital converter 301 via an internal high-speed bus 60 or a parallel interface. The programmable logic chip 302 receives high-speed target bandwidth signals from multiple ADCs in real time and performs preprocessing operations such as protocol packaging, formatting, or parallel-to-serial conversion.

[0056] In some embodiments, storage chip 303 primarily refers to high-speed dynamic random access memory or similar cache media. Due to the extremely high data rates of WiFi 6E / 7, direct writing to a large-capacity hard drive may cause data congestion or loss. Therefore, programmable logic chip 302 is used to first store the target bandwidth signal in storage chip 303. This storage process is essentially a high-speed write operation; the logic chip, through the storage controller, writes the data stream sequentially to the cache area, providing a buffer for subsequent long-cycle storage or analysis.

[0057] In this embodiment, by configuring multiple analog-to-digital converters 301 corresponding to the signal branches in the baseband module 30 and driving them with a unified operating clock signal, synchronous digital conversion of multiple intermediate frequency analog signals is achieved. The analog-to-digital converters 301 accurately convert continuous waveforms into signals of the target bandwidth, ensuring the measured fidelity of the data. Subsequently, utilizing the high-speed parallel processing capability of the programmable logic chip 302, massive amounts of digital signals are scheduled in real time and stored in the memory chip 303 for local caching. This processing link, by combining high-speed sampling with real-time caching, effectively solves the problem of instantaneous data flow impact caused by the acquisition of ultra-large bandwidth (500MHz) signals, ensuring the integrity and time correlation of multi-channel signals during conversion and temporary storage, laying a digital foundation for high-precision data analysis.

[0058] In some embodiments, each analog-to-digital converter 301 includes a digitally controlled oscillator that generates a waveform signal of a first frequency based on a working clock signal; The analog-to-digital converter 301 performs frequency mixing processing based on the waveform signal of the first frequency and the bandwidth signal output by the down-conversion channel 102 to obtain the target bandwidth signal.

[0059] The digitally controlled oscillator (DCOS) is a purely digital frequency synthesis module whose main function is to generate a precise, adjustable frequency signal in the digital domain. In this embodiment, the ADC and its internal DCOS operate based on the same clock signal, thus ensuring complete synchronization between sampling and subsequent digital processing.

[0060] Specifically, the digitally controlled oscillator utilizes its internal phase accumulator to accumulate phase in each clock cycle of the operating clock signal, mapping the accumulated phase value to a sine or cosine amplitude to generate a waveform signal with a first frequency. In this embodiment, to match the 1.1 GHz intermediate frequency signal output from the pre-conversion channel 102, this first frequency is typically configured to 1.1 GHz. This waveform signal is represented in the digital domain as a high-precision quadrature digital sequence (I / Q signal).

[0061] Simultaneously, the ADC performs high-speed sampling of the bandwidth signal (i.e., the 1.1 GHz intermediate frequency signal) from the down-conversion channel 102, converting it from an analog signal to a digital intermediate frequency signal. Subsequently, the ADC module uses logic units such as digital multipliers to perform digital mixing processing on the sampled digital intermediate frequency signal and the waveform signal of the first frequency of 1.1 GHz generated by the digitally controlled oscillator.

[0062] The mixing process here is the core of Digital Down Conversion (DDC). Through digital multiplication, the original bandwidth signal with a center frequency of 1.1 GHz is shifted to a baseband position near 0 Hz. The mixed signal then undergoes digital filtering (such as low-pass filtering) to remove redundant frequency components, ultimately yielding the target bandwidth signal. In this embodiment, this target bandwidth signal is the digital baseband signal that can be directly analyzed and stored for protocol processing.

[0063] In this embodiment, by integrating a digitally controlled oscillator within the ADC and performing digital mixing, the system can complete the final conversion from intermediate frequency to baseband in the digital domain. First, since the waveform signal frequency (e.g., 1.1 GHz) generated by the digitally controlled oscillator is program-configurable and directly driven by the operating clock signal, its frequency accuracy is extremely high and it avoids the temperature drift problem of analog local oscillators, thus ensuring that the target bandwidth signal obtained after mixing has extremely high phase accuracy. Second, the digital mixing process avoids the additional filters and mixer 1023 hardware required by traditional secondary analog frequency conversion, which not only greatly reduces circuit complexity and cost but also avoids the nonlinear distortion and noise introduced by analog devices, resulting in a cleaner final acquired WIFI 6E / 7 signal and providing a precise digital data foundation for subsequent high-performance data analysis.

[0064] In some embodiments, the multi-channel device for acquiring WIFI6E and WIFI7 signals further includes: Reference clock source 40 is used to generate a reference clock signal; Frequency synthesizer 50 is connected to reference clock source 40 and is used to output working clock signal based on reference clock signal; The baseband module 30 also includes: The clock generation module 304 is connected to the programmable logic chip 302 and multiple analog-to-digital converters 301 respectively. It is used to receive the working clock signal and send the working clock signal to the programmable logic chip 302 and the analog-to-digital converters 301.

[0065] The reference clock source 40 serves as the frequency standard and time reference for the entire acquisition system; essentially, it is a device that provides a highly stable electrical signal. In this embodiment, the reference clock source 40 is used to generate a reference clock signal. This reference clock signal possesses extremely high frequency accuracy and extremely low temperature drift characteristics, serving as the original beat for all subsequent frequency synthesis.

[0066] In one specific embodiment, the reference clock source 40 can be a temperature-compensated crystal oscillator or a temperature-controlled crystal oscillator. The reference clock source 40 generates a reference clock signal at a first frequency, for example, 10MHz or 100MHz. This range of frequencies, from large to small, ensures that the system is compatible with external reference inputs of different precisions, thereby adapting to different test environment requirements.

[0067] The frequency synthesizer 50 is connected to the reference clock source 40. Its operating principle is based on phase-locked loop (PLL) technology, which multiplies, divides, or mixes the input low-frequency reference clock signal to output a higher-frequency working clock signal that is phase-locked with the reference signal. This working clock signal has a frequency (second frequency) greater than the reference signal frequency; for example, in the high-speed sampling scenario of Wi-Fi 6E / 7, the frequency of this working clock signal can reach the GHz level.

[0068] Specifically, a stable reference clock signal is generated by reference clock source 40, acquired, and input to frequency synthesizer 50. Next, frequency synthesizer 50 uses this reference signal as a frequency reference, performs frequency synthesis using an internal charge pump and voltage-controlled oscillator, extracts and outputs a high-speed operating clock signal that meets the ADC sampling rate requirements. Finally, clock generation module 304 receives this high-speed operating clock signal and performs a synchronization distribution operation. It simultaneously sends the operating clock signal with a very small bias (Skew) to programmable logic chip 302 and each analog-to-digital converter 301.

[0069] In this implementation, the programmable logic chip 302 performs logic operations and data scheduling under the drive of the working clock, while the analog-to-digital converter 301 synchronously samples the analog signals output by each down-conversion channel 102 under the edge triggering of the same working clock.

[0070] In this embodiment, a primary clock network constructed by introducing a reference clock source 40 and a frequency synthesizer 50, combined with a secondary distribution network constructed by the clock generation module 304 within the baseband module 30, achieves strict phase alignment from the system reference to the terminal sampling device. This hierarchical clock processing method allows multiple analog-to-digital converters 301 to share the same physical clock source and its derived synchronous sampling clock, fundamentally eliminating frequency drift errors caused by independent crystal oscillator operation between different channels. Combined with high-speed circuit routing design, this ultimately achieves a signal sampling time error of less than 20 ps between each acquisition branch. This extremely high data processing synchronization ensures accurate reconstruction of the logical correlation of data packets in different frequency bands on the time axis when acquiring multi-link signals such as WIFI 7, providing reliable underlying physical support for subsequent complex signal analysis.

[0071] In some embodiments, the multi-channel device for acquiring WIFI6E and WIFI7 signals further includes: High-speed bus 60 is connected to programmable logic chip 302; The storage module 70 is connected to the high-speed bus 60 and is used to store the target bandwidth signal via the high-speed bus 60.

[0072] The high-speed bus 60 refers to the physical channel and communication protocol for high-throughput data exchange between various hardware modules within the device. In this embodiment, the high-speed bus 60 is connected between the programmable logic chip 302 and the back-end storage architecture. Because the instantaneous bandwidth of WIFI 6E and WIFI 7 signals is extremely large, and the amount of data generated by four-channel parallel acquisition increases exponentially, traditional data transmission methods are insufficient to meet real-time requirements. Therefore, the high-speed bus 60 preferentially adopts a high-performance serial computer expansion bus standard, such as the PCI-Express (PCIe) bus, using its multi-channel (e.g., x8 or x16) high-bandwidth characteristics to ensure that the massive target bandwidth signals acquired can be transmitted from the baseband processing module losslessly and in real-time.

[0073] In some embodiments, the storage module 70 is acquired and implemented by combining multiple high-speed solid-state drives (SSDs) into a logical storage unit using RAID (Redundant Array of Independent Disks) technology. By using RAID 0 or other high-performance redundancy modes, not only can write speeds be multiplied, but storage capacity can also be significantly expanded. For example, in a specific scenario of this embodiment, the capacity of the storage module 70 can be configured to 128TB, enabling the device to support long-term, full-bandwidth continuous acquisition tasks, meeting the long-term packet capture requirements in complex electromagnetic environments.

[0074] Specifically, the programmable logic chip 302 formats and encapsulates the processed digital domain target bandwidth signal (i.e., the baseband signal after digital down-conversion and decimation filtering); then, the CPU in the data processing platform issues a scheduling instruction through the PCIe bus to initiate direct memory access transmission of the target bandwidth signal cached in the storage chip 303 through the high-speed bus 60; finally, the data stream is written at high speed to the disk array of the storage module 70 through the disk array card.

[0075] In this embodiment, by introducing a high-speed bus 60 and a high-performance storage module 70, and directly coupling them with the programmable logic chip 302, real-time, complete, and long-term storage of four-channel 500MHz bandwidth data is achieved. This feature, in conjunction with the aforementioned RF acquisition section, ultimately enables the acquisition of massive amounts of measured data in complex field environments for subsequent in-depth analysis, providing a solid data foundation for performance improvement and algorithm optimization of wearable devices.

[0076] In some embodiments, the frequency of the local oscillator signal is greater than or equal to 4.825 GHz and less than or equal to 6.025 GHz.

[0077] The local oscillator signal frequency is configured to be greater than or equal to 4.825 GHz and less than or equal to 6.025 GHz. This specific frequency range is calculated based on the difference frequency mixing principle coupled with the target signal bandwidth requirements. In practice, the data processing platform adjusts the phase-locked loop division ratio inside the local oscillator module 20 according to the target WiFi channel frequency that the user needs to collect, thereby outputting a specific local oscillator frequency within this range.

[0078] For example, when it is necessary to collect the signal at the beginning of the low-frequency band of WIFI 6E (approximately 5925MHz), the local oscillator module 20 is controlled to output a local oscillator signal of 4.825GHz. In the mixer 1023 of the down-conversion channel 102, the input signal (5925MHz) and the local oscillator signal (4825MHz) are mixed. According to the logic that RF frequency - local oscillator frequency = intermediate frequency, the resulting intermediate frequency signal is exactly 1.1GHz. Similarly, when it is necessary to collect the signal at the end of the high-frequency band of WIFI 7 (approximately 7125MHz), the local oscillator module 20 adjusts its output to a local oscillator signal of 6.025GHz, and the difference frequency result after mixing remains at 1.1GHz.

[0079] In practice, the frequency of the local oscillator signal is continuously adjustable or adjustable in steps within this range. This frequency adjustability allows the device to flexibly cover any WiFi channel within the entire 1.2GHz bandwidth (5925MHz~7125MHz). Furthermore, the local oscillator frequency range used in this invention is lower than the target RF signal frequency (i.e., a low-side injection scheme), which helps reduce the design difficulty and cost of the local oscillator source. Simultaneously, in conjunction with the aforementioned bandpass filter, it can effectively suppress image interference.

[0080] In this embodiment, by limiting the frequency of the local oscillator signal to a specific range of 4.825 GHz to 6.025 GHz, a linear mapping relationship is established between the RF input frequency and the fixed 1.1 GHz intermediate frequency output. This ensures that regardless of the location of the target WiFi signal within the 6 GHz band, the mixed signal will accurately fall within the passband of the second bandpass filter 1022 in the backend. This design not only achieves seamless coverage acquisition across the entire WiFi 6E and WiFi 7 frequency bands, but also simplifies the algorithm logic of the backend baseband processing module and the design complexity of the hardware filter through the fixed intermediate frequency output, ultimately guaranteeing the frequency accuracy of massive WiFi data during the frequency conversion process and the stability of the system operation.

[0081] In some embodiments, the target bandwidth signals corresponding to the multiple signal acquisition branches 10 are ping-pong stored in the storage chip 303.

[0082] In this context, ping-pong storage can be understood as the target bandwidth signals corresponding to multiple signal acquisition branches 10 being stored sequentially in the storage chip 303.

[0083] For example, if there are 4 signal acquisition branches 10, the target bandwidth signal corresponding to signal acquisition branch 1 is CH1, the target bandwidth signal corresponding to signal acquisition branch 2 is CH2, the target bandwidth signal corresponding to signal acquisition branch 3 is CH3, and the target bandwidth signal corresponding to signal acquisition branch 4 is CH4. The target bandwidth signals corresponding to the 4 signal acquisition branches 10 are stored in the storage chip 303 in the following order: CH1-CH2-CH3-CH4-CH1-CH2-CH3-CH4.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-channel device for WIFI 6E and WIFI 7 signal collection, characterized in that, include: Multiple signal acquisition branches, each of which includes a directional antenna and a down-conversion channel connected to the directional antenna; The local oscillator module is connected to the down-conversion channel in the multiple signal acquisition branches and is used to provide a local oscillator signal to each of the down-conversion channels. The baseband module is connected to multiple signal acquisition branches and is used to receive the bandwidth signal output by each of the downconversion channels. The downconversion channel includes a first bandpass filter, a second bandpass filter, and a mixer. The mixer performs mixing processing based on the local oscillator signal and the bandwidth signal filtered by the first bandpass filter, and sends the mixed bandwidth signal to the second bandpass filter for storage by the baseband module.

2. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 1, wherein, The first bandpass filter has a passband frequency between 5925 MHz and 7125 MHz; the second bandpass filter is a bandpass filter with a center frequency of 1.1 GHz and a bandwidth of less than or equal to 500 MHz.

3. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 1, wherein, Each of the downconversion channels further includes: The first gain adjustment module is located between the output of the first bandpass filter and the input of the mixer, and is used to adjust the power value of the bandwidth signal after being filtered by the first bandpass filter.

4. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 1, wherein, Each of the downconversion channels further includes: The second gain adjustment module is located between the output of the mixer and the input of the second bandpass filter, and is used to perform gain processing on the bandwidth signal after mixing.

5. The multi-channel device for WIFI 6E and WIFI 7 signal collection of any one of claims 1-4, wherein, The baseband module includes: Multiple analog-to-digital converters are provided, with multiple input terminals of the multiple analog-to-digital converters connected one-to-one with the output terminals of the multiple signal acquisition branches. These converters are used to sample the bandwidth signal output by the down-conversion channel based on the working clock signal to obtain the target bandwidth signal. The programmable logic chip is connected to the output of multiple analog-to-digital converters; A storage chip, connected to the programmable logic chip; The programmable logic chip is used to store the target bandwidth signal in the memory chip.

6. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 5, wherein, Each of the analog-to-digital converters includes a digitally controlled oscillator that generates a waveform signal of a first frequency based on the operating clock signal; The analog-to-digital converter performs frequency mixing processing based on the waveform signal of the first frequency and the bandwidth signal output by the down-conversion channel to obtain the target bandwidth signal.

7. The multi-channel device for acquiring WIFI6E and WIFI7 signals according to claim 5, characterized in that, The multi-channel device for acquiring WIFI6E and WIFI7 signals also includes: Reference clock source, used to generate a reference clock signal; A frequency synthesizer, connected to the reference clock source, is used to output the working clock signal based on the reference clock signal; The baseband module also includes: A clock generation module is connected to the programmable logic chip and the plurality of analog-to-digital converters respectively, and is used to receive the working clock signal and send the working clock signal to the programmable logic chip and the analog-to-digital converters.

8. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 5, wherein, The multi-channel device for acquiring WIFI6E and WIFI7 signals also includes: A high-speed bus is connected to the programmable logic chip; A storage module, connected to the high-speed bus, is used to store the target bandwidth signal via the high-speed bus.

9. The multi-channel device for WIFI 6E and WIFI 7 signal collection of any one of claims 1-4, wherein, The frequency of the local oscillator signal is greater than or equal to 4.825 GHz and less than or equal to 6.025 GHz.

10. The multi-channel device for WIFI 6E and WIFI 7 signal collection of claim 5, wherein, The target bandwidth signals corresponding to multiple signal acquisition branches are ping-pong stored in the storage chip.

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