A device synchronization control method, system, storage medium and product

Abstract

This invention discloses a device synchronization control method, system, storage medium, and product, relating to the field of communication technology. The device synchronization control method, applied to a synchronization control system, includes: issuing a synchronization control command through a base station host, invoking the synchronization control chip corresponding to the base station host to generate a frame synchronization signal, and synchronously sending the frame synchronization signal to all slave devices; triggering a receive interrupt in response to the frame synchronization signal, determining a local timestamp, and transmitting the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device; determining a synchronization compensation benchmark value based on the local timestamp, generating a unified start timestamp according to the synchronization compensation benchmark value, and sending it to each slave device through the synchronization control chip corresponding to the base station host; and receiving the unified start timestamp and executing a target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave devices.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a device synchronization control method, system, storage medium, and product. Background Technology

[0002] In a multi-device collaborative control system, the base station needs to issue unified commands to multiple servo stations / execution nodes to ensure that all devices start synchronously and act collaboratively. This is a core prerequisite for ensuring control accuracy and system stability. Currently, the industry commonly uses the QuadSerial Peripheral Interface (QSPI) to realize data communication between the base station and the servo station. This interface has the characteristics of simple circuitry, high transmission rate, and strong compatibility, making it the mainstream choice for short-distance serial communication.

[0003] However, existing general-purpose SPI / QSPI interfaces have significant technical shortcomings in multi-device synchronous communication scenarios, lacking a dedicated synchronization mechanism. The SPI / QSPI interface only defines basic clock, data, and chip select signals, without a dedicated frame synchronization signal. During multi-device communication, due to hardware delays, link jitter, and other factors, the timing of command reception varies among servo stations. This causes the same command sent by the base station to be unreceived synchronously by all servo stations, ultimately resulting in asynchronous device actions and severely impacting the accuracy of multi-axis / multi-joint collaborative control. This makes it difficult to meet the high synchronization, high real-time performance, and high reliability requirements of modern industrial control and robot control, becoming a technical bottleneck restricting the performance improvement of multi-device collaborative control. Therefore, how to conveniently and accurately synchronize devices has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a device synchronization control method, system, storage medium, and product to solve problems such as time jitter, unreliable data transmission, and poor configuration flexibility in device synchronization communication in the prior art.

[0005] According to one aspect of the present invention, a device synchronization control method is provided, applied to a synchronization control system, the synchronization control system including a base station host, a synchronization control chip, and at least one slave device, wherein the base station host and each slave device are respectively communicatively connected to a corresponding synchronization control chip, the method comprising: The base station host issues a synchronization control command, calls the synchronization control chip corresponding to the base station host to generate a frame synchronization signal, and synchronously sends the frame synchronization signal to all slave devices. The slave device triggers a reception interrupt in response to the frame synchronization signal, determines the local timestamp, and transmits the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device. The base station host determines the synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the synchronization compensation benchmark value, and sends it to each slave device through the synchronization control chip corresponding to the base station host. The slave device receives a unified start timestamp and executes the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0006] According to another aspect of the present invention, a device synchronization control system is provided, the synchronization control system comprising a base station host, a synchronization control chip and at least one slave device, wherein the base station host and each slave device are respectively communicatively connected to the corresponding synchronization control chip; The base station host is used to issue synchronization control commands, call the synchronization control chip corresponding to the base station host to generate frame synchronization signals, and synchronously send the frame synchronization signals to all slave devices. The slave device is used to respond to the frame synchronization signal triggering a reception interruption, determine a local timestamp, and transmit the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device. The base station host is also used to determine the synchronization compensation benchmark value based on the local timestamp, generate a unified start timestamp according to the synchronization compensation benchmark value, and send it to each slave device through the synchronization control chip corresponding to the base station host; The slave device is also used to receive a unified start timestamp and execute target control instructions according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the device synchronization control method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the device synchronization control method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, embodiments of the present invention also provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the device synchronization control method of any embodiment of the present invention.

[0010] The technical solution of this invention involves a base station host issuing a synchronization control command, which calls the corresponding synchronization control chip to generate a frame synchronization signal. This frame synchronization signal is then synchronously sent to all slave devices. Each slave device responds to the frame synchronization signal by triggering a reception interrupt, determining its local timestamp, and sending it back to the base station host based on its corresponding synchronization control chip. The base station host determines a synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the benchmark value, and sends it to each slave device through the corresponding synchronization control chip. Each slave device receives the unified start timestamp and executes the target control command accordingly, thus completing the collaborative synchronization control of the slave devices. This completely eliminates the transmission delay between different slave devices and the base station host, ensuring that the slave devices execute actions synchronously without timing deviations.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a device synchronization control method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of a device synchronization control method according to Embodiment 2 of the present invention; Figure 3 This is a flowchart of a device synchronization control method provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of a device synchronization control system according to Embodiment 4 of the present invention; Figure 5 This is a timing diagram of a frame synchronization signal provided according to Embodiment 4 of the present invention; Figure 6 This is a block diagram for generating a frame synchronization signal according to Embodiment 4 of the present invention; Figure 7 This is a system architecture block diagram of a device synchronization control system provided in Embodiment 4 of the present invention; Figure 8 This is a system architecture block diagram of another equipment synchronization control system provided according to Embodiment 4 of the present invention; Figure 9 This is an example diagram of a data transmission process provided in Embodiment 4 of the present invention; Figure 10 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention; Figure 11 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention; Figure 12 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention; Figure 13 This is a schematic diagram of a device synchronization control system according to Embodiment 5 of the present invention; Figure 14 This is a schematic diagram of another equipment synchronization control system provided in Embodiment 5 of the present invention; Figure 15 This is a schematic diagram of another equipment synchronization control system provided in Embodiment 5 of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1 This is a flowchart of a device synchronization control method according to Embodiment 1 of the present invention. This embodiment is applicable to the situation of synchronizing multiple slave devices. The method can be executed by a synchronization control system, which can be implemented in hardware and / or software. The synchronization control system includes a base station host, a synchronization control chip, and at least one slave device. The base station host and each slave device are respectively communicatively connected to their corresponding synchronization control chip. Figure 1 As shown, the method includes: S110. The base station host issues a synchronization control command to call the corresponding synchronization control chip of the base station host to generate a frame synchronization signal, and then sends the frame synchronization signal to all slave devices synchronously.

[0017] The base station host is the synchronization timing decision center of the entire system, responsible for issuing synchronization control commands, receiving feedback data from slave devices, calculating latency compensation, and issuing a unified start timestamp. Slave devices refer to the controlled execution units of the synchronization control system; generally, there can be one or more slave devices. In actual operation, slave devices may include, but are not limited to, servo motor stations and terminal execution devices. The synchronization control chip refers to the dedicated timing synchronization communication chip that accompanies both the base station host and each slave device. It is responsible for synchronization-related signal processing and data relay, ensuring the stability and timing accuracy of communication between the master and slave devices. Synchronization control commands are instructions issued by the base station host. Generally, synchronization control commands may include timing configuration parameters, such as the configuration information of registers in the synchronization control chip. Synchronization control commands can be used to control the synchronization control chip to generate frame synchronization signals. Frame synchronization signals are pulse signals generated by the synchronization control chip corresponding to the base station host.

[0018] In this embodiment, the base station host can generate synchronization control commands and then send them to its own associated synchronization control chip. After receiving the synchronization control commands, the synchronization control chip receives and parses the timing configuration parameters in the commands through its internal interface forwarding module. It then configures the internal registers of the synchronization control chip using these parameters. The interface forwarding module of the synchronization control chip determines the signal pull-up time and pulse width according to the parameters configured in the internal registers, generates a frame synchronization signal, and synchronously sends the frame synchronization signal to all slave devices, ensuring that all slave devices receive the frame synchronization signal at the same time. In actual operation, when the base station host, synchronization control chip, and all slave devices are powered on normally, and the communication links between the devices are connected normally, the base station host can generate synchronization control commands.

[0019] S120: The slave device triggers a receive interrupt in response to the frame synchronization signal, determines the local timestamp, and transmits the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device.

[0020] The local timestamp refers to the precise time value calculated after the slave device triggers a receive interrupt in response to the frame synchronization signal. In practice, the current timestamp recorded at the instant the receive interrupt is triggered is the actual time when the slave device receives the frame synchronization signal. The internal path loopback time is then determined, and the difference between the current timestamp and the internal path loopback time is used as the local timestamp. In one embodiment, the synchronization control chip includes a communication interface and an interface forwarding module. The interface forwarding module includes at least an Advanced High-performance Bus Interface (AHB) and a time processing unit. The communication interface refers to the external physical communication link integrated on the synchronization control chip, such as a General Purpose Input / Output (GPIO) link, which is the data transmission channel between the synchronization control chip and the base station host and slave devices. The interface forwarding module is used for command reception and data generation and forwarding. The Advanced High-performance Bus Interface (AHB) is used for high-speed data interaction between the synchronization control chip and the base station host (or slave device). It can receive synchronization control commands, timing configuration parameters, and start commands issued by the base station host and forward these commands to the time processing unit. The Time Processing Unit (TPU) is used to generate frame synchronization signals. Generally, the TPU has built-in programmable registers.

[0021] In this embodiment, after the slave device receives the frame synchronization signal, it will trigger a reception interrupt. At this time, the current timestamp and the internal path loopback time can be determined. The local timestamp is determined according to the current timestamp and the internal path loopback time. The slave device can send the determined local timestamp to its own matching synchronization control chip. The synchronization control chip transmits the local timestamp back to the base station host through its communication interface.

[0022] S130. The base station host determines the synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the synchronization compensation benchmark value, and sends it to each slave device through the synchronization control chip corresponding to the base station host.

[0023] The synchronization compensation benchmark value refers to the unified delay compensation standard value obtained by the base station host after receiving the local timestamp transmitted back from the slave device, and after filtering and calculation. The unified start timestamp refers to the globally unified execution time generated by the base station host based on the synchronization compensation benchmark value.

[0024] In this embodiment, after receiving the local timestamps returned by all slave devices, the base station host can first filter the data, eliminating abnormal data such as timestamps caused by transmission failures or hardware malfunctions, and then determine the local timestamps that meet a preset threshold as candidate timestamps. The base station host calculates the transmission delay value corresponding to each candidate timestamp. Generally, the transmission delay value is the difference between the time when the base station sends the frame synchronization signal and the candidate local timestamp. The candidate timestamp with the largest transmission delay value is determined as the unified start timestamp and sent to its own matching synchronization control chip. The synchronization control chip synchronously sends the unified start timestamp to all slave devices through its communication interface.

[0025] S140. Receive a unified start timestamp from the slave device and execute the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0026] In this context, the target control command refers to the specific action command that the slave device needs to execute. Generally, the target control command can be issued by the base station host. For example, the target control command may include, but is not limited to, the rotation angle of the servo motor, the running speed, and the start and stop of the terminal device.

[0027] In this embodiment, each slave device receives a unified start timestamp from the base station host via its own associated synchronization control chip. Generally, the synchronization control chip can forward the received unified start timestamp to the slave device's master control unit, ensuring that the slave master control unit can obtain the unified execution time in a timely manner. The slave device monitors its local system time in real time, and when the local time reaches the moment corresponding to the unified start timestamp, it immediately executes the target control command pre-issued by the base station host.

[0028] In this embodiment of the invention, the base station host issues a synchronization control command, which calls the corresponding synchronization control chip of the base station host to generate a frame synchronization signal. The frame synchronization signal is then synchronously sent to all slave devices. The slave devices respond to the frame synchronization signal by triggering a reception interrupt, determining their local timestamp, and sending the local timestamp back to the base station host based on the corresponding synchronization control chip. The base station host determines a synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the synchronization compensation benchmark value, and sends it to each slave device through the corresponding synchronization control chip. The slave devices receive the unified start timestamp and execute the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave devices. This completely eliminates the transmission delay between different slave devices and the base station host, and the slave devices will execute actions synchronously without any timing deviation.

[0029] In one embodiment, the interface forwarding module in the synchronization control chip further includes: an Advanced Scalable Interface to Memory interface, a transmit buffer random access memory, a receive buffer random access memory, a data conversion bridge, and an asynchronous bridge.

[0030] Among them, the Advanced Scalable Interface to Memory Interface is used for bidirectional data interaction between the base station host and the transmit buffer random access memory, as well as between the base station host and the receive buffer random access memory. The transmit buffer random access memory is connected to the advanced extensible interface to memory interface for temporarily storing business data to be sent out. The receive buffer random access memory is connected to the advanced extensible interface to the memory interface for temporary storage of externally accessed service data; The data conversion bridge is connected to the transmit buffer random access memory and the receive buffer random access memory respectively, and is used to convert the service data output from the transmit buffer random access memory into serial data adapted to the serial peripheral interface. The asynchronous bridge connects to the high-performance bus interface to resolve the asynchronous issue between the internal clock of the interface forwarding module and the high-performance bus interface clock.

[0031] In this embodiment, the Advanced eXtensible Interface (AXI) is responsible for bidirectional data interaction between the base station host and the buffer unit (including transmit buffer RRAM and receive buffer RRAM), serving as a data relay station connecting the host and the buffer. The transmit buffer RRAM temporarily stores control commands, timing configuration parameters, and service data to be transmitted from the base station host, preventing data loss or congestion due to excessively fast data transmission and ensuring stable transmission of subsequent data via the data conversion bridge. The receive buffer RRAM (receive buffer RAM) temporarily stores data fed back from external sources (such as slave devices) and then transmits it to the base station host via the AXI interface for data analysis. The data conversion bridge can convert wide data to narrow data, adapting to SPI / QSPI interface transmission. It is used to resolve the asynchronous issue between the internal clock of the interface forwarding module and the high-performance bus interface clock, ensuring stable data transmission of the interface forwarding module.

[0032] Example 2 Figure 2 This is a flowchart of a device synchronization control method according to Embodiment 2 of the present invention. This embodiment is a further optimization and extension based on the above embodiments, and can be combined with various optional technical solutions in the above embodiments. Figure 2 As shown, the method includes: S210, Send synchronization control commands through the base station host.

[0033] S220: Receives synchronization control commands from the base station host via the high-performance bus interface, extracts the timing configuration parameters contained in the synchronization control commands, and configures the register parameters of the internal registers in the time processing unit according to the timing configuration parameters.

[0034] The advanced high-performance bus interface serves as a high-speed command transmission channel between the synchronization control chip and the base station host, used for receiving and forwarding commands and timing configuration parameters. Preset timing configuration parameters define the timing of the frame synchronization signal, primarily including the signal rising edge delay and pulse duration. Internal registers refer to the internal storage units of the timing processing unit, used to store the timing configuration parameters and ensure consistent timing output.

[0035] In this embodiment, the synchronization control chip receives synchronization control commands through the high-performance bus interface in its interface forwarding module. The synchronization control chip parses the received synchronization control commands, extracts timing configuration parameters, and writes the extracted timing configuration parameters into the internal registers within the time processing unit, thus completing the register parameter configuration.

[0036] S230: The timing trigger signal is generated by the timing processing unit according to the register parameters.

[0037] Among them, the timing trigger signal refers to the start timing reference signal generated by the timing processing unit according to the timing configuration parameters, which serves as the start switch for generating the frame synchronization signal.

[0038] In this embodiment, the time processing unit can read the register parameters in the internal register in real time and generate timing trigger signals according to a preset period.

[0039] S240. The time processing unit generates a frame synchronization signal according to the timing trigger signal, and sends the frame synchronization signal to all slave devices synchronously through the communication interface.

[0040] In this embodiment, after receiving the timing trigger signal, the time processing unit can determine the signal's pull-up time and pulse width according to the register parameters stored in its internal registers, and finally generate a frame synchronization signal that conforms to a preset standard. The frame synchronization signal is then transmitted to the communication interface (such as a GPIO interface) of the synchronization control chip, and simultaneously sent to all slave devices in the system through the communication interface, ensuring that all slave devices can receive a unified time reference signal at the same time.

[0041] In one embodiment, a frame synchronization signal is generated by a time processing unit according to a timing trigger signal, and the frame synchronization signal is synchronously sent to all slave devices via a communication interface, including: The timing processing unit responds to the timing trigger signal, calls the timing configuration parameters stored in the internal register to determine the signal pull-up time and pulse width, and generates a frame synchronization signal.

[0042] The signal pull-up moment refers to the precise time point at which the frame synchronization signal transitions from a low level to a valid high level, used to unify the timing alignment start point across the entire network. The pulse width is the duration for which the valid high level of the frame synchronization signal is maintained, ensuring that the slave device can stably identify the synchronization reference signal.

[0043] In this embodiment, when the timing processing unit receives a timing trigger signal, it immediately responds to the trigger signal, actively retrieves the timing configuration parameters stored in the internal register, and generates a frame synchronization signal according to the signal pull-up time and pulse width. In one embodiment, the rising edge pull-up time and the pulse width are both equal to the product of the timing configuration parameters in the register and one cycle of the clock signal.

[0044] S250. After receiving the frame synchronization signal, the slave device triggers a receive interrupt, collects the current timestamp, determines the internal path loopback time, and uses the difference between the current timestamp and the internal path loopback time as the local timestamp.

[0045] The current timestamp refers to the original timing value of the slave system read in real time at the moment the slave interrupt is triggered, which is the actual moment when the slave device receives the frame synchronization signal. The internal path loopback time refers to the fixed inherent delay caused by the internal signal routing or circuit response of the slave device, which is an inherent error of the device.

[0046] In this embodiment, after receiving the frame synchronization signal from the base station host via its own synchronization control chip, the slave device immediately triggers its own receive interrupt, suspends the currently executing non-core tasks, and collects the raw timing values ​​of its local system in real time. This value is the current timestamp. The internal path loopback time is retrieved, and the difference between the current timestamp and the internal path loopback time is determined as the local timestamp.

[0047] S260: The local timestamp is sent to the base station host through the corresponding synchronization control chip of the slave device.

[0048] In this embodiment, after the slave device completes the correction of its local timestamp, it sends the local timestamp to its own matching synchronization control chip. The synchronization control chip then sends the local timestamp back to the base station host through its communication interface.

[0049] S270. The base station host determines local timestamps that are less than a preset threshold as candidate timestamps, determines the delay value corresponding to each candidate timestamp, and determines the candidate timestamp corresponding to the maximum delay value as the unified start timestamp, which is then sent to each slave device through the synchronization control chip corresponding to the base station host.

[0050] The preset threshold refers to the upper limit of normal communication latency set in advance by the base station host, used to filter invalid, excessively large timestamp data caused by transmission anomalies or equipment failures. Generally, the preset threshold can be set according to business needs. Candidate timestamps refer to valid local timestamps that meet the normal latency range after filtering and can participate in synchronization calculations. The latency value refers to the time difference between the frame synchronization time sent by the base station host and the corrected local timestamp of the slave device, representing the actual master-slave transmission delay.

[0051] In this embodiment, after receiving the local timestamps returned by all slave devices, the base station host, based on a pre-set threshold, filters out local timestamps with values ​​less than the threshold and uses them as candidate timestamps. The base station host calculates the difference between the time when it sends the frame synchronization signal and each candidate timestamp as the corresponding delay value. From all the delay values ​​corresponding to the candidate timestamps, the host selects the candidate timestamp with the highest value and determines it as the unified start timestamp for the entire network. This unified start timestamp is then sent to each slave device through the synchronization control chip corresponding to the base station host.

[0052] S280: Receive a unified start timestamp from the slave device and execute the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0053] In this embodiment of the invention, a synchronization control command is issued by a base station host. An advanced high-performance bus interface receives the synchronization control command, extracts the timing configuration parameters contained in the synchronization control command, configures the register parameters of the internal registers in the time processing unit according to the timing configuration parameters, generates a timing trigger signal according to the register parameters, generates a frame synchronization signal according to the timing trigger signal, and synchronously sends the frame synchronization signal to all slave devices via the communication interface. This achieves precise control of the rising edge pull-up time and pulse width of the frame synchronization signal based on the timing configuration parameters, avoiding the signal timing deviation problem in traditional synchronization schemes and providing a unified and accurate time reference for all slave devices. Upon receiving the frame synchronization signal, the slave device triggers a receive interrupt, collects the current timestamp, and determines the internal... The loopback time is calculated by using the difference between the current timestamp and the internal loopback time as the local timestamp. The slave device sends its local timestamp to the base station host via its corresponding synchronization control chip, effectively eliminating latency errors in the slave's own hardware path and ensuring accurate latency data transmitted back to the base station host. The base station host determines local timestamps below a preset threshold as candidate timestamps, determines the latency value corresponding to each candidate timestamp, and determines the candidate timestamp corresponding to the maximum latency value as the unified start timestamp. This unified start timestamp is then sent to each slave device via the corresponding synchronization control chip. Upon receiving the unified start timestamp, the slave device executes the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave devices, completely eliminating transmission latency between different slave devices and the base station, and achieving synchronization of multiple slave devices.

[0054] Example 3 Figure 3 This is a flowchart of a device synchronization control method according to Embodiment 3 of the present invention. This embodiment is a further optimization and extension based on the above embodiments, and can be combined with various optional technical solutions in the above embodiments. Figure 3 As shown, the method includes: S310: Send synchronization control commands through the base station host.

[0055] S320 receives synchronization control commands from the base station host through the high-performance bus interface, extracts the timing configuration parameters contained in the synchronization control commands, and configures the register parameters of the internal registers in the time processing unit according to the timing configuration parameters.

[0056] S330 receives startup commands from the base station host via an advanced high-performance bus interface.

[0057] The start command refers to a dedicated command issued by the base station host to trigger the generation of frame synchronization signals. It serves only as a trigger command for the time processing unit to start the frame synchronization signal generation process and can be issued independently according to business needs.

[0058] In this embodiment, after the base station host completes the issuance of the synchronization control command and confirms the configuration of the internal register parameters of the time processing unit, it can issue a start command. The start command can be transmitted at high speed to the synchronization control chip through the high-performance bus interface, and then forwarded to the time processing unit by the high-performance bus interface.

[0059] S340 generates a frame synchronization signal based on the start instruction and register parameters through the time processing unit, and sends the frame synchronization signal to all slave devices synchronously via the communication interface.

[0060] In this embodiment, after receiving the start command forwarded by the high-performance bus interface, the time processing unit can immediately respond to the trigger, actively retrieve the timing configuration parameters in its internal register, and combine the timing configuration parameters to precisely control the waveform of the frame synchronization signal, determine the signal pull-up time and pulse width, and finally generate the frame synchronization signal. The frame synchronization signal is then synchronously sent to all slave devices via the communication interface.

[0061] S350: After receiving the frame synchronization signal, the slave device triggers a receive interrupt, collects the current timestamp, determines the internal path loopback time, and uses the difference between the current timestamp and the internal path loopback time as the local timestamp.

[0062] S360: The local timestamp is sent to the base station host through the corresponding synchronization control chip of the slave device.

[0063] S370. The base station host determines local timestamps that are less than a preset threshold as candidate timestamps, determines the delay value corresponding to each candidate timestamp, and determines the candidate timestamp corresponding to the maximum delay value as the unified start timestamp, which is then sent to each slave device through the synchronization control chip corresponding to the base station host.

[0064] S380: Receive a unified start timestamp from the slave device and execute the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0065] In this embodiment of the invention, a synchronization control command is issued by a base station host and received via an advanced high-performance bus interface. Timing configuration parameters contained in the synchronization control command are extracted, and register parameters in the internal registers of the time processing unit are configured according to these parameters. A start command issued by the base station host is received via the advanced high-performance bus interface. The time processing unit generates a frame synchronization signal based on the start command and register parameters, and synchronously sends the frame synchronization signal to all slave devices via the communication interface. This enables the generation of frame synchronization signals triggered by the start command according to user needs, ensuring timely generation of frame synchronization signals as required by services.

[0066] Example 4 Figure 4 This is a schematic diagram of a device synchronization control system according to Embodiment 4 of the present invention. This embodiment, based on the above embodiments, uses a servo station / user chip as a slave device, a host peripheral interface as an interface forwarding module, and a host as a base station host to further illustrate a device synchronization control method. The core of this invention is a host port interface (HPI) with a frame synchronization (FS) signal, i.e., an interface forwarding module. This module is integrated between the base station and the servo station, serving as an intermediate forwarding layer for SPI / QSPI communication. It is also equipped with a multi-device synchronization control method, achieving multi-device synchronous communication through a "hardware trigger + software collaboration" approach. The interface forwarding module supports both master and slave modes for transmission and reception, and has built-in dual 1KB cache RAM, adaptable to multi-clock domain scenarios such as AXI 400MHz, AHB 200MHz, and SPI 100MHz. When the FS signal is used to end the interrupt pulse output from GPIO, its rising edge pull-up time and pulse width can be configured through two built-in registers. The rise time and pulse width are both equal to (register configuration value × one cycle of HPI_CLK). When the peer device (slave device) receives the FS pulse, it enters interrupt handling. The software acquires the timestamp and subtracts the internal path loopback time. The timestamp can be system time or Coordinated Universal Time (UTC). Timestamp accuracy depends on the accuracy of the peer software; using hardware timestamps can significantly improve accuracy.

[0067] like Figure 4 As shown, the system includes: The user chip, the synchronization control chip (Hillstream Chip), and the base station host (not shown in the diagram, connected to the Hillstream Chip via the bottom AXI bus and AHB bus) are all part of the system. The TPU (Time Processing Unit) generates periodic trigger signals (Tx_REQ) to provide a hardware clock source for data transmission and synchronization. The Hillstream Chip (synchronization control chip) includes AHB_SLAVE (AHB interface) to configure internal registers and supports cross-clock domain processing. Due to asynchronous processing from the AHB clock domain to the HPI clock domain, the configuration gap must be greater than 5ns. It generates a programmable FS signal, supporting attribute configuration (END high level / CSN), pulse width adjustment, and defining frame boundaries. It also converts AHB bus signals into level or pulse signals usable by internal submodules. The AXI2MEM (AXI to MEM interface) enables communication between the system AXI bus and the module's internal cache RAM, facilitating the transfer of wide data (128 bits). The MEM2SPI_BRIDGE (data conversion bridge) converts 128-bit wide data into 8-bit narrow data, adapting to SPI / QSPI interface transmission. The hardware latency is 645ns / 128bit, a fixed delay caused by the serial-to-parallel conversion logic during the frame header transition from the MEM2SPI_bridge to the QSPI / SPI interface. TPRAM Tx (1KB) is the transmit buffer RAM, temporarily storing pending service data to prevent data overflow. TPRAM Rx (1KB) is the receive buffer RAM, temporarily storing received service data and isolating the receiving and processing flow. The SPI / QSPI module implements serial transmission and reception of 8-bit data, communicating with the servo station externally through GPIO interfaces (SCK, CSN, MOSI, MISO). The AHB_ASYNC_BRIDGE (asynchronous bridge) resolves the asynchronous issue between the HPI internal clock and the AHB bus clock, ensuring reliable transmission of configuration commands.

[0068] The Hillstream Chip (synchronization control chip) includes a service data path and a synchronization and control path. The service data path is the bidirectional data transmission and reception between the base station host and slave devices. This is a high-speed channel carrying service data (such as control commands and acquired data), and its core components are the AXI2MEM (Advanced Scalable Interface to Memory Interface) and MEM2SPI_BRIDG (data conversion bridge) within the HPI module.

[0069] The AXI2MEM connects to an external AXI BUS and serves as the data entry / exit point for the host. It is responsible for writing data sent by the host into TPRAM Tx (1KB transmit buffer RAM, i.e., receive buffer random access memory) and reading data from TPRAM Rx (1KB receive buffer RAM, i.e., transmit buffer random access memory) and returning it to the host.

[0070] TPRAM Tx temporarily stores data to be sent from the master, isolating the data from the master's write speed and SPI transmission speed difference to prevent data loss. TPRAM Rx temporarily stores data returned from the slave, isolating the timing conflicts between SPI reception and master reading. MEM2SPI_BRIDGE (Memory to SPI Conversion Bridge): Transmit direction: Converts the 128-bit wide data output from TPRAM Tx into the 8-bit narrow data required by SPI, while introducing a fixed hardware delay. Receive direction: Converts the 8-bit narrow data received from SPI into 128-bit data and writes it to TPRAM Rx.

[0071] The communication interface (SPI controller + GPIO interface) completes the serial data transmission and reception, and communicates directly with the UserChip (slave device) through GPIO pins. The synchronization and control path (frame synchronization signal transmission) is the core channel for realizing multi-device synchronization. It is dominated by the TPU (Time Processing Unit) and is responsible for generating and transmitting frame synchronization signals.

[0072] Module and Signal Flow: AHB_ASYNC_BRIDGE (AHB Asynchronous Bridge) resolves the cross-clock domain issue between the external AHB BUS and the internal HPI clock, ensuring stable transmission of host configuration commands. AHB_SLAVE (AHB Slave Interface) receives synchronization control commands and timing configuration parameters from the host and writes them to its internal registers. It receives the TX_REQ trigger signal from the TPU and generates frame synchronization signal-related control. The TPU (Time Processing Unit) receives the timing configuration parameters written by AHB_SLAVE and completes register configuration. Combining the configuration parameters and the start command from the host, it generates the FS (Frame Sync) signal. The GPIO interface (FS / CSn pin) directly outputs the FS signal generated by the TPU to the User Chip (slave device) as a synchronization trigger reference. The Rx_IRQ GPIO pin reports the SPI receive completion interrupt signal to the host, notifying the host to read the data returned by the slave.

[0073] In one embodiment, Figure 5 This is a timing diagram of a frame synchronization signal provided according to Embodiment 4 of the present invention. Figure 5As shown, HPI_CLK is the master clock of the HPI module, controlling the synchronization of request, delay, and set signals, and serving as the reference clock for the entire send request link. Tx_REQ_dly is the delayed send request, delayed by two HPI_CLK cycles for cross-clock domain synchronization. Tx_REQ_set is the level signal generated by the internal logic of the send request pulse within the HPI module. TPU_CLK is the operating clock of the Time Processing Unit (TPU), used to control data transmission, counters, and the generation of frame synchronization signals. Tx_Trans is the "enable" level signal for transmission validity, generally used to describe software operation switches. After Tx_REQ_set is triggered, Tx_Trans goes high to start data transmission; it goes low after transmission is complete. SPI_RAM_DATA is data read from the TPRAMTx buffer, ready to be sent via SPI. After Tx_Trans goes high, the data is read in segments, divided into two frames, DATA1 and DATA2, as shown in the diagram. Trans_CNT is a data bit counter that starts counting from 0. It increments sequentially (1→2→…→7) after Tx_Trans goes high, with each count representing one unit of data transmitted. Once full, it returns to 0, and the next round of transmission begins. End_CNT is a transmission end counter that starts counting after Trans_CNT has accumulated all the data in DATA1 (1→2→3→4→5). When the count ends, it indicates that DATA1 transmission is complete and is used to trigger the subsequent frame synchronization signal. In one embodiment, when Tx_Trans goes high and data transmission begins, FS goes low (indicating the start of a frame). When End_CNT finishes counting (DATA1 transmission ends), FS goes high (indicating the end of a frame). When the next round of DATA2 transmission begins, FS goes low again, and this cycle repeats.

[0074] In one embodiment, Figure 6 This is a block diagram illustrating the generation of a frame synchronization signal according to Embodiment 4 of the present invention. Figure 6 As shown, TPU_REQ is the trigger signal (timing trigger signal) issued by the TPU, CSR_START is the trigger signal configured by the register, START_SEL is the selection level signal (start instruction) configured by the register, FS_CNT0 is the rising edge delay parameter, and FS_CNT1 is the FS signal pulse width parameter. The first-stage register receives the start signal output from the multiplexer at its D terminal, and the C terminal is the HPI_CLK clock, used to synchronize the asynchronous start signal to the HPI_CLK clock domain. The second-stage register receives the output of the first-stage flip-flop at its D terminal, and the C terminal is the HPI_CLK clock, used to completely eliminate metastability and output a stable frame synchronization start signal. In one embodiment, the timestamp acquisition scheme includes: if a large frame interval, such as 1ms, is used, then software timestamps are used directly. A timestamp is generated directly upon receiving an FS pulse. The timestamp accuracy depends on the software response time; alternatively, hardware timestamps, such as high-precision timers, are used. Upon receiving an FS pulse, the current count value is recorded at regular intervals and stored in a register for software retrieval.

[0075] In one embodiment, the timestamp calculation delay compensation method includes: During the initialization phase, a maximum-length data packet is sent. After receiving the FS interrupt, the servo device timestamps (local timestamp) and sends the timestamp value back to the base station host. After receiving the timestamps from different servo stations, the base station host takes the reasonable value with the largest delay (if the timestamp difference is too large, it will be retransmitted). Then, it uniformly distributes the timestamp delay values ​​of each servo station.

[0076] If software timestamps are used, the peer device records the current UTC time in software after receiving the FS pulse via GPIO and feeds it back to the host via the QSPI interface. This timestamp is then uniformly uploaded to the main control base station upon receipt. If hardware timestamps are used, the FS signal is used as the trigger signal for hardware logic timestamp generation.

[0077] When performing the timestamp calculation above, the transmission delays in the sending and receiving directions within the data path must be consistent, and the hardware path delay must be fixed. The HPI module has been specifically designed to address these two points, such as fixed frame intervals and negotiated fixed frame lengths, and since there is no internal buffer, there is no random hardware path delay. The start-transmission trigger signal is triggered only after the TXFIFO and RX FIFO are ready, and it can be flexibly adjusted to avoid time jitter caused by inconsistent start times.

[0078] In one embodiment, Figure 7 This is a system architecture block diagram of a device synchronization control system provided according to Embodiment 4 of the present invention. Figure 7As shown, the MCU Master is the main controller unit, the control center of the system, running the synchronization control algorithm and issuing control commands and data. QSPI is a four-wire serial peripheral interface, the control / data channel between the MCU Master and the synchronization control chip, used for configuring parameters and issuing commands. The synchronization control chip integrates an HPI module, a TPU timing unit, an SPI controller, etc., responsible for generating frame synchronization signals, implementing data transmission and reception, and timing control. HPI is the host peripheral interface, the physical interface for external communication of the synchronization control chip, used to establish links with each servo slave station. The base station host's synchronization control chip establishes bidirectional communication with the synchronization control chips of each servo slave station through HPI, realizing the transmission and reception of service data (control commands, acquired data). Frame synchronization signal link (broadcast): The base station host's synchronization control chip generates a frame synchronization signal (FS), which is broadcast to all servo slave station synchronization control chips via HPI, triggering all slave stations to simultaneously collect their local timestamps, achieving multi-device timing alignment. The slave station expansion diagram 1...N-1 indicates that the system supports expansion to N servo slave stations. All slave stations share the same set of frame synchronization signals, realizing collaborative synchronization control of large-scale devices.

[0079] In one embodiment, the master-slave switching logic is that the master sends a chip select signal CSN, and the slave receives the chip select signal.

[0080] 1. Negotiate dynamic master-slave switching at the application layer. Before each business transmission, send a negotiation operation code to agree on the master-slave structure.

[0081] 2. Fixed master-slave architecture with one transmitter and one receiver. After each data packet is transmitted, the system automatically switches to slave receiver mode. Only the master-slave structure needs to be fixed during initialization.

[0082] In traditional QSPI transmission, such as that of STMicroelectronics MCUs, the master cannot detect whether the slave has prepared the data when reading it, which can easily lead to underflow errors or reading residual data. Furthermore, when the master sends data, it cannot synchronize the sending and ending times of multiple masters, causing the QSPI interface to only transmit simple register data and not the service flow data packets required for communication between the two ends. This invention solves these two major problems by using the FS signal and the dedicated Rx_IRQ signal.

[0083] For example, in a certain industrial control transmission scenario, Figure 8 This is a system architecture block diagram of another equipment synchronization control system provided according to Embodiment 4 of the present invention, such as... Figure 8As shown, the timestamp (TS) is used. During the initialization phase, after receiving the initialization command, the server station's main control chip creates a timestamp, TS1, and uploads it along with the path to the base station's main control chip. Upon receiving TS1 from each server station, the base station first checks for values ​​with excessively large differences (greater than 5%). If a difference is found, it initiates an abnormal latency troubleshooting procedure. If no abnormal timestamps are found, the base station sends out a timestamp TS2, which is greater than the slowest TS1 plus the path delay. Upon receiving TS2, each server station sends out terminal operation commands at TS2, ensuring all server station terminals start up simultaneously.

[0084] The SPI / QSPI interface forwarding module and multi-device synchronization control method proposed in this invention have the following significant technical effects and advantages compared with existing general-purpose SPI / QSPI interfaces: By combining hardware FS synchronization signal + timestamp acquisition + software delay compensation, the time jitter problem in multi-device communication is completely solved. The working clock frequency is 400MHz, the fixed delay of the hardware path in the module is 600ns, and the software processing delay can achieve microsecond-level synchronization accuracy. Calculated with a 1K-byte data packet, the overall transmission delay is within 50 microseconds, which fully meets the requirements of highly synchronized scenarios such as industrial robots and humanoid robots. It greatly improves the stability and accuracy of multi-axis / multi-joint collaborative control, realizes precise synchronization of multiple devices, and breaks through performance bottlenecks. Meanwhile, it features dual 1KB independent cache RAM to achieve isolated storage of transmitted and received data, completely avoiding data flushing and loss issues; it is equipped with a dedicated data conversion bridge and cross-clock domain processing module, compatible with multi-clock domain scenarios, and solves transmission errors caused by clock mismatch; the hardware FS signal clearly defines frame boundaries, replacing custom SOP / EOP, reducing frame recognition error rate, improving data transmission reliability, and reducing the probability of failure.

[0085] It supports programmable configuration of multiple parameters such as master-slave mode, SPI / QSPI switching, FS signal attributes, transmission length, and frame interval, and can flexibly adapt to different scenarios such as base station-servo station communication, multi-joint control of industrial robots, distributed control of humanoid robots, and multi-axis industrial control. No hardware architecture modification is required, and its adaptability and flexibility far exceed existing interfaces, offering high flexibility and covering multiple business scenarios. It replaces the traditional manual latency calculation method, realizing an automated synchronization process of automatic hardware triggering, automatic timestamp acquisition, and automatic software calculation of compensation values, improving synchronization efficiency and meeting the low-latency, high-efficiency requirements of real-time control. The synchronization process is simplified, and control efficiency is improved. Through distributed communication and buffer design, the communication pressure on the base station is reduced. Each servo station can indirectly achieve information interaction through the HPI module, supporting the distributed deployment architecture of multi-axis control systems. At the same time, the distributed communication node design reduces the risk of single-point failure, significantly improving system fault tolerance and reducing system risk. The HPI module is a standardized, reusable independent module, integrated with the standard AXI / AHB bus and GPIO interface. Users do not need to redevelop SPI / QSPI synchronous communication logic, reducing hardware development costs and shortening product development cycles.

[0086] In one embodiment, Figure 9 This is an example diagram of a data transmission process provided in Embodiment 4 of the present invention, as shown below. Figure 9 As shown, when reading data as the master in Direct Memory Access (DMA) mode, if DMA receive-direction interrupts are enabled, data can only be read from the Rx_FIFO after an interrupt is detected. Data can only be read from the slave after an Rx_IRQ is detected, and transmission is initiated using register configuration. Before reading actual service data from the slave, the size of the service data needs to be negotiated via a custom protocol.

[0087] The Slave QSPI external slave device uses a serial interface, which is the physical source of data and sends serial data to the master side. The four-wire serial peripheral controller on the QSPI master side is responsible for receiving the serial data and performing initial parsing. The MEM2SPI_bridge is a memory-SPI bridge module that performs bit-width conversion from serial to parallel data, adapting to the subsequent FIFO format. The 1KB buffer on the RxFIFO (1KByte) receiver is used to isolate the rate difference between the SPI and AXI sides, preventing data loss. The brite_axi2mem AXI bus-to-memory bridge module converts the data in the FIFO into AXI bus transactions, initiating the write to SRAM. The AXI BUS system-level high-level scalable interface bus carries the final data transmission, writing the data to SRAM. SRAM (Static Random Access Memory) serves as the final storage location for the data, allowing the CPU to read and process it. The Rx IRQ is a receive completion interrupt signal; after data reception and buffering are complete, it sends an interrupt request to the CPU, notifying it to read the data and avoiding polling overhead. CPU / BD is the system control unit. The CPU handles interrupts and reads data from SRAM. BeiDou (BD) is responsible for wireless data forwarding and encoding / decoding, i.e., the BeiDou wireless encoding / decoding module, which differs from the wired transmission of HPI in inter-rack networking. HPI does not require descriptor processing; CPU instructions are directly issued to HPI registers.

[0088] The slave device sends its data back serially to the QSPI controller on the base station host side via the Slave QSPI interface. The MEM2SPI_bridge converts the serial data to parallel format and temporarily stores it in the Rx FIFO (Receive Buffer Random Access Memory), resolving the rate mismatch between SPI and AXI. When the FIFO data volume reaches a threshold, the brite_axi2mem module initiates a write operation via the AXI BUS, writing the data to the system SRAM. After the interrupt notification phase is completed, the Rx IRQ signal goes high, notifying the CPU to read the data from the SRAM, completing the entire slave data back transmission process. Data flows in from the bottom SlaveQSPI (Slave-side peripheral interface), undergoes bit width conversion, buffering, and bridging, and is finally written to the system memory SRAM via the AXI BUS, simultaneously generating an interrupt notification for CPU processing. The complete flow of the receive link is SlaveQSPI → QSPI controller → MEM2SPI_bridge → RxFIFO → brite_axi2mem → AXIBUS → SRAM, accompanied by an RxIRQ interrupt signal reported to the CPU.

[0089] In one embodiment, Figure 10 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention, as shown below. Figure 10 As shown, when the host sends data in DMA mode, if DMA_TX_IRQ is enabled, data can only be moved into Tx_FIFO after an interrupt is detected. The TPU triggers this process. The service data to be sent is stored in SRAM. The CPU configures the transmission parameters, obtains the raw data through the BD Beidou wireless codec module, and stores it in the system SRAM, awaiting HPI forwarding. The brite_axi2mem module reads data from SRAM via AXI BUS and writes it to the Tx FIFO (transmit buffer random access memory) for temporary storage, resolving the rate mismatch between AXI and SPI. The TPU generates a Tx_REQ signal based on the configured timing parameters or the start command issued by the host, triggering the MEM2SPI_bridge to start reading data from the FIFO and converting the parallel data into a serial format. The converted serial data is sent to the Slave QSPI through the QSPI controller, simultaneously outputting an FS frame synchronization signal as the trigger reference for the slave device to collect its local timestamp, achieving timing alignment across multiple devices.

[0090] In one embodiment, Figure 11 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention, as shown below. Figure 11 As shown, when sending data as a slave device, the master and slave must negotiate the size and quantity of data to be transmitted before sending the actual service packet data, and configure the data size in the Spi_Data_len register. If DMA is used, it is necessary to wait for CR3.tx_dma_bsy to go low and for RX_IRQ to be sent to the master before transmission can begin. The service data to be transmitted is stored in SRAM. The CPU issues a Start command via AXI BUS to configure the transmission parameters. The brite_axi2mem module reads data from SRAM via AXI BUS and writes it to the Tx FIFO (transmit buffer random access memory) for temporary storage, resolving the rate mismatch between AXI and SPI. MEM2SPI_bridge reads the parallel data in the FIFO and converts it into the serial format required by the SPI interface. The converted serial data is sent to the Master QSPI via the QSPI controller. After the transmission is completed, the Rx IRQ signal goes high to notify the CPU that the transmission has ended.

[0091] In one embodiment, Figure 12 This is an example diagram of another data transmission process provided in Embodiment 4 of the present invention, as shown below. Figure 12As shown, when receiving data as a slave device, after register configuration, the slave continuously receives data sent by the master in a streaming manner and passes it through to the Rx_FIFO. The application layer protocol needs to strictly limit the amount of data transmitted and the frame interval to prevent overflow errors. The slave device sends the return data serially to the QSPI controller on the base station host side through the Master QSPI interface. The MEM2SPI_bridge converts the serial data into a parallel format and writes it to the Rx FIFO (Receive Buffer Random Access Memory) for temporary storage, resolving the rate mismatch issue between SPI and AXI. When the FIFO data volume reaches the threshold, the brite_axi2mem module initiates a write operation through AXIBUS to write the data to the system SRAM. After transmission is complete, the CPU reads the data from the SRAM through AXI BUS, completing the slave's return data reception process.

[0092] Example 5 Figure 13 This is a schematic diagram of a device synchronization control system according to Embodiment 5 of the present invention. Figure 13 Taking two slave devices as an example, the system includes: a base station host 10, a synchronization control chip, and at least one slave device 20. The base station host and each slave device are respectively connected to the corresponding synchronization control chip 30. Among them, the base station host 10 is used to issue synchronization control commands, call the synchronization control chip 30 corresponding to the base station host to generate frame synchronization signals, and synchronously send the frame synchronization signals to all slave devices.

[0093] Slave device 20 is used to respond to a frame synchronization signal triggering a reception interruption, determine a local timestamp, and transmit the local timestamp back to the base station host based on the synchronization control chip 30 corresponding to the slave device.

[0094] The base station host 10 is also used to determine the synchronization compensation benchmark value based on the local timestamp, generate a unified start timestamp according to the synchronization compensation benchmark value, and send it to each slave device through the synchronization control chip 30 corresponding to the base station host. The slave device 20 is also used to receive a unified start timestamp and execute target control instructions according to the unified start timestamp in order to complete the collaborative synchronization control of the slave devices.

[0095] The technical solution of this invention involves a base station host issuing a synchronization control command, which calls the corresponding synchronization control chip to generate a frame synchronization signal. This frame synchronization signal is then synchronously sent to all slave devices. Each slave device responds to the frame synchronization signal by triggering a reception interrupt, determining its local timestamp, and sending it back to the base station host based on its corresponding synchronization control chip. The base station host determines a synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the benchmark value, and sends it to each slave device through the corresponding synchronization control chip. Each slave device receives the unified start timestamp and executes the target control command accordingly, thus completing the collaborative synchronization control of the slave devices. This completely eliminates the transmission delay between different slave devices and the base station host, ensuring that the slave devices execute actions synchronously without timing deviations.

[0096] In one embodiment, Figure 14 This is a schematic diagram of another equipment synchronization control system provided according to Embodiment 5 of the present invention. Figure 14 As shown, the synchronization control chip 30 includes a communication interface 31 and an interface forwarding module 32. The interface forwarding module 32 includes at least an advanced high-performance bus interface 321 and a time processing unit 322.

[0097] The advanced high-performance bus interface 321 is used to receive synchronization control commands issued by the base station host, extract timing configuration parameters contained in the synchronization control commands, and configure the register parameters of the internal registers in the time processing unit according to the timing configuration parameters. The timing processing unit 322 is used to generate timing trigger signals according to the register parameters; The time processing unit 322 is also used to generate a frame synchronization signal according to the timing trigger signal, and to synchronously send the frame synchronization signal to all slave devices based on the communication interface.

[0098] In one embodiment, the timing processing unit 322 is used to respond to the timing trigger signal, call the timing configuration parameters stored in the internal register to determine the signal pull-up time and pulse width, and generate a frame synchronization signal.

[0099] In one embodiment, the advanced high-performance bus interface 321 is used for: Receive the synchronization control command issued by the base station host 10, extract the timing configuration parameters contained in the synchronization control command, and configure the register parameters of the internal register in the time processing unit according to the timing configuration parameters; Receive the start command sent by the base station host; The time processing unit 322 is also used to generate a frame synchronization signal based on the start instruction and register parameters, and to synchronously send the frame synchronization signal to all slave devices 20 via the communication interface.

[0100] In one embodiment, the slave device 20 is configured to: Upon receiving the frame synchronization signal, a receive interrupt is triggered, the current timestamp is collected, and the internal path loopback time is determined. The difference between the current timestamp and the internal path loopback time is used as the local timestamp. The local timestamp is sent to the base station host 10 via the synchronization control chip 30 corresponding to the slave device.

[0101] In one embodiment, the base station host 10 is configured to: Local timestamps less than a preset threshold are selected as candidate timestamps. The delay value corresponding to each candidate timestamp is determined. The candidate timestamp corresponding to the maximum delay value is selected as the unified start timestamp. The unified start timestamp is then sent to each slave device through the synchronization control chip corresponding to the base station host.

[0102] In one embodiment, Figure 15 This is a schematic diagram of another equipment synchronization control system provided according to Embodiment 5 of the present invention. Figure 15 As shown, the interface forwarding module 32 in the synchronous control chip 30 also includes: an advanced scalable interface to memory interface 323, a transmit buffer random access memory 324, a receive buffer random access memory 325, a data conversion bridge 326, and an asynchronous bridge 327. Among them, the Advanced Scalable Interface to Memory Interface 323 is used for bidirectional data interaction between the base station host and the transmit buffer random access memory 324, and between the base station host and the receive buffer random access memory 325. The transmit buffer random access memory 324 is connected to the advanced scalable interface to memory interface 323 and is used to temporarily store service data to be sent out. The receive buffer random access memory 325 is connected to the advanced scalable interface to memory interface 323 for temporarily storing externally accessed service data. The data conversion bridge 326 is connected to the transmit buffer random access memory 324 and the receive buffer random access memory 325 respectively, and is used to convert the service data output from the transmit buffer random access memory into serial data adapted to the serial peripheral interface. The asynchronous bridge 327 is connected to the high-performance bus interface 321 to solve the asynchronous problem between the internal clock of the interface forwarding module and the clock of the high-performance bus interface.

[0103] The equipment synchronization control system provided in the embodiments of the present invention can execute the equipment synchronization control method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0104] Example 6 This invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a device synchronization control method applied to a synchronization control system. The synchronization control system includes a base station host, a synchronization control chip, and at least one slave device. The base station host and each slave device are communicatively connected to their respective synchronization control chip. The method includes: The base station host issues a synchronization control command, calls the synchronization control chip corresponding to the base station host to generate a frame synchronization signal, and synchronously sends the frame synchronization signal to all slave devices. The slave device triggers a reception interrupt in response to the frame synchronization signal, determines the local timestamp, and transmits the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device. The base station host determines the synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the synchronization compensation benchmark value, and sends it to each slave device through the synchronization control chip corresponding to the base station host. The slave device receives a unified start timestamp and executes the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

[0105] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute a device synchronization control method described in the various embodiments of the present invention.

[0106] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein. In one embodiment, the present invention also includes a computer program product, which includes a computer program that, when executed by a processor, implements the device synchronization control method of any embodiment of the present invention.

[0107] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0108] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0109] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for synchronous control of equipment, characterized in that, An application is made to a synchronization control system, the synchronization control system comprising a base station host, a synchronization control chip, and at least one slave device, wherein the base station host and each slave device are respectively communicatively connected to a corresponding synchronization control chip, the method comprising: The base station host issues a synchronization control command, calls the synchronization control chip corresponding to the base station host to generate a frame synchronization signal, and synchronously sends the frame synchronization signal to all slave devices. The slave device triggers a reception interrupt in response to the frame synchronization signal, determines the local timestamp, and transmits the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device. The base station host determines the synchronization compensation benchmark value based on the local timestamp, generates a unified start timestamp according to the synchronization compensation benchmark value, and sends it to each slave device through the synchronization control chip corresponding to the base station host. The slave device receives a unified start timestamp and executes the target control command according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

2. The method according to claim 1, characterized in that, The synchronization control chip includes a communication interface and an interface forwarding module. The interface forwarding module includes at least an advanced high-performance bus interface and a time processing unit. The synchronization control chip corresponding to the base station host generates a frame synchronization signal and synchronously sends the frame synchronization signal to all slave devices, including: The system receives synchronization control commands from the base station host through the high-performance bus interface, extracts timing configuration parameters contained in the synchronization control commands, and configures the register parameters of the internal registers in the time processing unit according to the timing configuration parameters. The timing processing unit generates a timing trigger signal according to the register parameters. The time processing unit generates a frame synchronization signal according to the timing trigger signal, and then sends the frame synchronization signal to all slave devices synchronously through the communication interface.

3. The method according to claim 2, characterized in that, The step of generating a frame synchronization signal according to a timing trigger signal through the time processing unit, and synchronously sending the frame synchronization signal to all slave devices via the communication interface, includes: The timing processing unit responds to the timing trigger signal, calls the timing configuration parameters stored in the internal register to determine the signal pull-up time and pulse width, and generates a frame synchronization signal.

4. The method according to claim 2, characterized in that, The synchronization control chip corresponding to the base station host generates a frame synchronization signal and synchronously sends the frame synchronization signal to all slave devices, and also includes: The system receives synchronization control commands from the base station host through the high-performance bus interface, extracts timing configuration parameters contained in the synchronization control commands, and configures the register parameters of the internal registers in the time processing unit according to the timing configuration parameters. The system receives the startup command issued by the base station host through the high-performance bus interface. The time processing unit generates a frame synchronization signal based on the start command and the register parameters, and then sends the frame synchronization signal to all slave devices synchronously via the communication interface.

5. The method according to claim 1, characterized in that, The step of triggering a receive interrupt in response to the frame synchronization signal by the slave device, determining a local timestamp, and transmitting the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device includes: Upon receiving the frame synchronization signal, the slave device triggers a receive interrupt, collects the current timestamp, determines the internal path loopback time, and uses the difference between the current timestamp and the internal path loopback time as the local timestamp. The local timestamp is sent to the base station host via the corresponding synchronization control chip of the slave device.

6. The method according to claim 1, characterized in that, The step of determining a synchronization compensation benchmark value based on the local timestamp by the base station host, generating a unified start timestamp according to the synchronization compensation benchmark value, and distributing it to each slave device through the synchronization control chip corresponding to the base station host includes: The base station host determines local timestamps that are less than a preset threshold as candidate timestamps, determines the delay value corresponding to each candidate timestamp, and determines the candidate timestamp corresponding to the maximum delay value as the unified start timestamp. The unified start timestamp is then sent to each slave device through the synchronization control chip corresponding to the base station host.

7. The method according to claim 1, characterized in that, The interface forwarding module in the synchronous control chip further includes: an advanced extensible interface to memory interface, a transmit buffer random access memory, a receive buffer random access memory, a data conversion bridge, and an asynchronous bridge; The Advanced Scalable Interface-to-Memory Interface is used for bidirectional data interaction between the base station host and the transmit buffer random access memory, and between the base station host and the receive buffer random access memory. The transmit buffer random access memory is connected to the Advanced Scalable Interface to memory interface and is used to temporarily store service data to be sent out. The receive buffer random access memory is connected to the Advanced Scalable Interface to memory interface and is used to temporarily store externally accessed service data. The data conversion bridge is connected to the transmit buffer random access memory and the receive buffer random access memory respectively, and is used to convert the service data output by the transmit buffer random access memory into serial data adapted to the serial peripheral interface. The asynchronous bridge is connected to the high-performance bus interface and is used to solve the asynchronous problem between the internal clock of the interface forwarding module and the clock of the high-performance bus interface.

8. A synchronous control system for equipment, characterized in that, The synchronization control system includes a base station host, a synchronization control chip, and at least one slave device. The base station host and each slave device are respectively connected to the corresponding synchronization control chip. The base station host is used to issue synchronization control commands, call the synchronization control chip corresponding to the base station host to generate frame synchronization signals, and synchronously send the frame synchronization signals to all slave devices. The slave device is used to respond to the frame synchronization signal triggering a reception interruption, determine a local timestamp, and transmit the local timestamp back to the base station host based on the synchronization control chip corresponding to the slave device. The base station host is also used to determine the synchronization compensation benchmark value based on the local timestamp, generate a unified start timestamp according to the synchronization compensation benchmark value, and send it to each slave device through the synchronization control chip corresponding to the base station host; The slave device is also used to receive a unified start timestamp and execute target control instructions according to the unified start timestamp to complete the collaborative synchronization control of the slave device.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the device synchronization control method according to any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the device synchronization control method according to any one of claims 1-7.

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