A method and system for clock synchronization

Abstract

This invention discloses a clock synchronization method and system, belonging to the field of clock synchronization. The method comprises: executing at least two measurement processes, each measurement process acquiring a first associated time value between a first reference clock and a first local clock of a master device at a corresponding measurement time; for each measurement process executed by the master device, after receiving the corresponding first associated time value, the slave device executes a corresponding measurement process once to acquire a second associated time value between a second reference clock and a second local clock of the slave device at the corresponding measurement time; based on the first associated time value and the corresponding second associated time value from at least two different measurement processes, determining the synchronization deviation between the second local clock and the first local clock; calibrating the first local clock and / or the second local clock according to the synchronization deviation; the first reference clock and the second reference clock are clock sources that maintain clock synchronization with each other. This invention can reduce synchronization errors and improve clock synchronization accuracy.

Description

Technical Field

[0001] This invention relates to the technical field of clock synchronization, and more particularly to a clock synchronization method and system. Background Technology

[0002] In the field of communication equipment, clock synchronization is the key to ensuring system stability and reliable information transmission. It ensures that the receiving end can correctly identify the data sent by the transmitting end by keeping the transmitting and receiving end devices consistent in time, frequency and phase, thus avoiding information loss or bit errors.

[0003] To achieve clock synchronization between devices, a commonly used clock synchronization method is as follows: the transmitting device sends a timestamp to the receiving device at a fixed frequency. After receiving the timestamp, the receiving device uses a high-frequency timer to count and correct and compensate its own clock, thereby synchronizing the clocks of the transmitting and receiving devices.

[0004] However, due to the inevitable delay fluctuations and complex environmental interferences such as electromagnetic interference and signal attenuation during wireless communication, the timestamps received by the receiving device often deviate. The above-mentioned methods directly use the received timestamps for clock correction and compensation without processing the timestamp deviations. This causes the deviations to be further accumulated and amplified during the correction process, ultimately resulting in low clock synchronization accuracy and poor stability, which cannot meet the requirements of high-precision wireless communication systems. Therefore, how to improve the accuracy of clock synchronization in wireless communication environments has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a clock synchronization method and system, aiming to solve the problem of how to improve clock synchronization accuracy in wireless communication environments.

[0006] To address the aforementioned technical problems, the embodiments of this application disclose the following technical solutions: A first aspect of this invention provides a clock synchronization method applied to a system including a master device and a slave device, the method comprising: At least two measurement processes are executed. In each measurement process, the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time is obtained, and the first associated time value is sent to the slave device. For each measurement process executed by the master device, after receiving the corresponding first associated time value, the slave device executes the corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time; Based on the first associated time value from at least two different measurement processes and the corresponding second associated time value, the synchronization deviation between the second local clock and the first local clock is determined; The first local clock and / or the second local clock are calibrated according to the synchronization deviation. The first reference clock and the second reference clock are clock sources that keep each other synchronized.

[0007] A second aspect of the present invention provides a clock synchronization system, the system comprising: The master device acquisition module is used to execute at least two measurement processes. In each measurement process, the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time is acquired, and the first associated time value is sent to the slave device. The slave device acquisition module is used for each measurement process executed by the master device. After receiving the corresponding first associated time value, the slave device executes a corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time. The deviation determination module is used to determine the synchronization deviation between the second local clock and the first local clock based on the first associated time value from at least two different measurement processes and the corresponding second associated time value; A calibration module is used to calibrate the first local clock and / or the second local clock according to the synchronization deviation; The first reference clock and the second reference clock are clock sources that keep each other synchronized.

[0008] Compared to existing technologies, the clock synchronization method and system provided in this invention offer the following advantages: By introducing clock synchronization modules into both the master and slave devices, this invention reconstructs the traditional synchronization process, which relies on cross-device wireless transmission timestamps, into an internal device synchronization alignment operation. The master device executes at least two measurement processes, each acquiring a first associated time value between the master device's first reference clock and its first local clock at the corresponding measurement moment. For each measurement process executed by the master device, the slave device, upon receiving the first associated time value, executes the corresponding measurement process to acquire a second associated time value. This ensures that critical data is generated internally, avoiding deviations introduced by delay fluctuations or environmental interference during wireless transmission. The synchronization deviation between the master device's first local clock and the slave device's second local clock is calculated using the first associated time value and the corresponding second associated time value, and the clock is calibrated. Therefore, this method architecturally reduces the impact of cross-device signal transmission delay on key synchronization data, ensures data reliability through a unified synchronization triggering and recording mechanism, and eliminates reliance on the real-time transmission accuracy of wireless timestamps for clock synchronization, significantly improving synchronization accuracy and system stability. Attached Figure Description

[0009] Figure 1 This is a schematic flowchart of a clock synchronization method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the main device terminal provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the slave device structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a master device and several slave devices provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a connection between a master device and a slave device via GPIO wires according to an embodiment of the present invention; Figure 6 This is a schematic diagram of level changes provided in an embodiment of the present invention; Figure 7 This is an operation flowchart of the master device and slave device provided in an embodiment of the present invention; Figure 8 This is an interactive operation flowchart of a first type of master-slave architecture provided in an embodiment of the present invention; Figure 9 This is an interactive operation flowchart of a second type of master-slave architecture provided in an embodiment of the present invention; Figure 10 This is an interactive operation flowchart of a third type of master-slave architecture provided in an embodiment of the present invention; Figure 11This is an interactive operation flowchart of the fourth type of master-slave architecture provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of a device for synchronizing the clock of a smart device according to an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] In the field of wireless device clock synchronization, traditional methods typically rely on the master device periodically sending timestamp signals to the slave device. Upon receiving the timestamp, the slave device uses a local high-frequency timer to count and compensate for clock fluctuations, achieving clock synchronization between the two ends. The industry generally recognizes that latency fluctuations and environmental interference (such as electromagnetic interference and signal attenuation) during wireless transmission affect the accuracy of timestamps, and therefore strives to improve synchronization accuracy by optimizing timestamp transmission frequency, enhancing error correction coding mechanisms, or improving clock compensation algorithms. However, these improvements have always revolved around the idea of ​​"how to perform more accurate correction based on transmission with interference," failing to overcome the fundamental constraint on the reliability of critical synchronization data inherent in the cross-device transmission process itself.

[0012] The inventors of this application, through in-depth analysis of the synchronization error generation path, discovered that existing methods tightly couple the timestamp generation time with the cross-device wireless transmission time. This exposes the timestamp value to channel interference as soon as it leaves the master device, making the deviation undetectable and uneliminable at the receiving end. This means that even with more sophisticated correction algorithms, the input reference itself is already distorted, and all subsequent processing may amplify the error. The essence of this problem is not simply timestamp transmission error or insufficient correction, but rather that the critical moment information upon which high-precision synchronization depends is placed in an unreliable transmission stage within the synchronization architecture. The industry has long focused on the post-transmission correction stage, failing to realize that by shifting the reference point for time recording from "after cross-device transmission" back to "the instant of triggering by the internal hardware of each device," the impact of transmission interference on the reference data can be avoided at the source.

[0013] This identification of the root cause of the problem requires breaking away from the long-standing technical inertia surrounding the optimization of transmission and correction, and re-examining the possibility of decoupling the spatiotemporal relationship between "data generation" and "data transmission" in clock synchronization.

[0014] In view of this, embodiments of this application provide a clock synchronization method and system, which aims to ensure data reliability through hardware-level simultaneous recording, so that the clock synchronization process no longer depends on easily interfered wireless timestamps, significantly improving synchronization accuracy and system stability.

[0015] To address the aforementioned issues, a clock synchronization method and system provided in this application will be described in detail and explained below through specific embodiments.

[0016] Reference Figure 1 This illustration shows a flowchart of a clock synchronization method provided in an embodiment of this application. This application provides a clock synchronization method applied to a system including a master device and slave devices. The system can be, for example, a conference call system where the master device is a conference host and the slave devices are wireless microphones, requiring synchronization of the audio sampling clocks of each microphone; it can also be a scenario where the master device is a conference host and the slave devices are wireless cameras, requiring synchronization of the camera video frame clock and the host audio clock; it can also be a scenario where the master device is any device with clock reference capability among cameras, wireless microphones, or wireless speakers, and the slave devices are one or more of the remaining microphones, speakers, or cameras, requiring synchronization of the local clocks of each slave device based on the master device's local clock; it can also be a scenario where the master device is the main conference host and the slave devices are branch conference terminals, requiring synchronization of audio clocks across conference venues; or it can be a scenario requiring clock synchronization between devices, such as a wireless speaker system or a distributed data acquisition system.

[0017] In one embodiment, the clock synchronization method may include the following steps: S11. Execute at least two measurement processes. In each measurement process, obtain the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time, and send the first associated time value to the slave device. The sending method can be broadcast, multicast, or unicast. In some application scenarios of this application embodiment, the master device and the slave device can communicate through a WiFi network, so the first associated time value can be encapsulated in UDP or TCP packets for transmission. "Reference clock" refers to a clock source integrated inside the device (master device or slave device) that has the ability to synchronize with the reference clock of another external device. The reference clock acts as a "common time scale" in this invention to measure the frequency characteristics of their respective local clocks. The reference clock can originate from the device's internal wireless communication module (such as a WiFi TSF timer, Bluetooth local clock, Zigbee MAC timer), a wired network time synchronization protocol (such as an IEEE 1588 PTP hardware timestamp unit), or an external time synchronization system (such as a GPS second pulse and its counter). In this application embodiment, "reference clock" is a higher-level concept and does not limit the specific physical implementation.

[0018] A "local clock" refers to the internal clock of a device used to drive its core functions (such as audio playback, audio acquisition, and data sampling). This clock is typically generated by hardware such as crystal oscillators and phase-locked loops, and is the object that needs to be "synchronized" or used as a "reference" in this invention. Unlike a reference clock, a local clock does not require natural synchronization with the clocks of other devices, and its frequency may have errors.

[0019] "Associated time value" refers to a pair of clock readings that are correlated in time and acquired by the same device (master or slave) during a single measurement process. Specifically, an associated time value includes a reference clock value and a local clock value obtained from a single sampling. The associated time value is the basic data unit for subsequent calculations of time difference and frequency ratio. The two values ​​can be acquired at the same physical moment (e.g., through hardware triggering) or sequentially within a preset time tolerance window; as long as the two readings have a definite temporal correlation, they can constitute an associated time value.

[0020] Those skilled in the art will understand that the associated time value can be a timestamp pair, a synchronization data pair, or any other two values ​​that are time-related by a reference clock and a local clock.

[0021] S12. For each measurement process executed by the master device, after receiving the corresponding first associated time value, the slave device executes a corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time.

[0022] The first reference clock is a reference clock located on the master device side. The master device obtains the reading of the common time scale on the master device side by reading the value of the first reference clock. The second reference clock is a reference clock located on the slave device side. The first reference clock and the second reference clock keep clock synchronized with each other (e.g., through the protocol mechanism of accessing the same wireless network). Therefore, the readings of the two at any physical moment are equal or differ by a known fixed offset.

[0023] The first local clock is the local clock located on the master device side. In typical audio application scenarios, the first local clock is the audio playback clock (DAC working clock) of the master device. It is usually used as the frequency reference of the entire system. It has high stability and is generally not frequently adjusted. The second local clock is the local clock located on the slave device side. In typical audio application scenarios, the second local clock is the audio acquisition clock (ADC working clock) of the slave device. Its frequency needs to be calibrated to follow the first local clock.

[0024] The first associated time value is the associated time value obtained by the master device at a certain measurement moment in a measurement process, which includes the reading of the first reference clock and the reading of the first local clock; the second associated time value is the associated time value obtained by the device at another measurement moment in a measurement process, which includes the reading of the second reference clock and the reading of the second local clock.

[0025] "Master device" refers to the core device in the clock synchronization method described in this application, which is a timing reference source, integrates an audio clock source and a wireless device, and can output a synchronization reference signal. The master device plays a core role in initiating the clock source, issuing synchronization signaling, and calibrating the audio sampling timing. It sends synchronization instructions and a first associated time value to the slave devices, providing a unified clock reference for the entire audio link.

[0026] A "slave device" refers to a subordinate device that follows the timing reference of the master device, receives synchronization signals, and completes its own audio clock calibration. The slave device plays the role of clock following, deviation compensation, and audio timing matching. By receiving the synchronization command and the first associated time value issued by the master device, the slave device obtains the second associated time value, and calculates the synchronization deviation between the slave device's local audio clock and the master device's local audio clock. This achieves alignment with the master device's audio sampling and playback timing, ensuring zero latency and no echo distortion in audio transmission and reception between multiple devices.

[0027] The master device can also be called an audio reference device, synchronization initiator device, master clock device, etc. Its core feature is that the master device has a priority clock reference and can actively output a synchronization signal as the sole reference standard for all slave devices to perform audio clock calibration and sampling alignment.

[0028] The slave device, also known as an audio follower device, a synchronously controlled device, or a slave clock device, is a device that uses the master device's audio clock as its sole reference, does not independently serve as a timing reference, and maintains consistent audio timing with the master device. All such devices fall under the category of this embodiment.

[0029] In the field of video conferencing, the master device or slave device can be any audio and video processing device with the ability to generate audio clock sources and distribute synchronous signaling, such as a host, speaker or microphone. There can be one master device and one or more slave devices. This application does not limit this.

[0030] A "measurement process" refers to a complete data acquisition process initiated by the master device and ultimately responded to by the slave device. A measurement process includes: the master device acquiring a first associated time value and sending it to the slave device; the slave device receiving the value and acquiring a corresponding second associated time value. Therefore, executing N measurement processes will generate N first associated time values ​​and N corresponding second associated time values. In this embodiment, at least two measurement processes need to be executed. This embodiment can be applied to scenarios where the master and slave devices synchronize their clocks in a video conferencing system. By executing at least two measurement processes, the time deviation between the two devices is accurately calculated, and clock synchronization calibration is completed based on the time deviation. The master and slave devices execute the measurement processes sequentially. The master device's measurement process involves its local clock and reference clock acquiring the first associated time value corresponding to the measurement moment and sending the time value to the slave device. The slave device's measurement process involves receiving the time value from the master device, then its local clock and reference clock acquiring the second associated time value corresponding to the measurement moment, completing the measurement process for the number of times the master device's process is executed. This may include cases where only two measurement processes are executed or cases where multiple measurement processes are executed repeatedly.

[0031] When the clock synchronization method performs only two measurement processes, the interval between the two measurement processes must fall within the preset time error. The first and second associated time values ​​collected in the first measurement process and the first and second associated time values ​​collected in the second measurement process are used to calculate the time deviation between the local clocks of the master and slave devices.

[0032] When the clock synchronization method only executes multiple measurement processes, and the multiple measurement processes are repeatedly executed according to preset trigger conditions or cycles, two measurement processes constitute one large cycle. The interval between two measurement processes within a large cycle must be within a preset time error. The first and second associated time values ​​collected in the first measurement process and the first and second associated time values ​​collected in the second measurement process are used to calculate the time deviation between the local clocks of the master and slave devices. However, there is no time limit between adjacent large cycles.

[0033] Among these, by filtering valid large-cycle samples and removing abnormal fluctuation samples, the time deviation can be calculated using the same logic based on the associated time values ​​of two measurement processes within any valid large-cycle; alternatively, the calculation results of multiple large-cycles can be fused to further improve measurement stability.

[0034] It should be noted that the two embodiments described above differ only in the number of executions. The core calculation principles used are exactly the same, both relying on the time values ​​obtained from the two measurement processes to calculate the time deviation and following the timing rules. The only difference lies in the number of large loop executions. The core measurement method and timing constraint logic are consistent and both fall within the protection scope of this invention.

[0035] S13. Based on the first associated time value from at least two different measurement processes and the corresponding second associated time value, determine the synchronization deviation between the second local clock and the first local clock.

[0036] "Synchronization bias" refers to the frequency deviation of the slave device's second local clock relative to the master device's first local clock (i.e., the difference in clock speed per unit time), or the cumulative phase shift expressed in time length. Synchronization bias can be positive (slave device clock too fast), negative (too slow), or zero (perfectly synchronized). Once the synchronization bias is calculated, it can be eliminated by adjusting the clock source frequency or digitally resampling the data. Since at least two measurement procedures have been performed, the master device generates at least two first associated time values ​​(corresponding to the first and second measurements, respectively), and the slave device generates at least two corresponding second associated time values. Based on these associated time values ​​from different measurement procedures, the slave device (or master device, or cloud server) calculates the synchronization bias between the second and first local clocks. This synchronization bias reflects the direction and magnitude of the frequency deviation of the slave device's local clock relative to the master device's local clock.

[0037] S14. Based on the synchronization deviation, calibrate the first local clock and / or the second local clock. Specifically, only the second local clock of the slave device can be calibrated (so that its frequency follows the master device), or only the first local clock of the master device can be calibrated (so that the master device follows the slave device), or both can be calibrated in opposite directions simultaneously. The calibration method can be adjusting the physical frequency of the clock source (e.g., changing the crystal oscillator load capacitance, adjusting the PLL division factor), or resampling compensation of the clock-driven data in the digital domain.

[0038] In this embodiment, the first reference clock and the second reference clock are clock sources that maintain clock synchronization with each other. That is, the first reference clock (located on the master device side) and the second reference clock (located on the slave device side) are not two independent, free clocks, but are forced to maintain the same frequency and phase through an external synchronization mechanism, i.e., they maintain clock synchronization with each other. The so-called "maintaining clock synchronization with each other" means that for any given physical moment, the difference between the readings of the first reference clock and the second reference clock is always a known, negligible constant (usually zero or a fixed time offset), and this synchronization relationship remains effective during system operation, unaffected by factors such as wireless communication delays and device temperature changes.

[0039] Typical methods for achieving synchronization include, but are not limited to, the following: Protocol layer synchronization within the same wireless network: When a master device and a slave device connect to the same WiFi network, the TSF (Time Synchronization Function) timer inside the WiFi chip automatically synchronizes via beacon frames in the IEEE 802.11 protocol. The access point (AP) periodically broadcasts a beacon containing its own TSF value. All STAs (stations, including master and slave devices) receive this and adjust their own TSF to match the AP, thus synchronizing the TSF timers of all devices in the network, with an error typically within 1 microsecond. Similarly, in a Bluetooth micronet, the master device broadcasts clock information, and slave devices adjust their own clocks accordingly, achieving nanosecond-level synchronization. Zigbee networks also employ a similar beacon synchronization mechanism.

[0040] Hardware-assisted synchronization using Precision Time Protocol (PTP, IEEE 1588): In wired or dedicated wireless networks, both the master and slave devices integrate hardware timestamp units supporting PTP. The master device periodically sends Sync messages, and the slave device records the precise arrival time of these messages. By exchanging Follow_Up, Delay_Req, and Delay_Resp messages, the time offset and transmission delay between the master and slave clocks are calculated, and the slave device adjusts its own clock accordingly, ultimately achieving sub-microsecond synchronization. This method typically requires hardware assistance, but it can also be implemented purely in software (with lower precision).

[0041] Global Navigation Satellite System (GNSS) timing: Both the master and slave devices are equipped with satellite receiving modules such as GPS and BeiDou. These modules output high-precision pulse-of-seconds (PPS) and the corresponding absolute time (e.g., UTC time). The device's processor locks its local reference clock to the satellite time by capturing PPS interrupts. Since all devices' reference clocks trace back to the same satellite time system, they are naturally synchronized. This method can achieve nanosecond-level accuracy and is suitable for devices used in outdoor or open environments.

[0042] Wired synchronization signal distribution: In a distributed system, a high-frequency synchronization clock signal (such as a 10MHz sine wave or TTL pulse) is transmitted via a dedicated coaxial cable or twisted pair. All devices use a phase-locked loop (PLL) to track this signal. In this case, the internal reference clock of each device is a local multiplier or division version of the distributed signal. All devices share the same physical clock source, thus achieving strict synchronization.

[0043] Those skilled in the art will understand that the core of the embodiments of this application does not lie in the specific implementation of these synchronization mechanisms themselves, but rather in utilizing an existing synchronization reference clock guaranteed by an external mechanism as a "bridge." That is, the master device and the slave device each have a reference clock that is already synchronized with the other, and the embodiments of this application indirectly calibrate their independent local clocks by using these two synchronized reference clocks. Therefore, regardless of which method is used, as long as the first reference clock and the second reference clock meet the condition of "keeping their clocks synchronized," they fall within the protection scope of the embodiments of this application.

[0044] Those skilled in the art will understand that "keeping clocks synchronized" does not require the two reference clocks to be absolutely equal at any minute moment (because it is physically impossible to completely eliminate all jitter and drift), but rather that their long-term frequencies are consistent, and that the instantaneous deviation is much smaller than the local clock synchronization accuracy required by this invention. For example, if the goal of this invention is to synchronize the local clock to ±1 ppm, then the instantaneous deviation between the reference clocks only needs to be less than 0.1 ppm (i.e., on the order of 0.1 microseconds / second) to meet the requirement. Therefore, any synchronization means that can control the difference between the first reference clock and the second reference clock within an acceptable error range falls within the scope of this feature.

[0045] In some embodiments of this application, both the master and slave devices are WiFi devices supporting the 802.11 protocol and connected to the same WiFi network. In this case, the first reference clock and the second reference clock are the TSF timers inside their respective WiFi modules. Since the 802.11 protocol forces all STAs to maintain TSF synchronization with the AP, no additional configuration is required; the TSF timers of the master and slave devices naturally satisfy the requirement of "keeping clocks synchronized with each other." This is the most convenient and economical implementation method in the embodiments of this application.

[0046] The reference clock refers to a clock source integrated within the master or slave device that can be synchronized with the reference clock of another device. In this invention, the first reference clock is located on the master device side, and the second reference clock is located on the slave device side. The two maintain time synchronization through an external synchronization mechanism (e.g., a protocol of the same wireless communication network, such as IEEE 802.11). The reference clock acts as a "common time scale" to measure the frequency characteristics of their respective local clocks.

[0047] The reference clock can be called a base clock or network clock, or a synchronization clock source or other clock source that can keep the master and slave devices synchronized, so that the difference between the two reference clocks in the master and slave devices can truly reflect the physical time interval.

[0048] This embodiment of the application executes at least two measurement processes on the master device side. Each time, it acquires a first associated time value between a first reference clock and a first local clock at the corresponding measurement moment and sends this value to the slave device. Upon receiving each first associated time value, the slave device executes the corresponding measurement process to acquire a second associated time value between a second reference clock and a second local clock at the corresponding measurement moment. Since the first and second reference clocks are clock sources that are synchronized with each other, the two sets of first associated time values ​​obtained from the at least two measurement processes can reflect the frequency characteristics of the first local clock relative to the synchronized clock source over a certain time interval. Similarly, the two sets of second associated time values ​​reflect the frequency characteristics of the second local clock relative to the same synchronized clock source over another time interval. Based on these cross-measurement process associated data, the synchronization deviation between the second local clock and the first local clock can be calculated, and either local clock can then be calibrated.

[0049] In this embodiment, the determination of synchronization deviation no longer relies on the instantaneous transmission accuracy of a single timestamp between master and slave devices. Instead, it uses a time window formed by multiple measurements to compare the frequency drift of the two local clocks. Since the associated time value in each measurement only involves the device's internal recording of the reference clock and the local clock, and the slave device's measurement action is triggered only after receiving the associated time value from the master device, this naturally creates an order of master device priority and slave device follow-up in the entire synchronization process, avoiding phase ambiguity that may be introduced by simultaneous independent measurements from both sides. Simultaneously, by employing at least two measurement processes, the system can effectively smooth out random disturbances that may exist in a single measurement and base the core synchronization calculation on the time difference, thereby reducing the sensitivity to single message delay fluctuations in wireless transmission. Therefore, this scheme can achieve high-precision frequency synchronization of local clocks between master and slave devices through multiple sequential measurements and cross-device associated data comparisons without relying on high-precision hardware synchronization signals, significantly improving the robustness and feasibility of clock synchronization in a wireless environment.

[0050] The working principle of the embodiments of this application is illustrated below through a simplified numerical example: Assume the master device's first reference clock is absolutely accurate (e.g., WiFi TSF), and its first local clock is 0.1% faster than the real time; the slave device's second reference clock is synchronized with the first reference clock (i.e., also accurate), and its second local clock is 0.05% slower than the real time. The system performs two measurement procedures, with a real time interval of 1 second between the first and second procedures.

[0051] First measurement: The master device records (TSF1 = 1000.000000 seconds, AUDIO1 = 1001.000000 seconds) and sends it to the slave device; the slave device receives and records (TSF2 = 1000.000100 seconds, AUDIO2 = 999.999900 seconds). (Note the slight difference between TSF2 and TSF1 is due to the time required to receive and process the message, but TSF2 itself is still accurate.) Second measurement (1 second later): Master device record (TSF3=1001.000000 seconds, AUDIO3=1002.001000 seconds); Slave device record (TSF4=1001.000100 seconds, AUDIO4=1000.999400 seconds).

[0052] Calculate the difference: On the master device side, ΔTSF = 1 second, ΔAUDIO = 1.001 seconds; on the slave device side, ΔTSF = 1 second, actual ΔAUDIO = 0.9995 seconds. The frequency ratio on the master device side is R = 1.001. The slave device's expected AUDIO difference = R × ΔTSF = 1.001 seconds, while the actual difference is 0.9995 seconds, a deviation of +0.0015 seconds (i.e., the slave device is slow by 0.0015 seconds / second, equivalent to -0.15%). Based on this deviation, synchronization can be achieved by increasing the slave device's clock frequency by 0.15%. Therefore, this embodiment can accurately calculate the frequency deviation through simple arithmetic operations, without the need for complex delay measurements or bidirectional message exchange.

[0053] In some embodiments, after calculating the synchronization deviation, the slave device can also feed back a message containing the deviation information to the master device. Upon receiving the message, the master device can adjust its own first local clock according to the deviation (e.g., adjust its clock generator or perform frequency compensation in the digital domain) to achieve synchronization from the perspective of the slave device. This mode is suitable for scenarios where the master device's clock accuracy is adjustable and the slave device serves as a reference.

[0054] In some embodiments, after calculating the synchronization deviation, the slave device sends a message carrying the deviation information back to the master device. Based on this synchronization deviation, both the master and slave devices simultaneously adjust their respective local clocks: the slave device corrects its second local clock, and the master device synchronously optimizes its first local clock. Bidirectional calibration can be achieved through hardware clock configuration or digital domain frequency and phase compensation. This mode is suitable for scenarios where both the master and slave device clocks are adjustable, requiring bidirectional mutual calibration to improve the overall stability of clock synchronization.

[0055] The clock synchronization method described in the above embodiments, through the design of a feedback mechanism, enables the master device to obtain the synchronization deviation and adjust the clock path accordingly. This gives the system the freedom to select the calibration subject and calibration direction, achieving flexibility in clock synchronization. It breaks the technical bias in the traditional unidirectional synchronization architecture that "the master device clock must be used as an absolute reference and can only be aligned unidirectionally by the slave device." By utilizing the absolute symmetry of the synchronization deviation, the system can flexibly select the calibration subject according to actual needs, seamlessly switch master-slave logical roles, and configure multiple synchronization strategies. It can dynamically allocate synchronization tasks according to application scenarios, improving the flexibility of clock synchronization operation.

[0056] It is understandable that the principle of synchronization by calculating the deviation between two local clocks can theoretically be achieved by adjusting the first local clock or adjusting both clocks simultaneously. However, based on the application scenario of solving the problem of matching the microphone clock with the host clock, which is the focus of this application, the following embodiments are all illustrated using the calibration of the second local clock as an example.

[0057] In one embodiment, obtaining the first associated time value between the first reference clock and the first local clock of the master device at the corresponding measurement time includes: S111. Obtain the first clock value of the first reference clock and the second clock value of the first local clock that are associated with each other in time.

[0058] "Temporal correlation" refers to a definite and traceable temporal correspondence between the first clock value and the second clock value. This means that the time difference between their acquisition times is known, controllable, or negligible within a preset tolerance range. This correlation allows the first and second clock values ​​to be considered as clock snapshot pairs corresponding to the same measurement time or the same extremely short time period, thus providing a valid data foundation for subsequent frequency ratio calculations. In the embodiments of this application, the implementation of "temporal correlation" includes, but is not limited to, the following: acquisition at the same physical moment, that is, the first clock value and the second clock value are recorded at the same physical instant in response to the same hardware trigger event (such as GPIO level transition), and the acquisition time difference between the two is only the hardware signal propagation delay (usually on the nanosecond level), which can be regarded as strict simultaneity; acquisition within a preset time tolerance window, that is, under the condition that hardware trigger signal lines cannot be laid out, the first clock value and the second clock value are acquired sequentially within a preset time tolerance window, ensuring that the difference between the acquisition times of the two is less than the tolerance window; acquisition by synchronization instruction marker, that is, the first clock value and the second clock value are both recorded sequentially in the process triggered by the same synchronization instruction, and the order and interval between the two are determined and controllable, thus constituting temporal correlation. As long as there is a clear temporal correspondence between the first clock value and the second clock value, which can support the use of the logarithmic value as the first associated time value of a valid measurement process, it can be considered to meet the "temporal correlation" defined in this application.

[0059] In one embodiment, the master clock synchronization module can respond to the synchronization command of the main processing module, record the first reference clock at this moment, and then record the clock value of this first reference clock to obtain the first clock value. Simultaneously, the master clock synchronization module prompts the main processing module. After recognizing the prompt, the main processing module records the timestamp of the first local clock at this moment to obtain the second clock value. The prompt can be a hardware-triggered level transition signal, a software-triggered callback function call or interrupt service routine execution, or a message on the inter-processor communication interface. The core requirement for the prompt is that its transmission delay is much smaller than the interval between two measurement processes and the system's acceptable synchronization error; no specific signal type or transmission medium is limited.

[0060] The "synchronization command" refers to a synchronization trigger request initiated by the main processing module to the master clock synchronization module to start a single measurement process. The synchronization command can be a custom software command, a register write operation, or a hardware interrupt signal. The core function of the synchronization command is to mark the start time of the measurement process, enabling the master clock synchronization module to perform subsequent recording operations at a specific, traceable time node. In this embodiment, the "synchronization command" is a higher-level concept and does not limit the specific command format or transmission path. For example, the main processing module can proactively send a "start measurement" command after power-on initialization, or it can be triggered by an external application layer.

[0061] The "first clock value" refers to the reading of the first reference clock recorded by the master clock synchronization module of the master device at the moment of responding to the synchronization command during a measurement process. The first clock value and the second clock value constitute the first associated time value on the master device side. The first clock value can be called the master reference clock sampling value, the reference clock reading, or the synchronization clock snapshot. The function of the first clock value is to provide a common time scale on the master device side during this measurement process, providing a reference for subsequent calculation of time difference values ​​across measurement processes. In the embodiments of this application, the first clock value can be a TSF value; it can also be any one of the following: Bluetooth local clock value, Zigbee MAC timer value, PTP hardware timestamp value, or GPS second pulse count value; it is a hardware-level high-precision unified time base, which can achieve accurate synchronization of wireless and audio clocks at low cost, low latency, and low drift.

[0062] The "second clock value" refers to the reading of the first local clock recorded by the main processing module of the master device when it receives a prompt from the master clock synchronization module during the same measurement process. The second clock value is temporally correlated with the first clock value, and the two together constitute the first associated time value. The second clock value can be called the master local clock sampling value, the master device timestamp, or the master processing module clock snapshot. In the embodiments of this application, the second clock value is the instantaneous reading of the master device's local clock (such as the audio DAC operating clock) at the measurement moment.

[0063] A "timestamp" is a numerical value marked with a time stamp, formed by recording the instantaneous reading of a local clock at a specific moment. In this embodiment, the second clock value is the timestamp of the first local clock recorded by the main processing module, corresponding to the time when the notification occurs. The timestamp can be a counter value, a system clock cycle number, a floating-point number in seconds or microseconds, or a composite data structure containing year / month / day / hour / minute / second / sub-second fields. The specific representation of the timestamp is not limited here, as long as the value can reflect the running state of the first local clock at the corresponding physical moment and can be used to perform a difference operation with the timestamp of another moment.

[0064] After completing the above operations, the master clock synchronization module can package the first clock value and the second clock value to obtain the first associated time value. The master clock synchronization module can then send the first associated time value to several connected slave devices, or to the slave devices that need clock synchronization, thereby triggering the slave devices to execute a measurement process. Packaging can be done by concatenating the two values ​​into a message according to a preset frame format (such as filling in the message payload field sequentially), or by encapsulating the two values ​​into a data structure or object and then handing it over to the communication protocol stack for processing, or by adding auxiliary fields such as measurement flow program number, device identifier, and verification information to the two values ​​before encapsulation.

[0065] The clock synchronization method described in this embodiment proposes a novel clock synchronization architecture of "internal calibration first, then external synchronization". By obtaining the time-correlated clock values ​​of the processing module and the wireless module in the master device, a linear mapping relationship between two independent clock domains is established. This provides a unified and accurate time reference for the precise calculation of synchronization deviation between the master and slave devices, fundamentally solving the problem of synchronization deviation calculation error caused by the asynchronous internal clock of the device in traditional methods. This technical improvement not only achieves an order-of-magnitude improvement in synchronization accuracy, but also brings a series of important technical effects such as enhanced synchronization stability, reduced calibration frequency, improved cross-platform consistency, and multi-hop synchronization support. This opens up new possibilities for the widespread application of wireless clock synchronization technology in various time-sensitive fields.

[0066] In one embodiment, the first clock value and the second clock value are recorded in response to the same first trigger event so that they correspond to the same physical moment; and / or, the third clock value and the fourth clock value are recorded in response to the same second trigger event so that they correspond to the same physical moment.

[0067] In this context, a "trigger event" refers to an event that can trigger the device to begin executing the measurement process and recording clock values. When the device is the master device, the trigger event can be a synchronization command generated when the master processing module powers on and initializes, a synchronization command generated when the master processing module receives external commands, or a periodic trigger signal generated by the internal timer of the master clock synchronization module. When the device is the slave device, the trigger event can be a synchronization command generated by the slave processing module after receiving the first associated time value sent by the master device, or a periodic trigger signal generated by the internal timer of the slave clock synchronization module. It is worth noting that in this embodiment, "trigger event" is a higher-level concept, ensuring that the same trigger event acts simultaneously on the clock synchronization module and the processing module of the corresponding device, so that both record the corresponding clock values ​​at the same physical moment, rather than one module recording first and then notifying the other module to record. It does not limit the type or source of the event, nor does it limit whether it acts on the master device side or the slave device side.

[0068] "Same physical moment" refers to the instant at which a physical phenomenon or event occurs. In the embodiments of this application, since the master clock synchronization module and the main processing module capture clock values ​​through the same transition edge of the same hardware trigger signal (such as GPIO level transition), the recording operations of the two clock values ​​are synchronously driven by the same physical event (level transition), achieving clock cycle-level alignment at the hardware circuit level. Therefore, the two correspond to the same physical moment.

[0069] Compared with traditional synchronization methods, this embodiment relies on the existing wireless modules and processing modules of the master and slave devices to complete timestamp interaction, obtain the first clock value and the second clock value of the first reference clock and the first local time of the master device, and ensure that the two clock values ​​are correlated in time. By changing the position of the trigger source and the timing control method, the alignment accuracy of the clock value is improved, which solves a fundamental error source in the traditional internal clock calibration method, ensures accurate acquisition of the real clock offset, avoids additional errors introduced by sampling interval and scheduling delay, and makes the performance of wireless clock synchronization technology leapfrog. It can quickly complete the calibration of the master and slave device clocks, realize the accurate synchronization of the master and slave device clocks, and ensure that the clock calibration is accurate and effective, thus clearing the key technical obstacles for its widespread application in various time-sensitive fields.

[0070] In one embodiment, within the same measurement process, a first trigger signal is generated using the first reference clock, such that the operation of recording the first clock value is time-aligned with the operation of recording the second clock value; and / or, a second trigger signal is generated using the second reference clock, such that the operation of recording the third clock value is time-aligned with the operation of recording the fourth clock value.

[0071] Here, "trigger signal" refers to a hardware signal generated by the clock module of the reference clock, which can be simultaneously sensed by the clock synchronization module and processing module of the corresponding device, and is used to drive both ends to record their respective clock values ​​at the same physical moment. In the embodiments of this application, "trigger signal" is a higher-level concept, and its lower-level implementation can be a level transition signal (such as rising edge or falling edge), a pulse signal, a PPS second pulse signal, or an edge event on a dedicated synchronization bus, without limiting the specific waveform, amplitude, or duration of the signal.

[0072] Taking the master device side as an example, in a measurement process, the clock module of the first reference clock generates a first trigger signal. This first trigger signal is simultaneously connected to the edge detection pins of the master clock synchronization module and the main processing module via hardware traces. When the transition edge of the first trigger signal arrives, the master clock synchronization module records the reading of the first reference clock at the instant the edge detection circuit captures the event, obtaining the first clock value. At the same time, the main processing module records the reading of the first local clock under the drive of the same edge event, obtaining the second clock value. Since the two modules are synchronously driven by the same transition edge of the same hardware trigger signal, their recording operations are aligned at the hardware clock cycle level, rather than one module completing its recording and then notifying the other module to record, thus eliminating the timing deviation introduced by sequential recording at the root.

[0073] Similarly, on the slave device side, the clock module of the second reference clock generates a second trigger signal, simultaneously driving the slave clock synchronization module to record a third clock value and the slave processing module to record a fourth clock value, thus aligning the operations of recording the third clock value and recording the fourth clock value in time. The specific implementation of the second trigger signal can be referred to the first trigger signal, and will not be repeated here.

[0074] This embodiment replaces the serial method of recording first and then notifying by setting a hardware trigger signal directly generated by the reference clock. This allows the clock value recording operations of two modules within the same device to be synchronously driven by the same physical event. At the hardware circuit level, it achieves precise alignment of recording time, avoids additional errors introduced by sampling interval or scheduling delay, and provides a data foundation for subsequent cross-measurement process synchronization deviation calculation that eliminates time deviation at its source, significantly improving clock synchronization accuracy.

[0075] In one operating mode, the first triggering event can be a first hardware trigger signal generated by the clock module of the first reference clock. For example, if the first reference clock is in the main processing module, the first hardware trigger signal is generated by the main processing module; if the first reference clock is in the main clock synchronization module, the first hardware trigger signal is generated by the main clock synchronization module.

[0076] The first hardware trigger signal can be a level transition signal. In this embodiment, the first clock value and the second clock value are recorded at the same physical moment by using the level change signal as the hardware trigger signal. Level change is the most basic and instantaneous physical event in digital circuits. The transition process from low level to high level (rising edge) or from high level to low level (falling edge) only takes a few picoseconds to nanoseconds. Moreover, all modern microcontrollers (MCUs), FPGAs and application-specific integrated circuits (ASICs) have built-in dedicated edge detection hardware circuits. This circuit is directly synchronized with the clock domain of the chip and can capture the event within the first clock cycle of the level transition. This ensures that the period from triggering the level change signal to capturing the event is infinitely close, so that this embodiment can achieve the limit of hardware physical measurement accuracy at the same moment.

[0077] Reference Figure 5 This diagram illustrates a connection diagram of a master device and a slave device connected via GPIO wires according to an embodiment of the present invention.

[0078] In one embodiment, the master clock synchronization module and the master processing module of the master device are connected via GPIO wires. Similarly, the slave clock synchronization module and the slave processing module of the slave device are connected via GPIO wires. It should be noted that in one or more embodiments of this application, the GPIO wires are merely examples, and signal transmission can also be achieved through other fast-transmitting prompt information. For example, using a PPS signal line with PPS pulses as prompts can achieve fast transmission of prompt information, thereby shortening the prompt processing time of the synchronization module.

[0079] Reference Figure 6 The diagram illustrates a level change according to an embodiment of the present invention.

[0080] Taking the master device as an example: The master processing module of the master device can send a synchronization command to the master clock synchronization module. After responding to the synchronization command, the master clock synchronization module can record the first clock value at time one and simultaneously notify the master processing module, enabling the master processing module to record the second clock value. During this process, after responding to the synchronization command, the master clock synchronization module adjusts the level of any pin. The level adjustment can be a level flip or a trigger pulse. At this time, the master processing module will approximately simultaneously sense the level change and trigger the corresponding operation. The master processing module can take the time node of the level change as time two and record the timestamp at this time to obtain the second clock value.

[0081] Because the time for the level change is very short, the processing time of the synchronization module prompt can be greatly reduced.

[0082] Figure 6 The waveform above is a level-to-level inversion waveform. Figure 6 The waveform below represents a level pulse change. When the prompt is a level change, the time of the waveform change, i.e., the rising or falling edge time, is read. At this time, time one equals time two, corresponding to time one when the synchronization command is received and time two when the timestamp is recorded. When the prompt is a level pulse, the rising edge time is read. At this time, time one also equals time two, corresponding to time one when the synchronization value is recorded and time two when the timestamp is recorded. Therefore, by connecting the master clock synchronization module and the main processing module of the master device using GPIO wires, the time nodes of the first clock value and the second clock value recorded are the same.

[0083] Specifically, Figure 6 The dashed line indicates the moment when the clock synchronization module records the synchronization value. Normally, the GPIO level is stable. When the clock synchronization module needs to acquire the corresponding synchronization value, it triggers a level shift on the pin or generates a pulse signal. Simultaneously, the processing module connected to the clock synchronization module via the GPIO receives the level change or pulse signal notification and can read its own timestamp based on the level change, which is then used for subsequent clock synchronization processing.

[0084] Taking the case where the clock synchronization module is a WiFi module as an example, different devices only need to add a wire connected to a specific GPIO of the WiFi module during the hardware design process, and modify the WiFi module's firmware to add a specific instruction as a synchronization instruction. The synchronization instruction is that when the WiFi module receives the instruction from the processing module, it needs to toggle the level or send a pulse signal and simultaneously record the TSF value at the time of toggle / send. This synchronization instruction does not have to be an instruction specified by the WiFi protocol, nor is it an extended instruction of the WiFi module; it can be customized separately.

[0085] During operation, a specific instruction can be added by modifying the WiFi module's firmware. This instruction is neither a standard WiFi protocol instruction nor an extension instruction of the WiFi module; it is custom-designed. Upon receiving this instruction, the WiFi module toggles or triggers a pulse on a specific GPIO pin and records the TSF value at the moment of toggle or pulse. The host also records the audio timestamp. The WiFi module then sends the TSF value back to the instruction sender (host). This specific GPIO pin is also not included in the original WiFi module's communication; it is specifically implemented using a reserved GPIO pin that is not currently used by the WiFi module.

[0086] This establishes a common reference clock for different devices within the same wireless system. The processing module can then send commands to the WiFi module to record the GPIO toggle timestamps and the TSF value recorded by the WiFi module. Subsequently, clock synchronization can be performed based on the recorded timestamps and TSF values ​​to eliminate communication delays between different devices and reduce the impact of environmental interference.

[0087] Upon receiving the synchronization command, the WiFi module will toggle or trigger a pulse on any GPIO level or a specific GPIO level. At this time, the WiFi module can record the TSF value at the toggle or pulse moment to obtain the first clock value. The processing module, upon receiving the level toggle or pulse signal, also synchronously records the audio timestamp to obtain the second clock value.

[0088] The WiFi module then sends the TSF value back to the processing module. By utilizing GPIO, the time spent recording the reference synchronization value and timestamp can be reduced, thus speeding up clock synchronization and improving its accuracy.

[0089] It should be noted that this specific GPIO may not be included in the original WiFi module communication; rather, it may be a specific chip pin not used by the WiFi module that is connected to the processing module. This allows communication between the clock synchronization module and the processing module within the same device. Optionally, the GPIO may be a port of the GPIO wires between the master clock synchronization module and the slave clock synchronization module.

[0090] In WiFi modules, TSF stands for Timing Synchronization Function. Defined by the IEEE 802.11 Wireless Local Area Network (WLAN) standard, this function ensures timing synchronization between users. TSF operates at a 1MHz clock, which is crucial for maintaining synchronization among all devices within the basic service area. Furthermore, WiFi modules support various APIs to operate the TSF counter, thereby effectively managing various timing functions.

[0091] The IEEE 802.11 standard stipulates that clock synchronization must be performed between different Wi-Fi modules during the connection process. While connected, they are constantly being calibrated and synchronized. Therefore, the TSF (Time Sequence Flow) between the master and slave devices can be considered completely synchronized. The Wi-Fi modules of the master and slave devices are completely synchronized. The operation of this invention is performed based on the premise of Wi-Fi module synchronization to achieve clock synchronization.

[0092] Reference Figure 9In another embodiment, if neither the master nor slave device can connect to the GPIO wire, resulting in a discrepancy between the time nodes of the recorded first clock value and the second clock value, the first clock value and the second clock value can also be obtained separately within a first preset time tolerance window; the first preset time tolerance window is the acceptable time difference between the first clock value and the second clock value.

[0093] Reference Figure 10-11 This illustrates a scenario where only one of the master or slave devices can not connect to the GPIO wire. In such a scenario, the side without the GPIO wire cannot simultaneously record clock values ​​via a hardware trigger signal, resulting in a time node deviation between the first and second clock values, or between the third and fourth clock values ​​recorded on that side. In this case, the two clock values ​​on that side can be obtained separately within their respective preset time tolerance windows. As long as the difference between their acquisition times falls within this tolerance window, they are still considered to meet the condition of temporal correlation and can continue to be used for subsequent synchronization deviation calculations.

[0094] The "time tolerance window" refers to the maximum acceptable time difference between the acquisition of the reference clock value and the local clock value when there is no strict hardware simultaneous triggering capability. The time tolerance window can also be called the allowable time deviation, synchronization window, or alignment tolerance. The size of the time tolerance window is set according to the synchronization accuracy requirements of the specific application scenario: in audio echo cancellation scenarios, the time difference between the acquisition of two clock readings is usually required to be no more than 1 microsecond; while in some industrial control scenarios with lower accuracy requirements, it can be relaxed to tens of microseconds or even milliseconds. It is worth noting that the preset time tolerance window should be much smaller than the interval between two measurement processes to ensure that the error introduced by time-division recording is negligible relative to the overall synchronization accuracy requirements.

[0095] The first preset time tolerance window is the acceptable time difference range between the first and second clock values ​​on the master device side. When the time difference between the first and second clock values ​​falls within this range, the accuracy requirements for clock synchronization are met. The second preset time tolerance window is the acceptable time difference range between the third and fourth clock values ​​on the slave device side. When the time difference between the third and fourth clock values ​​falls within this range, the accuracy requirements for clock synchronization are also met. The first and second preset time tolerance windows can be set to the same value, or they can be set to different values ​​according to the hardware conditions and accuracy requirements of the master and slave devices, which is not limited in this embodiment.

[0096] The first preset time tolerance window is the time difference range between the first and second clock values. When the time difference between the first and second clock values ​​falls within this range, the clock synchronization accuracy requirement is met. Similarly, the second preset time tolerance window is the time difference range between the third and fourth clock values. When the time difference between the third and fourth clock values ​​falls within this range, the clock synchronization accuracy requirement is also met. This technical solution, under the limitations of not being able to lay connecting wires and not being able to use hardware trigger signals, achieves simultaneous capture of audio data within the allowable error range; effectively reduces timing deviations caused by wireless environmental interference, significantly improves the synchronization accuracy of the audio clock, and enhances the anti-interference capability and long-term operational stability of the wireless audio system.

[0097] It is worth noting that the first trigger signal on the master device side and the second trigger signal on the slave device side are generated independently and act independently within their respective devices, without requiring time synchronization or correlation between them. The protection scope of this application also covers the following situations: trigger signal alignment is used only on the master device side (time tolerance window method is used on the slave device side), trigger signal alignment is used only on the slave device side (time tolerance window method is used on the master device side), or both the master and slave sides use trigger signal alignment or both use time tolerance window method.

[0098] In one embodiment, during each measurement process, the master device can obtain a first associated time value (a first associated time value includes a first clock value and a second clock value). During each measurement process, the slave device can obtain a second associated time value (a second associated time value includes a third clock value and a fourth clock value).

[0099] After both the master and slave devices have completed one measurement cycle, a second measurement cycle can be executed after a preset interval. The specific operation is explained in the steps above. The main processing module sends a synchronization command to the master clock synchronization module, enabling the master clock synchronization module to respond to the synchronization command and record the first clock value.

[0100] Optionally, the preset time interval between two measurement processes can be pre-set.

[0101] When performing clock synchronization, at least two different measurement processes can be used to obtain the first associated time value and the corresponding second associated time value to determine the synchronization deviation between the slave device's second local clock and the master device's first local clock.

[0102] The two different measurement processes can be two measurement processes executed in close proximity in time. "Close proximity in time" means that the time interval between the two measurement processes is close enough that the relative drift between the two local clocks is negligible. This limitation excludes measurements with excessively large intervals, as long time intervals may introduce nonlinear factors such as temperature changes and voltage fluctuations, causing the linear proportional model to fail. In the audio synchronization application of this invention, proximity typically means that the interval between two measurement processes does not exceed 10 seconds, preferably not exceeding 1 second. Those skilled in the art can reasonably set the specific threshold for "proximity" based on the synchronization accuracy requirements of the actual application and the severity of environmental changes.

[0103] It is worth noting that the specific time interval is given only as an example. As long as the particle size is any value within the range of 0-10 seconds, it is within the protection scope of this application and can be adjusted according to actual needs.

[0104] This application uses two measurement processes executed in close proximity in time for clock tiling, which can reduce clock deviation caused by the relative drift of the local clock between the two measurement processes and further improve clock synchronization accuracy.

[0105] For example, the master device executes the first measurement procedure, the slave device executes the first measurement procedure, after a 1-second interval, the master device executes the second measurement procedure, the slave device also executes the second measurement procedure, after another 1-second interval, the master device executes the third measurement procedure, the slave device also executes the third measurement procedure, and so on. The first associated time value of the master device in the first measurement procedure and the first associated time value of the second measurement procedure are obtained. Similarly, the second associated time value of the slave device in the first measurement procedure and the second associated time value of the second measurement procedure are obtained.

[0106] As explained above, the first associated time value includes a first clock value and a second clock value. The first associated time value for at least two different measurement procedures includes the first and second clock values ​​of the first measurement procedure, and the first and second clock values ​​of the second measurement procedure. Similarly, the second associated time value includes a third clock value and a fourth clock value. The second associated time value for at least two different measurement procedures includes the third and fourth clock values ​​of the first measurement procedure, and the third and fourth clock values ​​of the second measurement procedure.

[0107] The "difference" refers to the result of subtracting two clock readings from two different measurement processes on the same device using the same clock source. It reflects the change in the clock source over a time interval. The difference is used for calculation instead of the absolute value of a single clock reading: since the first and second reference clocks are synchronized, their changes within the same physical time interval are equal. Therefore, the difference between the reference clocks acts as a "physical time interval scale." By comparing the difference of the local clock with this scale, the frequency deviation of the local clock relative to the actual time can be identified, eliminating the impact of cross-device transmission delay and absolute offset of the reference clock on synchronization calculations.

[0108] Based on the first associated time value and the corresponding second associated time value from at least two different measurement procedures, the synchronization deviation is determined, which may specifically include the following steps: S131. Based on at least two of the first associated time values, determine a first difference of the first reference clock and a second difference of the first local clock.

[0109] Specifically, the difference between the first clock value of the first measurement process and the first clock value of the second measurement process is calculated to obtain the first difference of the first reference clock; the difference between the second clock value of the first measurement process and the second clock value of the second measurement process is calculated to obtain the second difference of the first local clock.

[0110] S132. Based on at least two of the second associated time values, determine a third difference of the second reference clock and a fourth difference of the second local clock.

[0111] Specifically, the difference between the third clock value of the first measurement process and the third clock value of the second measurement process is calculated to obtain the third difference of the second reference clock; the difference between the fourth clock value of the first measurement process and the fourth clock value of the second measurement process is calculated to obtain the fourth difference of the second local clock.

[0112] S133. Determine the first frequency ratio relationship based on the second difference and the first difference.

[0113] S134. Calculate the expected time difference of the second local clock based on the first frequency ratio relationship and the third difference.

[0114] S135. Determine the synchronization deviation based on the expected time difference and the fourth difference.

[0115] "Synchronization deviation" refers to the deviation in frequency or phase of the second local clock of the slave device relative to the first local clock of the master device, used to quantify the degree of time mismatch between the two local clocks. Synchronization deviation can be expressed as frequency deviation (i.e., the difference in timekeeping speed per unit time, measured in ppm or seconds / second), phase deviation (i.e., the absolute difference between the two clock readings at a reference time, measured in seconds or clock cycles), or a function mapping phase deviation to frequency deviation. In this embodiment, "synchronization deviation" is a general concept and its specific representation is not limited, as long as the deviation reflects the degree of mismatch between the second and first local clocks and allows for calibration of at least one of the local clocks.

[0116] The methods for obtaining synchronization deviation include, but are not limited to, the following: One method is based on difference calculation. This involves determining the first, second, third, and fourth differences using the calculation steps described in S131 to S135, then sequentially determining the first frequency ratio and the expected time difference, and finally comparing these with the fourth difference to obtain the synchronization deviation. Besides the frequency ratio, this method has the advantage of being intuitive in its calculation process and relying solely on the associated time values ​​recorded by the master and slave devices in the two measurement processes. It requires no additional mathematical modeling or parameter fitting, making it suitable for embedded devices with limited computing resources.

[0117] The second method is based on a linear regression model. This involves performing the measurement process more than twice to obtain multiple sets of first-related time values ​​and corresponding second-related time values. Using the reference clock reading (third clock value) from the second-related time values ​​as the independent variable and the local clock reading (fourth clock value) from the second-related time values ​​as the dependent variable, a linear regression is used to fit the frequency slope of the second local clock relative to the second reference clock. Similarly, using the reference clock reading (first clock value) from the first-related time values ​​as the independent variable and the local clock reading (second clock value) from the first-related time values ​​as the dependent variable, the frequency slope of the first local clock relative to the first reference clock is fitted. The difference between the two frequency slopes is the synchronization deviation. Using linear regression can smooth out the random disturbances of a single measurement using multiple measurement data, improving the stability of the synchronization deviation estimation.

[0118] Thirdly, there is the Kalman filter-based acquisition method. This involves establishing a state-space model of the relative frequency drift between the local clocks of the master and slave devices. The associated time values ​​obtained from each measurement process are used as observations and input into the Kalman filter. Through recursive prediction and iterative updates, the optimal synchronization deviation value is estimated in real time. The advantage of this method is that it can dynamically track the slow changes in clock drift and has strong robustness to sudden external interference (such as occasional WiFi packet retransmission delays).

[0119] Fourth, the acquisition method is based on frequency domain analysis. This involves converting the associated time value sequence obtained from multiple measurement processes to the frequency domain using Fourier transform or wavelet transform, identifying the characteristic frequency difference components between the master and slave local clocks, and then obtaining the estimated synchronization deviation in the time domain through inverse transform. This method is suitable for application scenarios with periodic interference (such as clock jitter caused by power supply ripple).

[0120] It is worth noting that the above four acquisition methods are merely exemplary examples of synchronization deviation acquisition methods and are not mutually exclusive. Those skilled in the art can choose a combination of one or more methods based on the computing power, accuracy requirements, and environmental interference characteristics of the actual application scenario. In the embodiments of this application, regardless of the method used to acquire the synchronization deviation, as long as the underlying data is the associated time value recorded in at least two measurement processes described in this application, and the acquisition result can reflect the frequency deviation between the second local clock and the first local clock, it falls within the protection scope of this application.

[0121] This application can obtain the clock frequency difference between the master and slave devices through the above calculation, and then adjust the clock frequency of any device according to the clock frequency difference to improve the clock consistency between the master and slave devices.

[0122] In one embodiment, after determining the synchronization deviation between the second local clock and the first local clock, the first local clock of the master device can be calibrated using the synchronization deviation, the second local clock of the slave device can be calibrated, or both the first local clock of the master device and the second local clock of the slave device can be calibrated simultaneously.

[0123] Specifically, the master device can obtain the synchronization deviation through master device unicast polling, slave device active reporting, event-triggered reporting, or piggyback transmission.

[0124] Specifically, the calibration of the first local clock and / or the second local clock based on the synchronization deviation can be achieved through direct or indirect time synchronization (by adjusting the frequency, phase, or timestamp of the local clock), calibration using algorithms to compensate and correct data, clock synchronization by switching or gating to access a new clock source, clock discipline by adjusting the crystal oscillator operating conditions with control signals, or calibration by resetting the clock timestamp with a synchronization pulse, among other methods. It is worth noting that the calibration methods for clock synchronization described here are merely illustrative; any calibration method that can achieve local clock calibration for both master and slave devices is within the scope of this application.

[0125] The calibration process, which involves directly or indirectly adjusting the first local clock and / or the second local clock based on the synchronization deviation, specifically includes the following steps: S141. If the synchronization deviation is greater than zero, then the frequency of the first local clock is reduced and / or the frequency of the second local clock is increased.

[0126] S142. If the synchronization deviation is less than zero, then increase the frequency of the first local clock and / or decrease the frequency of the second local clock.

[0127] Specifically, if the synchronization deviation is greater than zero, the frequency of the first local clock can be lowered individually, or the frequency of the second local clock can be raised individually, or the frequency of the first local clock can be lowered and the frequency of the second local clock can be raised simultaneously.

[0128] Similarly, if the synchronization deviation is less than zero, the frequency of the first local clock can be increased individually, or the frequency of the second local clock can be decreased individually, or the frequency of the first local clock can be increased and the frequency of the second local clock can be decreased simultaneously.

[0129] By combining with an existing synchronous clock to achieve precise synchronization of another clock, clock consistency between master and slave devices can be improved quickly and efficiently, thereby reducing clock deviation between the two devices.

[0130] In conference call applications, the sound played by the speaker is picked up by the microphone, causing an "echo" at the other end of the call. This application, by combining existing synchronization clocks and adjusting the clock of any device, can synchronize the wireless microphone with the host clock, avoiding the "echo" phenomenon and thus improving the echo cancellation effect.

[0131] In one embodiment, the measurement process and deviation determination steps can be repeated, and clock calibration can be performed based on the determined synchronization deviation each time to achieve clock synchronization between the master device and the slave device.

[0132] For ease of understanding, the explanation will use the timestamps and reference synchronization values ​​of two communication cycles.

[0133] Specifically, the first associated time value (including the first clock value and the second clock value) sent by the master device can be obtained, and the slave device can trigger the generation of the corresponding third clock value and fourth clock value for the first time based on the first associated time value of the master device.

[0134] After waiting for a preset time, the first associated time value sent by the master device for the second time can be obtained. The slave device can generate the second third and fourth clock values ​​based on the first associated time value sent by the master device for the second time.

[0135] Next, the difference between the two first clock values ​​of the master device can be obtained to obtain the first difference value, and the difference between the two second clock values ​​of the master device can be obtained to obtain the second difference value; then the difference between the two third clock values ​​of the slave device can be calculated to obtain the third difference value, and the difference between the two fourth clock values ​​of the master device can be obtained to obtain the fourth difference value.

[0136] Based on the time synchronization relationship between the reference synchronization value and the slave device synchronization value, the deviation value of the slave device timestamp from the reference timestamp is obtained to obtain the synchronization deviation. The clock of the slave processing module is then adjusted using the synchronization deviation to achieve clock adjustment between the slave processing module and the master processing module, that is, complete clock synchronization between the master device and the slave device.

[0137] Reference Figure 7 The diagram illustrates the operation flowchart of a master device and a slave device provided in an embodiment of the present invention.

[0138] The master device is the host, and the slave device is the wireless microphone. Both the host and the wireless microphone have a built-in WiFi module. In addition to the conventional data and command buses, the host and the wireless microphone are connected to their respective WiFi modules via an additional GPIO connection to achieve the above functions.

[0139] Alternatively, any device that can receive and process audio and connect to accessories (to communicate) can be used as a host.

[0140] In scenarios where wireless microphones are synchronized with the host, the host acts as an access point (AP), connecting multiple wireless microphones. The host, the wireless microphones, and their respective WiFi modules all follow the aforementioned technical solution for functional development. The host periodically acquires the TSF value (ap_tsf) of its WiFi module and the timestamp of the DAC's operating clock (ap_audio) for audio playback, obtaining the first and second clock values ​​respectively. The host packages these two times into a time synchronization packet and periodically sends it to all connected wireless microphones. Upon receiving the time synchronization packet, each wireless microphone similarly acquires its own WiFi module's TSF value (sta_tsf) and the timestamp of the ADC's operating clock (sta_audio) for audio acquisition, obtaining the third and fourth clock values ​​respectively.

[0141] By repeating this process, the first, second, third, and fourth clock values ​​of at least two measurement cycles can be obtained. Then, through calculation, the clock frequency difference between the wireless microphone and the host can be obtained. Finally, the clock frequency can be adjusted to achieve clock synchronization.

[0142] Reference Figure 7Within a communication cycle, the host first initializes the driver and network; then, in the first communication cycle, the host sends a specific synchronization command to its own WiFi module; next, it obtains the WiFi module TSF value and the AUDIO timestamp, packages them into the first associated time value, sends it to the microphone, and then sleeps and waits for the predicted duration, completing one cycle.

[0143] The process initializes the driver, network, and microphone connected to the host. It can determine whether the first associated time value has been received. If received, the first associated time value is received and parsed, and a specific synchronization command is sent to its own WiFi module to obtain its own TSF value and AUDIO timestamp. Within this cycle, both the host and the microphone complete their operations.

[0144] Reference Figure 8 The diagram illustrates the interactive operation flowchart of a master device and a slave device according to an embodiment of the present invention.

[0145] The same operation is repeated in the next cycle. During clock synchronization, the microphone can acquire the host's TSF value and AUDIO timestamp for at least two cycles, and also acquire its own TSF value and AUDIO timestamp for at least two cycles.

[0146] The microphone then synchronizes its clock based on the TSF value of the host in two cycles and the timestamp of the AUDIO, as well as the TSF value and timestamp of the AUDIO generated in its own two cycles.

[0147] Specifically, after initialization, the host sends specific instructions to its WiFi module at regular intervals to obtain its TSF timestamp. Based on the interrupt triggered by the WiFi module's level signal, it records the corresponding audio playback timestamp of the host. Then, it sends these two timestamps to all connected wireless microphones. After receiving the clock synchronization packet from the host, the wireless microphone parses it to obtain the host's TSF and audio playback timestamp. Then, the wireless microphone sends specific instructions to its own WiFi module to obtain the TSF and reads its own clock through the interrupt caused by the pin level change triggered by the WiFi module. This is one process. After two processes, there will be 8 timestamps, which correspond to 4 time differences that can be calculated. Based on the TSF time difference, the ratio of the host's audio playback time to the TSF is calculated. This ratio is multiplied by the TSF difference obtained by the wireless microphone to calculate the microphone's expected time difference. This is then compared with the actual difference to calculate the clock deviation between the microphone and the host, and the microphone clock is adjusted to achieve clock synchronization.

[0148] By calculating the time difference between the host and the wireless microphone, the direction of adjustment for the wireless microphone clock frequency can be determined. By adjusting the capacitance of the resonant capacitor of the crystal oscillator, the crystal oscillator frequency can be adjusted, thereby adjusting the wireless microphone clock and achieving clock synchronization.

[0149] As long as multiple devices have a clock synchronization module and are equipped with instructions that allow them to record timestamps and pass them to the CPU when the module aligns its time, these multiple devices can synchronize their time; it doesn't necessarily have to be a host device, as long as a reference device is identified.

[0150] To further illustrate this, let's take an application scenario as an example.

[0151] Taking clock synchronization between the host (master device) and the wireless microphone (slave device) as an example, the specific implementation process is as follows: Both the main unit and the wireless microphone are equipped with WiFi modules. In addition to the standard data and command buses, an extra GPIO wire is used for level signal transmission to connect them. The main unit acts as an access point (AP) to connect multiple wireless microphones, and both devices have completed firmware and hardware adaptation.

[0152] The first step is for the host to initialize the driver and network, and then periodically send specific synchronization commands to its own WiFi module. The second step involves the host WiFi module responding to the command, recording the TSF value (ap_tsf, i.e., the first clock value), and triggering a GPIO level change; the host audio playback module interrupts the level change and records the DAC working clock timestamp (ap_audio, i.e., the second clock value). The third step is for the host to package ap_tsf and ap_audio into a first associated time value and send it to all connected wireless microphones. Fourth, after the wireless microphone receives and parses the first associated time value, it sends a synchronization command to its own WiFi module. Fifth, the wireless microphone WiFi module responds to the command, records the TSF value (sta_tsf, i.e., the third clock value), and triggers a GPIO level change; the wireless microphone audio acquisition module records the ADC working clock timestamp (sta_audio, i.e., the fourth clock value) through the level change interrupt. Step 6: Repeat the above steps to obtain at least two sets of parameters for consecutive periods (ap_tsf(n), ap_audio(n), sta_tsf(n), sta_audio(n)) and (ap_tsf(n+1), ap_audio(n+1), sta_tsf(n+1), sta_audio(n+1)). Step 7: Calculate the target timestamp using the following formula: Δap_tsf = ap_tsf (n+1) - ap_tsf (n); Δap_audio = ap_audio (n+1) - ap_audio (n); Δsta_tsf = sta_tsf (n+1) - sta_tsf (n); sta_audio_adjust = (Δap_audio / Δap_tsf) × Δsta_tsf + sta_audio(n); Step 8: The wireless microphone adjusts its own clock frequency according to the target timestamp (this can be achieved by adjusting the capacitance of the crystal oscillator capacitor), and finally achieves clock synchronization with the host.

[0153] This invention also provides a clock synchronization system, see [link to relevant documentation]. Figure 8 The diagram shows a schematic representation of a clock synchronization system according to an embodiment of the present invention.

[0154] As an example, the clock synchronization system may include: The master device acquisition module is used to execute at least two measurement processes. In each measurement process, the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time is acquired, and the first associated time value is sent to the slave device. The slave device acquisition module is used for each measurement process executed by the master device. After receiving the corresponding first associated time value, the slave device executes a corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time. The deviation determination module is used to determine the synchronization deviation between the second local clock and the first local clock based on the first associated time value from at least two different measurement processes and the corresponding second associated time value; A calibration module is used to calibrate the first local clock and / or the second local clock according to the synchronization deviation; The first reference clock and the second reference clock are clock sources that keep each other synchronized.

[0155] This embodiment, by setting up a master device acquisition module and a slave device acquisition module, can execute at least two measurement processes. Each time, it acquires a first associated time value between a first reference clock and a first local clock at the corresponding measurement moment and sends this value to the slave device. After receiving each first associated time value, the slave device executes the corresponding measurement process to acquire a second associated time value between a second reference clock and a second local clock at the corresponding measurement moment. Since the first and second reference clocks are clock sources that are synchronized with each other, the two sets of first associated time values ​​obtained from at least two measurement processes can reflect the frequency characteristics of the first local clock relative to the synchronized clock source within a certain time interval. Similarly, the corresponding two sets of second associated time values ​​reflect the frequency characteristics of the second local clock relative to the same synchronized clock source within another time interval.

[0156] By utilizing the deviation determination module and the calibration module, based on the correlation data across the measurement process, the synchronization deviation between the second local clock and the first local clock can be calculated, and then either local clock can be calibrated.

[0157] In this embodiment, the determination of synchronization deviation no longer relies on the instantaneous transmission accuracy of a single timestamp between master and slave devices. Instead, it uses a time window formed by multiple measurements to compare the frequency drift of the two local clocks. This transforms the traditional "relative reference based on transmission timestamp" architecture into an "absolute reference based on a shared reference clock pre-synchronized within the device" architecture. This fundamentally isolates the impact of wireless transmission interference on the synchronization reference data, elevating the reliability of the synchronization reference from the wireless channel level to the device's internal hardware clock level. By executing at least two measurement processes to extract the relative frequency characteristics of the local clock relative to the global reference, rather than a single absolute time difference, the system's anti-interference capability against transmission delay fluctuations is significantly enhanced. It achieves complete decoupling of random errors in wireless transmission from the inherent drift error of the local clock, eliminating the inherent error accumulation and amplification problem in traditional systems. This scheme achieves high-precision frequency synchronization of local clocks between master and slave devices through multiple sequential measurements and cross-device data comparisons without relying on high-precision hardware synchronization signals, significantly improving the robustness and feasibility of clock synchronization in wireless environments.

[0158] Optionally, obtaining the first associated time value between the first reference clock and the first local clock of the master device at the corresponding measurement time includes: Obtain the first clock value of the first reference clock and the second clock value of the first local clock that are correlated in time; The step of obtaining the second associated time value between the second reference clock and the second local clock of the slave device at the corresponding measurement time includes: Obtain the third clock value of the second reference clock that is time-correlated with the fourth clock value of the second local clock.

[0159] Optionally, the first clock value and the second clock value are recorded in response to the same first trigger event, so that they correspond to the same physical moment; and / or, The third clock value and the fourth clock value are recorded in response to the same second triggering event so that they correspond to the same physical moment.

[0160] Optionally, within the same measurement process, a first trigger signal is generated using the first reference clock, such that the operation of recording the first clock value is time-aligned with the operation of recording the second clock value; and / or, A second trigger signal is generated by the second reference clock, so that the operation of recording the third clock value is time-aligned with the operation of recording the fourth clock value.

[0161] Optionally, the first trigger event is a first hardware trigger signal generated by the clock module of the first reference clock; and / or, The second trigger event is a second hardware trigger signal generated by the clock module of the second reference clock.

[0162] Optionally, the first hardware trigger signal and / or the second hardware trigger signal are level transition signals.

[0163] Optionally, the first clock value and the second clock value are obtained respectively within a first preset time tolerance window; and / or, The third clock value and the fourth clock value are obtained respectively within the second preset time tolerance window.

[0164] Optionally, at least two different measurement procedures used to determine the synchronization deviation are performed in close proximity in time.

[0165] Optionally, determining the synchronization deviation based on the first associated time value and the corresponding second associated time value from at least two different measurement procedures includes: Based on at least two of the first associated time values, a first difference of the first reference clock and a second difference of the first local clock are determined; Based on at least two of the second associated time values, a third difference of the second reference clock and a fourth difference of the second local clock are determined.

[0166] Optionally, determining the synchronization deviation further includes: The first frequency ratio relationship is determined based on the second difference and the first difference; Based on the first frequency ratio and the third difference, calculate the expected time difference of the second local clock; The synchronization deviation is determined based on the expected time difference and the fourth difference.

[0167] Optionally, if the synchronization deviation is greater than zero, the frequency of the first local clock is reduced and / or the frequency of the second local clock is increased; if the synchronization deviation is less than zero, the frequency of the first local clock is increased and / or the frequency of the second local clock is reduced.

[0168] Optionally, the method further includes: repeatedly executing the measurement process and deviation determination steps, and performing clock calibration based on the determined synchronization deviation each time, so as to achieve clock synchronization between the master device and the slave device.

[0169] Those skilled in the art will understand that, for ease of description and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0170] Furthermore, embodiments of this application also provide an electronic device, including: a memory, a processor, and an acquisition program stored in the memory and executable on the processor, wherein the processor executes the program to implement the clock synchronization method as described in the above embodiments.

[0171] Furthermore, embodiments of this application also provide a machine-readable storage medium storing a machine-executable program, which is used to cause the machine to perform the clock synchronization method as described in the above embodiments.

[0172] In the description of the embodiments of the present invention, it should be noted that the terms "above," "below," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. When an element such as a layer, region, or substrate is referred to as being "above" or "on top of" another element, it may be directly on the other element, or there may be an intermediate element. Conversely, when an element is referred to as being "directly on" or "above" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "below" or "under" another element, it may be directly below or under the other element, or there may be an intermediate element. Conversely, when an element is referred to as being "directly below" or "under" another element, there is no intermediate element. Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0173] Those skilled in the art will understand that embodiments of this application may also include computer program products. Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0174] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), devices, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0175] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0176] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0177] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A clock synchronization method, characterized in that, Applied to a system including a master device and a slave device, the method includes: At least two measurement processes are executed. In each measurement process, the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time is obtained, and the first associated time value is sent to the slave device. For each measurement process executed by the master device, after receiving the corresponding first associated time value, the slave device executes the corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time; Based on the first associated time value from at least two different measurement processes and the corresponding second associated time value, the synchronization deviation between the second local clock and the first local clock is determined; The first local clock and / or the second local clock are calibrated according to the synchronization deviation. The first reference clock and the second reference clock are clock sources that keep each other synchronized.

2. The method according to claim 1, characterized in that, The step of obtaining the first associated time value between the first reference clock and the first local clock of the master device at the corresponding measurement time includes: Obtain the first clock value of the first reference clock and the second clock value of the first local clock that are correlated in time; The step of obtaining the second associated time value between the second reference clock and the second local clock of the slave device at the corresponding measurement time includes: Obtain the third clock value of the second reference clock that is time-correlated with the fourth clock value of the second local clock.

3. The method according to claim 2, characterized in that, The first clock value and the second clock value are recorded in response to the same first trigger event, so that they correspond to the same physical moment; and / or, The third clock value and the fourth clock value are recorded in response to the same second triggering event so that they correspond to the same physical moment.

4. The method according to claim 3, characterized in that, In the same measurement process, a first trigger signal is generated by the first reference clock, so that the operation of recording the first clock value and the operation of recording the second clock value are time-aligned. And / or, A second trigger signal is generated by the second reference clock, so that the operation of recording the third clock value is time-aligned with the operation of recording the fourth clock value.

5. The method according to claim 3, characterized in that, The first triggering event is a first hardware triggering signal generated by the clock module of the first reference clock; And / or, The second trigger event is a second hardware trigger signal generated by the clock module of the second reference clock.

6. The method according to claim 5, characterized in that, The first hardware trigger signal and / or the second hardware trigger signal are level transition signals.

7. The method according to claim 2, characterized in that, The first clock value and the second clock value are obtained respectively within a first preset time tolerance window; and / or, The third clock value and the fourth clock value are obtained respectively within the second preset time tolerance window.

8. The method according to claim 1, characterized in that, The at least two different measurement procedures used to determine the synchronization deviation are performed in close proximity in time.

9. The method according to claim 1, characterized in that, The step of determining the synchronization deviation based on the first associated time value and the corresponding second associated time value from at least two different measurement processes includes: Based on at least two of the first associated time values, a first difference of the first reference clock and a second difference of the first local clock are determined; Based on at least two of the second associated time values, a third difference of the second reference clock and a fourth difference of the second local clock are determined.

10. The method according to claim 9, characterized in that, The determination of synchronization deviation also includes: The first frequency ratio relationship is determined based on the second difference and the first difference; Based on the first frequency ratio and the third difference, calculate the expected time difference of the second local clock; The synchronization deviation is determined based on the expected time difference and the fourth difference.

11. The method according to claim 9, characterized in that, If the synchronization deviation is greater than zero, the frequency of the first local clock is reduced and / or the frequency of the second local clock is increased; if the synchronization deviation is less than zero, the frequency of the first local clock is increased and / or the frequency of the second local clock is reduced.

12. The method according to claim 1, characterized in that, The method further includes: repeatedly executing the measurement process and deviation determination steps, and performing clock calibration based on the determined synchronization deviation each time, so as to achieve clock synchronization between the master device and the slave device.

13. A clock synchronization system, characterized in that, The system includes: The master device acquisition module is used to execute at least two measurement processes. In each measurement process, the first associated time value of the first reference clock and the first local clock of the master device at the corresponding measurement time is acquired, and the first associated time value is sent to the slave device. The slave device acquisition module is used for each measurement process executed by the master device. After receiving the corresponding first associated time value, the slave device executes a corresponding measurement process once to obtain the second associated time value of the slave device's second reference clock and second local clock at the corresponding measurement time. The deviation determination module is used to determine the synchronization deviation between the second local clock and the first local clock based on the first associated time value from at least two different measurement processes and the corresponding second associated time value; A calibration module is used to calibrate the first local clock and / or the second local clock according to the synchronization deviation; The first reference clock and the second reference clock are clock sources that keep each other synchronized.

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