Programmable logic based multi-sensor timestamp synchronization method and system

Abstract

This invention discloses a multi-sensor timestamp synchronization method and system based on programmable logic, belonging to the field of multi-sensor timing synchronization technology. It aims to solve the problems of insufficient synchronization accuracy and poor reliability in existing multi-sensor timestamp synchronization methods, which are susceptible to interference from hardware link differences, operating condition drift, and single-point clock failures. The method includes: receiving synchronization requirement parameters, configuring reconfigurable logic circuits and loading configuration bitstreams; constructing a dual-mode redundant global clock tree, measuring delays to generate a compensation table; matching the acquisition trigger mode, correcting timestamps and normalizing the acquisition frequency; dynamically updating the compensation table according to operating conditions; and identifying timing synchronization anomalies through external time calibration. This application can achieve high-precision timing alignment of heterogeneous sensors, significantly improving the stability and anti-interference capability of multi-sensor synchronization in industrial scenarios.

Description

Technical Field

[0001] This invention relates to the field of multi-sensor timing synchronization technology, and more specifically to a multi-sensor timestamp synchronization method and system based on programmable logic. Background Technology

[0002] In real-time multi-sensor fusion control scenarios such as industrial automation, smart warehousing, and industrial robots, the collaborative acquisition of data from multiple heterogeneous sensors and the completion of timing alignment are crucial prerequisites for achieving precise closed-loop control. The accuracy of timestamp synchronization directly determines the accuracy of multi-sensor data fusion, attitude calculation, and motion control. Existing multi-sensor timestamp synchronization schemes commonly suffer from inherent timing errors due to differences in hardware link transmission and the discreteness of individual sensor responses. Furthermore, dynamic changes in operating conditions such as ambient temperature and power supply voltage can easily cause delay drift, leading to a continuous deterioration in synchronization accuracy. Moreover, traditional synchronization architectures lack clock reliability, only providing general detection of timing anomalies and failing to accurately distinguish between global clock failures and single-channel local timing anomalies. This makes them unsuitable for the high-precision, high-reliability timing synchronization requirements of industrial scenarios, limiting the long-term stable operation of multi-sensor fusion control systems. Therefore, to overcome these limitations, this invention proposes a multi-sensor timestamp synchronization method and system based on programmable logic. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a multi-sensor timestamp synchronization method and system based on programmable logic, which solves the problems of existing multi-sensor timing synchronization being susceptible to hardware differences and operating condition disturbances, having low synchronization accuracy, and being difficult to accurately identify timing anomalies.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] Multi-sensor timestamp synchronization methods based on programmable logic include:

[0006] Receive synchronization requirement parameters, calculate the number and configuration parameters of reconfigurable logic circuits, generate a configuration bit stream, and load it into the programmable logic device;

[0007] A dual-mode redundant global clock tree is built inside the programmable logic device to provide a global time reference; and the hardware link delay of each sensor interface and the physical response delay of each sensor are measured to generate a hardware link delay compensation table and an individual delay compensation table.

[0008] According to the synchronization requirement parameters, the acquisition trigger mode is matched for each sensor and the sensor data acquisition is completed; based on the global time base, hardware link delay compensation table and individual delay compensation table, the sensor data acquired by each sensor is corrected for the real timestamp of perception, and the multi-sensor acquisition frequency normalization processing is completed.

[0009] Collect operating condition parameters, and when changes in operating conditions cause substantial delay drift, generate dynamic delay compensation values ​​for operating conditions, and correct the hardware link delay compensation table and individual delay compensation table.

[0010] The global time base is calibrated by an external absolute time synchronization signal, the drift is counted, the existence of timing synchronization anomalies is determined, and the anomaly type of the programmable logic device is identified.

[0011] Specifically, receiving synchronization requirement parameters, calculating the number and configuration parameters of reconfigurable logic circuits, generating a configuration bit stream, and loading it into the programmable logic device includes:

[0012] The upper-level control unit sends a synchronization requirement parameter packet to the processing unit through an industrial communication interface. After the processing unit verifies the validity of the synchronization requirement parameter packet, it extracts the synchronization requirement parameters.

[0013] The processing unit calculates the number and configuration parameters of various reconfigurable logic circuits based on the preset logical resource mapping relationship;

[0014] The processing unit calls the reconfigurable logic circuit library and, based on the calculated number and configuration parameters of various reconfigurable logic circuits, splices together to generate a configuration bit stream.

[0015] The processing unit performs a security check on the generated configuration bitstream. Once the security check is passed, the configuration bitstream is loaded into the programmable logic device in either full load mode or incremental load mode.

[0016] Specifically, the steps for constructing a dual-mode redundant global clock tree within a programmable logic device to provide a global time base include:

[0017] A dual-mode redundant global clock tree containing two independent clock generation paths is built inside the programmable logic device;

[0018] The operating status of the two clock generation paths is monitored in real time by a programmable logic device, and a global clock signal is output.

[0019] The global timestamp counting logic inside the programmable logic device is continuously driven by a global clock signal to construct a global time base composed of a clock source and continuous global timestamp count values.

[0020] Specifically, the steps of monitoring the operating status of the two clock generation paths in real time through programmable logic devices and outputting a global clock signal include:

[0021] The two clock generation paths of the dual-mode redundant global clock tree output the main global clock signal and the backup global clock signal respectively.

[0022] Configure the clock monitoring operation parameters of the programmable logic device and establish clock fault judgment criteria. The clock monitoring operation parameters include monitoring frequency, frequency measurement window, jitter measurement cycle number, phase difference measurement cycle and preset normal threshold.

[0023] The programmable logic device monitors operating parameters according to a preset clock and collects clock operating parameters of the two clock generation paths in real time. The clock operating parameters include frequency, jitter, and phase difference parameters.

[0024] The operating status of the main global clock signal is determined based on the collected clock operating parameters. If the main global clock signal fails, the backup global clock signal switching operation is triggered, and the global clock signal is output.

[0025] Specifically, the steps for generating the hardware link delay compensation table and the individual delay compensation table include:

[0026] The calibration operation is triggered at the initial startup time of the programmable logic device and at the arrival time of the preset measurement cycle;

[0027] When the programmable logic device is initially started, based on the built-in measurement function and standard signal source, and based on the global time reference, it completes the full measurement of the hardware link delay of all sensor channels and the physical response delay of individual sensors, and generates and initializes the hardware link delay compensation table and the individual delay compensation table.

[0028] When the preset measurement period arrives, the programmable logic device performs incremental delay measurement within the service idle time window, and completes the dynamic update of the hardware link delay compensation table and the individual delay compensation table through parameter drift determination.

[0029] Specifically, the steps of correcting the sensing data collected by each sensor for the actual sensing timestamp and completing the multi-sensor acquisition frequency normalization process include:

[0030] Based on the synchronization requirement parameters, a matching acquisition trigger mode is configured for each sensor, and a timestamp marker resource in the reconfigurable logic circuit is independently allocated to each sensor interface.

[0031] Relying on the global clock signal to drive the timestamp marker resources, and combined with the corresponding acquisition trigger mode, the data of each sensor channel is acquired and bound to the original timestamp;

[0032] Retrieve the hardware link delay compensation table, match the corresponding hardware link delay compensation value for each channel, and perform reverse compensation correction on the original timestamp to obtain the hardware link corrected timestamp.

[0033] Retrieve the individual delay compensation table, match the individual delay compensation value of the corresponding sensor, and perform a second correction on the hardware link correction timestamp to obtain the true perception timestamp of the sensor data.

[0034] The sampling frequencies of each sensor are obtained and standardized to a preset standard output frequency. Interpolation synchronization timestamps are then bound to the standardized sensor data.

[0035] Specifically, the steps of collecting operating condition parameters, generating dynamic delay compensation values ​​in response to substantial delay drift caused by changes in operating conditions, and correcting the hardware link delay compensation table and individual delay compensation table include:

[0036] The programmable logic device collects operating parameters in real time and determines whether changes in operating conditions cause substantial delay drift based on a preset threshold for allowable fluctuations in operating conditions. If substantial delay drift is determined, a dynamic delay compensation value for operating conditions is generated, which includes the amount of hardware link delay drift and the amount of individual response delay drift.

[0037] Based on the generated dynamic delay compensation values ​​for operating conditions, the parameters of the hardware link delay compensation table and the individual delay compensation table are updated and corrected in layers.

[0038] Specifically, the steps for generating dynamic delay compensation values ​​for operating conditions include:

[0039] The programmable logic device continuously collects field operating parameters and updates the operating parameter reference values ​​in real time. The operating parameters include ambient temperature and power supply voltage.

[0040] Calculate the difference between the current operating condition parameter baseline value and the previous compensation effective operating condition parameter baseline value to obtain the ambient temperature fluctuation and power supply voltage fluctuation. Combine this with the preset operating condition fluctuation allowable threshold to determine whether a substantial delay drift has occurred.

[0041] If a substantial delay drift is determined, a preset delay correction coefficient matrix is ​​invoked to match the correction coefficient range corresponding to the current operating condition parameters. The target correction coefficient is obtained through interpolation, and the dynamic delay compensation value for the operating condition is generated based on the target correction coefficient.

[0042] Specifically, the steps of calibrating the global time base using an external absolute time synchronization signal, calculating the drift, determining whether timing synchronization anomalies exist, and identifying the anomaly type of the programmable logic device include:

[0043] Receive external absolute time synchronization signals according to the preset calibration cycle, latch the real-time value of global timestamp count, and establish a global time calibration reference pair;

[0044] Based on the global time calibration reference pair, calculate the global time deviation for this calibration cycle, and combine the calibration cycle to calculate the single global calibration drift, and construct a global drift sequence;

[0045] Statistical analysis of the global drift sequence is performed, and the existence of global time-series synchronization anomalies is determined by combining the single drift anomaly threshold and the sequence fluctuation anomaly threshold as dual judgment criteria.

[0046] If the global clock is determined to be abnormal, global clock fault tolerance processing is performed; otherwise, the sensor acquisition channel with local timing abnormalities enters the single-channel local abnormality identification process to identify single-channel abnormalities, including abnormalities in the original timestamp marking, abnormalities in the perceived real timestamp, and abnormalities in the dynamic delay compensation of the operating condition.

[0047] A multi-sensor timestamp synchronization system based on programmable logic includes:

[0048] Dynamic configuration module: used to receive synchronization requirement parameters, calculate the number of reconfigurable logic circuits and configuration parameters, generate configuration bit stream, and load it into programmable logic device;

[0049] Delay calibration module: used to build a dual-mode redundant global clock tree inside the programmable logic device to provide a global time reference; and to measure the hardware link delay of each sensor interface and the physical response delay of each sensor, generating a hardware link delay compensation table and an individual delay compensation table;

[0050] Preprocessing module: Used to match the acquisition trigger mode for each sensor according to the synchronization requirement parameters and complete the acquisition of sensor data; based on the global time base, hardware link delay compensation table and individual delay compensation table, it corrects the sensing data acquired by each sensor for the real timestamp of perception and completes the normalization processing of the multi-sensor acquisition frequency.

[0051] Compensation and Correction Module: Used to collect operating condition parameters, and in response to substantial delay drift caused by changes in operating conditions, generate dynamic delay compensation values ​​for operating conditions, and correct the hardware link delay compensation table and individual delay compensation table.

[0052] Anomaly identification module: used to calibrate the global time base through an external absolute time synchronization signal, count the drift, determine whether there is a timing synchronization anomaly, and identify the anomaly type of the programmable logic device.

[0053] The beneficial effects of this invention are:

[0054] This invention enables on-demand deployment of synchronous logic through dynamically configured reconfigurable logic circuits. It builds a stable and reliable global time reference based on a dual-mode redundant global clock tree. Combined with hierarchical delay compensation of hardware links and individual sensors, as well as dynamic delay correction under operating conditions, it effectively offsets timing deviations caused by inherent hardware differences and environmental disturbances. At the same time, it accurately locates fault types by using external absolute time calibration and multi-dimensional timing anomaly identification mechanisms, achieving high-precision timing alignment of multiple sensors. This significantly improves the reliability, anti-interference capability, and long-term operational stability of timing synchronization in multi-sensor fusion control scenarios. Attached Figure Description

[0055] Figure 1 This is a flowchart of the multi-sensor timestamp synchronization method based on programmable logic according to the present invention;

[0056] Figure 2 This is a flowchart of step S1 of the present invention;

[0057] Figure 3 This is a flowchart of step S3 of the present invention;

[0058] Figure 4 This is a flowchart of step S41 of the present invention;

[0059] Figure 5 This is a flowchart of step S5 of the present invention. Detailed Implementation

[0060] Example 1:

[0061] Please see Figure 1 This embodiment introduces a multi-sensor timestamp synchronization method based on programmable logic, applied to real-time multi-sensor fusion control scenarios. These scenarios refer to industrial automation applications that simultaneously process data from multiple heterogeneous sensors and execute real-time control tasks, including anti-derailment control of intelligent warehousing and logistics robots, multi-motor synchronous control of four-way shuttles, distributed edge node control in fully intelligent factories, and motion control of industrial robots. This embodiment uses anti-derailment control of intelligent warehousing and logistics robots as a specific application scenario. The intelligent warehousing and logistics robot is equipped with positioning sensors, attitude sensors, distance sensors, and speed sensors, operates at a speed of 1.5 m / s, and requires a lateral control accuracy of ≤ ±5 mm. The method includes:

[0062] Step S1: Receive the synchronization requirement parameters input by the upper-level control unit, calculate the number and configuration parameters of the required reconfigurable logic circuits according to the preset logic resource mapping relationship, call the reconfigurable logic circuit library to automatically splice and generate a configuration bit stream containing only the necessary functional circuits, and load it into the programmable logic device in full loading mode or incremental loading mode after security verification.

[0063] Please see Figure 2 Furthermore, step S1 includes:

[0064] Step S11: The upper-level control unit sends a synchronization requirement parameter packet to the processing unit through the industrial communication interface. After the processing unit verifies the validity of the synchronization requirement parameter packet, it extracts the synchronization requirement parameters.

[0065] The upper-level control unit refers to the control circuit responsible for overall scheduling and task management, including the main control circuit of intelligent warehousing and logistics robots, the central control circuit of automated production lines, and factory edge computing gateways; the industrial communication interface refers to the standardized communication interface used for data transmission between industrial devices, including CAN bus interface, RS485 bus interface, and Ethernet interface; the processing unit refers to the general-purpose processing unit responsible for performing software calculations and logic control, including the processor part of heterogeneous on-chip systems, embedded microprocessors, and digital signal processors; the synchronization requirement parameter package refers to a structured data set containing all configuration parameters of the time synchronization circuit, including sensor configuration parameters and synchronization accuracy requirement parameters.

[0066] In this embodiment, the upper-level control unit sends a JSON-formatted synchronization requirement parameter packet to the ARM processor in the heterogeneous on-chip system via the CAN bus. The ARM processor first performs a CRC check on the synchronization requirement parameter packet to verify the integrity of the data transmission, and then performs a format check to verify whether the fields of the synchronization requirement parameter packet are complete and whether the values ​​are within the legal range. If the legality check fails, the ARM processor immediately sends a parameter check failure alarm signal to the upper-level control unit and requests a retransmission of the synchronization requirement parameter packet. If the legality check passes, the following core synchronization requirement parameters are extracted: the number of sensors is 6, and the sensor types include 1 RFID positioning sensor, 1 six-axis IMU attitude sensor, 2 lateral ultrasonic distance sensors, and 2 wheel speed sensors, with corresponding sampling frequencies of 1Hz, 100Hz, 20Hz, and 50Hz, respectively; the maximum allowable synchronization error is ≤10ns, the control period is 10ms, and the maximum allowable response delay is ≤1μs.

[0067] Step S12: The processing unit calculates the number and configuration parameters of various types of reconfigurable logic circuits required based on the preset logic resource mapping relationship.

[0068] The preset logical resource mapping relationship refers to the correspondence between pre-established synchronization requirement parameters and programmable logic resource consumption. It is established by actually measuring and statistically analyzing the resource consumption of each reconfigurable logic circuit on mainstream programmable logic devices. The reconfigurable logic circuit refers to a programmable logic circuit that is divided into multiple independent, single-function hardware functional circuits that can be individually instantiated and reconfigured. Each hardware functional circuit completes a specific time synchronization related function, including a timestamp marking circuit, a phase-locked loop circuit, a data buffer circuit, an interpolation calculation circuit, a condition compensation calculation circuit, a fault detection circuit, an analog-to-digital conversion circuit, a clock mutual detection circuit, and a timing anomaly detection circuit. Each circuit is responsible for timestamp marking, multi-frequency clock generation, data buffering, frequency interpolation, condition delay compensation, full-link fault monitoring, condition parameter acquisition, clock redundancy monitoring, and timing anomaly identification.

[0069] In this embodiment, the preset logic resource mapping relationship is established by actually measuring the resource consumption of each reconfigurable logic circuit on the programmable logic device. For example, a 32-bit timestamp marking circuit consumes 12 slices and 1 16-bit multiplier; a single-channel 12-bit analog-to-digital converter circuit consumes 8 slices and 1 dedicated IO logic unit; a set of dual-mode clock mutual detection circuits consumes 15 slices and 2 16-bit counters; and a set of timing anomaly detection circuits consumes 20 slices and 1 32-bit statistical operation unit. Based on this logical resource mapping relationship, the ARM processor calculates the following: the number of timestamp marking circuits equals the number of sensors, which is 6; the number of phase-locked loop circuits equals the number of sensor types with different sampling frequencies plus 1, where the addition of 1 is to generate a dedicated high-precision clock for the global timestamp counting circuit, resulting in 5 circuits, corresponding to 1Hz, 20Hz, 50Hz, and 100Hz sampling clocks and a 100MHz global timestamp counting circuit clock; the first-in-first-out memory depth in the data cache circuit equals the maximum sampling frequency multiplied by the maximum allowable transmission delay multiplied by 2, where multiplying by 2 is to reserve twice the cache space to prevent data transmission errors. Overflow occurred, and the calculated result was 200, which was taken as the industrial standard value of 256. The number of interpolation calculation circuits was equal to the number of sensor groups with different output frequencies, which was 2, used for 5x interpolation of the 20Hz ultrasonic distance sensor and 2x interpolation of the 50Hz wheel speed sensor, respectively. The number of working condition compensation calculation circuits was 1, used for centralized processing of working condition parameter acquisition and dynamic delay compensation value calculation. The number of fault detection circuits was equal to the number of sensors plus 2, where the addition of 2 was to set up 1 clock fault detection circuit and 1 logic fault detection circuit. The calculated result was 8, including 6 sensor fault detection circuits, 1 clock fault detection circuit and 1 logic fault detection circuit. The number of analog-to-digital conversion circuits is equal to the total number of analog channels for operating condition monitoring. In this embodiment, two analog operating condition parameters, namely ambient temperature and power supply voltage, need to be collected. Correspondingly, two single-channel 12-bit analog-to-digital conversion circuits are configured to complete the quantization acquisition of the temperature analog signal and the power supply voltage analog signal, respectively, providing raw data input for operating condition delay compensation. The number of clock mutual detection circuits is one set, corresponding to the two independent clock generation paths of the dual-mode redundant global clock tree. It is used to realize the real-time mutual detection and comparison of the frequency, jitter and phase difference between the main global clock signal and the backup global clock signal, providing hardware measurement support for clock fault judgment and seamless switching. The number of timing anomaly detection circuits is one, which centrally carries the global drift sequence statistical analysis, dual anomaly threshold judgment and single-channel local anomaly hierarchical identification logic, and uniformly completes the monitoring of the timing synchronization status of the entire link and the anomaly type discrimination.

[0070] Step S13: The processing unit calls the reconfigurable logic circuit library pre-stored in the non-volatile memory, and automatically splices together the configuration bit stream according to the calculated number and configuration parameters of various reconfigurable logic circuits.

[0071] The non-volatile memory includes QSPI Flash memory, eMMC memory, and SD card memory; the reconfigurable logic circuit library is a collection of netlist files that have been pre-designed, synthesized, and verified using a hardware description language. Each circuit has a standardized interface and fixed resource consumption parameters, including timestamp marking circuits, phase-locked loop configuration circuits, data buffer circuits, interpolation calculation circuits, fault detection circuits, etc.

[0072] In this embodiment, the ARM processor calls the reconfigurable logic circuit library pre-stored in the external QSPI Flash and concatenates it to generate a configuration bitstream in the following order: First, it concatenates the bitstream segments of static region logic, which refers to the core basic logic that never needs to be modified, including the global timestamp counting circuit, clock mutual detection circuit, and configuration interface module; then, based on the calculated number and configuration parameters of various reconfigurable logic circuits, it calls the corresponding number of circuit netlists from the reconfigurable logic circuit library to dynamically concatenate and generate bitstream segments of 6 timestamp marking circuits and 8 fault detection circuits; then, according to the sampling frequency requirements... The process involves configuring the frequency division coefficients and phase parameters of five phase-locked loop (PLL) circuits. The input clock for each PLL circuit is an external 50MHz high-precision active crystal oscillator, which outputs sampling clocks of 1Hz, 20Hz, 50Hz, and 100Hz, and a global clock of 100MHz. Finally, based on interpolation requirements, the netlists of two linear interpolation calculation circuits are called, configured for 5x and 2x interpolation respectively, and concatenated into the configuration bitstream. The netlist of one operating condition compensation calculation circuit is also called, configuring the storage addresses for the temperature and voltage acquisition interfaces and the delay correction coefficient matrix table, and concatenating them into the configuration bitstream. The entire generation process is completed on the ARM processor. If errors such as insufficient resources or missing circuits occur during the generation process, the ARM processor immediately sends a configuration generation failure alarm signal to the upper-level control unit.

[0073] Step S14: The processing unit performs a security check on the generated configuration bitstream. After the security check passes, the configuration bitstream is loaded into the programmable logic device in either full load mode or incremental load mode.

[0074] The security verification includes integrity verification and identity authentication. Integrity verification includes SHA-256 hash verification and CRC32 verification, while identity authentication includes RSA digital signature authentication and ECC digital signature authentication. The full loading mode refers to loading the entire configuration bitstream and covering all logic of the programmable logic device, which is suitable for scenarios involving power-on initialization or full logic updates. The incremental loading mode refers to loading only the dynamic area logic that has changed, without affecting the normal operation of the static area logic, which is suitable for scenarios involving partial logic updates. The programmable logic device includes field-programmable gate arrays, complex programmable logic devices, and programmable logic portions in heterogeneous on-chip systems. The static and dynamic areas are pre-divided during the FPGA design phase. The static area contains the core basic logic that never needs to be modified, while the dynamic area is used to load reconfigurable functional logic.

[0075] In this embodiment, the ARM processor first performs a security verification operation on the generated configuration bitstream: SHA-256 hash calculation is performed on the configuration bitstream to generate the current hash value; the current hash value is compared bit-by-bit with the standard hash value pre-stored in non-volatile memory. If they are completely identical, the integrity verification passes; otherwise, the integrity verification fails. After the integrity verification passes, the RSA-2048 digital signature attached to the configuration bitstream is further verified. The digital signature is decrypted using the pre-stored public key to obtain the decrypted hash value. The decrypted hash value is compared with the current hash value. If they are identical, the authentication passes; otherwise, the authentication fails. If any verification fails, the ARM processor immediately discards the configuration bitstream and sends a configuration verification failure alarm signal to the upper-level control unit, requesting the regeneration of the configuration bitstream. After the security verification passes, the ARM processor performs a resource check: if a full load mode is used, it checks whether the required logic resources do not exceed the total resource capacity of the FPGA; if an incremental load mode is used, it checks whether the required logic resources do not exceed the maximum resource capacity of the dynamic area; if resources are insufficient, a resource shortage alarm signal is sent to the upper-level control unit. After the resource check is passed, the ARM processor determines the current operating state of the programmable logic device: when it is in the idle state of power-on initialization or full logic update, it selects the full load mode to write the complete configuration bit stream into the configuration memory inside the FPGA; when it is in the running state of executing a transportation task and only needs to update part of the logic, it selects the incremental load mode, and only writes the configuration bit stream of the dynamic area into the corresponding configuration partition of the FPGA. During the loading process, the core logic such as the global timestamp counting circuit and the clock mutual detection circuit in the static area continues to operate normally, without affecting the driving control of the intelligent warehousing and logistics robot. After loading is complete, the ARM processor reads the contents of the FPGA's internal configuration memory and performs a CRC32 check. Upon successful check, it sends a logic start signal to the FPGA, and all reconfigurable logic circuits within the FPGA begin normal operation. The logic fault detection circuit in the fault detection circuit monitors the operating status of all reconfigurable logic circuits in real time, including the timestamp marking circuit, interpolation calculation circuit, operating condition compensation calculation circuit, analog-to-digital conversion circuit, and timing anomaly detection circuit. It outputs logic operation anomaly signals in real time and reports them to the upper-level control unit. If the loading process times out beyond the preset loading timeout threshold or if the post-loading check fails, the ARM processor re-executes the loading operation. If three consecutive loading failures occur, a configuration loading failure alarm signal is sent to the upper-level control unit, and the processor enters a safe standby state. The preset loading timeout threshold is set based on the size of the configuration bitstream and the loading interface rate; for example, the full loading timeout threshold is 500ms, and the incremental loading timeout threshold is 100ms.

[0076] Specifically, step S1 is the pre-configuration and logic generation stage of the entire multi-sensor timestamp synchronization method based on programmable logic. Its core design addresses the key challenges in industrial automation scenarios, such as the diverse combinations of multiple sensors, frequent changes in requirements, high maintenance costs of traditional fixed logic architectures, and the inability to quickly adapt to different application scenarios. It provides a dedicated hardware logic foundation that perfectly matches current needs for subsequent stages such as time base construction, data acquisition and synchronization, and error compensation. Industrial equipment such as intelligent warehousing and logistics robots require different numbers and types of sensors to be configured according to different needs. Traditional fixed-logic FPGA solutions require writing, compiling, and debugging code separately for different needs, resulting in development cycles of several days or even weeks and extremely high maintenance costs. Simultaneously, industrial environments demand extremely high circuit reliability; the security of configuration files and the stability of the loading process directly affect the normal operation of the equipment and the safety of personnel. Step S1, through the reception and parsing of synchronization requirement parameters in S11, transforms the actual requirements into standardized configuration parameters recognizable by the circuit, providing accurate input for subsequent resource calculation and logic generation. Step S12, through automatic calculation of reconfigurable logic circuit resource requirements, quickly obtains the required number of logic units and parameters based on pre-established logic resource mapping relationships, avoiding errors and tedious manual calculations. Step S13, through dynamic splicing and generation of configuration bitstreams, automatically generates configuration files by calling a pre-verified reconfigurable logic circuit library, eliminating the need for manual coding and shortening the development cycle from days to seconds. Step S14, through configuration bitstream security verification and loading, ensures the security of the configuration file through integrity verification and authentication, and balances the needs of circuit initialization and online upgrades through both full loading and incremental loading modes. Furthermore, post-loading verification and failure retry mechanisms ensure the reliability of the loading process. Without step S1, the circuit cannot dynamically generate corresponding hardware logic according to different synchronization requirements, and can only adopt a fixed logic scheme, resulting in an inability to adapt to different sensor combinations and application scenarios, significantly increasing development and maintenance costs.

[0077] Step S2: Construct a dual-mode redundant global clock tree inside the programmable logic device. The global clock signal output by the dual-mode redundant global clock tree drives the global timestamp counting logic to run, providing a global time reference. Measure the hardware link delay of each sensor interface and the physical response delay of each sensor channel by channel, generate and store a dedicated hardware link delay compensation table for each channel and an individual delay compensation table for each sensor.

[0078] Furthermore, step S2 includes:

[0079] Step S21: Construct a dual-mode redundant global clock tree inside the programmable logic device, monitor the operating status of the two global clock generation paths in real time through the built-in logic of the programmable logic device, and output and obtain the global clock signal.

[0080] The dual-mode redundant global clock tree contains two independent and backup global clock generation paths. The two global clock generation paths output clock signals with the same frequency and synchronized phase. One is used as the master clock and the other as the backup clock. The programmable logic device realizes real-time monitoring and fault diagnosis of the operating status of the two clocks through built-in monitoring logic.

[0081] Furthermore, step S21 includes:

[0082] Step S211: Output the main global clock signal and the backup global clock signal respectively through the two global clock generation paths of the dual-mode redundant global clock tree;

[0083] Two global clock generation paths simultaneously acquire input clock signals from the same external active crystal oscillator, outputting clock signals of the same frequency and phase. The output of one global clock generation path serves as the master global clock signal, driving all logic circuits requiring clocking. The output of the other global clock generation path serves as a backup global clock signal, in a hot standby state, ready to take over from the master clock at any time. After phase synchronization processing, both clocks are output as a unified global clock signal. A phase-locked loop (PLL) circuit provides multiple synchronous sampling clocks for the two global clock generation paths, ensuring phase synchronization between the global clock and the sampling clocks of each sensor.

[0084] Step S212: Configure the clock monitoring operation parameters of the programmable logic device and establish clock fault judgment criteria;

[0085] The clock monitoring operating parameters include monitoring frequency, frequency measurement window, jitter measurement cycle number, phase difference measurement cycle, and preset normal thresholds. The preset normal thresholds include frequency error threshold, jitter threshold, and phase difference threshold, which are set based on time synchronization accuracy requirements and industrial site environment reliability requirements. For example, the frequency error threshold is ≤1ppm, the jitter threshold is ≤100ps, and the phase difference threshold is ≤10°. When the clock operating parameters exceed the corresponding preset normal thresholds, the synchronization accuracy will fail to meet the design requirements.

[0086] The monitoring frequency is set based on the maximum allowable response time for clock failures, ensuring that a switch can be detected and completed within a specified time after a clock failure occurs. The frequency measurement window is set based on the frequency measurement accuracy requirements; the longer the measurement window, the higher the frequency measurement accuracy. The jitter measurement cycle number is set based on the confidence requirements for jitter statistics; the more measurement cycles, the more accurate the jitter measurement results. The phase difference measurement cycle is set based on the real-time requirements for phase difference measurement.

[0087] In this embodiment, the clock monitoring operation parameters of the programmable logic device are configured as follows: the monitoring frequency is 1kHz, that is, the operating status of the two clocks is detected once every 1ms; the frequency measurement window is 1ms, and the clock under test is counted within 1ms; the jitter measurement cycle is 1000, and the length of 1000 clock cycles is continuously measured; the phase difference measurement cycle is 1ms, and the phase difference between the two clocks is measured once every 1ms.

[0088] Step S213: The programmable logic device monitors the operating parameters according to the preset clock and measures the clock operating parameters of the global clock generation path in real time. The clock operating parameters include frequency, jitter and phase difference parameters.

[0089] Specifically, the reference clock counting method is adopted. An independent reference clock is used to count the main global clock signal and the backup global clock signal respectively. Within the preset frequency measurement window, the number of rising edges of each measured clock is counted, and the actual frequency f_actual of each measured clock is calculated. The calculation formula is: f_actual=N / T, where N is the number of rising edges of the measured clock within the frequency measurement window, and T is the time length of the frequency measurement window.

[0090] The jitter value of the clock under test is obtained by continuously measuring the length of 1000 preset clock cycles using the continuous cycle measurement method and calculating the standard deviation of all cycle lengths.

[0091] A phase comparison algorithm is used to compare the phases of the main global clock signal and the backup global clock signal, outputting a pulse signal proportional to the phase difference between the two clocks. The width of the pulse signal is measured, and the phase difference between the two clocks is calculated. The clock fault monitoring logic in the fault detection circuit synchronously acquires clock measurement parameters to achieve dual verification of clock faults.

[0092] Step S214: Based on the clock operation parameters of the global clock generation path, determine whether the main global clock signal is normal. If not, trigger the backup global clock signal switching operation and output the global clock signal.

[0093] The backup global clock signal switching operation refers to the process of switching the clock source of all logic circuits from the main global clock signal to the backup global clock signal when the main global clock signal fails. The frequency, jitter, and phase difference parameters of the main global clock signal are compared with preset normal thresholds; when any parameter exceeds the preset normal threshold, it is determined that the main global clock signal has failed, and the backup global clock signal switching operation is immediately triggered; the switching operation is performed on the falling edge of the clock to ensure that no glitches are generated during the switching process; after the switching is completed, the clock source of all logic circuits automatically switches to the backup global clock signal.

[0094] In this embodiment, the programmable logic device reads the measurement parameters of the main global clock signal every 1ms; when the frequency error of the main global clock signal is detected to be >1ppm, jitter >100ps, or phase difference >10°, the main global clock signal is immediately determined to be abnormal; on the next falling edge of the main global clock signal, the clock source of all logic circuits is automatically switched from the main global clock signal to the backup global clock signal.

[0095] Step S215: If the backup global clock signal switching operation is triggered, update the clock operating status and report the clock fault information to the upper-level control unit;

[0096] The clock operating status includes the current clock source, clock operating parameters, and fault occurrence time; the clock fault information includes the fault occurrence time, the faulty clock path number, the fault type, and the operating status after switching; the fault types include frequency abnormality, jitter abnormality, and phase difference abnormality.

[0097] Specifically, step S21 is the core of the entire global time base construction process. Its core design aims to solve the key problems in existing technologies, such as high risk of single-point failure of the global clock, untimely clock failure detection, and easy circuit interruption during switching. It provides the circuit with a highly reliable and uninterrupted global clock source. Industrial environments are complex, and factors such as electromagnetic interference, power fluctuations, and temperature changes can all cause clock anomalies. In traditional single-clock solutions, once the clock fails, the entire circuit will immediately be paralyzed, leading to problems such as equipment malfunction and cargo damage. At the same time, most existing clock failure detection methods have low accuracy and slow response, and cannot detect subtle changes in clock operating parameters in time, resulting in a gradual and undetectable decrease in circuit synchronization accuracy. Step S21 establishes two independent global clock generation paths through step S211, achieving redundant backup of the clock source; step S212 configures scientifically reasonable monitoring operating parameters and fault judgment criteria to ensure accurate detection of clock faults; step S213 employs high-precision frequency, jitter, and phase difference measurement methods to achieve real-time and accurate monitoring of the clock's operating status; step S214 performs a seamless switching operation on the falling edge of the clock, ensuring a glitch-free and uninterrupted switching process; and step S215 promptly reports fault information, facilitating timely repair by maintenance personnel. Without step S21, the circuit would be at risk of a single point of failure in the global clock, leading to immediate circuit paralysis if the clock fails; simultaneously, abnormal changes in clock operating parameters cannot be detected in a timely manner, causing a gradual decrease in circuit synchronization accuracy and ultimately failing to meet the high-precision control requirements of industrial environments.

[0098] Step S22: The global clock signal output by the dual-mode redundant global clock tree drives the global timestamp counting logic to run and establish a global time base;

[0099] The global timestamp counting logic refers to a continuous counting logic driven by a global clock, used to generate the system's global timestamp count value. The global time base refers to the reference standard for the timestamps of all sensor data in the system, which is composed of a clock source and continuous global timestamp count values. The global clock signal is synchronously distributed to the global timestamp counting logic via the FPGA's internal global clock routing network. The global timestamp counting logic continuously increments the count based on the global clock signal, providing a unified time base for subsequent timestamp marking of all sensors.

[0100] Step S23: Based on the global time reference, a periodic calibration mechanism is adopted. The hardware link delay parameters of each sensor channel and the physical response delay parameters of each sensor are quantized and measured by the delay measurement logic built into the programmable logic device and the standard signal source. A hardware link delay compensation table and an individual delay compensation table are constructed.

[0101] This step uses the global time reference established in step S22 as the basis for unified timing traceability. Relying on the high-precision measurement logic and synchronous standard signal source built into the programmable logic device, the calibration process is triggered during the device power-on and startup phase and at preset measurement cycle nodes. The quantitative acquisition and statistical processing of hardware link delay and sensor individual physical response delay are completed in sequence. Based on the measured delay parameters, structured hardware link delay compensation tables and individual delay compensation tables are constructed and stored respectively, realizing hierarchical filing of hardware inherent transmission error and sensor body response error, providing dynamically updatable reference parameters for subsequent timestamp correction.

[0102] Furthermore, step S23 includes:

[0103] Step S231: In response to the initial startup of the programmable logic device and the arrival of the measurement cycle, a calibration operation is triggered; the measurement cycle refers to the fixed time interval between two background periodic calibrations, which is used to adapt to the slow time-varying drift caused by temperature, device aging, and environmental interference. Its setting is based on the rate of temperature change in the industrial environment, the slow aging characteristics of the device, and the system synchronization accuracy and stability requirements. Under the premise of ensuring that the timing compensation accuracy is not degraded, the background calibration occupancy rate of logic resources is reduced as much as possible. For example, the measurement cycle is 30 minutes.

[0104] Step S232: When the programmable logic device is initially started, the programmable logic device synchronously starts the built-in delay measurement logic and standard signal source, and sequentially completes the full measurement of the hardware link delay of all sensor channels and the physical response delay of individual sensors based on the global time reference, and generates a hardware link delay compensation table and an individual delay compensation table.

[0105] The hardware link delay refers to the transmission delay of the electrical signal from the sensor output to the timestamp input of the programmable logic device, including PCB trace delay and interface circuit delay. During calibration, for sensor interfaces with loopback testing capabilities, a loopback measurement method is used: a standard pulse signal is sent to the transmitting end of the interface, and the transmission delay of the pulse signal from the transmitting end to the receiving end is measured; after repeating the measurement a preset number of times, the average value is taken as the hardware link delay of that channel. For unidirectional input interfaces, a factory pre-calibration and field comparison method is used: before the equipment leaves the factory, a high-precision time measuring instrument is used to calibrate the hardware link delay of each sensor interface and the individual response delay of each sensor, and the results are written into the hardware link delay compensation table and the individual delay compensation table.

[0106] The standard signal source refers to the hardware logic integrated within a programmable logic device that can output standard trigger pulses; the physical response delay refers to the time from when the sensor senses a change in a physical quantity to when it outputs a corresponding electrical signal, which is an inherent characteristic of the sensor. During calibration, standard trigger pulses are sent to all sensors simultaneously, and the arrival time of the response signal of each sensor is recorded. The individual physical response delay of the sensor is equal to the arrival time of the response signal minus the trigger pulse transmission time minus the hardware link delay of that channel; after repeating the measurement a preset number of times, the average value is taken as the individual delay compensation value of the sensor.

[0107] The preset number of times refers to the number of consecutive effective measurements of a single channel and a single sensor during a single calibration process. Its setting needs to take into account both the random measurement noise suppression effect and the calibration time. The higher the number of measurements, the more stable the statistical mean and the smaller the random error. At the same time, it will moderately increase the initial calibration time. For example, the preset number of times is 1000.

[0108] The hardware link delay compensation table consists of a channel index, the sensor type corresponding to the channel, single measurement delay data, average delay of multiple sets of measurements, global measurement timestamp, and channel calibration status identifier. With the sensor hardware channel number as the core index, it independently stores the exclusive transmission delay parameters of each channel, realizing independent recording and differentiated compensation of hardware differences among multiple channels.

[0109] The individual delay compensation table consists of sensor number, bound channel number, sensor type, individual average response delay obtained from multiple sets of measurement statistics, measurement environment temperature, calibration global timestamp, and parameter validity status identifier; using the sensor body number and channel number as a joint index, it independently records the individual response delay characteristics of each sensor, realizing accurate archiving of individual discrete errors of the same model of sensor.

[0110] Step S233: When the measurement cycle arrives, the programmable logic device performs incremental delay measurement based on the global time reference within the idle timing window, and dynamically updates the hardware link delay compensation table and individual delay compensation table through drift determination.

[0111] The idle timing window refers to the bus idle and logic idle period after the programmable logic device has completed two consecutive frames of sensor data acquisition. During this period, there are no data acquisition tasks or real-time control calculation tasks. The idle timing window between sensor data acquisitions is used to perform background incremental calibration. Without interrupting business operation or occupying real-time control timing, the built-in delay measurement logic and standard signal source are reused to complete the quantitative measurement of the hardware link delay of all sensor channels and the physical response delay of individual sensors. The hardware link delay of all sensor channels and the physical response delay of individual sensors are compared with the arrival time of the previous measurement cycle. Drift judgment is performed, and the hardware link delay compensation table and individual delay compensation table are hot-updated to realize the adaptive adaptation of delay parameters to the environment and device aging.

[0112] The drift determination refers to calculating the difference between the delay parameter obtained from the current periodic calibration measurement and the effective delay parameter of the previous period stored in the compensation table, and then combining this with a system-preset delay drift threshold to determine whether the parameter has experienced effective drift. When the parameter difference is less than the preset delay drift threshold, the current link and sensor status is considered stable, and the original compensation parameters are retained without updating. When the parameter difference is greater than or equal to the preset delay drift threshold, it is determined that factors such as ambient temperature fluctuations or device aging have caused delay drift. The average parameter of the current measurement is immediately used to overwrite the original data table parameters, completing the dynamic hot update of the compensation table and ensuring the long-term stability of the system's timing compensation accuracy. The preset delay drift threshold is a critical deviation amount preset by the system to determine whether the delay parameter has experienced substantial drift. It is a quantitative judgment threshold that distinguishes between random measurement noise and actual operating condition drift. Its setting is based on the system's timing synchronization accuracy design requirements, the random error characteristics of the hardware measurement logic, and the normal fluctuation range of industrial environmental disturbances. It can effectively identify the actual delay offset caused by temperature changes and device aging while suppressing frequent erroneous parameter updates. For example, the preset drift threshold is 50ps.

[0113] Specifically, step S23 relies on a unified global time reference to achieve time-series traceability of delayed measurements, completes basic parameter filing through initial power-on calibration, achieves dynamic adaptation of slow time-varying errors through periodic background calibration, and achieves differential error quantification for each channel and each sensor through a structured compensation table. This solves the technical defects of traditional methods, such as inconsistent measurement references, mixed errors, and inability to be dynamically updated, and provides hierarchical, traceable, and iterative reference parameter support for subsequent accurate correction of multi-sensor timestamps.

[0114] Specifically, step S2 is the time base establishment and initial calibration stage of the entire multi-sensor timestamp synchronization method based on programmable logic. Its core design addresses the key issues in existing technologies, such as the high risk of single-point failure of the global clock and the fact that only coarse uniform calibration ignores individual differences, leading to actual synchronization accuracy far below theoretical values. This provides a precise and reliable time basis for subsequent timestamp marking and data alignment. Industrial environments are complex; electromagnetic interference, temperature changes, and other factors can cause clock anomalies. In traditional single-clock solutions, once the clock fails, the entire circuit immediately collapses. Simultaneously, differences in PCB trace lengths and the discreteness of individual sensor physical response delays introduce systematic errors of tens or even hundreds of nanoseconds. If these errors are not calibrated, they will directly lead to a decrease in synchronization accuracy. Step S2, through the dual-mode redundant global clock tree construction and clock status monitoring in S21, achieves high reliability of the clock system. In the event of a master clock failure, the system can seamlessly switch to the backup clock without affecting normal operation. By driving the global timestamp counting logic and using balanced clock tree routing, a unified, continuous, and low-skew global time reference is established, ensuring that all timestamps have the same reference standard. Through channel-by-channel measurement of hardware link delay and measurement of individual sensor physical response delay, time errors caused by PCB trace length differences and individual sensor differences are eliminated. Without step S2, the circuit would be at risk of a single point of failure in the global clock, which could lead to circuit paralysis. Simultaneously, uncalibrated hardware link delays and individual sensor delays would introduce significant systematic errors, resulting in actual synchronization accuracy far lower than the theoretical value, failing to meet the high-precision control requirements of industrial environments, and ultimately causing equipment malfunction and cargo damage.

[0115] Step S3: Match the acquisition trigger mode for each sensor according to the synchronization requirement parameters, allocate an independent timestamp marking circuit, and acquire sensor data; based on the global time reference, hardware link delay compensation table, and individual delay compensation table output in step S2, correct the sensing real timestamp of the sensor data acquired by each sensor, and complete the dynamic error correction by combining the hardware link delay compensation parameters and sensor individual delay compensation parameters, so as to obtain the effective sampling data of each sensor with accurate synchronization, and complete the multi-sensor acquisition frequency normalization processing.

[0116] Please see Figure 3 Furthermore, step S3 includes:

[0117] Step S31: Configure the acquisition trigger mode differently for each sensor according to the synchronization requirement parameters. The acquisition trigger mode includes synchronous trigger mode, asynchronous sampling mode and interrupt trigger mode; and independently allocate a timestamp marking circuit for each sensor interface. The timestamp marking circuits of each channel do not reuse each other and work independently.

[0118] This step, based on the overall system timing synchronization accuracy, sensor output cycle characteristics, and data output format, completes the classification and adaptation of acquisition trigger modes. At the same time, it achieves physical isolation of channel timing marker resources through hardware resource partitioning configuration, avoiding timing crosstalk and resource contention between channels.

[0119] For high-frequency sensors with fixed-period output, a synchronous triggering mode is used; for sensors with random data output, an asynchronous sampling mode is used; and for sensors with event-triggered output, an interrupt triggering mode is used, achieving adaptability configuration for heterogeneous sensor acquisition logic. For example, a synchronous triggering mode is used for a 100Hz IMU attitude sensor and a 50Hz wheel speed sensor; an asynchronous sampling mode is used for a 20Hz ultrasonic distance sensor; and an interrupt triggering mode is used for a 1Hz RFID positioning sensor. The timestamp marking circuit is a reconfigurable logic circuit dynamically configured in step S1, driven throughout by the global clock signal output in step S2, and strictly synchronized with the global timestamp counting logic timing to ensure complete consistency between the marking timing and the global time reference.

[0120] Step S32: Drive the timestamp marking circuit based on the global clock signal, and combine it with the acquisition trigger mode to complete the acquisition of sensor data from each channel and bind it with the original timestamp;

[0121] The sensing data refers to the initial sensing data collected and output by each sensor without time correction, including position data, attitude data, distance data, velocity data, etc.

[0122] Each channel's independent timestamp marking circuit continuously monitors the physical pin level of the corresponding sensor interface. At the instant the effective transmission edge of the sensing data reaches the physical pin of the programmable logic device, it latches the real-time global timestamp count value of the current global timestamp counting logic and binds this global timestamp count value as the original timestamp to the sensor sensing data of the corresponding frame, forming a sensing data frame carrying the original timestamp. The timestamp marking operations of all channels are executed in parallel and independently, and there is no timing interference between channels, ensuring the real-time and parallelism of marking multi-channel heterogeneous sensor data. This eliminates the problem of timing lag in marking from the hardware level. The sensor fault detection circuit monitors the validity of the sensing data of the corresponding channel in real time. If data loss or abnormality is detected, it is reported immediately.

[0123] In this embodiment, the six sensors correspond to six independent timestamp marking circuits, all of which are synchronously driven by a global clock signal, with a timestamp resolution of 10ns. The timestamp marking circuit monitors the data transmission signals of each sensor interface in real time. For the different sampling frequencies of the 1Hz RFID positioning sensor, 100Hz six-axis IMU attitude sensor, 20Hz ultrasonic distance sensor, and 50Hz wheel speed sensor, it adaptively matches the data trigger timing. For each frame of valid sensor data received, the global timestamp count value is immediately latched and bound to the original timestamp.

[0124] Step S33: Retrieve the hardware link delay compensation table. The programmable logic device reads the hardware link delay compensation value corresponding to the current sensing data channel by channel, performs reverse compensation correction on the original timestamp, and obtains the hardware link corrected timestamp to eliminate the timing lag error caused by hardware link transmission. The correction logic is: Hardware link corrected timestamp = Original timestamp - Hardware link delay compensation value of the corresponding channel. The hardware timing error calibration of all sensing data is completed frame by frame. The original timestamp is the time when the data arrives at the FPGA physical pin. Subtracting the hardware link transmission delay, the time when the data is sent from the sensor output is obtained.

[0125] Step S34: Based on the hardware link delay correction, the programmable logic device further retrieves the individual delay compensation value corresponding to the current sensor from the single sensor individual delay compensation table to complete the secondary correction, obtaining the true sensing timestamp of the sensing data and eliminating the timing deviation caused by the inherent response delay of the sensor; the correction logic is: True sensing timestamp = Hardware link correction timestamp - Corresponding sensor individual delay compensation value. By subtracting the sensor individual response delay, the true moment when the sensor actually senses the change in the physical quantity is obtained.

[0126] Step S35: Obtain the sampling frequency of each sensor data pre-configured in the synchronization requirement parameters of the programmable logic device, determine the unified output frequency, call the interpolation calculation circuit, perform upsampling or downsampling to unify the output frequency, and bind the sensor data with the unified output frequency to the corresponding interpolation synchronization timestamp.

[0127] In this embodiment, the sensor configuration parameters obtained in step S1 are extracted to acquire the sampling frequencies of the six sensors: a 1Hz RFID positioning sensor, a 100Hz six-axis IMU attitude sensor, a 20Hz lateral ultrasonic distance sensor, and a 50Hz wheel speed sensor. Based on a 10ms control cycle, a globally unified output frequency of 100Hz is determined, ensuring that the final output data of all sensors is aligned with this 10ms cycle, guaranteeing that the upper-level control unit can synchronously acquire the latest data from all sensors in each control cycle. The two sets of linear interpolation calculation circuits configured in step S1 are invoked, and channel-by-channel processing is performed according to the strategy of high-frequency hold, low-frequency upsampling, and ultra-low-frequency time axis fitting. For the 100Hz six-axis IMU attitude sensor, whose original sampling frequency matches the target frequency, the sampling frequency is not... Interpolation is performed, directly retaining the original data and corresponding perceived real timestamps. For the 50Hz wheel speed sensor, the first set of interpolation calculation circuits performs 2x linear upsampling: based on two adjacent frames of original wheel speed data and the corresponding perceived real timestamps, one linear interpolation data point is evenly inserted on the time axis to align the output data beat to 100Hz. For the 20Hz lateral ultrasonic distance sensor, the second set of interpolation calculation circuits performs 5x linear upsampling: based on two adjacent frames of original distance data and the corresponding perceived real timestamps, four linear interpolation data points are evenly inserted on the time axis to normalize to 100Hz output. For the 1Hz... The RFID positioning sensor employs time-axis sliding linear fitting interpolation: a linear fitting model is established based on three consecutive frames of original positioning data and their corresponding real-time sensing timestamps. Fitted interpolation data is generated in real time at each 10ms control cycle node and padded to 100Hz output. Frequency normalization operations for all channels are performed in parallel. Each frame of data after normalization is re-bound to an interpolation synchronization timestamp aligned with the 100Hz beat, ultimately outputting standardized sensor data frames with uniform format, consistent frequency, and accurate timing.

[0128] Step S36: Encapsulate the frequency-normalized sensor data and the corresponding interpolation synchronization timestamp into a unified format data frame, cache it in the data cache circuit, and complete the multi-sensor timing alignment preprocessing.

[0129] The sensor data, after undergoing double delay correction, possesses a unified global time reference, eliminates hardware transmission errors and individual sensor errors, and forms synchronous sensor data with consistent timing and uniform accuracy. The sensor data with interpolated synchronization timestamps is cached in the data cache circuit of the corresponding channel, providing a high-precision time data source for subsequent multi-sensor fusion, robot posture calculation, and track derailment prevention closed-loop control.

[0130] Specifically, step S3 is the core execution step of multi-sensor timing synchronization and data preprocessing. Its core design aims to solve the key problems in existing technologies where multi-sensor data are only uniformly time-stamped, without distinguishing between hardware link differences and individual sensor differences, resulting in timing misalignment and insufficient synchronization accuracy. Building upon the clock reference and error calibration results of step S2, it achieves end-to-end timing optimization from clock reference and error calibration to timestamp marking. In industrial settings, multiple heterogeneous sensors have different sampling frequencies, different hardware link delays, and significant differences in individual response characteristics. Traditional uniform timestamp marking methods cannot adapt to multi-dimensional errors, easily leading to data timing misalignment, causing deviations in robot posture calculation, misjudgments of track offsets, and resulting in malfunctions such as derailment and cargo tipping. Step S3, through steps S31 and S32, utilizes the global clock signal to achieve global synchronization timestamp marking, ensuring that all sensor data are based on the same time reference. Step S33 calibrates hardware link transmission errors channel by channel, eliminating fixed timing deviations caused by PCB traces and interface circuits. Step S34 calibrates individual response errors sensor by sensor, compensating for dynamic errors caused by sensor process discreteness and environmental drift. Steps S35 and S36 output high-precision synchronized data, providing reliable data support for upper-level fusion control. Without step S3, the sensor data from each channel will have inherent timing errors, the timing of multi-source data cannot be aligned, the accuracy of multi-sensor fusion will be significantly reduced, failing to meet the high-precision real-time control requirements of industrial robots, and greatly reducing the stability and safety of equipment operation.

[0131] Step S4: Collect operating condition parameters, and when changes in operating conditions cause substantial delay drift, generate dynamic delay compensation values ​​for operating conditions, and correct the hardware link delay compensation table and individual delay compensation table.

[0132] This step collects operating parameters in real time, uses a threshold triggering mechanism to generate dynamic delay compensation values ​​for operating conditions, and updates the hardware link delay compensation table and individual delay compensation table. This enables the delay compensation parameters to adapt to changes in on-site operating conditions in a conditional manner, providing a dynamically adjustable compensation basis for subsequent timing synchronization stability optimization.

[0133] Furthermore, step S4 includes:

[0134] Step S41: Real-time acquisition of operating parameters through analog-to-digital conversion circuit, setting the allowable threshold for operating fluctuation of each operating parameter to determine whether the change in operating condition causes substantial delay drift. If so, the operating condition dynamic delay compensation value is generated through the operating condition compensation calculation circuit. The operating condition dynamic delay compensation value includes hardware link delay drift and individual response delay drift.

[0135] Please see Figure 4 Furthermore, step S41 includes:

[0136] Step S411: The programmable logic device continuously collects operating parameters through its built-in analog-to-digital converter circuit; the operating parameters include ambient temperature and power supply voltage; for each set of operating parameters collected, the current operating parameter reference value is updated for subsequent fluctuation calculation; the collected operating parameter data is directly input into the operating condition compensation calculation circuit for real-time processing.

[0137] Step S412: Calculate the difference between the current operating condition parameter baseline value and the operating condition parameter baseline value when the compensation was last effective to obtain the operating condition fluctuation amount. Combine this with the preset operating condition fluctuation allowable threshold to determine whether the change in operating condition has caused substantial delay drift. The operating condition fluctuation amount includes the ambient temperature fluctuation amount and the power supply voltage fluctuation amount.

[0138] The preset operating condition fluctuation allowable threshold refers to the maximum change in operating condition parameters that is pre-set and will not cause the timing synchronization accuracy to exceed the design specifications. It serves as a quantitative judgment boundary to distinguish between normal operating condition fluctuations and substantial drifts that require compensation. Its setting is based on the system's maximum allowable synchronization error of ≤10ns, the temperature delay characteristics of the programmable logic device interface circuit, the voltage response characteristics of the sensor, and the typical operating condition fluctuation range in industrial settings. While ensuring that synchronization accuracy does not deteriorate, it aims to minimize the compensation update frequency and avoid frequent parameter jitter. For example, the preset ambient temperature fluctuation allowable threshold is 2℃, and the preset power supply voltage fluctuation allowable threshold is 0.1V.

[0139] If the ambient temperature fluctuation |ΔT| > 2℃ or the power supply voltage fluctuation |ΔV| > 0.1V, it is determined that the change in operating conditions has caused a substantial drift in hardware link transmission delay and sensor response delay, and the calculation of the dynamic delay compensation value for the operating conditions is immediately triggered; otherwise, it is determined that the change in operating conditions is within the normal fluctuation range, no new dynamic delay compensation value for the operating conditions is generated, and the currently effective compensation parameters are used.

[0140] In this embodiment, the ambient temperature when the compensation was last effective was 25°C and the power supply voltage was 5.0V. When the current ambient temperature is 27.5°C and the power supply voltage is 5.05V, the ambient temperature fluctuation ΔT = 2.5°C > 2°C, triggering dynamic compensation calculation. When the current ambient temperature is 26°C and the power supply voltage is 5.08V, the ambient temperature fluctuation ΔT = 1°C ≤ 2°C and the voltage fluctuation ΔV = 0.08V ≤ 0.1V, so compensation is not triggered.

[0141] Step S413: If the change in operating conditions causes a substantial drift in delay, the pre-calibrated delay correction coefficient matrix is ​​called, the corresponding correction coefficient is matched based on the interval where the current operating condition parameters are located, and the target correction coefficient is calculated by combining linear interpolation to generate the dynamic delay compensation value of the operating condition.

[0142] The delay correction coefficient matrix refers to a structured mapping table established before the equipment leaves the factory through full-condition calibration. It is used to quantify the coupling effect of operating condition parameters on hardware link delay and sensor response delay. It consists of operating condition parameter range index, channel-by-channel hardware link delay correction coefficient, and sensor-by-sensor individual response delay correction coefficient.

[0143] In this embodiment, the delay correction coefficient matrix is ​​a two-dimensional structured data table stored in the non-volatile memory inside the programmable logic device. The row dimension represents the temperature range, divided with a temperature fluctuation tolerance threshold of 2°C, covering the entire operating temperature range of -40°C to 85°C in industrial environments, totaling 63 temperature ranges. The column dimension represents the voltage range, divided with a voltage fluctuation tolerance threshold of 0.1V, covering the rated power supply voltage range of 4.5V to 5.5V, totaling 11 voltage ranges. Each element of the delay correction coefficient matrix corresponds to the intersection of a temperature range and a voltage range, storing the channel-by-channel hardware link delay correction coefficient and the sensor-by-sensor individual response delay correction coefficient under that operating condition. The delay correction coefficient matrix is ​​generated through full-condition calibration before the equipment leaves the factory: the equipment is placed in a high and low temperature test chamber, and with the help of an adjustable DC power supply, all temperature and voltage ranges are traversed. The hardware link delay of each channel and the individual response delay of each sensor are measured respectively. The ratio is calculated with the reference delay under the standard operating condition of 25℃ / 5.0V to obtain the correction coefficient for the corresponding range. The measurement is repeated and the average value is stored in the delay correction coefficient matrix.

[0144] Furthermore, step S413 includes:

[0145] Step S4131: Based on the current operating condition parameter baseline value, locate the vertex of the adjacent interval in the delay correction coefficient matrix:

[0146] In this embodiment, the operating condition compensation calculation circuit calculates the interval index of the current ambient temperature T and power supply voltage U in the delay correction coefficient matrix:

[0147] Temperature range index i = floor((T - (-40℃)) / 2℃), where floor( `i` is a floor function that returns the largest integer not greater than the input value; if `i` < 0, then `i` = 0; if `i` ≥ 63, then `i` = 62; the voltage range index `j` = `floor((U - 4.5V) / 0.1V)`, if `j` < 0, then `j` = 0; if `j` ≥ 11, then `j` = 10; here, `i` and `j` are both range indices, used to identify the basic range in which the current operating condition parameters fall. The lower left vertex of this basic range corresponds to index (i, j), and the upper right vertex corresponds to index (i+1, j+1); thus, the basic range in which the current operating condition is located is obtained. The four adjacent vertices constituting this basic interval are indexed as (i,j), (i,j+1), (i+1,j), and (i+1,j+1). The hardware link correction coefficients k_hw(i,j), k_hw(i,j+1), k_hw(i+1,j), and k_hw(i+1,j+1), as well as the individual response correction coefficients k_sen(i,j), k_sen(i,j+1), k_sen(i+1,j), and k_sen(i+1,j+1), are read from these four vertices. If the current operating condition parameter falls exactly at an interval vertex, i.e., the temperature or voltage parameter is exactly equal to the interval boundary value, then the correction coefficient of the corresponding vertex is directly used, without needing to perform subsequent interpolation calculations.

[0148] Step S4132: Calculate the target correction coefficient under the current operating condition using bilinear interpolation. Since the actual operating parameters usually fall within the interval rather than at the apex, bilinear interpolation is used to eliminate the calculation error caused by interval discretization, ensuring the accuracy of the correction coefficient.

[0149] Calculate the temperature direction interpolation weight: w_T = (T - (-40℃) - i × 2℃) / 2℃, with a value range of 0 ≤ w_T ≤ 1; Calculate the voltage direction interpolation weight: w_U = (U - 4.5Vj × 0.1V) / 0.1V, with a value range of 0 ≤ w_U ≤ 1; Calculate the hardware link target correction coefficient k_hw_final:

[0150] k_hw_final=k_hw(i,j)×(1-w_T)×(1-w_U)+k_hw(i,j+1)×(1-w_T)×w_U+k_hw(i+1,j)×w_T×(1-w_U)+k_hw(i+1,j+1)×w_T×w_U;

[0151] Calculate the target correction coefficient k_sen_final for the individual sensor response:

[0152] k_sen_final=k_sen(i,j)×(1-w_T)×(1-w_U)+k_sen(i,j+1)×(1-w_T)×w_U+k_sen(i+1,j)×w_T×(1-w_U)+k_sen(i+1,j+1)×w_T×w_U;

[0153] Step S4133: Calculate the dynamic delay compensation value for the layered operating conditions based on the target correction coefficient, and calculate the corresponding drift amount for both hardware link delay and individual sensor response delay:

[0154] Single-channel hardware link delay drift = current reference compensation value of the channel × (k_hw_final-1), single sensor individual response delay drift = current reference compensation value of the sensor × (k_sen_final-1);

[0155] The current baseline compensation value is the compensation parameter currently in effect in the hardware link delay compensation table and the individual delay compensation table.

[0156] Step S4134: Update the current operating condition parameter baseline value to the operating condition parameter baseline value for this compensation, for use in the next calculation of operating condition fluctuation.

[0157] Step S42: Based on the dynamic delay compensation value under operating conditions, update the hardware link delay compensation table and the individual delay compensation table in layers;

[0158] For hardware link delay drift, the corresponding drift is superimposed on each channel to complete the parameter update; for individual sensor response delay drift, the corresponding drift is superimposed on each sensor to complete the parameter update; the parameter update adopts background hot update method, which is executed within the idle time window defined in step S233, and the real-time data acquisition and timestamp correction process is not interrupted during the update process.

[0159] Specifically, step S4 builds upon the timing marking results of step S3. Through a clearly defined upsampling, downsampling, and fitting interpolation process, it achieves unified and regularized frequencies across multiple sensors. Simultaneously, it uses threshold-triggered operating condition compensation and two-dimensional matrix interpolation calculation to achieve precise dynamic adaptation of delay parameters. This solves the problems of inconsistent frequencies among heterogeneous sensors and the inability of static compensation to adapt to changes in operating condition coupling, providing frequency-unified and timing-stable sensor data for subsequent global timing calibration and anomaly identification. Without step S4, the output frequencies of multiple sensors would be mismatched, and the operating condition drift caused by temperature and voltage coupling could not be adaptively compensated, leading to a continuous deterioration in synchronization accuracy with environmental changes. This step differs from traditional fixed-parameter compensation schemes, abandoning the static calibration parameter-unchanging compensation mode. Through a hierarchical mechanism of real-time operating condition monitoring, threshold-triggered compensation, and precise correction via bilinear interpolation, it achieves dynamic iterative updates of delay compensation parameters, effectively solving the problem of timing synchronization accuracy attenuation caused by temperature and pressure drift in industrial settings, and ensuring the timing stability of equipment under all operating conditions and for extended periods of continuous operation.

[0160] Step S5: Receive the external absolute time synchronization signal through the external synchronization signal receiving logic to calibrate the global time base, and use the built-in statistical and discrimination logic of the programmable logic device to count the drift amount, determine whether there is a timing synchronization abnormality, and identify the abnormality type of the programmable logic device.

[0161] This step uses an external high-precision absolute time synchronization signal as an independent truth benchmark to quantify the overall deviation characteristics of the global timing system. When the global deviation exceeds the normal aging range, the source is traced layer by layer according to the timestamp generation process to identify the anomaly type, providing a clear technical basis for subsequent fault isolation, fault tolerance processing and preventive maintenance of equipment.

[0162] Please see Figure 5 Furthermore, step S5 includes:

[0163] Step S51: The external synchronization signal receiving logic receives the external absolute time synchronization signal according to the preset calibration cycle, and latches the real-time count value of the global timestamp counting logic at the moment of the signal's effective trigger edge to establish a global time calibration reference pair;

[0164] The system receives external high-precision absolute time synchronization signals at fixed time intervals during the calibration cycle. At the effective trigger edge of the signal, it instantaneously latches the current count value of the global timestamp counting logic within the programmable logic device. The system then pairs the standard time truth value carried by the external absolute time synchronization signal with the latched global timestamp count value to form a global time calibration reference pair for subsequent calibration and deviation calculation. The fault detection circuit's fault monitoring logic monitors the operating status of the external synchronization signal receiving logic in real time, and immediately reports any signal loss or abnormality detected.

[0165] The preset calibration cycle refers to a fixed time interval between two external absolute time calibrations. Its setting is based on the long-term aging drift characteristics of the crystal oscillator, the design specification of a maximum permissible synchronization error ≤10ns, the rate of change of industrial field conditions, and the continuous operating time requirements of the equipment. While ensuring that the accuracy of the global time reference does not deteriorate, it aims to minimize the dependence on external synchronization signals and the impact of the calibration process on real-time control. For example, the preset calibration cycle is 10 minutes; this cycle ensures that the accumulated aging drift of the crystal oscillator does not exceed 2ns, which is far less than the maximum permissible synchronization error of 10ns, while avoiding frequent calibrations that consume logic resources and interrupt normal data acquisition processes. The external absolute time synchronization signals include GPS second pulse signals, BeiDou second pulse signals, and industrial Ethernet PTP precise time protocol synchronization signals.

[0166] Step S52: The built-in deviation calculation logic of the programmable logic device calculates the global time deviation of the current calibration cycle based on the global time calibration reference pair, and calculates the single global calibration drift in combination with the calibration cycle to construct a global drift sequence;

[0167] Based on the global time measurement value and the external absolute time true value in the global time calibration reference pair, the global time absolute deviation of this calibration is calculated; combined with the fixed time interval between two calibrations, the single global calibration drift of the global time series system is calculated; the single global calibration drift obtained from each calibration is arranged in chronological order to construct a global drift sequence for characterizing the long-term trend of global time series changes.

[0168] Step S53: The statistical analysis logic built into the programmable logic device performs statistical analysis on the global drift sequence, establishes a dual abnormal drift judgment benchmark including a single drift abnormal threshold and a sequence fluctuation abnormal threshold, and determines whether there is a global timing synchronization abnormality.

[0169] A global timing synchronization anomaly is determined to exist when any of the following conditions are met:

[0170] Condition 1: The current single global calibration drift amount is greater than the single drift anomaly threshold;

[0171] Condition 2: The standard deviation of the global drift sequence of the most recent 10 calibrations is greater than the abnormal threshold of the sequence fluctuation.

[0172] If a global timing synchronization anomaly exists, it is determined to be a global clock anomaly; if no global timing synchronization anomaly exists, a single-channel local deviation is calculated for each sensor acquisition channel. The single-channel local deviation = the channel's actual sensing timestamp - the external absolute time truth value - the global time deviation. When the absolute value of the single-channel local deviation is greater than the system's maximum allowable synchronization error, it is determined that the channel has a local timing anomaly, and all sensor acquisition channels with local timing anomalies are identified.

[0173] The single-event drift anomaly threshold refers to the critical frequency deviation value that distinguishes between normal aging drift and sudden abnormal drift of the crystal oscillator. It is set based on the upper limit of normal aging drift for industrial-grade high-precision active crystal oscillators, the maximum permissible synchronization error requirement of the system, and the calibration cycle length. It is used to identify large timing jumps that exceed the normal range during a single calibration. For example, the single-event drift anomaly threshold is 0.5 ppm; this value corresponds to a time deviation of approximately 3 ns within a 10-minute calibration cycle, which is far less than the maximum permissible synchronization error of 10 ns.

[0174] The sequence fluctuation anomaly threshold refers to the critical standard deviation that distinguishes between normal and stable operation and persistent instability of a global timing system. It is set based on the statistical characteristics of the drift sequence of an industrial-grade high-precision active crystal oscillator during normal operation, the system's timing stability requirements, and the level of interference in the industrial environment. It is used to identify persistent, minor fluctuations in the global timing system. For example, the sequence fluctuation anomaly threshold is 0.1 ppm; this value is the upper limit of the standard deviation of the drift sequence of an industrial-grade high-precision active crystal oscillator under normal operating conditions.

[0175] Step S54: If the global clock is determined to be abnormal, the built-in abnormality discrimination logic of the programmable logic device performs global clock fault tolerance processing; otherwise, for sensor acquisition channels with local timing abnormalities, a single-channel local abnormality identification process is entered to identify single-channel abnormalities, including abnormalities in the original timestamp mark, abnormalities in the perceived real timestamp, and abnormalities in the dynamic delay compensation of the operating condition; the execution of global clock fault tolerance processing means: immediately triggering the backup global clock signal switching operation in step S214, switching the clock source of all logic circuits from the faulty main global clock signal to the hot-backup backup global clock signal; at the same time, updating the clock operating status, reporting global clock fault information including the fault occurrence time, fault type, and operating status after switching to the upper-level control unit; recording the fault log and increasing the monitoring frequency of the clock monitoring logic to 10kHz to continuously monitor the operating status of the backup clock.

[0176] Furthermore, step S54 includes:

[0177] Step S541: The original timestamp discrimination logic built into the programmable logic device extracts the original timestamp of a single channel with timing synchronization abnormality, calculates the statistical characteristics of the original timestamp interval, compares the statistical characteristics of the original timestamp interval with the preset normal characteristic range of the original timestamp, and if it exceeds the normal characteristic range of the original timestamp, it is determined that the original timestamp marking is abnormal.

[0178] The statistical characteristics of the original timestamp interval include the standard deviation of the original timestamp interval and the maximum jump in the original timestamp interval. The standard deviation of the original timestamp interval is a statistical measure characterizing the degree of random jitter of the original timestamp in a single channel, obtained by calculating the standard deviation of the original timestamp interval values ​​of a consecutive preset number of frames within the current calibration period. The larger the value, the more severe the random jitter of the original timestamp and the worse the stability of the timestamp. The maximum jump in the original timestamp interval is a statistical measure characterizing the degree of sudden deviation of the original timestamp in a single channel, obtained by calculating the maximum absolute difference between the original timestamp interval values ​​of a consecutive preset number of frames within the current calibration period and the corresponding preset sampling period of the sensor. The larger the value, the higher the probability of sudden timing jumps in the original timestamp. The normal characteristic range of the original timestamp is set based on the maximum allowable synchronization error requirement of the system, the timing characteristics of the sensor output, and the electromagnetic interference level in the industrial environment. Under the premise of ensuring that normal random noise is not misjudged as abnormal, it can effectively identify timing jitter and jumps that cause degradation of synchronization accuracy. For example, the normal characteristic range of the original timestamp is: the standard deviation of the original timestamp interval ≤ 5% of the preset sampling period of the corresponding sensor, and the maximum jump of the original timestamp interval ≤ 20% of the preset sampling period of the corresponding sensor.

[0179] Step S542: The static deviation discrimination logic built into the programmable logic device retrieves the reference parameters of the hardware link delay compensation table and individual delay compensation table corresponding to the single channel with timing synchronization abnormality, and calculates the static correction deviation characteristics; compares the static correction deviation characteristics with the preset static correction normal deviation range, and if it exceeds the static correction normal deviation range, it is determined that the perceived real timestamp is abnormal.

[0180] The static correction deviation characteristics include average hardware link correction deviation and average individual response correction deviation. The average hardware link correction deviation is a statistical measure characterizing the overall accuracy of the single-channel hardware link delay correction stage, obtained by calculating the average absolute difference between the hardware link correction timestamps of a consecutive preset number of frames within the current calibration period and the theoretical hardware link correction timestamps. A larger value indicates worse accuracy in the hardware link delay correction stage. The average individual response correction deviation is a statistical measure characterizing the overall accuracy of the single-channel sensor individual response delay correction stage, obtained by calculating the average absolute difference between the perceived real timestamps of a consecutive preset number of frames within the current calibration period and the theoretical perceived real timestamps. A larger value indicates worse accuracy in the sensor individual response delay correction stage. The theoretical hardware link correction timestamp is equal to the difference between the original timestamp and the factory-calibrated hardware link delay reference value under standard operating conditions of 25℃ / 5.0V. The theoretical perceived real timestamp is equal to the difference between the theoretical hardware link correction timestamp and the factory-calibrated individual response delay reference value under standard operating conditions of 25℃ / 5.0V.

[0181] The static correction normal deviation range is set based on the system's maximum permissible synchronization error requirement, the measurement accuracy of the programmable logic device's built-in measurement logic, and the normal drift range of device aging. This effectively distinguishes between normal measurement errors and abnormal parameter drift or logic errors. For example, the static correction normal deviation range is: average hardware link correction deviation < 50 ps and average individual response correction deviation < 50 ps.

[0182] Step S543: The dynamic compensation discrimination logic built into the programmable logic device retrieves the dynamic delay compensation value under operating conditions within the current calibration cycle and the actual delay drift obtained from the most recent periodic calibration, and calculates the dynamic compensation deviation rate characteristic; the dynamic compensation deviation rate characteristic is compared with the preset normal deviation rate range for dynamic compensation. If it exceeds the normal deviation rate range for dynamic compensation, it is determined that the dynamic delay compensation under operating conditions is abnormal. The actual delay drift is the difference between the delay parameter measured in the current periodic calibration and the delay parameter measured in the previous calibration, used to characterize the actual change in hardware link delay and sensor individual response delay within the interval between two calibration cycles.

[0183] The dynamic compensation deviation rate features include the hardware link compensation deviation rate and the individual response compensation deviation rate. The hardware link compensation deviation rate is a relative quantity characterizing the accuracy of the dynamic compensation stage in compensating for hardware link delay drift. It is obtained by calculating the percentage of the absolute difference between the actual hardware link delay drift and the theoretical hardware link delay compensation value relative to the actual hardware link delay drift. The smaller the value, the higher the degree of matching between the dynamic compensation value and the actual drift. The individual response compensation deviation rate is a relative quantity characterizing the accuracy of the dynamic compensation stage in compensating for sensor individual response delay drift. It is obtained by calculating the percentage of the absolute difference between the individual sensor response delay drift and the theoretical individual response delay compensation value relative to the actual individual response delay drift. The smaller the value, the higher the degree of matching between the dynamic compensation value and the actual drift. The theoretical hardware link delay compensation value refers to the theoretical hardware link delay drift generated in step S4 based on the current operating parameters and used to update the hardware link delay compensation table. It is equal to the current reference compensation value of the channel × (hardware link target correction coefficient - 1). The hardware link target correction coefficient is calculated by calling a pre-calibrated delay correction coefficient matrix, combined with the interval of the current operating parameters and bilinear interpolation. The theoretical individual response delay compensation value refers to the theoretical individual response delay drift generated in step S4 based on the current operating parameters and used to update the individual delay compensation table. It is equal to the current reference compensation value of the sensor × (individual response target correction coefficient - 1). The individual response target correction coefficient is calculated by calling a pre-calibrated delay correction coefficient matrix, combined with the interval of the current operating parameters and bilinear interpolation.

[0184] The dynamic compensation normal deviation rate range is set based on the full-condition calibration accuracy, the system's allowable compensation error, and the accuracy of operating parameter acquisition. This effectively distinguishes between normal calibration errors and abnormal coefficient mismatches or calculation errors. For example, the dynamic compensation normal deviation rate range is: hardware link compensation deviation rate < 30% and individual response compensation deviation rate < 30%.

[0185] Specifically, step S5 is the closed-loop calibration and health monitoring stage of the entire timing synchronization system. Its core design addresses the key issues in existing technologies, such as the lack of independent true-value benchmark calibration, weak anomaly identification capabilities, and inability to pinpoint specific faulty components. This provides the system with long-term stable timing accuracy assurance and maintainability support. Industrial environments are complex and variable; factors such as crystal oscillator aging, electromagnetic interference, and hardware parameter drift can all lead to a gradual deterioration of timing synchronization accuracy. If anomalies cannot be detected and located in a timely manner, the accuracy of multi-sensor fusion will decrease, ultimately causing control errors. Step S5 quantifies the overall deviation characteristics of the global timing system by using the external absolute time synchronization signal as an independent reference through steps S51-S52; Step S53 establishes a dual anomaly judgment benchmark to accurately distinguish between global clock anomalies and single-channel local anomalies; Step S54 follows the physical process of timestamp generation to trace the source layer by layer, accurately locating the anomaly types of the three core links: original timestamp marking, static delay correction, and dynamic operating condition compensation. Without step S5, the system will not be able to detect the degradation of timing synchronization accuracy in a timely manner, and will not be able to locate the specific fault link, resulting in a significant reduction in equipment operating reliability and increased fault diagnosis and maintenance costs.

[0186] Example 2:

[0187] This embodiment introduces a multi-sensor timestamp synchronization system based on programmable logic. Built using programmable logic devices, it includes a dynamic configuration module, a delay calibration module, a preprocessing module, a compensation and correction module, and an anomaly detection module.

[0188] Dynamic Configuration Module: This module is responsible for receiving synchronization requirement parameter packets transmitted by the upper-level control unit through the industrial communication interface, performing parameter packet validity verification and core synchronization requirement parameter extraction, accurately calculating the deployment quantity and corresponding configuration parameters of various reconfigurable logic circuits based on the preset logical resource mapping relationship, automatically splicing configuration bitstreams by calling the pre-verified reconfigurable logic circuit library in non-volatile memory, performing dual security verification of integrity and identity authentication on the generated configuration bitstream, and loading the verified configuration bitstreams into the programmable logic devices through full loading mode or incremental loading mode, combined with the operating status of the programmable logic devices. At the same time, it completes status monitoring, error alarm and retry processing during the loading process, realizing the automatic generation and deployment of dedicated hardware logic adapted to real-time multi-sensor fusion control scenarios, solving the problem that fixed logic architecture cannot adapt to diverse sensor combinations and dynamic synchronization requirements.

[0189] Delay calibration module: This module is responsible for building a dual-mode redundant global clock tree inside the programmable logic device (PLD). It monitors the clock operating parameters such as frequency, jitter, and phase difference of the two independent global clock generation paths in real time through the built-in clock monitoring logic of the PLD. It achieves seamless switching between the primary and backup clocks and reports fault information based on preset fault judgment criteria. It drives the global timestamp counting circuit to operate based on the normally operating global clock signal to establish a unified global time reference. At the same time, during the device power-on initialization phase and preset periodic calibration nodes, it uses the high-precision measurement circuit and standard signal source built into the PLD to quantize and measure the transmission delay of the sensor hardware link and the physical response delay of individual sensors channel by channel. It generates and stores a structured hardware link delay compensation table and an individual delay compensation table. It also completes the drift judgment and dynamic hot update of delay parameters within the device idle timing window, eliminating the basic timing errors caused by inherent hardware differences, device aging, and environmental disturbances.

[0190] Preprocessing Module: This module is responsible for configuring three data acquisition trigger modes—synchronous trigger mode, asynchronous sampling mode, and interrupt trigger mode—differentiatedly based on the output characteristics and synchronization requirements of each sensor. It completes the acquisition of sensor data from each channel and binds the original timestamps based on a global time reference. It sequentially retrieves the hardware link delay compensation table and the individual delay compensation table, performing a two-layer reverse correction on the original timestamps to calculate the actual perceived timestamps of changes in the physical quantities sensed by the sensors. Combining the system control cycle, it determines a unified data output frequency and performs upsampling, downsampling, or time-axis fitting interpolation processing on heterogeneous sensor data with different sampling frequencies to normalize the multi-sensor data acquisition frequency. Finally, it encapsulates the standardized sensor data and the aligned interpolated synchronization timestamps into a unified data frame and caches it, completing the timing alignment and preprocessing of multi-source heterogeneous sensor data.

[0191] Compensation and Correction Module: This module is responsible for real-time acquisition of core operating parameters such as ambient temperature and power supply voltage in the industrial environment. It calculates the real-time fluctuation of operating parameters and combines them with preset allowable thresholds for operating condition fluctuations to accurately determine whether changes in operating conditions cause substantial drift in sensor hardware link delay and individual response delay. When substantial drift in delay is determined, it calls the delay correction coefficient matrix calibrated by the device at the factory, uses bilinear interpolation to match the correction coefficient corresponding to the current operating condition, and performs hierarchical calculation of dynamic delay compensation values ​​for hardware link delay and individual sensor response delay. Within the idle time window without interrupting the device's real-time operations, it hot-updates the hardware link delay compensation table and the individual delay compensation table in the background, realizing the adaptive adaptation of the time delay compensation parameters to the dynamic changes in industrial operating conditions and suppressing the degradation of synchronization accuracy caused by operating condition fluctuations.

[0192] Anomaly Identification Module: This module is responsible for receiving external absolute time synchronization signals such as GPS second pulses, Beidou second pulses, and Industrial Ethernet PTP Precision Time Protocol according to a preset calibration cycle. It constructs a global time calibration benchmark pair and calculates the global timing deviation and drift sequence. Through dual judgment rules of single drift anomaly threshold and sequence fluctuation anomaly threshold, it distinguishes between global clock anomalies and sensor single-channel local timing anomalies. For global clock anomalies, it performs fault-tolerant processing such as master / backup clock switching, fault reporting, and enhanced monitoring. For single-channel local timing anomalies, it traces the source layer by layer to detect three types of faults: original timestamp marking anomaly, perceived real timestamp anomaly, and dynamic delay compensation anomaly under operating conditions. It accurately locates the abnormal link in the timing synchronization link, generates structured fault logs and anomaly reporting information, and realizes closed-loop calibration of system timing accuracy and full-link health status monitoring.

[0193] Working principle and its effects:

[0194] This invention leverages the dynamic and reconfigurable hardware characteristics of programmable logic devices to build a comprehensive timing synchronization system that integrates dynamic logic configuration, redundant clock reference construction, hierarchical delay calibration, adaptive compensation for operating conditions, and closed-loop monitoring of timing anomalies. Through a full-link, hierarchical timing control and fault-tolerant mechanism, it systematically solves the industry pain points of poor adaptability, easy accuracy drift, weak reliability, and inability to locate faults in the timing alignment process of multiple heterogeneous sensors, providing a stable and accurate timing foundation for industrial multi-sensor fusion control.

[0195] This invention first automatically calculates and generates a reconfigurable logic circuit bitstream based on actual on-site synchronization requirements and completes its loading and deployment. This enables on-demand customization of synchronization hardware logic, flexibly adapting to different sensor quantities, types, and synchronization accuracy requirements, significantly improving the versatility of the solution. By constructing a dual-mode redundant global clock tree and monitoring the clock's operating status in real time, seamless switching can be completed when the master clock malfunctions, eliminating single-point clock failures and ensuring a continuous and stable output of the global time reference. Utilizing a combination of full-scale power-on calibration and periodic incremental calibration, it accurately measures and iteratively updates hardware link delay and sensor individual response delay compensation parameters, effectively eliminating inherent timing errors caused by hardware routing differences and sensor individual process discreteness. Furthermore, it differentiates the sensor acquisition trigger modes through configuration. By combining a dual-layer delay correction algorithm to obtain the perceived real timestamp of the sensor data and completing the multi-sensor acquisition frequency normalization processing, accurate timing alignment of heterogeneous sensor data is achieved. At the same time, on-site operating parameters such as temperature and voltage are collected in real time, and delay compensation values ​​are dynamically generated through threshold judgment and matrix interpolation algorithms. The compensation parameters are corrected in real time to effectively offset the timing drift caused by operating condition fluctuations and device aging, ensuring long-term stability of synchronization accuracy. Finally, the global timing is periodically calibrated by an external absolute time synchronization signal. A dual threshold judgment mechanism distinguishes between global clock failures and single-channel local anomalies, and the specific anomaly types in the timestamp marking, static correction, and dynamic compensation links are traced layer by layer to locate the specific anomaly types in the links, achieving accurate identification and fault-tolerant handling of timing faults, and comprehensively improving the stability and maintainability of the system's timing synchronization.

[0196] In summary, this invention achieves dynamic adaptation, high-precision compensation, stable operation under all working conditions, and full-link health monitoring for multi-sensor timing synchronization. It significantly improves the timing consistency of multi-sensor data fusion and the reliability of system operation in complex industrial scenarios, and can effectively meet the long-term stable operation requirements of high-precision real-time control scenarios such as industrial automation and intelligent robots.

[0197] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A multi-sensor timestamp synchronization method based on programmable logic, characterized in that, include: Receive synchronization requirement parameters, calculate the number and configuration parameters of reconfigurable logic circuits, generate a configuration bit stream, and load it into the programmable logic device; A dual-mode redundant global clock tree is constructed inside the programmable logic device to provide a global time base; It also measures the hardware link delay of each sensor interface and the physical response delay of each sensor, and generates a hardware link delay compensation table and an individual delay compensation table. Match the acquisition trigger mode for each sensor according to the synchronization requirement parameters and complete the sensor data acquisition. Based on the global time base, hardware link delay compensation table and individual delay compensation table, the sensing data collected by each sensor is corrected for the real timestamp of perception, and the multi-sensor acquisition frequency normalization processing is completed. Collect operating condition parameters, and when changes in operating conditions cause substantial delay drift, generate dynamic delay compensation values ​​for operating conditions, and correct the hardware link delay compensation table and individual delay compensation table. The global time base is calibrated by an external absolute time synchronization signal, the drift is counted, the existence of timing synchronization anomalies is determined, and the anomaly type of the programmable logic device is identified.

2. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The process of receiving synchronization requirement parameters, calculating the number and configuration parameters of reconfigurable logic circuits, generating a configuration bit stream, and loading it into the programmable logic device includes: The upper-level control unit sends a synchronization requirement parameter packet to the processing unit through an industrial communication interface. After the processing unit verifies the validity of the synchronization requirement parameter packet, it extracts the synchronization requirement parameters. The processing unit calculates the number and configuration parameters of various reconfigurable logic circuits based on the preset logical resource mapping relationship; The processing unit calls the reconfigurable logic circuit library and, based on the calculated number and configuration parameters of various reconfigurable logic circuits, splices together to generate a configuration bit stream. The processing unit performs a security check on the generated configuration bitstream. Once the security check is passed, the configuration bitstream is loaded into the programmable logic device in either full load mode or incremental load mode.

3. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The step of constructing a dual-mode redundant global clock tree within the programmable logic device to provide a global time reference includes: A dual-mode redundant global clock tree containing two independent clock generation paths is built inside the programmable logic device; The operating status of the two clock generation paths is monitored in real time by a programmable logic device, and a global clock signal is output. The global timestamp counting logic inside the programmable logic device is continuously driven by a global clock signal to construct a global time base composed of a clock source and continuous global timestamp count values.

4. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 3, characterized in that, The step of monitoring the operating status of the two clock generation paths in real time through a programmable logic device and outputting a global clock signal includes: The two clock generation paths of the dual-mode redundant global clock tree output the main global clock signal and the backup global clock signal respectively. Configure the clock monitoring operation parameters of the programmable logic device and establish clock fault judgment criteria. The clock monitoring operation parameters include monitoring frequency, frequency measurement window, jitter measurement cycle number, phase difference measurement cycle and preset normal threshold. The programmable logic device monitors operating parameters according to a preset clock and collects clock operating parameters of the two clock generation paths in real time. The clock operating parameters include frequency, jitter, and phase difference parameters. The operating status of the main global clock signal is determined based on the collected clock operating parameters. If the main global clock signal fails, the backup global clock signal switching operation is triggered, and the global clock signal is output.

5. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The steps for generating the hardware link delay compensation table and the individual delay compensation table include: The calibration operation is triggered at the initial startup time of the programmable logic device and at the arrival time of the preset measurement cycle; When the programmable logic device is initially started, based on the built-in measurement function and standard signal source, and based on the global time reference, it completes the full measurement of the hardware link delay of all sensor channels and the physical response delay of individual sensors, and generates and initializes the hardware link delay compensation table and the individual delay compensation table. When the preset measurement period arrives, the programmable logic device performs incremental delay measurement within the service idle time window, and completes the dynamic update of the hardware link delay compensation table and the individual delay compensation table through parameter drift determination.

6. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The steps of correcting the sensing data collected by each sensor for the actual sensing timestamp and completing the multi-sensor acquisition frequency normalization process include: Based on the synchronization requirement parameters, a matching acquisition trigger mode is configured for each sensor, and a timestamp marker resource in the reconfigurable logic circuit is independently allocated to each sensor interface. Relying on the global clock signal to drive the timestamp marker resources, and combined with the corresponding acquisition trigger mode, the data of each sensor channel is acquired and bound to the original timestamp; Retrieve the hardware link delay compensation table, match the corresponding hardware link delay compensation value for each channel, and perform reverse compensation correction on the original timestamp to obtain the hardware link corrected timestamp. Retrieve the individual delay compensation table, match the individual delay compensation value of the corresponding sensor, and perform a second correction on the hardware link correction timestamp to obtain the true perception timestamp of the sensor data. The sampling frequencies of each sensor are obtained and standardized to a preset standard output frequency. Interpolation synchronization timestamps are then bound to the standardized sensor data.

7. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The steps of collecting operating condition parameters, generating dynamic delay compensation values ​​in response to substantial delay drift caused by changes in operating conditions, and correcting the hardware link delay compensation table and individual delay compensation table include: The programmable logic device collects operating parameters in real time and determines whether changes in operating conditions cause substantial delay drift based on a preset threshold for allowable fluctuations in operating conditions. If substantial delay drift is determined, a dynamic delay compensation value for operating conditions is generated, which includes the amount of hardware link delay drift and the amount of individual response delay drift. Based on the generated dynamic delay compensation values ​​for operating conditions, the parameters of the hardware link delay compensation table and the individual delay compensation table are updated and corrected in layers.

8. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 7, characterized in that, The steps for generating the dynamic delay compensation value under the specified operating condition include: The programmable logic device continuously collects on-site operating condition parameters and updates the benchmark values ​​of the operating condition parameters in real time. The operating condition parameters include ambient temperature and power supply voltage. Calculate the difference between the current operating condition parameter baseline value and the previous compensation effective operating condition parameter baseline value to obtain the ambient temperature fluctuation and power supply voltage fluctuation. Combine this with the preset operating condition fluctuation allowable threshold to determine whether a substantial delay drift has occurred. If a substantial delay drift is determined, a preset delay correction coefficient matrix is ​​invoked to match the correction coefficient range corresponding to the current operating condition parameters. The target correction coefficient is obtained through interpolation, and the dynamic delay compensation value for the operating condition is generated based on the target correction coefficient.

9. The multi-sensor timestamp synchronization method based on programmable logic as described in claim 1, characterized in that, The steps of calibrating the global time reference using an external absolute time synchronization signal, calculating the drift, determining whether there is a timing synchronization anomaly, and identifying the anomaly type of the programmable logic device include: Receive external absolute time synchronization signals according to the preset calibration cycle, latch the real-time value of global timestamp count, and establish a global time calibration reference pair; Based on the global time calibration reference pair, calculate the global time deviation for this calibration cycle, and combine the calibration cycle to calculate the single global calibration drift, and construct a global drift sequence; Statistical analysis of the global drift sequence is performed, and the existence of global time-series synchronization anomalies is determined by combining the single drift anomaly threshold and the sequence fluctuation anomaly threshold as dual judgment criteria. If the global clock is determined to be abnormal, global clock fault tolerance processing is performed; otherwise, the sensor acquisition channel with local timing abnormalities enters the single-channel local abnormality identification process to identify single-channel abnormalities, including abnormalities in the original timestamp marking, abnormalities in the perceived real timestamp, and abnormalities in the dynamic delay compensation of the operating condition.

10. A multi-sensor timestamp synchronization system based on programmable logic, used to implement the multi-sensor timestamp synchronization method based on programmable logic as described in any one of claims 1-9, characterized in that, include: Dynamic configuration module: used to receive synchronization requirement parameters, calculate the number of reconfigurable logic circuits and configuration parameters, generate configuration bit stream, and load it into programmable logic device; Delay calibration module: used to build a dual-mode redundant global clock tree inside the programmable logic device to provide a global time reference; It also measures the hardware link delay of each sensor interface and the physical response delay of each sensor, and generates a hardware link delay compensation table and an individual delay compensation table. Preprocessing module: used to match the acquisition trigger mode for each sensor according to the synchronization requirement parameters and complete the sensor data acquisition; Based on the global time base, hardware link delay compensation table and individual delay compensation table, the sensing data collected by each sensor is corrected for the real timestamp of perception, and the multi-sensor acquisition frequency normalization processing is completed. Compensation and Correction Module: Used to collect operating condition parameters, and in response to substantial delay drift caused by changes in operating conditions, generate dynamic delay compensation values ​​for operating conditions, and correct the hardware link delay compensation table and individual delay compensation table. Anomaly identification module: used to calibrate the global time base through an external absolute time synchronization signal, count the drift, determine whether there is a timing synchronization anomaly, and identify the anomaly type of the programmable logic device.

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