A quadtree subchannel decomposition system and method thereof

Abstract

This invention relates to the field of digital signal processing technology, and discloses a four-way tree-structured subchannel decomposition system and method. The system includes a signal sampling module, a four-way overlapping filter cascade module, a resolution adaptive gating module, and a multi-channel parallel energy decision demodulation module. The four-way overlapping filter cascade module adopts an asymmetric four-channel parallel architecture with one direct pass-through and three mixing channels. The three mixing channels respectively employ F... s / 4、2F s / 4、3F s The / 4 local oscillator achieves equivalent mixing through simple operations such as sign inversion and I / Q data exchange, and inverted I / Q data exchange, without requiring multiplication operations; the coefficients of each filter stage can be integer powers of 2, and filtering is achieved through shift addition; controllable overlap is used to eliminate spectral holes; and it supports hierarchical differentiated parameter configuration and multi-resolution parallel output. This invention replaces the traditional high-radix FFT, significantly reducing hardware overhead and power consumption, with no blocking delay, and is suitable for broadband communication, IoT baseband, and high-precision spectrum sensing chips.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and in particular to a four-part tree-shaped subchannel decomposition system and method. Background Technology

[0002] Spectrum analysis is one of the core technologies in the field of digital signal processing, widely used in various production and daily life scenarios such as wireless communication, radar detection, electronic warfare, radio astronomy, biomedical signal processing, industrial automation monitoring, and IoT communication. In wireless communication, with the rapid development of 5G and next-generation broadband communication technologies, base stations and terminal equipment need to perform real-time spectrum analysis on broadband signals ranging from 100MHz to hundreds of MHz to complete key baseband processing tasks such as multi-carrier demodulation, channel estimation, interference detection, and frequency synchronization. In radar detection, high-resolution spectrum analysis directly determines the accuracy of target range and velocity resolution, and is a core supporting technology for achieving high-precision detection in synthetic aperture radar (SAR), phased array radar, and cognitive radar. In the Internet of Things (IoT) field, low-power wide-area network (LPWAN) technologies such as LoRa and NB-IoT need to complete the reception and demodulation of multi-rate, multi-standard signals under extremely low power constraints; the hardware overhead of the spectrum analysis module directly determines the standby time and deployment cost of terminal equipment. Furthermore, in radio astronomy observation, high dynamic range and high resolution spectrum analysis is required for extremely weak celestial radiation signals to achieve spectral line identification; in industrial equipment fault diagnosis, vibration spectrum analysis is used to achieve abnormal detection and predictive maintenance of rotating machinery; and in cognitive radio and spectrum monitoring, real-time perception of the spectrum occupancy status across the entire frequency band is required to achieve dynamic spectrum access and management.

[0003] In the above typical application scenarios, spectrum analysis systems all face common underlying technical requirements: low latency (to meet the latency constraints of real-time signal processing), high resolution (to achieve effective differentiation of adjacent signals and effective detection of weak signals), low power consumption (to adapt to the power supply constraints of mobile terminals and IoT nodes), and multi-resolution parallel processing capability (to adapt to complex electromagnetic environments where multiple rates and multiple standards of mixed signals coexist).

[0004] Currently, the mainstream technology for high-speed, high-precision spectrum analysis is the high-radix Fast Fourier Transform (FFT). This technology reduces the butterfly operation levels by increasing the iteration radix (e.g., radix-4, radix-8, or even higher), thereby improving the computational efficiency of large-point spectrum transformations. However, the high-radix FFT still faces several technical challenges, making it difficult to meet the stringent requirements of modern baseband processing for low latency, low power consumption, and high concurrency. Specifically, the technical problems faced by the high-radix FFT are as follows:

[0005] Technical problem one: High-radix FFT has a fixed blocking delay, which cannot meet the real-time processing requirements of pipelines; FFT is a block orthogonal transformation, which requires the complete caching of the entire frame of time-domain data before the operation can start. When the data frame length is large (such as 4096 points and above), the caching delay and the operation delay are superimposed to form a fixed and non-reducible processing delay, which seriously restricts low-latency communication and real-time spectrum monitoring scenarios; at the same time, FFT relies on a large number of complex butterfly operations, rotation factor multiplication and iterative accumulation logic, which requires a large number of multipliers, caches and storage units, resulting in large hardware area and power consumption, making it difficult to be used in lightweight low-power chip design scenarios;

[0006] The second technical issue is the significant spectral leakage problem in high-radius FFT. FFT is equivalent to N-channel parallel mixing and filtering operations, with its filtering being equivalent to first-order CIC filtering. Its first sidelobe only attenuates by 13dB, making it highly sensitive to frequency synchronization. FFT is affected by the time-domain window truncation effect; the truncation error manifests as sidelobe leakage in the spectrum. High-radius iterations further amplify this truncation error, resulting in weak out-of-band suppression and weak signals being easily submerged in the sidelobes, severely reducing the demodulation accuracy and stability of multi-signal parallel reception. Although windowing can be used to suppress spectral leakage, windowing operations increase computational overhead and cannot fundamentally eliminate the source of leakage.

[0007] The third technical problem is that the high-base FFT has a fixed resolution and cannot work in parallel with multiple resolutions. A single FFT operation can only output a spectrum result with a single resolution. When faced with scenarios where multiple rates and multiple standards of mixed signals coexist, the parameters can only be switched in a time-division manner, resulting in switching blind spots and timing conflicts. The system has poor concurrency capabilities and cannot meet the needs of cognitive radio and multi-mode communication for multi-resolution parallel spectrum sensing.

[0008] The fourth technical problem is that existing tree-based filtering architectures are inefficient and suffer from spectral holes. While step-by-step frequency division architectures, such as binary trees, can achieve progressive spectral decomposition, the 2x step-by-step frequency division results in a large number of levels, large cumulative delay and cumulative error, and low efficiency in improving high-frequency resolution. Conventional four-way frequency division filtering architectures use fixed parameters and non-overlapping bandwidth designs, resulting in spectral holes and signal energy loss at the frequency division boundaries. Furthermore, the parameters are not adjustable, making it impossible to balance spectral accuracy and hardware power consumption, which severely restricts their application value in practical systems.

[0009] Therefore, those skilled in the art urgently need a low-level spectrum decomposition technology that is highly efficient in iteration, free of spectral holes, free of blocking delays, has flexible and configurable parameters, and supports multi-resolution parallel processing. Summary of the Invention

[0010] The core technical problem solved by this invention is: how to construct a brand-new underlying spectrum processing architecture that can completely replace the traditional high-radix FFT, fundamentally eliminating the inherent technical bottlenecks of FFT such as block transform blocking delay, spectrum leakage, large hardware overhead and resolution fixation, while overcoming the defects of existing tree filtering architecture such as hierarchical redundancy, spectrum holes and parameter fixation, and realizing high-efficiency, lossless, low-power, multi-resolution parallel general spectrum decomposition.

[0011] The aforementioned core technical problems have not been effectively solved by those skilled in the art for a long time, and the reason is as follows:

[0012] First, since the Cooley-Tukey algorithm was proposed in 1965, FFT has developed into a highly mature theoretical system and engineering implementation scheme after decades of development. For a long time, those in the field have been limited by the technical prejudice that "spectral analysis must rely on FFT" and have failed to break through the mindset of Fourier transform at the architectural level.

[0013] Second, although the tree-shaped filtering architecture conceives the basic idea of ​​multi-resolution analysis, the excessive number of binary tree levels leads to unacceptable delay accumulation, while the conventional four-way frequency division architecture cannot achieve continuous coverage of the entire frequency band due to the problem of spectral holes. Those skilled in the art lack technical inspiration to organically combine tree-shaped frequency division with a controllable overlap mechanism.

[0014] Third, in traditional understanding, mixing operations inevitably involve complex multiplication and trigonometric function operations. Those skilled in the art have not realized that under certain frequency division ratios (1 / 4 sampling frequency and its integer multiples), multiplication and addition operations can be completely replaced by inversion and commutation logic, thus failing to reconstruct the spectrum decomposition architecture from the perspective of minimal hardware.

[0015] For those skilled in the art, solving the aforementioned core technical problems is of paramount importance:

[0016] First, from a theoretical perspective, the successful implementation of this invention means that spectrum analysis can completely break free from its theoretical dependence on Fourier transform, establish a new spectrum decomposition theory system based on multi-level integer frequency division tree filtering, provide an original underlying technical path for the field of digital signal processing, and fill the theoretical gap in non-FFT-type high-precision spectrum analysis architecture.

[0017] Secondly, from an engineering perspective, breaking through the hardware overhead bottleneck of FFT means that, with the same spectrum analysis accuracy, the chip area can be reduced by more than 65% and the dynamic power consumption can be reduced by more than 60% (40nm CMOS process). This will directly drive the performance leap of ultra-low power IoT chips, wearable devices and space electronic devices, and enable high-precision spectrum analysis capabilities to be deployed in terminal devices that were previously unable to be deployed due to power consumption constraints.

[0018] Furthermore, from a system perspective, pipelined point-to-point processing eliminates congestion delays, reducing the end-to-end latency of the signal processing link to nanosecond-level pipeline cycles, providing key technical support for ultra-low latency communication, real-time spectrum sensing, and agile electronic countermeasures systems; multi-resolution parallel processing capabilities enable the system to output multi-level spectrum results at the same time, providing an architecture-level solution for cognitive radio dynamic spectrum access and multi-mode communication baseband integrated processing.

[0019] Finally, from an industry perspective, the general architecture of this invention can be seamlessly extended to cascaded architectures of eight-part, sixteen-part, and arbitrary integer N-part tree structures and hybrid tree structures, forming a complete and independently controllable spectrum processing technology system. This is of great strategic significance for breaking free from path dependence on foreign FFT core algorithms and building an independent intellectual property baseband chip technology stack.

[0020] To address the aforementioned core technical challenges, this invention designs a four-part tree-structured subchannel decomposition system and method. Its purpose is to minimize the number of levels by using an integer division ratio of 4 or higher through iterative steps based on a tree-structured cascaded filtering architecture. Controllable overlap design eliminates spectral holes to ensure continuous coverage across the entire frequency band. Leveraging the key mathematical characteristic that mixing operations at a specific division ratio can degenerate to extremely simple logical operations, a multiplication-free, pure hardware implementation is achieved. Furthermore, differentiated configuration of hierarchical parameters balances high-frequency anti-interference with low-frequency low-power requirements. Ultimately, this constructs a pipelined, non-blocking, multi-resolution parallel output general-purpose spectrum decomposition system and method, fundamentally replacing traditional high-radix FFT and breaking through the performance ceiling of existing spectrum analysis techniques.

[0021] To achieve the above objectives, the specific technical solution of the present invention is a four-part tree-shaped subchannel decomposition system, comprising:

[0022] The signal sampling module is used to continuously sample the input analog signal at a preset sampling frequency and output a digital time-domain data stream.

[0023] A four-level overlapping filter (which can also be replaced by ordinary filtering + in-band roll-off compensation in some scenarios) cascaded module, the input of which is connected to the output of the signal sampling module, the four-level overlapping filter cascaded module includes multiple levels of sequentially cascaded quadtree filter units, each of which is used to perform four-channel parallel spectrum filtering and four-decimation downsampling on the input signal, and the quadtree filter units at each level are cascaded to progressively improve the spectrum resolution;

[0024] A resolution adaptive gating module, the input of which is connected to the outputs of different levels of the four-level overlapping filter cascade module, is used to select the spectrum output of the corresponding level output according to the target signal bandwidth and resolution requirements.

[0025] A multi-channel parallel energy decision demodulation module is provided, the input of which is connected to the output of the resolution adaptive gating module. The multi-channel parallel energy decision demodulation module is used to perform parallel energy detection, frequency point identification and signal demodulation on each sub-channel of the gating level output.

[0026] Each of the four-way tree filtering units adopts an asymmetric four-channel parallel architecture with one direct-through channel and three mixing channels. The direct-through channel directly filters and downsamples the input signal by decimation (4 / 10). The three mixing channels each use a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4 After performing equivalent complex downmixing on the input signal, filtering and decimation-4 downsampling are applied. F s The sampling frequency of the current input signal to the quadtree filter unit;

[0027] It should be noted that "four-in-one downsampling" means reducing the sampling rate of the signal to one-quarter of its original value; specifically, in every four consecutive input sample data, only one sample is retained, and the other three samples are discarded.

[0028] In the quadtree subchannel decomposition system described in this application, this operation is not only a simple data compression, but also a key step in improving spectral resolution. After downsampling, the bandwidth of the signal is synchronously reduced to 1 / 4 of the original, which makes the frequency resolution (i.e. the smallest frequency interval that can be distinguished) increase by 4 times accordingly.

[0029] The equivalent complex downmixing of the three mixing channels is achieved through sign inversion logic and data sequence exchange logic, without multiplication operations.

[0030] Preferably, the four-level overlapping filter cascade module includes six sequentially cascaded quadtree filter units, with a normalized sampling frequency of:

[0031] The filter order of the first-level quadtree filter unit and the filter order of the second-level quadtree filter unit can generally be higher, such as 64th order for both. The specific order can be adjusted according to the actual needs of the scenario.

[0032] The filter orders of the third-level and fourth-level quartic tree filtering units are generally lower than those of the first two levels. In other words, the filter orders of both the third-level and fourth-level quartic tree filtering units must be less than the minimum of the filter orders of the first-level and second-level quartic tree filtering units. Specifically, the filter orders of both the third-level and fourth-level quartic tree filtering units cannot be greater than or equal to either the first-level or second-level quartic tree filtering units. For example, both the third-level and fourth-level quartic tree filtering units may have a filter order of 32. The specific order can be adjusted according to the actual needs of the scenario.

[0033] The filter orders of the fifth-level and sixth-level quartet filtering units are the lowest. That is, the filter orders of the fifth-level and sixth-level quartet filtering units are both lower than the filter orders of the third-level and fourth-level quartet filtering units. In other words, the filter orders of the fifth-level and sixth-level quartet filtering units cannot be greater than or equal to any one of the filter orders of the third-level and fourth-level quartet filtering units. For example, the filter orders of the fifth-level and sixth-level quartet filtering units are both 16th order. The specific order can be adjusted according to the actual needs of the scenario.

[0034] Preferably, in each of the four-way tree filtering units, the three mixing channels use a local oscillator frequency of F. s The equivalent complex undermixing of / 4 is achieved in the following way:

[0035] For the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3):

[0036] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0037] When r=1, I-channel output = Q-channel input, and Q-channel output = -I-channel input;

[0038] When r=2, I-way output = -I-way input, and Q-way output = -Q-way input;

[0039] When r=3, I-way output = -Q-way input, and Q-way output = I-way input;

[0040] Wherein, I-path represents the in-phase component and Q-path represents the quadrature component;

[0041] It is important to note that The equivalent complex downmixing only requires multiplying by a complex local oscillator. Therefore, the mathematical expression for the complex local oscillator decomposition is as follows:

[0042] ;

[0043] The formula for complex mixing is:

[0044] ;

[0045] In the formula, represents an imaginary number, For continuous sampling time, The time step during discrete sampling. To input the sample number, For I-channel input, For Q-path input;

[0046] The three mixing channels use a local oscillator frequency of 2F. s The equivalent complex downmixing of / 4 is achieved by the following expression:

[0047] For the input sample index n = 2k + r (k is a non-negative integer, r = 0, 1):

[0048] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0049] When r=1, I-way output = -I-way input, and Q-way output = -Q-way input;

[0050] The equivalent complex downmixing only requires multiplying by a complex local oscillator. Therefore, the mathematical expression for the complex local oscillator decomposition is as follows:

[0051] ;

[0052] The formula for complex mixing is:

[0053] ;

[0054] The three mixing channels use a local oscillator frequency of 3F. s The equivalent complex downmixing of / 4 is achieved by the following expression:

[0055] For the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3):

[0056] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0057] When r=1, I-way output = -Q-way input, and Q-way output = I-way input;

[0058] When r=2, I-way output = -I-way input, and Q-way output = -Q-way input;

[0059] When r=3, I-channel output = Q-channel input, and Q-channel output = -I-channel input;

[0060] For complex downmixing, simply multiply by a complex local oscillator. The decomposition of the complex local oscillator is as follows:

[0061] ;

[0062] The formula for complex mixing is:

[0063] .

[0064] This invention supports the configuration of filter parameters at each level using either identical or differentiated parameters, flexibly adapting to high-precision anti-interference or low-power lightweight scenarios. It also breaks through the traditional four-way divider's lack of overlapping bandwidth, employing a controllable small-amplitude overlap design to eliminate spectral holes at the divider boundaries, achieving lossless spectral decomposition across the entire frequency band. All filter coefficients are fixed using integer powers of 2, requiring only shift and addition operations throughout the process, constructing a low-leakage, low-power, and highly parallel general-purpose spectrum processing architecture. Only the 2-way and 4-way divider architectures can achieve purely logical, non-multiply-address, extremely simple mixing; higher-order N-way divider architectures represent a conventional extension of the principles of this invention.

[0065] Preferably, the filter coefficients of each channel in each level of the quadtree filtering unit are integer powers of 2. The filter completes the filtering process through shift and addition operations, without multipliers, rotation factor storage units, or trigonometric function operation units.

[0066] Preferably, the 3dB cutoff frequency of each channel of the four-way tree filter unit at each stage is extended outward relative to the nominal frequency division boundary to form a controllable spectrum overlap. The controllable spectrum overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel. The controllable spectrum overlap is used to eliminate spectral holes at the frequency division boundary and achieve continuous and gapless spectrum coverage across the entire frequency band.

[0067] Preferably, the four-level overlapping filter cascade module supports a unified parameter configuration mode across all levels and a progressively differentiated parameter configuration mode.

[0068] In the step-by-step differentiated parameter configuration mode, the high-frequency level adopts a high stopband suppression and low overlap configuration, the mid-frequency level adopts a compromise configuration, and the low-frequency level adopts a low-order filter and high overlap configuration.

[0069] Preferably, the four-level overlapping filter cascade module adopts a point-by-point pipelined processing architecture. The digital time-domain data stream output by the signal sampling module flows continuously into each level of the four-tree filtering unit, and each level of the four-tree filtering unit performs synchronous pipelined processing without the need to buffer the entire frame of data.

[0070] Preferably, the resolution adaptive gating module includes a hardware multiplexer, each input terminal of which is connected to the output terminals of different levels of the four-level overlapping filter cascade module. The control terminal of the hardware multiplexer receives the resolution gating control signal, and the output terminal of the hardware multiplexer outputs the spectrum data of each sub-channel of the gating level.

[0071] Preferably, the multi-channel parallel energy decision demodulation module includes multiple energy detection sub-modules that operate in parallel. Each energy detection sub-module corresponds to a sub-channel. Each energy detection sub-module independently completes the energy calculation, threshold decision and signal demodulation of the corresponding sub-channel. There is no need for global synchronization and phase locking between the sub-channels.

[0072] Preferably, it further includes a sub-channel shutdown control module, which is connected to the four-level overlapping filter cascade module. The sub-channel shutdown control module is used to determine invalid sub-channels based on the target signal bandwidth information and send shutdown control signals to the corresponding four-level tree filter units. The corresponding four-level tree filter units respond to the shutdown control signals and stop filtering and downsampling the invalid sub-channels.

[0073] This application also discloses a quadtree-based subchannel decomposition method, which is implemented based on the aforementioned system and includes the following steps:

[0074] Step A: The signal sampling module continuously samples the input analog signal at a preset sampling frequency and outputs a digital time-domain data stream;

[0075] Step B: The digital time-domain data stream is input into a multi-level sequentially cascaded quadtree filter unit. Each level of the quadtree filter unit performs four-channel parallel spectrum filtering and four-to-one downsampling processing on the input signal. The quadtree filter units at each level are cascaded to progressively improve the spectrum resolution.

[0076] Step C: The resolution adaptive gating module selects the corresponding level of spectrum output based on the target signal bandwidth and resolution requirements;

[0077] Step D: The multi-channel parallel energy decision demodulation module performs parallel energy detection, frequency point identification, and signal demodulation on each sub-channel output by the gating level;

[0078] The processing of each level of the quadtree filtering unit in step B includes:

[0079] Establish a direct path for the input signal and use the local oscillator frequency F respectively. s / 4、2F s / 4 and 3F s / 4 performs equivalent complex number down-mixing on three mixing channels, F s The sampling frequency of the input signal of the current stage;

[0080] The equivalent complex downmixing of the three mixing channels is achieved through sign inversion logic and data order exchange logic, without multiplication operations;

[0081] The direct-through channel signal and the three-channel mixing channel signal are filtered separately.

[0082] The filtered four-channel signals are downsampled by 1 / 4 sampling rate.

[0083] Preferably, in step B, the filtering coefficient of each level of the quartic tree filtering unit is an integer power of 2, and the filtering process is completed through shift operations and addition operations.

[0084] Preferably, in step B, the 3dB cutoff frequency of each channel of the four-way tree filter unit at each stage is extended outward relative to the nominal frequency division boundary to form a controllable spectrum overlap. The controllable spectrum overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel, which is used to eliminate spectral holes at the frequency division boundary and achieve continuous and gapless spectrum coverage across the entire frequency band.

[0085] Preferably, in step B, the multi-level sequentially cascaded quadtree filtering unit has six levels;

[0086] The filter order of the first-level quartic tree filter unit and the filter order of the second-level quartic tree filter unit are generally higher, such as 64th order.

[0087] The filter order of the third-level and fourth-level quadtree filtering units is generally lower than that of the first two levels, such as 32nd order.

[0088] The filter order of the fifth-level quadtree filter unit and the sixth-level quadtree filter unit are generally lower, such as 16th order.

[0089] Preferably, step B further includes:

[0090] Configure each level of the quadtree filtering unit as either a unified parameter mode across all levels or a progressively differentiated parameter mode.

[0091] In the aforementioned step-by-step differentiated parameter mode, the high-frequency level adopts a high stopband suppression and low overlap configuration, the mid-frequency level adopts a compromise configuration, and the low-frequency level adopts a low-order filter and high overlap configuration.

[0092] Preferably, in step B, the digital time-domain data stream flows continuously sample by sample into each level of the quadtree filtering unit, and each level of the quadtree filtering unit processes the data synchronously in a pipelined manner, without the need to buffer the entire frame of data, and there is no blocking delay between levels.

[0093] Preferably, step C includes:

[0094] In response to a broadband signal detection scenario, the resolution adaptive gating module selects the output of the preceding stage and outputs a low-resolution broadband spectrum.

[0095] In response to narrowband signal detection scenarios, the resolution adaptive gating module selects the output of the subsequent hierarchical level and outputs a high-resolution narrowband spectrum.

[0096] Each of the four-part tree filtering units at each level is stationary and outputs the spectrum results of its respective level in parallel. The gating operation is achieved by switching the output path using a multiplexer, without the need to reconfigure the hardware.

[0097] Preferably, in step D, each sub-channel independently performs energy detection, threshold decision and signal demodulation, and there is no need for global synchronization and phase locking between the sub-channels, which supports parallel blind reception of multi-rate and multi-standard mixed signals.

[0098] Preferably, the method further includes step E: the sub-channel shutdown control module determines the invalid sub-channel based on the target signal bandwidth information, sends a shutdown control signal to the corresponding quadtree filtering unit, and the corresponding quadtree filtering unit stops filtering and downsampling the invalid sub-channel in response to the shutdown control signal.

[0099] This application also discloses a quadtree-shaped subchannel decomposition device, the device configuring the system described above, comprising:

[0100] A sampling device, wherein the sampling device is used to continuously sample the input analog signal at a preset sampling frequency and output a digital time-domain data stream;

[0101] An N-stage cascaded quadtree filter, where N is an integer greater than or equal to 1, connects the input of the first-stage quadtree filter to the output of the sampling device. Each stage of the quadtree filter includes one direct-through filter branch and three mixing filter branches, with each of the three mixing filter branches using a local oscillator frequency of F. s / 4、2Fs / 4 and 3F s / 4 The input signal is subjected to equivalent complex downmixing. The equivalent complex downmixing is implemented by sign inversion logic and data order exchange logic. The output of each branch is filtered and then downsampled by decimation. The four-branch tree filtering devices at each stage are cascaded.

[0102] A gating output device is connected to the output terminal of each level of the quadtree filter device, and is used to select the corresponding level output according to the target signal resolution requirements;

[0103] A parallel demodulation device, which is connected to the output of the gating output device, is used to perform parallel energy decision and demodulation on each sub-channel of the gating level output;

[0104] The filter coefficients of each channel of the N-level sequentially cascaded quadtree filter device are integer powers of 2. Filtering is completed through shift and addition operations, without multiplication operations or rotation factor storage units.

[0105] Each channel of the four-way tree filter device at each stage extends outward from the nominal frequency division boundary to form a controllable spectrum overlap. The amount of controllable spectrum overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel, which is used to eliminate spectrum holes at the frequency division boundary.

[0106] Preferably, this application also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the steps of the method.

[0107] Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0108] First, this application realizes the mathematical discovery and engineering transformation of extremely simplified frequency mixing, and for the first time reveals that at a specific frequency division ratio (F... s / 4、2F s / 4、3F s Under the condition of / 4), the complex number under-mixing operation can be completely degraded to a very simple logical operation that only includes sign inversion and data order exchange (data order exchange mainly includes simple operations such as I / Q data exchange and inverted I / Q data exchange), without any multiplication or addition operations. Although this mathematical characteristic exists in traditional signal processing theory, those skilled in the art have long failed to recognize its engineering significance. In traditional understanding, mixing is necessarily accompanied by the overhead of complex multipliers. This invention organically integrates this mathematical degradation characteristic with the tree-shaped frequency division architecture, realizing a leap from mathematical characteristics to engineering architecture. This is a breakthrough direction that those skilled in the art have long found difficult to conceive of under the constraints of the FFT technology paradigm.

[0109] Second, this application uses a quadtree architecture instead of a binary tree architecture. When faced with the problem of too many levels in a binary tree, the most direct approach for those skilled in the art is to optimize the filtering efficiency of each level of the binary tree or to make local improvements based on the binary tree. However, this invention creatively chooses to skip the binary tree architecture and directly use a quadtree as the basic iterative unit, increasing the efficiency of single-level resolution improvement from 2 times to 4 times. This change in architecture may seem simple in form, but it actually involves a systematic reconstruction of multiple dimensions such as filter coefficient design, overlap strategy, and hardware architecture, which cannot be covered by the simple substitution thinking of "replacing two with four".

[0110] Third, this application adopts a reverse design approach to eliminate spectral holes using controllable overlap. Traditional filter bank design follows strict frequency division criteria, assuming that the frequency division boundaries must not overlap to ensure channel isolation. This invention reverses the above conventional design approach by actively introducing controllable spectral overlap (overlap amount controlled within 2%). Through the reverse thinking of "avoiding omissions by overlapping", it solves the fundamental problem of spectral holes that plagues the four-way divider architecture. The above reverse design approach has long been ignored or even rejected in this field. The successful implementation of this invention proves that controllable overlap is not only feasible in engineering practice but also has significant advantages.

[0111] Fourth, this application implements a hierarchical differentiated parameter configuration strategy. In traditional filtering architectures or FFT schemes, the parameters at each level are uniformly fixed. This invention proposes a "tight at the beginning and loose at the end" differentiated parameter configuration strategy—high-frequency level with high suppression and low overlap, and low-frequency level with low-order filtering and high overlap. This strategy links system-level power consumption optimization with hierarchical functional characteristics, reflecting the design idea of ​​optimizing the architecture from the overall system level rather than the level of a single module. This is something that those skilled in the art would find difficult to conceive of under the inertia of traditional unified parameter design.

[0112] Fifth, this application features an original asymmetric four-channel parallel architecture, employing an asymmetric parallel architecture with one through-channel and three mixing channels, which differs from the traditional design habit of using a symmetrical structure for all channels in filter banks. This asymmetric design fully utilizes the natural advantage of the through-channel not requiring mixing operations, minimizing hardware redundancy and embodying an advanced design concept of "functional differentiation driving architectural differentiation".

[0113] Compared with existing technologies, the present invention has the following beneficial effects: 1. The present invention achieves a significant improvement in iteration efficiency and a significant reduction in hierarchical overhead; the present invention adopts a 4x stepwise frequency division, and the cascading level is only 1 / 2 of that of a binary tree under the same spectral resolution; taking the equivalent realization of 65536-point ultra-high precision spectrum analysis as an example, a binary tree requires 16 cascading levels while the present invention only requires 8 cascading levels, effectively reducing accumulated delay, accumulated error and hardware overhead, and is suitable for high-speed ultra-high resolution spectrum analysis scenarios; at the same time, a single-level quartic tree can realize the parallel output of 4 sub-channels, and the total number of sub-channels increases by a power of 4 after multi-level cascading, and the spectrum decomposition efficiency is exponentially improved compared to the power of 2 increase of the binary tree;

[0114] 2. This invention eliminates spectral holes and energy loss through lossless and controllable overlapping spectral decomposition. Breaking through the strict non-overlapping design of traditional four-way frequency division, this invention pioneers a controllable spectral overlapping mechanism. By expanding the 3dB cutoff frequency of each channel to form a controllable overlap of less than 2%, it fills the gaps at the frequency division boundary, eliminates spectral holes and signal energy loss, and achieves continuous lossless spectral coverage across the entire frequency band. It has low spectral distortion and high detection accuracy, fundamentally solving the technical problem that traditional four-way frequency division architecture cannot be put into practical use due to spectral holes.

[0115] 3. This invention achieves an optimal balance between performance and overhead through flexible configuration of hierarchical parameters. It supports two configuration modes: unified parameters across all layers or differentiated parameters at each level. In the preferred embodiment, a "tight at the beginning, loose at the end" differentiated configuration is adopted: for example, layers L1-L2 use high suppression parameters of 61st order, 4% overlap, and stopband rejection ≥62dB to suppress out-of-band interference and spectral leakage; layers L3-L4 use a compromise configuration of 43-51st order, 6% overlap, and stopband rejection 57-60dB; and layers L5-L6 use a simplified configuration of 27-35th order, 9% overlap, and stopband rejection 52-55dB. Through this differentiated design, hardware power consumption is minimized while ensuring overall spectral resolution accuracy, solving the problem that traditional architectures cannot balance accuracy and power consumption.

[0116] 4. This invention achieves extreme hardware lightweighting and ultra-low power consumption. It eliminates high-radix FFT complex butterfly operations and twitch factor multiplication, using a design where all filter coefficients are fixed to integer powers of 2. The three mixing channels only employ sign inversion and data sequence exchange logic to achieve equivalent mixing, eliminating multiplication, twitch factor iteration, trigonometric function operations, and large-scale data buffering. Taking LoRa SF=12 (equivalent to 4096-point FFT) as an example, compared to traditional FFT schemes, the number of hardware gates is reduced by more than 65%, and power consumption is reduced by more than 60% (40nm CMOS process), making it suitable for ultra-low power IoT chip design scenarios.

[0117] 5. This invention has pipelined real-time processing capability with no blocking delay. This invention adopts a point-to-point pipelined continuous processing mechanism. After the signal sampling module outputs a distortion-free continuous time domain data stream, the four-level overlapping filter cascaded module processes it step by step in a pipelined manner. There is no need to buffer the entire frame of data, and there is no blocking delay inherent in block operations. The end-to-end processing latency is reduced to the pipeline tick level (sub-microsecond level), which is significantly better than the millisecond-level block latency of traditional FFT. It is suitable for ultra-low latency communication and real-time spectrum monitoring scenarios.

[0118] 6. This invention has multi-resolution blind parallel processing capability with no receiving blind zone; each tree level of this invention outputs spectrum results of different resolutions in parallel without global synchronization, phase locking and frequency offset pre-calibration, and supports full-blind spectrum decomposition; any level of sub-channel can be independently extracted and demodulated without time-series interference and without time-division switching blind zone, naturally supporting parallel blind reception of multi-rate and multi-standard mixed signals, greatly improving the system's network concurrency capacity and adaptability to complex electromagnetic environments;

[0119] 7. This invention adopts a general and scalable architecture to form a complete independent technology system. The core architecture of this invention can be seamlessly extended to eight-part, sixteen-part and arbitrary integer N-part tree-shaped cascaded architectures, including hybrid cascaded architectures, to form a complete multi-level integer frequency division general spectrum decomposition system, fully covering the same principle tree-shaped iterative scheme, with complete barriers and no dead ends. It is of great strategic significance for getting rid of the path dependence on foreign FFT core algorithms.

[0120] 8. This invention can shut down sub-channels as needed to further reduce power consumption; depending on the scenario (such as narrowband communication scenarios like LoRa), a large number of sub-channels that do not need to be calculated can be shut down during processing to avoid invalid calculations, further save dynamic power consumption, and extend the battery life of IoT terminal devices. Attached Figure Description

[0121] Figure 1 This is a schematic diagram of the system described in this invention;

[0122] Figure 2 This is a flowchart of the method described in this invention;

[0123] Figure 3 This is a block diagram of the pipeline architecture for the decomposition of 4096 sub-channels as described in this invention;

[0124] Figure 4 This is an architectural diagram of the basic unit of the tree-shaped four-molecule channel decomposition described in this invention;

[0125] Figure 5 This is another architectural diagram of the basic unit of the tree-shaped tetramolecular channel decomposition described in this invention. Detailed Implementation

[0126] The main technical features and embodiments of the present invention will now be described in detail with reference to the accompanying drawings;

[0127] In the technical solution of this invention, the quaternion tree cascaded architecture uses a quaternion tree (4 times frequency division) as the basic iterative unit, and multiple levels are sequentially cascaded to form a complete spectrum decomposition link. Each level implements four-channel parallel filtering and four-fold downsampling, progressively improving the spectrum resolution. Its main function is to take advantage of the characteristic that the resolution improvement efficiency of a single level of the quaternion tree is twice that of the binary tree (4 times vs. 2 times), so that the number of cascaded levels is halved under the same spectrum accuracy, directly reducing the accumulated delay, accumulated error and hardware overhead. This is the core architecture foundation of this invention.

[0128] In the technical solution of this invention, the asymmetric four-channel parallel structure comprises a direct-pass channel and three mixing channels in each stage of the four-part tree filtering unit. The direct-pass channel directly filters and downsamples, and the three mixing channels respectively use F s / 4、2F s / 4、3F s / 4 performs equivalent downmixing followed by filtering and downsampling; its main function is to utilize the functional differences between the through channel and the mixing channel to avoid unnecessary redundant mixing processing in the symmetrical architecture, thereby minimizing hardware overhead and making it a key structural design for achieving lightweight hardware.

[0129] In the technical solution of this invention, the simplified mixing logic (including sign inversion and data sequence exchange, where data sequence exchange mainly involves simple operations such as I / Q data exchange and inverted I / Q data exchange) is implemented by completely transforming the equivalent complex mixing of the three mixing channels through sign inversion logic and data sequence exchange logic. There are no multiplication operations, no addition operations, no trigonometric function operations, and no twitch factor iterations. This technical feature is one of the core technical features of this invention, which fundamentally eliminates the hardware overhead of mixing operations and completely frees the spectrum decomposition architecture from the dependence on multipliers. This is the core reason for achieving a reduction of more than 65% in the number of hardware gates.

[0130] In the technical solution of this invention, in addition to roll-off compensation technology, controllable spectrum overlap is the expansion of the 3dB cutoff frequency of each channel of the four-way tree filter unit relative to the nominal frequency division boundary to form a controllable spectrum overlap region. The overlap amount can be controlled within 2% of the channel bandwidth. This technical feature solves the fundamental defect of the traditional four-way architecture, which has spectrum holes and signal energy loss at the frequency division boundary due to the strict no-overlap design, and achieves continuous lossless spectrum coverage across the entire frequency band.

[0131] In the technical solution of this invention, the fixed filter coefficients, which are integer powers of 2, are all filter unit coefficients that are integer powers of 2 (0, ±1, ±2, ±4, etc.). They are fixed in hardware storage, without dynamic configuration or ROM parameter storage. Their main function is to reduce the filtering operation to shift and addition operations, eliminating the need for multipliers, greatly reducing hardware area and dynamic power consumption, and eliminating the storage overhead of rotation factor. This is the core technical means to achieve ultra-low power hardware implementation.

[0132] In the technical solution of this invention, the hierarchical differentiated parameter configuration supports independent differentiated configuration of filter parameters at each level. The preferred embodiment adopts a "tight at the front and loose at the back" strategy: high-frequency level with high stopband suppression and low overlap, and low-frequency level with low-order filtering and high overlap. This technical feature solves the contradiction that the unified parameters of the traditional architecture cannot take into account the performance of the entire frequency band and the overall power consumption, achieves the optimal balance between system-level performance and overhead, and enhances the flexibility of the architecture to adapt to different scenarios.

[0133] In the technical solution of this invention, pipeline point-to-point non-blocking processing means that signal data flows continuously into each level of the four-part tree filtering unit, and each level is processed synchronously in a pipelined manner. There is no need to buffer the entire frame of data, and there is no block-type blocking delay between levels. Its main function is to eliminate the inherent frame-level buffering delay and computation delay of traditional FFT, and realize nanosecond-level pipeline tick processing. It is a key technical feature to meet the needs of ultra-low latency communication and real-time spectrum monitoring scenarios.

[0134] In the technical solution of this invention, the multi-resolution blind parallel output is the spectral results of different resolutions that are constantly output in parallel by the four-part tree filtering units at each level. The output of each level is selected by a hardware multiplexer, and each sub-channel can be independently extracted and demodulated without global synchronization and phase locking. Its main function is to realize multi-resolution parallel output in a single processing, eliminate the time-division switching blind zone, and support the parallel blind reception of multi-rate and multi-standard mixed signals. This is the core system-level advantage feature of this invention.

[0135] In the technical solution of this invention, the sub-channel on-demand shutdown is based on the target signal bandwidth information, and the filtering and downsampling processing of the invalid sub-channel is turned off by the sub-channel shutdown control module. Its main function is to turn off a large number of sub-channels that do not need to be calculated in narrowband communication scenarios (such as LoRa), thereby further saving dynamic power consumption. It is an important optimization feature for ultra-low power consumption scenarios of the Internet of Things.

[0136] In the technical solution of this invention, the general N-part tree scalability is that the core architecture can be seamlessly extended to eight-part, sixteen-part, and arbitrary integer N-part tree cascade architectures, including hybrid cascade architectures; its main function is to form a complete multi-level integer frequency division general spectrum decomposition system, fully covering the same principle tree iterative scheme, ensuring that the patent barrier is complete and without dead ends, and has important strategic significance for industrialization.

[0137] refer to Figure 1This diagram illustrates a schematic block diagram of a four-level tree-structured subchannel decomposition system according to one or more embodiments of this application. The system is applied in wireless communication baseband processing chips, IoT multi-mode receivers, and high-precision spectrum sensing devices to replace traditional high-radius FFTs and achieve low-latency, low-power, multi-resolution parallel spectrum decomposition. The system includes: a signal sampling module, a four-level overlapping filter cascade module, a resolution adaptive gating module, and a multi-channel parallel energy decision demodulation module.

[0138] In one or more embodiments, the input of the signal sampling module receives an analog intermediate frequency (IF) or baseband signal from the radio frequency (RF) front end, and the module is configured to sample at a preset frequency F. s (e.g. F) s (30.72MHz, suitable for LTE / 5G baseband processing scenarios) The input analog signal is continuously sampled, and a digital time-domain data stream is output. This data stream is a complex baseband signal containing in-phase components (I-channel) and quadrature components (Q-channel). The sampling bit width is preferably 12 bits to balance dynamic range and hardware overhead. The digital time-domain data stream is continuously output to the subsequent four-stage overlapping filter cascade module in a sample-by-sample manner, without any frame buffering operation. The output of the signal sampling module is connected to the input of the four-stage overlapping filter cascade module.

[0139] In one or more embodiments, the input of the four-level overlapping filter cascade module is connected to the output of the signal sampling module. This module includes N sequentially cascaded quadtree filter units (N≥1, N=6 in a preferred embodiment of the invention), with each level of the quadtree filter unit cascaded sequentially to progressively improve the spectral resolution. Each level of the quadtree filter unit is configured to perform four-channel parallel spectral filtering and four-to-one downsampling processing on the input signal.

[0140] Specifically, the input of the first-stage quartet filter unit is connected to the output of the signal sampling module, the output of the first-stage quartet filter unit is connected to the input of the second-stage quartet filter unit, and so on, until the output of the Nth-stage quartet filter unit serves as the output of each level of the four-stage overlapping filter cascade module (i.e., the output of each quartet filter unit is an independent level output). The frequency resolution of each stage of the quartet filter unit is increased by 4 times compared to the previous stage, and the total frequency resolution after N-stage cascading is 4 times the initial resolution. N Multiple times. Taking N=6 as an example, a 6-stage cascade is equivalent to 4 times. 6 =4096 sub-channels, corresponding to an equivalent 4096-point FFT spectral resolution capability, such as Figure 3 As shown.

[0141] In one or more embodiments, each stage of the quartic tree filtering unit adopts an asymmetric four-channel parallel architecture with one through-channel and three mixing channels, such as Figure 4 and Figure 5 As shown. The direct-through channel directly filters and downsamples the input signal by 4-to-1, without frequency shifting the input signal; the three mixing channels each use a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4(F s The input signal is subjected to equivalent complex downmixing (where F is the sampling frequency of the current input signal at this stage). After shifting the target frequency band to the baseband, filtering and decimation-4 downsampling are performed. Since the sampling frequency of the input signal to the first-stage filtering unit is F... s (That is, the sampling frequency of the signal sampling module), after the first stage of 4-decimation downsampling, the sampling frequency of the input signal of the second-stage filtering unit becomes F. s / 4, the third level becomes F s / 16, and so on;

[0142] It should be noted that the specific operation process of the four-in-one downsampling is as follows:

[0143] 1. Preprocessing (filtering): Before downsampling, the input signal (whether it is a through channel or a three-way mixer channel) must be filtered first. This is to prevent high-frequency components from aliasing to low frequencies and causing interference after downsampling (anti-aliasing filtering).

[0144] 2. Perform extraction (retention and discard): Perform "one out of four" extraction on the filtered output data stream, that is, retain one sample out of every four output samples in chronological order, while discarding the three samples in the middle.

[0145] 3. Data rate change: After the extraction process is completed, the output data rate is reduced to 1 / 4 of the input data rate (i.e., );

[0146] 4. Cascading effect: This operation is performed in each quartic tree filtering unit. When moving to the next level, the sampling rate is divided by 4 again. For example, as described in the document: the sampling rate for the first level is... The second level becomes / 4, the third level becomes / 16, and so on, thus achieving progressive spectrum refinement.

[0147] In one or more embodiments, the 4-to-1 downsampling process is to match the quartic tree architecture. Each level reduces the data rate to 1 / 4, which matches the "quartic" (4x frequency division) tree architecture. This allows the local oscillator frequency of the next level mixer to decrease synchronously with the sampling rate. At the same time, the bandwidth is reduced to 1 / 4, which is equivalent to dividing the same frequency band more finely. This achieves the technical effect described in the document, which is "the efficiency of single-level resolution improvement is twice that of the binary tree (4x vs. 2x)".

[0148] In one or more embodiments, the equivalent complex downmixing of the three mixing channels is fully implemented through sign inversion logic and data sequence exchange logic, without the need for any multipliers, adders, trigonometric function operation units or rotation factor storage units.

[0149] In one or more embodiments, the local oscillator frequency is F. s The equivalent complex downmixing of the / 4 mixing channel is implemented as follows:

[0150] For the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3, representing the phase index of the current sample within a four-sample period):

[0151] When r=0, the I-channel output equals the I-channel input, and the Q-channel output equals the Q-channel input (i.e., 0° phase, no change).

[0152] When r=1, I-channel output = Q-channel input, and Q-channel output = -I-channel input (i.e., 90° phase, swapped and inverted Q-channel).

[0153] When r=2, the I-channel output = -I-channel input, and the Q-channel output = -Q-channel input (i.e., 180° phase, both channels are inverted).

[0154] When r=3, I-channel output = -Q-channel input, and Q-channel output = I-channel input (i.e., 270° phase, swapped and inverted I-channel).

[0155] In the above method, I-path represents the in-phase component, and Q-path represents the quadrature component; the operation loops once every four samples, and each time only data gating and sign inversion operations are performed. Through this method, F is achieved. s The complex number undermixing of / 4 has no multiplication and addition operations throughout.

[0156] In one or more embodiments, the local oscillator frequency is F. s The equivalent complex downmixing of the / 2 mixing channel is implemented as follows:

[0157] For the input sample index n = 2k + r (k is a non-negative integer, r = 0, 1):

[0158] When r=0, the I-channel output equals the I-channel input, and the Q-channel output equals the Q-channel input (i.e., 0° phase, no change).

[0159] When r=1, the I-channel output = -I-channel input, and the Q-channel output = -Q-channel input (i.e., 180° phase, both channels are inverted).

[0160] The above operation is performed once for every two samples, requiring only the sign inversion operation and no data exchange.

[0161] In one or more embodiments, the local oscillator frequency is 3F. s The equivalent complex downmixing of the / 4 mixing channel is implemented as follows:

[0162] For the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3):

[0163] When r=0, the I-channel output equals the I-channel input, and the Q-channel output equals the Q-channel input (i.e., 0° phase, no change).

[0164] When r=1, I-channel output = -Q-channel input, and Q-channel output = I-channel input (i.e., 90° phase, swapped and inverted I-channel).

[0165] When r=2, the I-channel output = -I-channel input, and the Q-channel output = -Q-channel input (i.e., 180° phase, both channels are inverted).

[0166] When r=3, the I-channel output = the Q-channel input, and the Q-channel output = -I-channel input (i.e., 270° phase, swapped and inverted Q-channel).

[0167] The above operation is repeated every four samples, and each time only the data gating and sign inversion operations need to be performed.

[0168] In one or more embodiments, the filter coefficients of each channel of each stage of the quadtree filtering unit are integer powers of 2 (e.g., 0, ±1, ±2, ±4, ±8, etc.), and all coefficients are hardware-fixed and stored in registers, without dynamic configuration logic or ROM parameter storage.

[0169] In one or more embodiments, the filtering operation is implemented as follows: when the input signal sample is multiplied by each filtering coefficient, since the coefficient is an integer power of 2, the multiplication operation degenerates into a shift operation (left shift corresponds to multiplication by a positive power, and right shift corresponds to division by a positive power); multiple shift results are accumulated through an adder to obtain the filtered output; no general-purpose multiplier is required throughout the process.

[0170] In one or more embodiments, the 3dB cutoff frequency of each channel of the quadtree filter unit at each stage is extended outward relative to the nominal frequency division boundary to form a controllable spectral overlap. This is achieved using a normalized sampling frequency F. s Taking 2 as an example, the nominal frequency division boundary is 0.25F. s (i.e., 0.5 normalized frequency), the 3dB cutoff frequency of each channel is extended outward, causing the -3dB frequency points of adjacent channels to overlap. The overlap amount is defined as the ratio of the overlap bandwidth to the bandwidth of a single channel. The controllable spectral overlap amount is greater than 0 and less than or equal to 2% of the bandwidth of each channel (in the preferred embodiment, the overlap amount is 2%, i.e., the unilateral extension amount is 1% of the channel bandwidth). Through the above-mentioned controllable overlap, the frequency response curves of adjacent sub-channels remain flat after being superimposed at the frequency division boundary, eliminating spectral holes at the frequency division boundary and achieving continuous and gapless spectrum coverage across the entire frequency band.

[0171] In one or more embodiments, the four-level overlapping filter cascade module includes six sequentially cascaded quadtree filter units, with a normalized sampling frequency F:

[0172] The filter order of the first-level and second-level quartic tree filtering units can generally be higher, such as 64th order (which can be adjusted according to the specific application scenario); the above high suppression parameters are suitable for high-frequency levels and are used to suppress out-of-band interference and spectral leakage.

[0173] The filter order of the third-level and fourth-level quartic tree filtering units can be slightly lower than that of the first two levels, such as 32nd order (which can be adjusted according to the specific application scenario).

[0174] The filter orders of the fifth-stage and sixth-stage quartet filter units can be lower, such as 16th order (which can be adjusted according to specific application scenarios). These simplified parameters reduce the hardware power consumption of the low-frequency stages.

[0175] In one or more embodiments, the overlap increases from 4% at the high-frequency level to 9% at the low-frequency level, forming a differentiated configuration strategy of "tight at the front and loose at the back". That is, at the front end of the signal passband (high-frequency level), high suppression and low overlap are used to ensure spectral purity and anti-interference capability, while at the back end of the signal passband (low-frequency level), low-order filtering and high overlap are used to reduce hardware power consumption.

[0176] In one or more embodiments, the four-level overlapping filter cascade module employs a point-to-point pipelined processing architecture. The digital time-domain data stream output from the signal sampling module flows continuously sample by sample into the first-level quartic tree filter unit. Each level of the quartic tree filter unit processes data synchronously in a pipelined manner (i.e., within the same clock cycle, the first level processes the current new sample, the second level processes the output from the previous cycle of the first level, the third level processes the output from the previous cycle of the second level, and so on), without buffering the entire frame of data. The output of each level of the quartic tree filter unit is an independent hierarchical output, simultaneously outputting spectral results at different resolutions. The end-to-end delay of the entire four-level overlapping filter cascade module depends only on the pipeline depth caused by the filter order (typically several to tens of clock cycles), and is independent of the data frame length.

[0177] In one or more embodiments, the input of the resolution adaptive gating module is connected to the output of each level of the four-level overlapping filter cascade module (i.e., connected to the output of the first to Nth level four-level tree filter units respectively), and the module is configured to gating the spectrum output of the corresponding level output according to the target signal bandwidth and resolution requirements.

[0178] In one or more embodiments, the resolution adaptive gating module includes a hardware multiplexer (MUX). Each input of the hardware multiplexer is connected to the outputs of different levels of the four-level overlapping filter cascade module. The control terminal of the hardware multiplexer receives a resolution gating control signal from the upper-level processor (e.g., when the target signal is a wideband signal, the output of the preceding level is gated to obtain a low-resolution wideband spectrum; when the target signal is a narrowband signal, the output of the following level is gated to obtain a high-resolution narrowband spectrum). The output terminal of the hardware multiplexer outputs the spectrum data of each sub-channel of the gating level (including I / Q data or energy values ​​of all sub-channels at that level). The above gating operation is achieved solely by switching the output path using the multiplexer, without requiring any hardware parameter reconstruction. The switching speed depends only on the propagation delay of the multiplexer (nanosecond level), with no time-division switching dead zone.

[0179] In one or more embodiments, the input of the multi-channel parallel energy decision demodulation module is connected to the output of the resolution adaptive gating module, which is configured to perform parallel energy detection, frequency point identification and signal demodulation on each sub-channel of the gating level output.

[0180] In one or more embodiments, the multi-channel parallel energy decision demodulation module includes multiple energy detection sub-modules operating in parallel (the number equal to the total number of sub-channels in the gating level, for example, 4096 sub-channels when gating level 6). Each energy detection sub-module corresponds to one sub-channel, and each energy detection sub-module independently completes the energy calculation for the corresponding sub-channel (calculation I). 2 +Q2 The functions include (cumulative or average value), threshold decision (comparing the calculated energy value with a preset threshold to determine if a signal exists), and signal demodulation (performing corresponding demapping and decoding operations according to the modulation method). No global synchronization or phase locking is required between sub-channels; the processing timing of each sub-channel is completely independent, naturally supporting parallel blind reception of multi-rate, multi-standard mixed signals.

[0181] In one or more embodiments, the system further includes a sub-channel shutdown control module connected to a four-level overlapping filter cascade module. The sub-channel shutdown control module is configured to determine invalid sub-channels (i.e., sub-channels outside the target signal frequency band) based on the target signal bandwidth information and send a shutdown control signal (e.g., a high-level active channel enable signal) to the corresponding four-level tree filter unit. The corresponding four-level tree filter unit responds to the shutdown control signal by disabling the clock gating or operand enable terminal of the corresponding sub-channel, thereby stopping the filtering and downsampling processing of the invalid sub-channel. The above shutdown operation can be flexibly enabled according to the scenario requirements. In narrowband communication scenarios (such as LoRa and NB-IoT), more than 90% of invalid sub-channels can be shut down, avoiding invalid computation and significantly saving dynamic power consumption.

[0182] In one or more embodiments, the signal sampling module, the four-level overlapping filter cascade module, the resolution adaptive gating module, and the multi-channel parallel energy decision demodulation module work together to realize a four-part tree subchannel decomposition system that completely replaces the high-radix FFT. This system has no multiplication operations, no blocking delay, supports multi-resolution parallel output, and has significantly lower hardware gate count and power consumption than traditional FFT schemes.

[0183] refer to Figure 2 The diagram illustrates a flowchart of a four-part tree-structured subchannel decomposition method according to one or more embodiments of this application. The method is applied to a baseband processing link of a wireless communication receiver and includes: step A, signal sampling; step B, four-level overlapping filtering cascade processing; step C, resolution adaptive gating; step D, multi-signal parallel energy decision demodulation; and step E, subchannel on-demand shutdown.

[0184] In one or more embodiments, step A is a signal sampling process, in which the signal sampling module uses a preset sampling frequency F. s (e.g. F) s =30.72MHz, adapted for 5G NR baseband processing) continuously samples the input analog signal (from the antenna after downconversion by the RF front end) and outputs a digital time domain data stream, which is a sample-by-sample continuous I / Q complex data stream.

[0185] In one or more embodiments, step B is a four-level overlapping filter cascade process, wherein the digital time-domain data stream is input to a multi-level sequentially cascaded quadtree filter unit (preferably 6 levels), and each level of the quadtree filter unit performs four-channel parallel spectrum filtering and four-to-one downsampling processing on the input signal. The quadtree filter units at each level are cascaded to progressively improve the spectral resolution.

[0186] In one or more embodiments, step B specifically includes the following sub-steps:

[0187] Sub-step B1, four-channel parallel expansion and mixing: Each stage of the four-way tree filter unit establishes a direct channel for the input signal and a mixing channel with a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4 performs equivalent complex number down-mixing on three mixing channels, F s The sampling frequency of the input signal in the current stage (first stage F) s The original sampling frequency is used, and each subsequent stage is 1 / 4 of the previous stage's frequency.

[0188] The direct-through channel does not shift the frequency of the input signal; it directly sends the input signal to the subsequent filter. The three mixing channels shift different frequency bands of the input signal to the baseband to facilitate subsequent filtering and extraction.

[0189] Sub-step B2, Simplified Mixing Operation: The equivalent complex down-mixing of the three mixing channels is achieved through sign inversion logic and data sequence exchange logic, without multiplication, addition, or trigonometric function operations. Specifically:

[0190] For F s The / 4 mixing channel is implemented as follows: for the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3):

[0191] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0192] When r=1, I-channel output = Q-channel input, and Q-channel output = -I-channel input;

[0193] When r=2, the I-way output = -I-way input, and the Q-way output = -Q-way input;

[0194] When r=3, I-channel output = -Q-channel input, and Q-channel output = I-channel input.

[0195] In the above operation, I-path represents the in-phase component, Q-path represents the quadrature component, and the cycle repeats once every four samples.

[0196] For F sThe / 2 mixing channel is implemented as follows: For the input sample index n = 2k + r (k is a non-negative integer, r = 0, 1):

[0197] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0198] When r=1, the I-way output equals -I-way input, and the Q-way output equals -Q-way input.

[0199] The above operation is repeated once for every two samples.

[0200] For 3F s The / 4 mixing channel is implemented as follows: for the input sample index n = 4k + r (k is a non-negative integer, r = 0, 1, 2, 3):

[0201] When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input;

[0202] When r=1, I-way output = -Q-way input, and Q-way output = I-way input;

[0203] When r=2, the I-way output = -I-way input, and the Q-way output = -Q-way input;

[0204] When r=3, I-channel output = Q-channel input, and Q-channel output = -I-channel input.

[0205] The above operation is repeated every four samples.

[0206] Sub-step B3, Filtering: The direct-through signal and the three-channel mixing signal are filtered separately. The filtering coefficients of each stage of the quartic tree filtering unit are integer powers of 2 (e.g., 0, ±1, ±2, ±4, ±8, etc.). The filtering is performed through shift and addition operations, without the need for any multipliers. Specifically, the expression for the filtered output is:

[0207] ;

[0208] in, The coefficient is an integer power of 2. By input samples Implemented by performing arithmetic shifting.

[0209] The 3dB cutoff frequency of each channel is extended outward relative to the nominal frequency division boundary to form a controllable spectral overlap. The amount of controllable spectral overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel, which is used to eliminate spectral holes at the frequency division boundary.

[0210] Sub-step B4, 4-to-1 Downsampling: The filtered four-channel signals are downsampled by 4-to-1, meaning one sample is retained out of every four output samples (one sample is discarded every three samples). This reduces the output data rate to 1 / 4 of the input data rate, and simultaneously reduces the bandwidth of each sub-channel to 1 / 4 of its original value, increasing the frequency resolution by a factor of four. The downsampled data is then used as the input data stream for the next-level quartic tree filtering unit.

[0211] In one or more embodiments, the multi-stage sequentially cascaded quadtree filtering unit has 6 stages, and the parameters of each stage are configured as follows:

[0212] The filter order of the first and second stage quartic tree filtering units can generally be higher, such as 64th order (the actual order can be adjusted according to the scenario).

[0213] The filter order of the third and fourth level quadtree filtering units can be slightly lower than that of the first two levels, such as 32nd order (the actual order can be adjusted according to the scenario).

[0214] The filter order of the fifth and sixth level quadtree filtering units can be lower, such as 16th order (the actual order can be adjusted according to the scenario).

[0215] The above configuration forms a differentiated parameter configuration of "tight at the beginning and loose at the end": the high-frequency stage adopts a high stopband suppression and low overlap configuration, the mid-frequency stage adopts a compromise configuration, and the low-frequency stage adopts a low-order filter and high overlap configuration, so as to achieve the optimal balance between performance and power consumption.

[0216] In one or more embodiments, the filtering parameters at each level can be selected via configuration registers to either a unified parameter mode across all levels (suitable for standardized general scenarios, with each level using the same order and overlap) or a progressively differentiated parameter mode (each level independently configures the aforementioned differentiated parameters). The four-part tree filtering units at each level operate synchronously in a pipelined manner, with the digital time-domain data stream continuously flowing into each level sample by sample, eliminating the need to buffer entire frames of data and preventing blocking delays between levels.

[0217] In one or more embodiments, step C is a resolution adaptive gating process, in which the resolution adaptive gating module selects the spectrum output of the corresponding level according to the target signal bandwidth and resolution requirements.

[0218] In one or more embodiments, in response to a broadband signal detection scenario (such as requiring rapid scanning of the full-band energy distribution), the resolution adaptive gating module selects the output of the preceding level (such as selecting the first or second level output), outputting a low-resolution broadband spectrum (few sub-channels but covering the full bandwidth); in response to a narrowband signal detection scenario (such as requiring identification of subtle spectral features at specific frequency points), the resolution adaptive gating module selects the output of the following level (such as selecting the fifth or sixth level output), outputting a high-resolution narrowband spectrum (many sub-channels, narrow bandwidth). The four-way tree filtering units at each level are resident and output the spectrum results of their respective levels in parallel (all levels are effective simultaneously). The gating operation is achieved only by switching the output path using a multiplexer, without requiring hardware reconfiguration, and the switching time is a single clock cycle.

[0219] In one or more embodiments, step D is a multi-signal parallel energy decision demodulation process, in which the multi-channel parallel energy decision demodulation module performs parallel energy detection, frequency point identification and signal demodulation on each sub-channel output by the gating level.

[0220] In one or more embodiments, each sub-channel independently performs energy detection (calculating the instantaneous or average power of the signal in each sub-channel), threshold decision (comparing the detected energy value with a preset threshold; if the value exceeds the threshold, a signal is considered present), and signal demodulation (performing corresponding demapping, despreading, and decoding operations based on the signal modulation type, such as BPSK, QPSK, LoRa Chirp, etc.). No global synchronization or phase locking is required between sub-channels; each sub-channel has independent frequency and timing, supporting parallel blind reception of multi-rate, multi-standard mixed signals.

[0221] In one or more embodiments, the method further includes step E, which is a sub-channel on-demand shutdown process. The sub-channel shutdown control module determines invalid sub-channels based on the target signal bandwidth information (for example, in LoRa communication, the received signal occupies only a very narrow bandwidth, and a large number of other sub-channels have no effective signal), and sends a shutdown control signal to the corresponding quartet filtering unit. The corresponding quartet filtering unit responds to the shutdown control signal by turning off the clock signal or operand input enable of the branch corresponding to the invalid sub-channel, and stops the filtering and downsampling processing of the invalid sub-channel, thereby further reducing dynamic power consumption.

[0222] In one or more embodiments, in response to an abnormal resolution gating control signal in step C (such as gating a non-existent level number or the target resolution exceeding the system's supported range), an error handling process is executed, wherein the error handling process includes at least one of the following operations: terminating the current gating operation, maintaining the previous valid gating state, recording an error log to a status register for the upper-level processor to read, and triggering a system-level reset to restore to the default gating state.

[0223] In one or more embodiments, in response to any subchannel energy detection overflow in step D (such as input signal power exceeding the ADC range causing I / Q data saturation), the subchannel automatically suspends demodulation operation, records the overflow flag, and waits for the upper-layer processor to adjust the gain before resuming processing.

[0224] In one or more embodiments, steps A through E work together to achieve a quadtree-shaped subchannel decomposition method that completely replaces the high-radix FFT. Compared to traditional FFT methods, this method, by employing a 4x progressive frequency division, halves the processing levels at the same resolution (for example, in equivalent 65536-point spectrum analysis, a binary tree requires 16 levels while this method only requires 8), significantly reducing accumulated delay and error. Due to the use of simplified mixing logic and fixed-coefficient filtering, there are no multiplication operations throughout, significantly reducing dynamic power consumption and chip area. The use of pipelined point-by-point processing eliminates frame-level blocking delay. The use of multi-level parallel output and independent subchannel demodulation naturally supports multi-resolution parallel processing and blind reception of multi-standard signals. In a 40nm CMOS process, in an equivalent 4096-point FFT processing scenario, the number of hardware gates is reduced by more than 65%, and power consumption is reduced by more than 60%.

[0225] In one or more embodiments, the present invention also discloses a quadtree-shaped subchannel decomposition device, which is a hardware accelerator core integrated into a wireless communication baseband chip or an Internet of Things SoC. The device includes a sampling device, an N-level sequentially cascaded quadtree filtering device, a gating output device, a parallel demodulation device, and a subchannel shutdown control device.

[0226] In one or more embodiments, the sampling device is used to continuously sample the input analog signal at a preset sampling frequency and output a digital time-domain data stream. Specifically, the sampling device 310 includes an analog-to-digital converter (ADC, such as a 12-bit successive approximation SAR ADC or ΔΣ ADC) and a digital down-converter (DDC). The ADC converts the analog signal into a digital intermediate frequency signal, and the DDC down-converts the digital intermediate frequency signal to baseband and outputs two complex data streams (I and Q). The sampling frequency F s =30.72MHz, data width 12 bits.

[0227] In one or more embodiments, an N-stage cascaded quadtree filter (N is an integer greater than or equal to 1, preferably N=6) is used. The input of the first-stage quadtree filter is connected to the output of the sampling device. Each stage of the quadtree filter includes one direct-through filter branch and three mixing filter branches. The three mixing filter branches each use a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4 performs equivalent complex downmixing on the input signal. This equivalent complex downmixing is implemented using sign inversion logic and data sequence exchange logic (the specific implementation is the same as the simplified mixing logic in the aforementioned system embodiment, and will not be repeated here). Each branch output is filtered (each channel filter coefficient is an integer power of 2, filtering is completed through shift and addition operations, without multipliers or twitch factor storage units) and then downsampled by decimation. The four-way tree filtering devices at each stage are cascaded (the first stage output connects to the second stage input, the second stage output connects to the third stage input, and so on), with each stage's output serving as an independent hierarchical output. The 3dB cutoff frequency of each channel in each stage of the four-way tree filtering device extends outward relative to the nominal frequency division boundary to form a controllable spectral overlap. This controllable spectral overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel, used to eliminate spectral holes at the frequency division boundary.

[0228] In one or more embodiments, the gating output device is connected to the output terminals of each level of the quadtree filter (i.e., connected to the branch output terminals of each quadtree filter from level 1 to level N), and is used to select the output of the corresponding level according to the target signal resolution requirements. The gating output device includes a multi-level multiplexer tree (MUX Tree) and an output buffer register. The control terminal of the multiplexer receives the resolution configuration register value from the processor bus, and selects all sub-channel output data of the corresponding level to the output buffer register according to the value.

[0229] In one or more embodiments, the parallel demodulation device is connected to the output of the gating output device and is used to perform parallel energy decision-making and demodulation on each sub-channel of the gating level output. The parallel demodulation device includes a number of demodulation processing units (PEs) equal to the total number of sub-channels in the gating level, and each demodulation processing unit independently performs energy calculation (I... 2 +Q 2 The demodulation processing units perform accumulation, threshold comparison (comparing with locally stored threshold register values), and demodulation operations (performing hard decision or soft output decoding based on the modulation type). There is no data dependency between the demodulation processing units; they operate entirely in parallel. Each demodulation processing unit also has a built-in state machine to control the energy accumulation period (e.g., accumulation in symbol length units) and demodulation timing.

[0230] In one or more embodiments, a sub-channel shutdown control device (optionally) is connected to each level of the quadtree filter device to determine invalid sub-channels based on target signal bandwidth information (e.g., parsing the target frequency point and bandwidth configuration information sent by the upper-level processor and calculating the sub-channel number outside the target frequency band coverage area), and sends a shutdown control signal to the corresponding quadtree filter device. The corresponding quadtree filter device responds to the shutdown control signal by stopping the filtering and downsampling processing of the invalid sub-channels through a clock gating cell or an operand isolation cell, thereby reducing dynamic power consumption.

[0231] In one or more embodiments, the filter coefficients of each channel in the quadtree filter device are permanently stored in hardware registers. The register values ​​are calculated by the design tool according to the filter design parameters (order, cutoff frequency, stopband suppression) and burned into the RTL code before chip fabrication. No dynamic loading is required after chip startup. The filtering operation of each channel is completed by a filter operation unit composed of a barrel shifter array (used to implement integer powers of 2 multiplication) and an adder tree (used to accumulate the shift results). The number of shift bits of the shifter array is determined by the fixed coefficients and implemented through hard-wired logic rather than programmable logic to minimize timing overhead and power consumption.

[0232] In one or more embodiments, the sampling device, the quard tree filter, the gating output device, and the parallel demodulation device work together to achieve the function of a low-power, low-latency, multi-resolution parallel quard tree subchannel decomposition device. This device can be integrated as a standalone hardware accelerator into the baseband chip, communicating with the main control processor via an AXI or AHB bus to receive configuration parameters and report spectrum detection results.

[0233] This application also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps of the quadtree subchannel decomposition method as described in the preceding method embodiments.

[0234] In one or more embodiments, the computer-readable storage medium is a non-volatile storage medium (e.g., read-only memory ROM, flash memory, solid-state drive SSD, embedded multimedia card eMMC, etc.). The computer program is burned into the internal ROM of the baseband chip in the form of firmware. After the chip is powered on, it is read and executed by the processor (e.g., ARM Cortex-M series or RISC-V core) to control the hardware accelerator (i.e., the quadtree subchannel decomposition device in the aforementioned device embodiments) to complete the spectrum decomposition operation.

[0235] In one or more embodiments, the computer program includes the following program instruction modules: a sampling control instruction module for configuring the sampling frequency and data bit width of the ADC; a filtering configuration instruction module for configuring the parameter modes (uniform mode across all levels or differentiated mode at each level) of the four-way tree filtering unit; a gating control instruction module for writing resolution gating values ​​to the control terminal of the multiplexer; a demodulation control instruction module for configuring the energy detection threshold and demodulation type of each sub-channel; and a shutdown control instruction module (optional) for calculating invalid sub-channels based on the target frequency band and writing them to the shutdown register. When the above program instruction modules are executed by the processor, the processor writes configuration values ​​to each control register of the hardware accelerator via the bus, triggering the hardware accelerator to perform spectrum decomposition operations in a pipelined manner.

[0236] In one or more embodiments, when the computer program is executed by a processor, in response to the target signal being a wideband signal (e.g., an LTE signal with a bandwidth of 20MHz), the processor executes a gating control instruction module to set the gating value of the multiplexer to the output of gating stage 1 or 2 to quickly acquire the full-band spectrum profile; in response to the target signal being a narrowband signal (e.g., a LoRa signal with a bandwidth of 125kHz), the processor executes a gating control instruction module to set the gating value of the multiplexer to the output of gating stage 5 or 6 to resolve the subtle spectral characteristics of the target frequency at high resolution.

[0237] In one or more embodiments, when the computer program is executed by the processor, error handling instructions are also executed: in response to an illegal configuration parameter (e.g., the gating level number exceeds the range of N, or the configured filter order is not a predefined value), the processor terminates the current configuration operation, writes the error code to the status register, and notifies the upper-level operating system via an interrupt; in response to a hardware accelerator operation overflow (e.g., the filtered output data exceeds a preset bit width range), the processor suspends the accelerator pipeline, reads the overflow flag register, and performs gain adjustment or data scaling operations before resuming processing.

[0238] In one or more embodiments, the coordinated execution of computer programs and processors, combined with the pipelined processing capabilities of hardware accelerators, enables a software scheduling and hardware acceleration fusion scheme for the quadtree subchannel decomposition method, balancing system flexibility and processing efficiency.

[0239] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A quadtree subchannel decomposition system, characterized by, include: The signal sampling module is used to continuously sample the input analog signal at a preset sampling frequency and output a digital time-domain data stream. The four-level overlapping filter cascade module has its input end connected to the output end of the signal sampling module. The four-level overlapping filter cascade module includes multiple sequentially cascaded quadtree filter units. Each level of the quadtree filter unit is used to perform four-channel parallel spectrum filtering and four-decimation downsampling processing on the input signal. The quadtree filter units at each level are cascaded to progressively improve the spectrum resolution. A resolution adaptive gating module, the input of which is connected to the outputs of different levels of the four-level overlapping filter cascade module, is used to select the spectrum output of the corresponding level output according to the target signal bandwidth and resolution requirements. A multi-channel parallel energy decision demodulation module is provided, the input of which is connected to the output of the resolution adaptive gating module. The multi-channel parallel energy decision demodulation module is used to perform parallel energy detection, frequency point identification and signal demodulation on each sub-channel of the gating level output. Each of the four-way tree filtering units adopts an asymmetric four-channel parallel architecture with one direct-through channel and three mixing channels. The direct-through channel directly filters and downsamples the input signal by decimation (4 / 10). The three mixing channels each use a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4 After performing equivalent complex downmixing on the input signal, filtering and decimation-4 downsampling are applied. F s The sampling frequency of the current input signal to the quadtree filter unit; The equivalent complex downmixing of the three mixing channels is achieved through sign inversion logic and data sequence exchange logic, without multiplication operations.

2. The system of claim 1, wherein, The four-level overlapping filter cascade module includes six sequentially cascaded quadtree filter units: The filter order of the first-level quartic tree filter unit and the filter order of the second-level quartic tree filter unit are both adjusted according to the requirements of the scenario. The filter order of the third-level quartet filter unit and the filter order of the fourth-level quartet filter unit are adjusted according to the scenario requirements, and the filter order of the third-level quartet filter unit and the filter order of the fourth-level quartet filter unit are lower than the lowest value among the filter order of the first-level quartet filter unit and the filter order of the second-level quartet filter unit. The filter order of the fifth-level quartet filter unit and the filter order of the sixth-level quartet filter unit are adjusted according to the requirements of the scenario, and the filter order of the fifth-level quartet filter unit and the filter order of the sixth-level quartet filter unit are lower than the lowest value among the filter order of the third-level quartet filter unit and the filter order of the fourth-level quartet filter unit.

3. The system of claim 1, wherein, In each stage of the quad-tree filter unit, the three-path mixing channel adopts a local oscillator frequency of F s The equivalent complex down-mixing at 1 / 4 is realized by the following way: For the input sample index n = 4k + r, where k is a non-negative integer and r = 0, 1, 2, 3: When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input; When r=1, I-channel output = Q-channel input, and Q-channel output = -I-channel input; When r=2, I-way output = -I-way input, and Q-way output = -Q-way input; When r=3, I-way output = -Q-way input, and Q-way output = I-way input; The three mixing channels use a local oscillator frequency of 2F. s The equivalent complex undermixing of / 4 is achieved in the following way: For the input sample index n = 2k + r, where k is a non-negative integer and r = 0, 1: When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input; When r=1, I-way output = -I-way input, and Q-way output = -Q-way input; The three mixing channels use a local oscillator frequency of 3F. s The equivalent complex undermixing of / 4 is achieved in the following way: For the input sample index n = 4k + r, where k is a non-negative integer and r = 0, 1, 2, 3: When r=0, I-channel output = I-channel input, and Q-channel output = Q-channel input; When r=1, I-way output = -Q-way input, and Q-way output = I-way input; When r=2, I-way output = -I-way input, and Q-way output = -Q-way input; When r=3, I-channel output = Q-channel input, and Q-channel output = -I-channel input; In the above expression, I-path represents the in-phase component, and Q-path represents the quadrature component.

4. The system according to claim 1, characterized in that, Each channel filter coefficient of the four-part tree filter unit at each level is an integer power of 2, and the filter completes the filtering process through shift operations and addition operations. Each channel of the four-way tree filter unit at each stage extends outward relative to the nominal frequency division boundary to form a controllable spectral overlap. The amount of controllable spectral overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel. The controllable spectral overlap is used to eliminate spectral holes at the frequency division boundary.

5. The system of claim 1, wherein, The four-level overlapping filter cascade module supports a unified parameter configuration mode across all levels and a progressively differentiated parameter configuration mode; the four-level overlapping filter cascade module adopts a point-by-point pipeline processing architecture.

6. The system of claim 1, wherein, The resolution adaptive gating module includes a hardware multiplexer. Each input of the hardware multiplexer is connected to the output of a different level of the four-level overlapping filter cascade module. The control terminal of the hardware multiplexer receives the resolution gating control signal, and the output terminal of the hardware multiplexer outputs the spectrum data of each sub-channel of the gating level.

7. The system of claim 1, wherein, It also includes a sub-channel shutdown control module, which is connected to the four-level overlapping filter cascade module. The sub-channel shutdown control module is used to determine invalid sub-channels based on the target signal bandwidth information and send shutdown control signals to the corresponding four-level tree filter units. The corresponding four-level tree filter units respond to the shutdown control signals and stop filtering and downsampling the invalid sub-channels.

8. A method for decomposing a quartic tree subchannel, said method being implemented based on the system as described in any one of claims 1 to 7, characterized in that, Includes the following steps: Step A: The signal sampling module continuously samples the input analog signal at a preset sampling frequency and outputs a digital time-domain data stream; Step B: The digital time-domain data stream is input into a multi-level sequentially cascaded quadtree filter unit. Each level of the quadtree filter unit performs four-channel parallel spectrum filtering and four-to-one downsampling processing on the input digital time-domain data stream. The quadtree filter units at each level are cascaded to progressively improve the spectrum resolution. Step C: The resolution adaptive gating module selects the corresponding level of spectrum output based on the target signal bandwidth and resolution requirements; Step D: The multi-channel parallel energy decision demodulation module performs parallel energy detection, frequency point identification, and signal demodulation on each sub-channel output by the gating level; The processing of each level of the quadtree filtering unit in step B includes: Establish a direct path for the input signal and use the local oscillator frequency F respectively. s / 4、2F s / 4 and 3F s / 4 performs equivalent complex number down-mixing on three mixing channels, F s The sampling frequency of the input signal at the current stage; The equivalent complex downmixing of the three mixing channels is achieved through sign inversion logic and data order exchange logic, without multiplication operations; The direct-through channel signal and the three-channel mixing channel signal are filtered separately. The filtered four-channel signals are downsampled by 1 / 4 sampling rate.

9. A quadtree subchannel decomposition device, the device configured as the system of any of claims 1 to 7, characterized in that, include: A sampling device, wherein the sampling device is used to continuously sample the input analog signal at a preset sampling frequency and output a digital time-domain data stream; An N-stage cascaded quadtree filter, where N is an integer greater than or equal to 1, connects the input of the first-stage quadtree filter to the output of the sampling device. Each stage of the quadtree filter includes one direct-through filter branch and three mixing filter branches, with each of the three mixing filter branches using a local oscillator frequency of F. s / 4、2F s / 4 and 3F s / 4 The input signal is subjected to equivalent complex downmixing. The equivalent complex downmixing is implemented by sign inversion logic and data order exchange logic. The output of each branch is filtered and then downsampled by decimation. The four-branch tree filtering devices at each stage are cascaded. A gating output device is connected to the output terminal of each level of the quadtree filter device, and is used to select the corresponding level output according to the target signal resolution requirements; A parallel demodulation device, which is connected to the output of the gating output device, is used to perform parallel energy decision and demodulation on each sub-channel of the gating level output; The filter coefficients of each channel of the N-level sequentially cascaded quadtree filter device are integer powers of 2. Filtering is completed through shift and addition operations, without multiplication operations or rotation factor storage units. Each channel of the four-way tree filter device at each stage extends outward from the nominal frequency division boundary to form a controllable spectrum overlap. The amount of controllable spectrum overlap is greater than 0 and less than or equal to 2% of the bandwidth of each channel, which is used to eliminate spectrum holes at the frequency division boundary.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it can implement the steps of the method of claim 8.

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