A five-dimensional sinusoidal cyclically symmetric conservative hyperchaotic circuit

Abstract

The application provides a five-dimensional sinusoidal cyclically symmetric conservative hyperchaotic circuit, relates to the technical field, and comprises a five-channel cyclically symmetric hardware architecture, integrated addition, integration and inversion modular circuits in each channel, matched resistance-capacitance devices and controlled voltage sources, and integrated sinusoidal nonlinear processing modules, so that the operation logic of each channel is unified, parameters are matched, high-complexity chaotic signals can be stably output, and the demand of signal diversity and stability in an encryption scene is met. The application combines the five-channel cyclically symmetric architecture with the sinusoidal nonlinear processing modules, outputs five-dimensional chaotic signals, breaks through the bottleneck of limited space in the dynamics space of a low-dimensional chaotic circuit, generates multiple independent chaotic signal orbits, improves the chaotic characteristics and security of signals, and provides stable and reliable hardware signal support for a high-security encryption scene.

Description

Technical Field

[0001] This invention relates to the field of conservative hyperchaotic technology, and more specifically, to a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit. Background Technology

[0002] With their complex dynamics and unpredictability, chaotic circuits have been widely applied in critical fields such as secure communication, demonstrating extremely broad application prospects. Early information encryption commonly used dissipative chaotic circuits, but their susceptibility to attacks and insufficient security performance limited their application in core security scenarios. Conservative chaotic circuits, with their advantages of phase volume conservation, absence of attractors, and strong resistance to attacks, have become a research hotspot. However, the types of existing high-dimensional conservative hyperchaotic circuits are limited, research results on cyclic symmetric chaotic circuits are lacking, and there is a lack of hardware implementation schemes suitable for high-security encryption.

[0003] Traditional dissipative chaotic circuits suffer from vulnerabilities to attacks, resulting in significantly insufficient overall security performance and severely limiting their application in core secure communication scenarios. Existing high-dimensional conservative hyperchaotic circuits are limited in variety and cannot meet diverse secure communication needs. While cyclic symmetric chaotic circuits have attracted attention, there is a lack of relevant research results; neither mature five-dimensional sinusoidal cyclic symmetric conservative chaotic circuit schemes nor corresponding hardware circuit support exist, making it difficult to meet the practical application and experimental verification requirements of high-security encryption scenarios.

[0004] Therefore, it is necessary to design a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit to solve the problem that the existing high-dimensional conservative hyperchaotic circuits are limited in type and cannot adapt to diverse secure communication needs. Summary of the Invention

[0005] In view of this, the present invention proposes a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, which aims to solve the problem that the existing high-dimensional conservative hyperchaotic circuits have limited types and are difficult to adapt to diverse secure communication requirements.

[0006] In one aspect, the present invention proposes a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, comprising: The first channel includes a first addition function module, a first integration function module, and a first inversion function module. The first addition function module, the first integration function module, and the first inversion function module are respectively implemented by a first operational amplifier U1A, a second operational amplifier U2A, and a third operational amplifier U3A. The second channel includes a second addition function module, a second integration function module, and a second inversion function module. The second addition function module, the second integration function module, and the second inversion function module are respectively implemented by the fourth operational amplifier U4A, the fifth operational amplifier U5A, and the sixth operational amplifier U6A. The third channel includes a third addition function module, a third integration function module, and a third inversion function module. The third addition function module, the third integration function module, and the third inversion function module are respectively implemented by the seventh operational amplifier U7A, the eighth operational amplifier U8A, and the ninth operational amplifier U9A. The fourth channel includes a fourth addition function module, a fourth integration function module, and a fourth inversion function module. The fourth addition function module, the fourth integration function module, and the fourth inversion function module are respectively implemented by the tenth operational amplifier U10A, the eleventh operational amplifier U11A, and the twelfth operational amplifier U12A. The fifth channel includes a fifth addition function module, a fifth integration function module, and a fifth inversion function module. The fifth addition function module, the fifth integration function module, and the fifth inversion function module are respectively implemented by the thirteenth operational amplifier U13A, the fourteenth operational amplifier U14A, and the fifteenth operational amplifier U15A.

[0007] Furthermore, the mathematical model of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit is as follows: In the formula, These are the state variables for the first channel, the second channel, the third channel, the fourth channel, and the fifth channel, respectively. They are respectively The first derivative.

[0008] Furthermore, the first path also includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first controlled voltage source V1, a second controlled voltage source V2, and a first capacitor C1. The inverting input terminal of U1A is connected in parallel to one end of R1, R2, R3, and R4; The other end of R1 is connected to y, the other end of R2 is connected to the positive terminal of V1, the negative terminal of V1 is connected to z, the other end of R3 is connected to the positive terminal of V2, the negative terminal of V2 is connected to -u, and the other end of R4 is connected to -w. The non-inverting input of U1A is grounded, the output of U1A is connected to the inverting input of U1A through R5, and the output of U1A is also connected to the inverting input of U2A through R7. The non-inverting input of U2A is grounded, the output of U2A is connected to the inverting input of U2A through C1, and the output of U2A is connected to the inverting input of U3A through R8. The non-inverting input of U3A is grounded, and the output of U3A is connected to the inverting input of U3A through R6.

[0009] Furthermore, the second channel also includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third controlled voltage source V3, a fourth controlled voltage source V4, and a second capacitor C2. The inverting input terminal of U4A is connected in parallel to one end of R9, R10, R11, and R12; The other end of R9 is connected to z, the other end of R10 is connected to the positive terminal of V3, the negative terminal of V3 is connected to u, the other end of R11 is connected to the positive terminal of V4, the negative terminal of V4 is connected to -w, and the other end of R12 is connected to -x. The non-inverting input of U4A is grounded, the output of U4A is connected to the inverting input of U4A through R13, and the output of U4A is also connected to the inverting input of U5A through R15. The non-inverting input of U5A is grounded, the output of U5A is connected to the inverting input of U5A through C2, and the output of U5A is connected to the inverting input of U6A through R16. The non-inverting input of U6A is grounded, and the output of U6A is connected to the inverting input of U6A through R14.

[0010] Furthermore, the third channel also includes: a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a fifth controlled voltage source V5, a sixth controlled voltage source V6, and a third capacitor C3. The inverting input terminal of U7A is connected in parallel to one end of R17, R18, R19, and R20; The other end of R17 is connected to u, the other end of R18 is connected to the positive terminal of V5, the negative terminal of V5 is connected to w, the other end of R19 is connected to the positive terminal of V6, the negative terminal of V6 is connected to -x, and the other end of R20 is connected to -y. The non-inverting input of U7A is grounded, the output of U7A is connected to the inverting input of U7A through R21, and the output of U7A is also connected to the inverting input of U8A through R23. The non-inverting input of U8A is grounded, the output of U8A is connected to the inverting input of U8A through C3, and the output of U8A is connected to the inverting input of U9A through R24. The non-inverting input of U9A is grounded, and the output of U9A is connected to the inverting input of U9A through R22.

[0011] Furthermore, the fourth channel also includes: the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the thirtieth resistor R30, the thirty-first resistor R31, the thirty-second resistor R32, the seventh controlled voltage source V7, the eighth controlled voltage source V8, and the fourth capacitor C4. The inverting input terminal of U10A is connected in parallel to one end of R25, R26, R27, and R28; The other end of R25 is connected to w, the other end of R26 is connected to the positive terminal of V7, the negative terminal of V7 is connected to x, the other end of R27 is connected to the positive terminal of V8, the negative terminal of V8 is connected to -y, and the other end of R28 is connected to -z. The non-inverting input of U10A is grounded, the output of U10A is connected to the inverting input of U10A through R29, and the output of U10A is also connected to the inverting input of U11A through R31. The non-inverting input of U11A is grounded, the output of U11A is connected to the inverting input of U11A through C4, and the output of U11A is connected to the inverting input of U12A through R32. The non-inverting input of U12A is grounded, and the output of U12A is connected to the inverting input of U12A through R30.

[0012] Furthermore, the fifth channel also includes: the thirty-third resistor R33, the thirty-fourth resistor R34, the thirty-fifth resistor R35, the thirty-sixth resistor R36, the thirty-seventh resistor R37, the thirty-eighth resistor R38, the thirty-ninth resistor R39, the fortieth resistor R40, the ninth controlled voltage source V9, the tenth controlled voltage source V10, and the fifth capacitor C5. The inverting input terminal of U13A is connected in parallel to one end of R33, R34, R35, and R36; The other end of R33 is connected to x, the other end of R34 is connected to the positive terminal of V9, the negative terminal of V9 is connected to y, the other end of R35 is connected to the positive terminal of V10, the negative terminal of V10 is connected to -z, and the other end of R36 is connected to -u. The non-inverting input of U13A is grounded, the output of U13A is connected to the inverting input of U13A through R37, and the output of U13A is also connected to the inverting input of U14A through R39. The non-inverting input of U14A is grounded, the output of U14A is connected to the inverting input of U14A through C5, and the output of U14A is connected to the inverting input of U15A through R40. The non-inverting input of U15A is grounded, and the output of U15A is connected to the inverting input of U15A through R38.

[0013] Furthermore, each controlled voltage source in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses the ABM_VOLTAGE function of the Multisim software.

[0014] Furthermore, each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses a TL082CM.

[0015] Furthermore, the power supply voltage of each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel is set to ±12V.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: It can output five-dimensional chaotic signals, which breaks through the bottleneck of limited dynamic behavior space of low-dimensional chaotic circuits compared with traditional four-dimensional and lower-dimensional chaotic circuits. The output signal has better chaotic characteristics, richer dynamic behavior and is more difficult to predict, providing stable and reliable hardware signal support for high-security encryption scenarios. The circuit adopts a cyclic symmetric hardware architecture and integrates a sinusoidal nonlinear processing module. Relying on the symmetry of the circuit structure and the nonlinearity and periodicity of the sine function, it can generate multiple independent chaotic signal tracks, enriching the dynamic characteristics of the hardware output signal, improving the hardware implementation security of secure communication, and adapting to the practical application needs of various encryption scenarios. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 The circuit structure diagram of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit provided in the embodiment of the present invention; Figure 2 The XY phase diagram of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit provided in the embodiments of the present invention; Figure 3 ZW phase diagram of a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit provided in an embodiment of the present invention; Figure 4 The output timing signal of the state variable u provided in the embodiments of the present invention. Detailed Implementation

[0018] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art. It should be noted that, without conflict, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Reference Figure 1 As shown in some embodiments of this application, a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit includes: a first channel, a second channel, a third channel, a fourth channel, and a fifth channel.

[0020] Specifically, the first channel includes a first addition module, a first integration module, and a first inversion module, which are implemented using a first operational amplifier U1A, a second operational amplifier U2A, and a third operational amplifier U3A, respectively. The second channel includes a second addition module, a second integration module, and a second inversion module, which are implemented using a fourth operational amplifier U4A, a fifth operational amplifier U5A, and a sixth operational amplifier U6A, respectively. The third channel includes a third addition module, a third integration module, and a third inversion module, which are implemented using a third addition module, a third integration module, and a third inversion module. The third inversion function module is implemented using the seventh operational amplifier U7A, the eighth operational amplifier U8A, and the ninth operational amplifier U9A, respectively. The fourth channel includes a fourth addition function module, a fourth integration function module, and a fourth inversion function module, which are implemented using the tenth operational amplifier U10A, the eleventh operational amplifier U11A, and the twelfth operational amplifier U12A, respectively. The fifth channel includes a fifth addition function module, a fifth integration function module, and a fifth inversion function module, which are implemented using the thirteenth operational amplifier U13A, the fourteenth operational amplifier U14A, and the fifteenth operational amplifier U15A, respectively.

[0021] Understandably, the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit has five independent channels to match the parallel dynamic evolution requirements of five-dimensional state variables. Each channel is equipped with three types of functional modules: addition, integration, and inversion. These modules can completely reproduce the core operational logic of algebraic superposition, time-domain integration, and signal inversion of the differential equations of the five-dimensional hyperchaotic circuit. Each functional module is built with an independent operational amplifier, which can ensure the electrical independence and operational accuracy of signal processing within the channel. The five channels are arranged in a cyclic symmetric structure, so that the hardware circuit topology and the mathematical model topology of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit are accurately mapped. Based on this architecture, the inherent physical characteristics of the conservative chaotic circuit, such as phase volume conservation and no attractors, are realized, thereby generating a highly complex and highly resistant five-dimensional hyperchaotic signal.

[0022] Specifically, the mathematical model of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit is as follows: In the formula, These are the state variables for the first channel, the second channel, the third channel, the fourth channel, and the fifth channel, respectively. They are respectively The first derivative.

[0023] It is understandable that the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit mathematical model constructs the core evolution equation of the circuit using the state variables corresponding to the five channels and their first derivatives. This equation establishes the dynamic correlation between variables in a sinusoidal cyclic symmetric form, transforming the signal transmission and transformation logic of the circuit hardware into a precise mathematical expression. Through the correspondence mapping between state variables and first derivatives, the physical and dynamic characteristics of the circuit are unified. Relying on the cyclic symmetric structure of the equation, the conservative property of the circuit phase volume conservation is maintained, so that the circuit output signal strictly follows the hyperchaotic dynamic evolution law, ensuring that the hardware circuit can stably reproduce the core dynamic behavior of the five-dimensional conservative hyperchaos.

[0024] Specifically, the first path further includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first controlled voltage source V1, a second controlled voltage source V2, and a first capacitor C1. The inverting input terminal of U1A is connected in parallel to one end of R1, R2, R3, and R4; The other end of R1 is connected to y, the other end of R2 is connected to the positive terminal of V1, the negative terminal of V1 is connected to z, the other end of R3 is connected to the positive terminal of V2, the negative terminal of V2 is connected to -u, and the other end of R4 is connected to -w. The non-inverting input of U1A is grounded, the output of U1A is connected to the inverting input of U1A through R5, and the output of U1A is also connected to the inverting input of U2A through R7. The non-inverting input of U2A is grounded, the output of U2A is connected to the inverting input of U2A through C1, and the output of U2A is connected to the inverting input of U3A through R8. The non-inverting input of U3A is grounded, and the output of U3A is connected to the inverting input of U3A through R6.

[0025] Understandably, the first channel is configured with resistors one through eight, a first controlled voltage source V1, a second controlled voltage source V2, and a first capacitor C1. Electrical connections are established for the first operational amplifier U1A, the second operational amplifier U2A, and the third operational amplifier U3A. Resistors one through four connect the state variable y, the z output of V1, the -u output of V2, and the state variable -w to the inverting input of U1A to achieve multi-channel signal superposition. The fifth resistor forms a feedback loop for U1A to complete the inverting addition operation. The output signal of U1A is transmitted to the inverting input of U2A via the seventh resistor. Capacitor C1 and U2A form an inverting integrator circuit to achieve time-domain integration. The integrated signal is sent to the inverting input of U3A through the eighth resistor. The sixth resistor forms a feedback loop for U3A to complete the signal inversion transformation. The non-inverting terminals of each operational amplifier are grounded to form a standard operational topology. V1 and V2 realize the transmission and conversion of sinusoidal nonlinear signals. The overall hardware connection and parameter settings accurately map the differential operation rules of the first channel of the five-dimensional sinusoidal cyclic symmetric conservative superchaotic circuit, maintaining the conservative properties of the circuit's cyclic symmetric structure and phase volume conservation, and ensuring that the channel output signal conforms to the superchaotic dynamic evolution characteristics.

[0026] For example, in the first channel, a 25kΩ first resistor R1 is connected to the state variable y, a 16.67kΩ second resistor R2 is connected to the first controlled voltage source V1 connected to the state variable z, a 16.67kΩ third resistor R3 is connected to the second controlled voltage source V2 connected to the state variable -u, and a 25kΩ fourth resistor R4 is connected to the state variable w. These four signals are input to the inverting input of the first operational amplifier U1A. A 1kΩ fifth resistor R5 forms the feedback loop for U1A to perform addition. The output signal of U1A is sent to the second operational amplifier via a 10kΩ seventh resistor R7. The inverting input of operational amplifier U2A, along with the 10nF first capacitor C1, forms an integration module with U2A to perform signal integration processing. The integrated signal is then input to the inverting input of the third operational amplifier U3A via the 10kΩ eighth resistor R8. The 10kΩ sixth resistor R6 forms a feedback loop for U3A to complete signal inversion. The non-inverting inputs of U1A, U2A, and U3A are all grounded. Relying on the ±12V power supply of the TL082CM operational amplifier and the ABM_VOLTAGE controlled voltage source, continuous hardware operations of addition, integration, and inversion are performed sequentially, ultimately outputting the state variable -x.

[0027] Specifically, the second channel also includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third controlled voltage source V3, a fourth controlled voltage source V4, and a second capacitor C2. The inverting input terminal of U4A is connected in parallel to one end of R9, R10, R11, and R12; The other end of R9 is connected to z, the other end of R10 is connected to the positive terminal of V3, the negative terminal of V3 is connected to u, the other end of R11 is connected to the positive terminal of V4, the negative terminal of V4 is connected to -w, and the other end of R12 is connected to -x. The non-inverting input of U4A is grounded, the output of U4A is connected to the inverting input of U4A through R13, and the output of U4A is also connected to the inverting input of U5A through R15. The non-inverting input of U5A is grounded, the output of U5A is connected to the inverting input of U5A through C2, and the output of U5A is connected to the inverting input of U6A through R16. The non-inverting input of U6A is grounded, and the output of U6A is connected to the inverting input of U6A through R14.

[0028] Understandably, the second channel is configured with resistors nine through sixteen, the third controlled voltage source V3, the fourth controlled voltage source V4, and the second capacitor C2. Electrical connections are established for the fourth operational amplifier U4A, the fifth operational amplifier U5A, and the sixth operational amplifier U6A. Resistors nine through twelfth connect the state variable z, the output u of V3, the output -w of V4, and the state variable -x to the inverting input of U4A to achieve multi-channel signal superposition. The thirteenth resistor forms the feedback loop of U4A to complete the inverting addition operation. The output signal of U4A is transmitted to the inverting input of U5A via the fifteenth resistor. Two capacitors C2 and U5A form an inverting integrator circuit to achieve time-domain integration. The integrated signal is sent to the inverting input of U6A through the sixteenth resistor. The fourteenth resistor forms a feedback loop for U6A to complete the signal inversion transformation. The non-inverting terminals of each operational amplifier are grounded to form a standard operational topology. V3 and V4 realize the transmission and conversion of sinusoidal nonlinear signals. The overall hardware connection and parameter settings accurately map the differential operation rules of the second channel of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, maintaining the conservative properties of the circuit's cyclic symmetric structure and phase volume conservation, and ensuring that the channel output signal conforms to the hyperchaotic dynamic evolution characteristics.

[0029] For example, in the second channel, the 25kΩ ninth resistor R9 is connected to state variable z, the 16.67kΩ tenth resistor R10 is connected to the third controlled voltage source V3 connected to state variable u, the 16.67kΩ eleventh resistor R11 is connected to the fourth controlled voltage source V4 connected to state variable -w, and the 25kΩ twelfth resistor R12 is connected to state variable -x. All four signals are input to the inverting input of the fourth operational amplifier U4A. The 1kΩ thirteenth resistor R13 forms the feedback loop of U4A to complete the addition operation. The output signal of U4A is sent to the fifteenth resistor R15 via the 10kΩ resistor. The fifth operational amplifier U5A's inverting input terminal, along with the 10nF second capacitor C2 and U5A, forms an integrating module to perform signal integration processing. The integrated signal is then input to the sixth operational amplifier U6A's inverting input terminal via the 10kΩ sixteenth resistor R16. The 10kΩ fourteenth resistor R14 forms the U6A feedback loop to complete signal inversion. The non-inverting inputs of U4A, U5A, and U6A are all grounded. Relying on the ±12V power supply of the TL082CM operational amplifier and the ABM_VOLTAGE controlled voltage source, continuous hardware operations of addition, integration, and inversion are performed sequentially, ultimately outputting the state variable -y.

[0030] Specifically, the third channel also includes: the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the twenty-fourth resistor R24, the fifth controlled voltage source V5, the sixth controlled voltage source V6, and the third capacitor C3. The inverting input terminal of U7A is connected in parallel to one end of R17, R18, R19, and R20; The other end of R17 is connected to u, the other end of R18 is connected to the positive terminal of V5, the negative terminal of V5 is connected to w, the other end of R19 is connected to the positive terminal of V6, the negative terminal of V6 is connected to -x, and the other end of R20 is connected to -y. The non-inverting input of U7A is grounded, the output of U7A is connected to the inverting input of U7A through R21, and the output of U7A is also connected to the inverting input of U8A through R23. The non-inverting input of U8A is grounded, the output of U8A is connected to the inverting input of U8A through C3, and the output of U8A is connected to the inverting input of U9A through R24. The non-inverting input of U9A is grounded, and the output of U9A is connected to the inverting input of U9A through R22.

[0031] Understandably, the third channel is configured with resistors seventeen to twenty-four, the fifth controlled voltage source V5, the sixth controlled voltage source V6, and the third capacitor C3. Electrical connections are then established for the seventh operational amplifier U7A, the eighth operational amplifier U8A, and the ninth operational amplifier U9A. Resistors seventeen to twenty connect the state variable u, the output w of V5, the output -x of V6, and the state variable -y to the inverting input of U7A to achieve multi-channel signal superposition. The twenty-first resistor forms the feedback loop for U7A to complete the inverting addition operation. The output signal of U7A is transmitted to the inverting input of U8A via the twenty-third resistor. The third capacitor C3 and U8A form an inverting integrator circuit to achieve time-domain integration. The integrated signal is sent to the inverting input of U9A through the twenty-fourth resistor. The twenty-second resistor forms a feedback loop for U9A to complete the signal inversion transformation. The non-inverting terminals of each operational amplifier are grounded to form a standard operational topology. V5 and V6 realize the transmission and conversion of sinusoidal nonlinear signals. The overall hardware connection and parameter settings accurately map the differential operation rules of the third channel of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, maintaining the conservative properties of the circuit's cyclic symmetric structure and phase volume conservation, and ensuring that the channel output signal conforms to the hyperchaotic dynamic evolution characteristics.

[0032] For example, in the third channel, the 25kΩ seventeenth resistor R17 is connected to the state variable u, the 16.67kΩ eighteenth resistor R18 is connected to the fifth controlled voltage source V5 connected to the state variable w, the 16.67kΩ nineteenth resistor R19 is connected to the sixth controlled voltage source V6 connected to the state variable -x, and the 25kΩ twentieth resistor R20 is connected to the state variable -y. All four signals are input to the inverting input of the seventh operational amplifier U7A. The 1kΩ twenty-first resistor R21 forms the feedback loop of U7A to complete the addition operation. The output signal of U7A passes through the 10kΩ twenty-third resistor R23. The signal is fed into the inverting input of the eighth operational amplifier U8A. The 10nF third capacitor C3 and U8A form an integration module to perform signal integration processing. The integrated signal is then input to the inverting input of the ninth operational amplifier U9A via the 10kΩ twenty-fourth resistor R24. The 10kΩ twenty-second resistor R22 forms a feedback loop for U9A to complete signal inversion. The non-inverting inputs of U7A, U8A, and U9A are all grounded. Relying on the ±12V power supply of the TL082CM operational amplifier and the ABM_VOLTAGE controlled voltage source, the continuous hardware operations of addition, integration, and inversion are completed in sequence, and the final output state variable -z is output.

[0033] Specifically, the fourth channel also includes: the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the thirtieth resistor R30, the thirty-first resistor R31, the thirty-second resistor R32, the seventh controlled voltage source V7, the eighth controlled voltage source V8, and the fourth capacitor C4. The inverting input terminal of U10A is connected in parallel to one end of R25, R26, R27, and R28; The other end of R25 is connected to w, the other end of R26 is connected to the positive terminal of V7, the negative terminal of V7 is connected to x, the other end of R27 is connected to the positive terminal of V8, the negative terminal of V8 is connected to -y, and the other end of R28 is connected to -z. The non-inverting input of U10A is grounded, the output of U10A is connected to the inverting input of U10A through R29, and the output of U10A is also connected to the inverting input of U11A through R31. The non-inverting input of U11A is grounded, the output of U11A is connected to the inverting input of U11A through C4, and the output of U11A is connected to the inverting input of U12A through R32. The non-inverting input of U12A is grounded, and the output of U12A is connected to the inverting input of U12A through R30.

[0034] Understandably, the fourth channel is configured with resistors 25 to 32, the seventh controlled voltage source V7, the eighth controlled voltage source V8, and the fourth capacitor C4. Electrical connections are then established for operational amplifiers U10A, U11A, and U12A. Resistors 25 to 28 connect the state variable w, the x output of V7, the -y output of V8, and the state variable -z to the inverting input of U10A to achieve multi-channel signal superposition. Resistor 29 forms the feedback loop for U10A to complete the inverting addition operation. The output signal of U10A is transmitted to the inverting input of U11A via resistor 31. The fourth capacitor... Capacitor C4 and U11A form an inverting integrator circuit to achieve time-domain integration. The integrated signal is sent to the inverting input of U12A through the 32nd resistor. The 30th resistor forms a feedback loop for U12A to complete the signal inversion transformation. The non-inverting terminals of each operational amplifier are grounded to form a standard operational topology. The controlled voltage source realizes the transmission and conversion of sinusoidal nonlinear signals. The overall hardware connection and parameter settings accurately map the differential operation rules of the fourth channel of the five-dimensional sinusoidal cyclic symmetric conservative superchaotic circuit, maintaining the conservative properties of the circuit's cyclic symmetric structure and phase volume conservation, and ensuring that the channel output signal conforms to the superchaotic dynamic evolution characteristics.

[0035] For example, in the fourth channel, the 25kΩ 25th resistor R25 is connected to the state variable w, the 16.67kΩ 26th resistor R26 is connected to the seventh controlled voltage source V7 connected to the state variable x, the 16.67kΩ 27th resistor R27 is connected to the eighth controlled voltage source V8 connected to the state variable -y, and the 25kΩ 28th resistor R28 is connected to the state variable -z. All four signals are input to the inverting input of the tenth operational amplifier U10A. The 1kΩ 29th resistor R29 forms the feedback loop of U10A to complete the addition operation. The output signal of U10A is sent to the 10kΩ 31st resistor R31. The signal is fed into the inverting input of the eleventh operational amplifier U11A. The fourth capacitor C4 (10nF) and U11A form an integrating module to perform signal integration processing. The integrated signal is then fed into the inverting input of the twelfth operational amplifier U12A via the thirty-second resistor R32 (10kΩ). The thirtieth resistor R30 (10kΩ) forms a feedback loop for U12A to complete signal inversion. The non-inverting inputs of U10A, U11A, and U12A are all grounded. Relying on the ±12V power supply of the TL082CM operational amplifier and the ABM_VOLTAGE controlled voltage source, the continuous hardware operations of addition, integration, and inversion are completed in sequence, and the final output state variable -u is output.

[0036] Specifically, the fifth channel also includes: the thirty-third resistor R33, the thirty-fourth resistor R34, the thirty-fifth resistor R35, the thirty-sixth resistor R36, the thirty-seventh resistor R37, the thirty-eighth resistor R38, the thirty-ninth resistor R39, the fortieth resistor R40, the ninth controlled voltage source V9, the tenth controlled voltage source V10, and the fifth capacitor C5. The inverting input terminal of U13A is connected in parallel to one end of R33, R34, R35, and R36; The other end of R33 is connected to x, the other end of R34 is connected to the positive terminal of V9, the negative terminal of V9 is connected to y, the other end of R35 is connected to the positive terminal of V10, the negative terminal of V10 is connected to -z, and the other end of R36 is connected to -u. The non-inverting input of U13A is grounded, the output of U13A is connected to the inverting input of U13A through R37, and the output of U13A is also connected to the inverting input of U14A through R39. The non-inverting input of U14A is grounded, the output of U14A is connected to the inverting input of U14A through C5, and the output of U14A is connected to the inverting input of U15A through R40. The non-inverting input of U15A is grounded, and the output of U15A is connected to the inverting input of U15A through R38.

[0037] Understandably, the fifth channel is configured with resistors 33 to 40, the ninth controlled voltage source V9, the tenth controlled voltage source V10, and the fifth capacitor C5. Electrical connections are then established for the thirteenth operational amplifier U13A, the fourteenth operational amplifier U14A, and the fifteenth operational amplifier U15A. Resistors 33 to 36 connect the state variable x, the output y of V9, the output -z of V10, and the state variable -u to the inverting input of U13A to achieve multi-channel signal superposition. Resistor 37 forms the feedback loop for U13A to complete the inverting addition operation. The output signal of U13A is transmitted to U14A via resistor 39. At the inverting input, the fifth capacitor C5 and U14A form an inverting integrator circuit to achieve time-domain integration. The integrated signal is sent to the inverting input of U15A through the fortieth resistor. The thirty-eighth resistor forms a feedback loop for U15A to complete the signal inversion transformation. The non-inverting terminals of each operational amplifier are grounded to form a standard operational topology. V9 and V10 realize the transmission and conversion of sinusoidal nonlinear signals. The overall hardware connection and parameter settings accurately map the differential operation rules of the fifth channel of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, maintain the conservative properties of the circuit's cyclic symmetric structure and phase volume conservation, and ensure that the channel output signal conforms to the hyperchaotic dynamic evolution characteristics.

[0038] For example, in the fifth channel, the 25kΩ 33rd resistor R33 is connected to state variable x, the 16.67kΩ 34th resistor R34 is connected to the 9th controlled voltage source V9 connected to state variable y, the 16.67kΩ 35th resistor R35 is connected to the 10th controlled voltage source V10 connected to state variable -z, and the 25kΩ 36th resistor R36 is connected to state variable -u. These four signals are input to the inverting input of the 13th operational amplifier U13A. The 1kΩ 37th resistor R37 forms the feedback loop for U13A to perform addition. The output signal of U13A passes through the 10kΩ 39th resistor R39. The signal is fed into the inverting input of the fourteenth operational amplifier U14A. The fifth capacitor C5 (10nF) and U14A form an integration module to perform signal integration processing. The integrated signal is then fed into the inverting input of the fifteenth operational amplifier U15A via the fortieth resistor R40 (10kΩ). The thirty-eighth resistor R38 (10kΩ) forms a feedback loop for U15A to complete signal inversion. The non-inverting inputs of U13A, U14A, and U15A are all grounded. Relying on the ±12V power supply of the TL082CM operational amplifier and the ABM_VOLTAGE controlled voltage source, the continuous hardware operations of addition, integration, and inversion are completed in sequence, and the final output state variable -w is output.

[0039] Specifically, each controlled voltage source in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses the ABM_VOLTAGE function of the Multisim software.

[0040] Understandably, the controlled voltage sources of the five channels in the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit are uniformly adopted using the ABM_VOLTAGE function of Multisim software. This controlled voltage source can accurately realize the generation of sinusoidal nonlinear signals and the mapping and transformation of state variables. It can strictly match the sinusoidal nonlinear operation rules in the circuit mathematical model, ensure the consistency and accuracy of nonlinear signal processing of each channel, maintain the conservative characteristics of the circuit's cyclic symmetric structure and phase volume conservation, and ensure the stable reproduction of hyperchaotic dynamic behavior.

[0041] Specifically, each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses a TL082CM.

[0042] It is understandable that the operational amplifiers for all five channels are of the TL082CM model. This operational amplifier has electrical characteristics that can adapt to linear operation of analog signals. Using the same component model can keep the electrical parameters such as gain and response of signal processing of each channel consistent. This fits the symmetrical topology of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit, stably completes the core operations of inverted addition, inverted integration and signal inversion, and ensures the consistency and stability of the overall dynamic behavior of the circuit.

[0043] Specifically, the power supply voltage of each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel is set to ±12V.

[0044] Understandably, setting the supply voltage of the TL082CM operational amplifiers in all five channels to ±12V provides the operational amplifiers with a suitable linear operating range, meets the signal swing requirements for inverting addition, inverting integration, and signal inversion operations, matches the signal processing level characteristics of the resistors, capacitors, and controlled voltage sources in each channel, maintains the electrical parameter balance under the cyclic symmetric topology of the circuit, and ensures the stable output of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit dynamics.

[0045] Reference Figure 2-4 As shown, in the phase diagram generated by the circuit in this embodiment, the circuit trajectory never converges to any fixed point, there is no attractor, and the generated hyperchaotic signal exhibits irregular fluctuations, which conforms to the characteristics of a typical conservative chaotic circuit.

[0046] In the above embodiments, a five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit can output a five-dimensional chaotic signal. Compared with traditional four-dimensional and lower-dimensional chaotic circuits, it breaks through the bottleneck of limited dynamic behavior space of low-dimensional chaotic circuits. The output signal has superior chaotic characteristics, richer dynamic behavior, and is more unpredictable, providing stable and reliable hardware signal support for high-security encryption scenarios. The circuit adopts a cyclic symmetric hardware architecture and integrates a sinusoidal nonlinear processing module. Relying on the symmetry of the circuit structure and the nonlinearity and periodicity of the sine function, it can generate multiple independent chaotic signal tracks, enriching the dynamic characteristics of the hardware output signal, improving the hardware implementation security of secure communication, and adapting to the practical application needs of various encryption scenarios.

[0047] By adopting a five-channel cyclic symmetrical hardware architecture, each channel accurately reproduces the corresponding mathematical operation logic through a modular circuit structure of addition, integration, and inversion. The circuit structure is regular and symmetrical, with high parameter matching degree, and stable and reliable operation. It can stably output highly complex conservative hyperchaotic signals, and has both excellent dynamic characteristics and hardware implementation feasibility. It can be directly adapted to engineering application scenarios such as high-security encrypted communication. At the same time, it provides a simple and efficient circuit implementation scheme for the hardware implementation and experimental verification of conservative hyperchaotic circuits.

[0048] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program goods. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program goods embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0049] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program goods according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0050] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0051] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A five-dimensional sinusoidal cyclically symmetric conservative hyperchaotic circuit, characterized in that, include: The first channel includes a first addition function module, a first integration function module, and a first inversion function module. The first addition function module, the first integration function module, and the first inversion function module are respectively implemented by a first operational amplifier U1A, a second operational amplifier U2A, and a third operational amplifier U3A. The second channel includes a second addition function module, a second integration function module, and a second inversion function module. The second addition function module, the second integration function module, and the second inversion function module are respectively implemented by the fourth operational amplifier U4A, the fifth operational amplifier U5A, and the sixth operational amplifier U6A. The third channel includes a third addition function module, a third integration function module, and a third inversion function module. The third addition function module, the third integration function module, and the third inversion function module are respectively implemented by the seventh operational amplifier U7A, the eighth operational amplifier U8A, and the ninth operational amplifier U9A. The fourth channel includes a fourth addition function module, a fourth integration function module, and a fourth inversion function module. The fourth addition function module, the fourth integration function module, and the fourth inversion function module are respectively implemented by the tenth operational amplifier U10A, the eleventh operational amplifier U11A, and the twelfth operational amplifier U12A. The fifth channel includes a fifth addition function module, a fifth integration function module, and a fifth inversion function module. The fifth addition function module, the fifth integration function module, and the fifth inversion function module are respectively implemented by the thirteenth operational amplifier U13A, the fourteenth operational amplifier U14A, and the fifteenth operational amplifier U15A.

2. A five-dimensional sinusoidally cyclically symmetric conservative hyperchaotic circuit according to claim 1, characterized in that, The mathematical model of the five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit is as follows: wherein are state variables of the first channel, the second channel, the third channel, the fourth channel and the fifth channel, respectively, are first derivatives of , respectively.

3. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 2, characterized in that, The first path further includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first controlled voltage source V1, a second controlled voltage source V2, and a first capacitor C1; The inverting input terminal of U1A is connected in parallel to one end of R1, R2, R3, and R4; The other end of R1 is connected to y, the other end of R2 is connected to the positive terminal of V1, the negative terminal of V1 is connected to z, the other end of R3 is connected to the positive terminal of V2, the negative terminal of V2 is connected to -u, and the other end of R4 is connected to -w. The non-inverting input of U1A is grounded, the output of U1A is connected to the inverting input of U1A through R5, and the output of U1A is also connected to the inverting input of U2A through R7. The non-inverting input of U2A is grounded, the output of U2A is connected to the inverting input of U2A through C1, and the output of U2A is connected to the inverting input of U3A through R8. The non-inverting input of U3A is grounded, and the output of U3A is connected to the inverting input of U3A through R6.

4. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 3, characterized in that, The second channel also includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a third controlled voltage source V3, a fourth controlled voltage source V4, and a second capacitor C2. The inverting input terminal of U4A is connected in parallel to one end of R9, R10, R11, and R12; The other end of R9 is connected to z, the other end of R10 is connected to the positive terminal of V3, the negative terminal of V3 is connected to u, the other end of R11 is connected to the positive terminal of V4, the negative terminal of V4 is connected to -w, and the other end of R12 is connected to -x. The non-inverting input of U4A is grounded, the output of U4A is connected to the inverting input of U4A through R13, and the output of U4A is also connected to the inverting input of U5A through R15. The non-inverting input of U5A is grounded, the output of U5A is connected to the inverting input of U5A through C2, and the output of U5A is connected to the inverting input of U6A through R16. The non-inverting input of U6A is grounded, and the output of U6A is connected to the inverting input of U6A through R14.

5. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 4, characterized in that, The third channel also includes: the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the twenty-fourth resistor R24, the fifth controlled voltage source V5, the sixth controlled voltage source V6, and the third capacitor C3. The inverting input terminal of U7A is connected in parallel to one end of R17, R18, R19, and R20; The other end of R17 is connected to u, the other end of R18 is connected to the positive terminal of V5, the negative terminal of V5 is connected to w, the other end of R19 is connected to the positive terminal of V6, the negative terminal of V6 is connected to -x, and the other end of R20 is connected to -y. The non-inverting input of U7A is grounded, the output of U7A is connected to the inverting input of U7A through R21, and the output of U7A is also connected to the inverting input of U8A through R23. The non-inverting input of U8A is grounded, the output of U8A is connected to the inverting input of U8A through C3, and the output of U8A is connected to the inverting input of U9A through R24. The non-inverting input of U9A is grounded, and the output of U9A is connected to the inverting input of U9A through R22.

6. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 5, characterized in that, The fourth channel also includes: the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the thirtieth resistor R30, the thirty-first resistor R31, the thirty-second resistor R32, the seventh controlled voltage source V7, the eighth controlled voltage source V8, and the fourth capacitor C4. The inverting input terminal of U10A is connected in parallel to one end of R25, R26, R27, and R28; The other end of R25 is connected to w, the other end of R26 is connected to the positive terminal of V7, the negative terminal of V7 is connected to x, the other end of R27 is connected to the positive terminal of V8, the negative terminal of V8 is connected to -y, and the other end of R28 is connected to -z. The non-inverting input of U10A is grounded, the output of U10A is connected to the inverting input of U10A through R29, and the output of U10A is also connected to the inverting input of U11A through R31. The non-inverting input of U11A is grounded, the output of U11A is connected to the inverting input of U11A through C4, and the output of U11A is connected to the inverting input of U12A through R32. The non-inverting input of U12A is grounded, and the output of U12A is connected to the inverting input of U12A through R30.

7. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 6, characterized in that, The fifth channel also includes: the thirty-third resistor R33, the thirty-fourth resistor R34, the thirty-fifth resistor R35, the thirty-sixth resistor R36, the thirty-seventh resistor R37, the thirty-eighth resistor R38, the thirty-ninth resistor R39, the fortieth resistor R40, the ninth controlled voltage source V9, the tenth controlled voltage source V10, and the fifth capacitor C5. The inverting input terminal of U13A is connected in parallel to one end of R33, R34, R35, and R36; The other end of R33 is connected to x, the other end of R34 is connected to the positive terminal of V9, the negative terminal of V9 is connected to y, the other end of R35 is connected to the positive terminal of V10, the negative terminal of V10 is connected to -z, and the other end of R36 is connected to -u. The non-inverting input of U13A is grounded, the output of U13A is connected to the inverting input of U13A through R37, and the output of U13A is also connected to the inverting input of U14A through R39. The non-inverting input of U14A is grounded, the output of U14A is connected to the inverting input of U14A through C5, and the output of U14A is connected to the inverting input of U15A through R40. The non-inverting input of U15A is grounded, and the output of U15A is connected to the inverting input of U15A through R38.

8. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 6, characterized in that, Each controlled voltage source in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses the ABM_VOLTAGE function of the Multisim software.

9. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 8, characterized in that, Each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel uses a TL082CM.

10. A five-dimensional sinusoidal cyclic symmetric conservative hyperchaotic circuit according to claim 9, characterized in that, The power supply voltage of each operational amplifier in the first channel, the second channel, the third channel, the fourth channel, and the fifth channel is set to ±12V.

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