A peak-to-average power ratio coordination control method and system of a digital pre-distortion system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-16
- Publication Date
- 2026-08-11
AI Technical Summary
尽管CFR与DPD的级联结构已经被广泛使用，但现有方案大多将CFR参数和DPD参数分开设计，缺乏面向功率放大器输入端峰均功率比约束的协调控制机制
Smart Images
Figure CN122554292A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of linearization technology for wireless communication transmitters, and more specifically to a method and system for coordinated control of peak-to-average power ratio in a digital predistortion system. Background Technology
[0002] Orthogonal Frequency Division Multiplexing (OFDM) signals typically have a high peak-to-average power ratio (PAPR) due to the coherent superposition of multiple subcarriers. When a high PPR signal enters the RF transmit link, it can easily cause the power amplifier to operate in the nonlinear region, leading to in-band distortion, spectral regeneration, and adjacent channel interference. To prevent the power amplifier from entering the deeply compressed region, it is usually necessary to increase the input backoff, but this reduces transmit efficiency and increases the complexity of system design.
[0003] Digital predistortion (DPD) is one of the main methods for compensating for nonlinear distortion in power amplifiers. It linearizes the power amplifier output by applying inverse characteristic compensation to the input signal before the amplifier. However, when offsetting the compression characteristics of the power amplifier, DPD often expands large signal samples, causing peak regeneration in the predistorted signal. This results in a higher peak-to-average power ratio (PAPR) at the power amplifier input than the original baseband signal. When peak regeneration is too pronounced, it can lead to clipping in the digital-to-analog converter (DAC), deep saturation of the power amplifier, and instability in the linearization algorithm.
[0004] To address this, existing technologies typically incorporate a peak-to-average power ratio (PAPR) reduction module (CFR) before the power amplifier (DPD). Peak-cancelling CFRs, by injecting band-limited cancellation pulses into peak samples exceeding a threshold, can effectively suppress peaks and control spectral leakage with relatively low complexity. Although cascaded CFR and DPD structures are widely used, most existing solutions design CFR and DPD parameters separately, lacking a coordinated control mechanism for PAPR constraints at the power amplifier input. In particular, the forgetting factor in recursive least squares algorithms is usually selected solely based on tracking performance, without considering its impact on signal peak regeneration after pre-distortion.
[0005] Therefore, how to meet the peak-to-average power ratio constraint at the power amplifier input while maintaining good linearization performance without changing the overall transmitter architecture, by coordinating the PC-CFR parameters and RLS forgetting factor, has become an urgent technical problem to be solved. Summary of the Invention
[0006] In order to overcome the problems existing in the prior art, the purpose of this invention is to provide a method and system for coordinated control of peak-to-average power ratio in a digital predistortion system. By reserving peak margin for DPD through the front-end PC-CFR, and by adjusting the back-end RLS forgetting factor to suppress peak regeneration caused by DPD, a better linearization performance can be achieved while meeting hardware peak constraints.
[0007] To achieve the above objectives, the present invention adopts the following technical solution.
[0008] This invention provides a method for coordinated control of peak-to-average power ratio (PAPR) in a digital predistortion system, comprising the following steps: First, obtaining the allowable PAPR constraint at the power amplifier input and determining the PC-CFR target PAPR accordingly; then, performing PC-CFR processing on the baseband signal to be transmitted through peak detection, cancellation pulse generation, and delay-aligned subtraction; next, inputting the peak-clipping signal into a digital predistortion module based on an indirect learning architecture, and identifying the post-distortor coefficients using a memory polynomial model and a recursive least squares algorithm; then, suppressing peak regeneration of the predistorted signal by adjusting the forgetting factor of the recursive least squares algorithm; finally, under the premise of satisfying the PAPR constraint at the power amplifier input, selecting the optimal forgetting factor based on the normalized mean square error and adjacent channel power ratio to obtain the coordinated parameter configuration.
[0009] Furthermore, the PC-CFR processing is implemented in parallel using a main signal delay path, a peak detection and scaling path, and a pulse generation path. The peak detection and scaling path is used to extract the amplitude and phase information of the peak sample points, and the pulse generation path is used to generate a band-limited finite-length impulse response (FIR) cancellation pulse and align it with the delayed main signal to complete the subtraction process.
[0010] Furthermore, the forgetting factor in the recursive least squares algorithm is used to control the weighting of historical observation samples. When the forgetting factor increases, the post-distortion coefficient changes more smoothly, and the regeneration of the signal peak after pre-distortion is weakened; when the forgetting factor decreases, the fluctuation of the post-distortion coefficient increases, and the regeneration of the signal peak after pre-distortion is intensified.
[0011] Furthermore, the present invention employs a two-stage coordination process: first, the operating point that allows the system to enter the feasible peak range is selected through PC-CFR; then, within the feasible peak range, a forgetting factor is selected that optimizes the normalized mean square error and the adjacent channel power ratio.
[0012] Compared with the prior art, the advantages and positive effects of the present invention are as follows: 1. This invention constructs a two-stage peak-to-average power ratio (PAPR) coordination framework through pre-stage PC-CFR and post-stage forgetting factor adjustment, which can systematically suppress peak regeneration caused by DPD and solve the peak constraint mismatch problem caused by the separate design of CFR and DPD parameters in the prior art; 2. The PC-CFR processing method used in this invention reduces the signal peak value through band-limited cancellation pulses. Compared with the direct hard clipping scheme, it can reduce the peak-to-average power ratio while mitigating additional spectral distortion. In this embodiment, under the conditions of a 10MHz LTE signal, 4QAM modulation, an oversampling factor of 12, and no DPD, the CFR processing reduces the signal peak-to-average power ratio from 10.05dB to 9.00dB, while the adjacent channel power ratio change is less than 0.4dB. 3. This invention achieves controllable constraints on the peak-to-average power ratio (PAPR) at the power amplifier input without altering the overall transmitter structure. In this embodiment, with a 10MHz LTE signal, 4QAM modulation, an oversampling factor of 12, and a fixed forgetting factor of 0.99, without CFR, DPD processing can increase the PAPR at the power amplifier input from 10.05dB to 12.67dB; after adopting the coordinated control scheme of this invention, the PAPR at the power amplifier input can be controlled at 10.19dB, satisfying the 11dB peak value constraint. 4. This invention utilizes the influence of the forgetting factor on peak regeneration after pre-distortion to further optimize linearization performance within a feasible range that satisfies peak constraints. In this embodiment, under the conditions of a 10 MHz LTE signal, 4QAM modulation, an oversampling factor of 12, and no CFR, after adjusting the forgetting factor from 0.99 to 0.999, the normalized mean square error improved from -41.31 dB to -45.91 dB, and the adjacent channel power ratio improved from -53.21 / -50.15 dBc to -56.79 / -55.36 dBc. Attached Figure Description
[0013] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings: Figure 1 This is a block diagram of the overall structure of the peak-to-average power ratio coordinated control of the digital predistortion system according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the hardware processing structure of the PC-CFR module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the time-domain effect of PC-CFR processing in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the relationship between the forgetting factor and the peak-to-average power ratio at the input of the power amplifier in an embodiment of the present invention; Figure 5 This is a schematic diagram of the hardware-in-the-loop test platform structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram showing the statistical and spectral results before and after CFR processing when DPD is not used in an embodiment of the present invention; Figure 7 This is a schematic diagram showing the peak-to-average power ratio at the input of the power amplifier and the output spectrum results when using DPD in an embodiment of the present invention, with and without CFR. Figure 8 This is a schematic diagram of the statistical distribution and power spectrum results of different forgetting factors when CFR is not used in an embodiment of the present invention; Figure 9 This is a schematic diagram of the statistical distribution and power spectrum results corresponding to different forgetting factors when using CFR in an embodiment of the present invention. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.
[0015] Example 1: System Overall Structure
[0016] like Figure 1 As shown, the system in this embodiment includes a signal input module, a PC-CFR processing module, a digital predistortion module, a power amplifier, a performance evaluation module, and a parameter coordination module. The signal input module generates the complex baseband signal to be transmitted; the PC-CFR processing module performs peak cancellation on large peak samples in the complex baseband signal; the digital predistortion module performs predistortion compensation on the signal after PC-CFR processing; the power amplifier amplifies the predistorted signal; the performance evaluation module calculates the peak-to-average power ratio, normalized mean square error, and adjacent channel power ratio at the power amplifier input; and the parameter coordination module adjusts the PC-CFR parameters and the RLS forgetting factor.
[0017] In this embodiment, the core of coordinated control is: first, using PC-CFR to reduce the peak-to-average power ratio of the DPD input signal to a preset target, thereby reserving margin for peak regeneration brought by the subsequent DPD; then, by adjusting the forgetting factor of the recursive least squares algorithm, reducing the peak amplification effect caused by the rapid fluctuation of the predistorter coefficient, so that the peak-to-average power ratio of the power amplifier input falls into the allowable range, and obtains the best linearization performance within this feasible range.
[0018] Example 2: PC-CFR Module Implementation
[0019] like Figure 2 As shown, the PC-CFR module includes three parallel data paths: the main signal delay path, the peak detection and scaling path, and the pulse generation path.
[0020] The main signal delay path is used to buffer input samples to compensate for processing delays caused by peak detection and pulse synthesis. The peak detection and scaling path is used to extract the amplitude and phase of the input signal and determine whether the sample amplitude exceeds a preset threshold. In hardware implementation, CORDIC units can be used to extract the amplitude and phase information of the samples in real time.
[0021] When the amplitude of a local peak sample exceeds a preset threshold, the pulse generation path generates a corresponding scaling factor based on the amount by which the peak exceeds the threshold, and uses a band-limited FIR pulse to generate a phase-aligned cancellation pulse. The cancellation pulse is subtracted from the delayed main signal at the corresponding time position, thereby reducing the instantaneous amplitude of the peak sample. Because the cancellation pulse is limited within the signal bandwidth, the spectral regeneration caused by the peak clipping process is controlled.
[0022] In this embodiment, the key parameters of PC-CFR include the cancellation pulse length. Pulse design method, search window length and maximum number of iterations Cancellation pulse length The spectral shaping capability of the band-limited pulse is determined; pulse design methods can employ least-squares FIR synthesis or window truncation; the search window length... Used to avoid repeatedly injecting cancellation pulses at the same physical peak; maximum number of iterations. Used to suppress peak regeneration during peak clipping.
[0023] Based on engineering analysis, the recommended parameters in this embodiment are shown in Table 1.
[0024]
[0025] Table 1
[0026] like Figure 3 As shown, after PC-CFR processing, the signal envelope is effectively constrained near a preset threshold, with only the local waveform near the peak being altered, while the remaining waveform remains essentially unchanged. This characteristic distinguishes it from direct hard clipping schemes and provides better spectral performance.
[0027] Example 3: DPD Implementation Based on RLS
[0028] In this embodiment, the digital predistortion module adopts an indirect learning architecture. First, a postdistorter model is constructed based on the power amplifier output signal. Then, the identified postdistorter coefficients are copied into the predistorter. To balance modeling capability and implementation complexity, the postdistorter uses a memory polynomial model, satisfying: in, This indicates the output signal of the power amplifier. Represents the nonlinear order. Indicates the depth of memory. Represents the model coefficients.
[0029] The post-distorter coefficients are identified using a recursive least squares algorithm. The objective function of the recursive least squares algorithm is:
[0030] in, Forgetting factor, To estimate the error, the gain vector, estimation error, coefficient vector, and inverse correlation matrix can be recursively updated using the matrix inversion lemma, thus avoiding the large-scale matrix inversion operations in the batch least squares algorithm.
[0031] The forgetting factor determines the weight of historical observation samples, which in turn determines the smoothness of the post-distortion coefficient update. When the forgetting factor is small, the coefficient update is more sensitive to the most recent samples, which is beneficial for fast tracking, but it will lead to increased coefficient fluctuations and amplify the instantaneous peak of the signal after pre-distortion through the nonlinear basis function. When the forgetting factor is large, the coefficient changes are smoother and the peak regeneration of the signal after pre-distortion is weakened, but if it is too large, it will weaken the ability to track time-varying characteristics.
[0032] like Figure 4 As shown, the peak-to-average power ratio (PAPR) at the power amplifier input increases as the forgetting factor decreases. Within the test range corresponding to this embodiment, the PAPR of the pre-distorted signal may even rise to an unacceptable level when the forgetting factor is low, indicating that the selection of the forgetting factor not only affects the linearization performance but also directly affects whether the PAPR constraint can be met.
[0033] Example 4: Implementation of Coordination Control Process
[0034] This embodiment adopts a two-stage coordination control process.
[0035] In the first stage, the PC-CFR operating point is selected based on hardware constraints. Specifically, the upper limit of the peak-to-average power ratio (PAPR) at the power amplifier input is determined based on the allowable instantaneous power constraints at the input of the digital-to-analog converter (DAC) and the power amplifier. For example, in this embodiment, this constraint is 11 dB. Then, the target PAPR of the PC-CFR is set so that the PAPR of the signal input to the power amplifier after DPD processing still meets the constraint and reserves a certain margin. In this embodiment, the target PAPR of the PC-CFR is preferably set to 9 dB.
[0036] In the second stage, a forgetting factor is selected within the feasible peak range. Specifically, after PC-CFR processing, the pre-distorted signals corresponding to different forgetting factors are evaluated, and the peak-to-average power ratio (PAPR), normalized mean square error (MSE), and adjacent channel power ratio (ADPR) at the power amplifier input are monitored. When the forgetting factor is too small, although some tracking capability may be maintained, the PAPR at the power amplifier input may exceed the 11 dB constraint; when the forgetting factor is too large, the PAPR decreases, but the linearization performance deteriorates. Therefore, within the feasible range that satisfies the PAPR constraint, a forgetting factor that minimizes the MSE and meets the ADPR performance requirements is selected.
[0037] The engineering configuration in this embodiment is as follows: cancellation pulse length Take 512 taps, search window A total of 32 samples were selected, the maximum number of iterations Imax was set to 3, and the forgetting factor was preferably set to 0.999. This configuration was verified by the experimental platform of this embodiment.
[0038] Example 5: Hardware-in-the-Loop Experiment Example
[0039] like Figure 5 As shown, this embodiment is verified on a transmitter linearization hardware-in-the-loop platform. The platform includes baseband signal generation, PC-CFR and DPD baseband processing, an RF transceiver chip, a 50 W power amplifier, a feedback acquisition link, and spectrum measurement equipment. The test signal is a 10 MHz LTE signal with 4QAM modulation, an oversampling factor of 12, a sampling rate of 122.88 Msps, and an original peak-to-average power ratio of 10.05 dB. The maximum output power of the power amplifier is 47 dBm.
[0040] The effect of CFR alone was verified without using DPD. Experimental results are as follows: Figure 6 As shown, after adopting PC-CFR, the peak-to-average power ratio (PAPR) decreased from 10.05 dB to 9.00 dB; the normalized mean square error (MSE) of the power amplifier output changed from -26.60 dB to -25.98 dB; and the adjacent channel power ratio changed from -36.24 / -34.40 dBc to -35.90 / -34.23 dBc. These results demonstrate that PC-CFR significantly reduces PAPR while introducing only limited additional distortion, and the change in adjacent channel performance is less than 0.4 dB.
[0041] With DPD and a fixed forgetting factor of 0.99, the effect of CFR on the peak-to-average power ratio constraint at the input of the power amplifier was verified. Experimental results are as follows: Figure 7As shown: Without CFR, the peak-to-average power ratio (PAPR) at the DPD input is 10.05 dB, while the PAPR at the power amplifier input increases to 12.67 dB, exceeding the 11 dB constraint. With CFR, the PAPR at the DPD input is limited to 9.00 dB, and the PAPR at the power amplifier input is 10.19 dB, satisfying the constraint. At this point, the normalized mean square error is -39.04 dB, and the adjacent channel power ratio is -54.35 / -52.69 dBc. This result indicates that the pre-stage CFR provides a usable margin for peak regeneration caused by the DPD.
[0042] Furthermore, the impact of different forgetting factors was evaluated in both scenarios with and without CFR.
[0043] In the absence of CFR, the experimental results are as follows: Figure 8 As shown in Table 2.
[0044]
[0045] Table 2
[0046] In scenarios with CFR, the experimental results are as follows: Figure 9 As shown in Table 3.
[0047]
[0048] Table 3
[0049] The results above show that the forgetting factor has a significant impact on both peak-to-average power ratio (PAPR) and linearization performance, but their optimal values do not coincide. In this embodiment, a forgetting factor of 0.999 achieves optimal or near-optimal NMSE and ACPR at an acceptable PAPR level, and is therefore selected as the preferred value.
[0050] In summary, this invention achieves excellent linearization performance while meeting hardware peak constraints through coordinated control of PC-CFR and RLS forgetting factor.
[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for coordinated control of peak-to-average power ratio in a digital predistortion system, characterized in that, Includes the following steps: S1. Obtain the baseband signal to be transmitted and obtain the allowable peak-to-average power ratio constraint at the input of the power amplifier; determine the PC-CFR processing target based on the allowable peak-to-average power ratio constraint at the input of the power amplifier and reserve the peak regeneration margin caused by digital predistortion, so that the peak-to-average power ratio of the signal input to the power amplifier after digital predistortion processing meets the constraint. S2. Perform peak-to-average power ratio (PAPR) reduction processing on the baseband signal to be transmitted, including: detecting peak samples with amplitudes exceeding a preset threshold; generating amplitude-scaled and phase-aligned band-limited cancellation pulses for the detected peak samples; subtracting the band-limited cancellation pulses from the delayed-compensated main signal after alignment to obtain the peak-shaving baseband signal. S3. Input the peak-shaving baseband signal into the digital predistortion module, construct the postdistorter model using an indirect learning architecture, and represent the inverse characteristics of the power amplifier using a memory polynomial model. S4. The recursive least squares algorithm is used to identify the coefficients of the post-distorter model, and the peak regeneration degree of the signal after digital predistortion is controlled by adjusting the forgetting factor of the recursive least squares algorithm. S5. Under the condition that the peak-to-average power ratio at the input of the power amplifier meets the constraint, select the forgetting factor with a small normalized mean square error and the adjacent channel power ratio meets the preset performance requirements from the candidate forgetting factor set, and copy the post-distortor coefficient corresponding to the forgetting factor to the pre-distortor to obtain the digital pre-distortion output signal after coordinated control.
2. The peak-to-average power ratio coordinated control method for a digital predistortion system according to claim 1, characterized in that, The process of reducing the peak-to-average power ratio of the baseband signal to be transmitted in step S2 includes: S21. Perform amplitude detection on the input complex baseband signal and use a search window to filter local peaks from samples that exceed a preset threshold. S22. Determine the scaling factor of the cancellation pulse based on the amount by which the local peak exceeds the preset threshold, and perform phase alignment of the cancellation pulse based on the instantaneous phase of the local peak. S23. The corresponding peak value is canceled by the band-limited finite-length impulse response (FIR) cancellation pulse, so that the peak value of the processed signal is limited to the target range.
3. The peak-to-average power ratio coordinated control method for a digital predistortion system according to claim 2, characterized in that, The PC-CFR processing parameters include at least the cancellation pulse length. Pulse design method, search window length and the maximum number of iterations Among them, the length of the cancellation pulse The search window length is determined based on the adjacent channel power ratio target and hardware resource constraints. The maximum number of iterations is determined based on the oversampling rate and peak width. Used to suppress peak regeneration during peak clipping.
4. The peak-to-average power ratio coordinated control method for a digital predistortion system according to claim 1, characterized in that, Step S5 includes: first, determining the feasible forgetting factor range based on the peak-to-average power ratio constraint at the input of the power amplifier; then, selecting the forgetting factor within the feasible forgetting factor range based on the criteria of a small normalized mean square error and adjacent channel power ratio meeting preset performance requirements.
5. A peak-to-average power ratio coordinated control system for a digital predistortion system, characterized in that, include: The signal input module is used to provide the baseband signal to be transmitted; The PC-CFR processing module is used for peak detection, band-limited cancellation pulse generation, and peak clipping of the baseband signal to be transmitted. The digital predistortion module is used to perform predistortion compensation on the peak-clipping signal according to the predistorter coefficient; The parameter identification module is used to identify the post-distorter coefficients using an indirect learning architecture, a memory multinomial model, and a recursive least squares algorithm. The feedback acquisition module is used to acquire the output signal of the power amplifier and send it back to the parameter identification module. The performance evaluation and coordination module is used to obtain the peak-to-average power ratio, normalized mean square error and adjacent channel power ratio at the input of the power amplifier, and to collaboratively determine the PC-CFR parameters and forgetting factor based on the above indicators.
6. The peak-to-average power ratio coordinated control system for the digital predistortion system according to claim 5, characterized in that, The PC-CFR processing module includes a main signal delay path, a peak detection and scaling path, and a pulse generation path; the performance evaluation and coordination module is used to first select the PC-CFR operating point that satisfies the constraint of the peak-to-average power ratio at the input of the power amplifier, and then select the forgetting factor with the best corresponding linearization performance.