A communication fault self-adaptive repairing method of a multi-protocol remote controller test device

Abstract

This invention belongs to the field of multi-protocol communication testing technology and relates to an adaptive repair method for communication faults in a multi-protocol remote control testing device. The method includes: polling to obtain the register status bit data of the controller; determining that when transmission blocking crosses a first threshold, suspending the direct memory access controller's transmission descriptor and locking the source memory address of the header-delayed data frame; extracting the sequence number and synchronization feature word of the header-delayed data frame, and constructing an intervention frame containing state reference values ​​in the bypass storage area; modifying the link pointer of the transmission descriptor to send the intervention frame; after obtaining the signal, overwriting the header field with the confirmation variable in its original position, restoring the link pointer, and resuming the original transmission order. This invention, through descriptor redirection and variable in-situ stitching, decouples the payload transmission and state recovery, achieving lossless link reconstruction, shortening recovery delay, and ensuring data integrity in a concurrent environment.

Description

Technical Field

[0001] This invention belongs to the field of multi-protocol communication testing technology and relates to an adaptive repair method for communication faults in multi-protocol remote control testing equipment. It is used in heterogeneous protocol concurrent testing scenarios such as high-frequency multimodal automotive digital key batch calibration production lines, and can achieve lossless link reconstruction and shorten fault recovery delay. Background Technology

[0002] Currently, adopting multi-protocol compatible scheduling and low-level bus communication architecture has become the core approach for complex remote control and control systems. However, existing technologies still have limitations in handling highly dynamic data scheduling mechanisms and the physical recovery from low-level hardware bus deadlocks. First, based on protocol-layer dynamic scheduling and computing power allocation technology; for example, Chinese invention patent application CN121509549A discloses a multi-protocol remote control high-frequency head compatibility method, which sets the security command to the highest preemptive priority through priority scheduling and dynamically adjusts the sliding window according to the data change rate to optimize computing power allocation. Its drawback is that: the scheme is essentially an instantaneous scheduling of application layer data state, and the control logic lacks rigid representation of the abnormal dead state of the underlying hardware link (such as I2C bus). It does not map the deadlock failure effect at the hardware level to the boundary constraints of the upper layer protocol solution space, which means that if the underlying physical bus collapses when the upper layer outputs commands, the scheme completely loses its control effectiveness.

[0003] Second, there is the bus recovery technology based on the forced low pull of the master control clock signal. For example, Chinese invention patent CN107562668B discloses a bus deadlock recovery system and method. The master device detects deadlock by detecting the clock and data signals of the I2C bus and controls the input / output interface to make the clock signal go low after a preset time period in an attempt to recover the bus. Its drawback is that this technology focuses on the open-loop signal intervention of the master control end. Although it can release mild blockage to a certain extent, it fails to establish a closed-loop association between the bus release logic and the internal dead state of the slave device. It cannot map in real time the physical compression of the communication path by the slave device continuously pulling the data line low, and it is difficult to cope with the risk of deadlock overdraft under extreme hardware failure.

[0004] Third, slave polling restart technology based on communication frequency priority; for example, Chinese invention patent application CN116627665A discloses a bus deadlock recovery method, device, equipment and storage medium. When the host is abnormally reset and the bus is deadlocked, the priority is determined based on the communication frequency between the slave and the host, and power-off or hard reset operations are performed on each target slave in sequence. Its drawback is that: existing recovery models of this kind usually regard fault diagnosis as discrete polling decision units, ignoring the continuous requirements of communication timing in high dynamic control scenarios over long time. When multiple nodes are optimized for reset, if there is no forced pruning mechanism to quickly locate the faulty node, the recovery trajectory time is very likely to accumulate drift, causing the system control to lose its practical value due to exceeding the physical carrying capacity of real-time response.

[0005] Therefore, how to construct a system architecture with accurate low-level deadlock detection and high dynamic timing constraints, so that the control and recovery logic converges to the real physical security communication boundary throughout the entire lifecycle, is the technical problem to be solved by this invention. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art, solve the technical problems of communication link recovery time delay and concurrent test data loss caused by destructive reset in heterogeneous protocol concurrent environment, and provide an adaptive repair method for communication faults of multi-protocol remote control test equipment.

[0007] To achieve the above-mentioned objectives, the present invention provides an adaptive repair method for communication faults in a multi-protocol remote control testing device, comprising the following steps: Step 101, Poll to obtain the register status bit data of the underlying controller: Poll to obtain the register status bit data of the underlying communication controller; Step 102, Suspend the transmission descriptor and lock the frame address when transmission is blocked: When the flag bit in the determination register status bit data representing the transmission blockage remains stagnant for a period of time exceeding the first threshold, suspend the current transmission descriptor of the direct memory access controller corresponding to the current communication channel, lock the source memory address of the data frame whose header is stuck in the main buffer storage area, and maintain the current distribution state of the data entities in the main buffer storage area. Step 103, Parse the header of the delayed frame to extract the sequence number and synchronization feature word: Parse the protocol header fields of the delayed data frame to extract the current transmission sequence number and state machine synchronization feature word; Step 104: Construct an intervention frame containing state reference values ​​in the bypass storage area: Based on the preset protocol rule base and the protocol type identifier currently bound to the communication channel, construct a protocol state intervention frame in the bypass storage area, and write the extracted current transmission sequence number and state machine synchronization feature word as state reference values ​​into the state identifier field of the protocol state intervention frame. Step 105, Modify the descriptor pointer to redirect the target and send an intervention frame: By modifying the next node link pointer of the current transport descriptor, the target address of the current transport descriptor is redirected to the base address of the bypass storage area, the underlying transmission enable signal is enabled, and the protocol status intervention frame is sent through the direct memory access controller. Step 106, Update the header and restore the descriptor pointer to restore the original order of transmission: After capturing the link confirmation signal returned by the peer device, extract the link recovery confirmation variable and update it in place to the protocol header field of the data frame with the header stuck. Restore the next node link pointer of the current transmission descriptor to the source memory address and cancel the suspended state of the direct memory access controller to restore the original order of transmission of data in the main buffer storage area.

[0008] Following step 105, the present invention further includes the following steps: Step 1051, opening a detection window with a clock period of 10μs; Step 1052, if the flip signal of the status bit in the corresponding communication channel receive register is not captured within the second threshold period set in the detection window, a port reset signaling is issued.

[0009] In step 105 of the present invention, when sending the protocol status intervention frame, the following steps are also included: step 1053, reading the cumulative count value of the preceding communication error; step 1054, based on the cumulative count value of the preceding communication error, reducing the physical layer drive baud rate of the underlying communication controller through a preset decrement function.

[0010] In step 104 of this invention, the protocol state intervention frame is constructed as follows: if the protocol type is identified as a connection-oriented transmission protocol, the protocol state intervention frame is set as a state synchronization message with a reset flag; if the protocol type is identified as a serial asynchronous protocol, the protocol state intervention frame is set as a dominant level sequence that breaks the current timing synchronization.

[0011] In step 105 of this invention, redirection is achieved by modifying the descriptor linked list of the direct memory access controller, which then bypasses the send queue of the application layer protocol stack based on the modified address pointer.

[0012] Following step 106, the present invention further includes the following steps: Step 1061, re-verify the cyclic redundancy check code of the header-residual data frame; Step 1062, regenerate and fill the check sequence based on the updated protocol header field.

[0013] In step 101 of this invention, the register status bit data includes the transmit buffer empty flag data and the receive buffer full flag data, and the first threshold is dynamically extracted according to a preset communication channel protocol priority mapping table.

[0014] In step 102 of this invention, the locking is achieved by disabling write protection interrupts for the source memory address through the driver of the underlying communication controller.

[0015] Following step 106, the present invention further includes the following steps: Step 1063, accumulating the repair frequency of the current communication channel; Step 1064, when the repair frequency exceeds a preset third threshold within a preset period, reducing the concurrent task scheduling weight of the current communication channel to avoid continuous blocking caused by link performance degradation.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: 1. In adaptive repair of communication faults, a master-slave separated memory descriptor suspension logic and bypass injection channel are adopted to transform the traditional destructive buffer cleaning operation into a non-linear scheduling of the logical channel. When faced with communication deadlock, the system maintains the test data entity in the master buffer unchanged and opens an independent path for the protocol intervention control frame. This mechanism decouples the rigid relationship between physical payload transmission and protocol state recovery, so that the repair process of the communication link no longer sacrifices data integrity.

[0017] 2. This method establishes a bidirectional logical connection between protocol intervention signaling and delayed data; the construction parameters of the intervention frame are extracted from the header of the suspended delayed data, and the synchronization state variables returned by the peer device after responding to the intervention frame are overwritten in the corresponding memory address of the delayed data; this micro-arrangement at the protocol feature level enables data packets that were originally invalid due to state machine misalignment to regain a legitimate protocol identity without changing the payload, thus achieving a closed-loop connection between data flow and link reconstruction.

[0018] 3. This method removes communication interlocks from the logic layer within a narrow time window by truncating the conventional driver-level reset process and using targeted memory pointer switching and protocol type matching intervention frame injection. This processing path avoids the delay caused by physical port re-enumeration and driver initialization, reducing the link recovery time from the millisecond-level hardware reset scale to the microsecond-level message interaction scale, and maintaining the robustness of system throughput in heterogeneous protocol concurrent test environment. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the communication fault adaptive repair logic flow of the multi-protocol remote control test device of the present invention; Figure 2 This is a schematic diagram of the communication system architecture and underlying interactive control block of the multi-protocol remote control test device of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings.

[0021] Example 1: An adaptive repair method for communication faults in a multi-protocol remote control testing device includes the following steps: Step 101, Poll to obtain the register status bit data of the underlying controller: Poll to obtain the register status bit data of the underlying communication controller; Step 102, Suspend the transmission descriptor and lock the frame address when transmission is blocked: When the flag bit in the determination register status bit data representing the transmission blockage remains stagnant for a period of time exceeding the first threshold, suspend the current transmission descriptor of the direct memory access controller corresponding to the current communication channel, lock the source memory address of the data frame whose header is stuck in the main buffer storage area, and maintain the current distribution state of the data entities in the main buffer storage area. Step 103, Parse the header of the delayed frame to extract the sequence number and synchronization feature word: Parse the protocol header fields of the delayed data frame to extract the current transmission sequence number and state machine synchronization feature word; Step 104: Construct an intervention frame containing state reference values ​​in the bypass storage area: Based on the preset protocol rule base and the protocol type identifier currently bound to the communication channel, construct a protocol state intervention frame in the bypass storage area, and write the extracted current transmission sequence number and state machine synchronization feature word as state reference values ​​into the state identifier field of the protocol state intervention frame. Step 105, Modify the descriptor pointer to redirect the target and send an intervention frame: By modifying the next node link pointer of the current transport descriptor, the target address of the current transport descriptor is redirected to the base address of the bypass storage area, the underlying transmission enable signal is enabled, and the protocol status intervention frame is sent through the direct memory access controller. Step 106, Update the header and restore the descriptor pointer to restore the original order of transmission: After capturing the link confirmation signal returned by the peer device, extract the link recovery confirmation variable and update it in place to the protocol header field of the data frame with the header stuck. Restore the next node link pointer of the current transmission descriptor to the source memory address and cancel the suspended state of the direct memory access controller to restore the original order of transmission of data in the main buffer storage area.

[0022] Following step 105 in this embodiment, the following steps are also included: Step 1051, opening a detection window with a clock period of 10μs; Step 1052, if the flip signal of the status bit in the corresponding communication channel receive register is not captured within the second threshold period set in the detection window, a port reset signaling is issued.

[0023] In step 105 of this embodiment, when sending the protocol status intervention frame, the following steps are also included: Step 1053, read the cumulative count value of the previous communication error; Step 1054, based on the cumulative count value of the previous communication error, reduce the physical layer drive baud rate of the underlying communication controller through a preset decrement function.

[0024] In step 104 of this embodiment, the protocol state intervention frame is constructed as follows: if the protocol type is identified as a connection-oriented transmission protocol, the protocol state intervention frame is set as a state synchronization message with a reset flag; if the protocol type is identified as a serial asynchronous protocol, the protocol state intervention frame is set as a dominant level sequence that breaks the current timing synchronization.

[0025] In step 105 of this embodiment, redirection is achieved by modifying the descriptor linked list of the direct memory access controller. The direct memory access controller bypasses the send queue of the application layer protocol stack based on the modified address pointer.

[0026] Following step 106 in this embodiment, the following steps are also included: Step 1061, re-verify the cyclic redundancy check code of the header-residual data frame; Step 1062, regenerate and fill the check sequence based on the updated protocol header field.

[0027] In step 101 of this embodiment, the register status bit data includes the transmit buffer empty flag data and the receive buffer full flag data, and the first threshold is dynamically extracted according to the preset communication channel protocol priority mapping table.

[0028] In step 102 of this embodiment, the locking is achieved by disabling write protection interrupts for the source memory address through the driver of the underlying communication controller.

[0029] Following step 106 in this embodiment, the following steps are also included: Step 1063, accumulating the repair frequency of the current communication channel; Step 1064, when the repair frequency exceeds a preset third threshold within a preset period, reducing the concurrent task scheduling weight of the current communication channel to avoid continuous blocking caused by link performance degradation.

[0030] Example 2: In this embodiment, in the application scenario of a high-frequency multimodal automotive digital key batch calibration production line, the test host needs to run heterogeneous communication protocols, including the transmission control protocol and the multi-baud rate universal asynchronous transceiver protocol, concurrently through a single hardware interface to verify the full communication matrix of the device under test. Due to the differences in frame structure and state machine transition logic between heterogeneous protocols, the concurrent high-frequency interaction overloads the receiving end processing queue, causing the flag representing the transmission blockage in the register status bit data of the underlying communication controller to remain stagnant for a period exceeding the first threshold, triggering contention for logical resources and interlocking of the protocol state machine within the multi-reusable channel. Faced with this communication deadlock problem caused by the blocking of the head of the rigid first-in-first-out queue, if the physical layer port reset method is used, the main buffer storage area will be cleared, resulting in data fragmentation of the complete data stream of the current batch of automated test cases. This technical solution redirects the processing logic to the time-division reuse layer of the logical channel. Specifically, it suspends the current transmission descriptor of the direct memory access controller corresponding to the current communication channel, locks the source memory address of the data frame stuck at the head in the main buffer storage area, and maintains the current distribution state of the data entities in the main buffer storage area to avoid physical payload loss.

[0031] Based on the aforementioned locked main buffer state, the underlying communication controller parses the protocol header fields of the congested data frames, extracts the current transmission sequence number and state machine synchronization feature, and constructs a protocol state intervention frame in a bypass storage area independent of the main buffer, according to a preset protocol rule base and the protocol type identifier currently bound to the communication channel. The extracted current transmission sequence number and state machine synchronization feature are written as state reference values ​​into the state identifier field of the protocol state intervention frame. By modifying the next node link pointer of the current transmission descriptor, the target address of the current transmission descriptor is redirected to the base address of the bypass storage area, and the underlying transmission enable signal is activated. The protocol state intervention frame is then issued via the direct memory access controller. This process extracts the state reference value of the blocked data as a prerequisite input condition for constructing the bypass intervention frame, thus intervening. The frame carries the state baseline quantity to forcibly wake up the state machine of the stalled peer device, resolving the resource contention between issuing deadlock release instructions and regular test data occupying the transmission queue. After capturing the link confirmation signal returned by the peer device, the underlying communication controller extracts the link recovery confirmation variable and updates the link recovery confirmation variable in place to the protocol header field of the delayed data frame to replace the original invalid state confirmation bit. It restores the next node link pointer of the current transmission descriptor to the source memory address and cancels the suspended state of the direct memory access controller, restoring the original order transmission of data in the main buffer storage area. The data packets that were stalled due to the state machine misalignment regain a legal protocol identity that conforms to the new link state without changing the data payload. Under this mechanism, the concurrent data stream of the test production line completes the in-situ lossless reconstruction and closed-loop connection of the communication link.

[0032] Example 3: In this embodiment, in a multimodal automotive digital key calibration and testing pipeline with a daily throughput of 100,000 times, the hardware verification platform includes a system-level test chip with gigabit Ethernet and multiple universal asynchronous transceiver interfaces, as well as a directly connected device-under-test (DUT) control microprocessor. The platform's direct memory access controller is configured in a dual-channel independent polling mode, and the main buffer storage area depth is set to 4096 bytes. An external wideband radio frequency interference generator continuously injects Gaussian white noise with a signal-to-noise ratio of 20dB into the vicinity of the physical transmission cable, and superimposes power frequency harmonic interference with a frequency of 50Hz. Under this signal-to-noise ratio condition, concurrent data push is blocked in the sending queue of the underlying communication controller due to the timing offset of the parsing of the peer state machine, triggering an adaptive repair process.

[0033] To address the aforementioned communication deadlock scenario, a control group and an experimental group were established. The control group employed a physical port reset mechanism based on watchdog timeout, while the experimental group adopted a repair mechanism that suspended the current transmission descriptor and issued protocol state intervention frames in the bypass storage area. Microsecond detection windows with clock periods of 5μs, 10μs, and 20μs were set as the second threshold, and 10,000 concurrent test cycles were continuously run. Statistical data showed that the average time for a single communication link reconstruction in the control group was 350ms, and the base address of the main buffer storage area was physically reset, with a 100% loss rate of effective data packets in the test batch. In the experimental group, with the microsecond detection window set to 10μs, the average time for a single communication link reconstruction was 45μs, and the data entities in the main buffer storage area maintained the source memory address locked distribution, with a 0% loss rate of effective test data packets excluding the blocking header.

[0034] The gradient test data within the microsecond detection window exhibits nonlinear differences. When the microsecond detection window is set to 5μs, this waiting time is shorter than the physical latency of the microprocessor interrupt response of the peer device. The underlying communication controller rolls back to trigger the physical layer port reset drive instruction, resulting in a packet loss rate of 42.5%. When the microsecond detection window is extended to 20μs, the packet loss rate is 0%, and the average time for a single communication link reconstruction increases to 55μs. Setting a 10μs microsecond detection window balances the underlying hardware response latency with the link reconstruction timeliness. In actual communication conditions, since the absolute time span of 10μs is much smaller than the single-bit transmission period of common low-speed serial protocols, this microsecond detection window is not used to wait for the physical transmission of a complete protocol frame, but rather as a sampling of the hardware interrupt line of the high-frequency polling receive pin of the underlying direct memory access controller. The timing is as follows: When the peer device's state machine captures the first abnormal level edge or start bit trigger signal generated by the protocol state intervention frame, its underlying control unit will directly set the frame error or bus wake-up flag in the hardware register within a nanosecond-level physical delay. The underlying communication controller can complete the handshake confirmation of the reconstruction timing by capturing the transient level transition of the hardware-level state bit, thereby physically eliminating the physical constraint of waiting for the entire cycle of low-speed messages. The bypassed protocol state intervention frame crosses the processing interval of the peer state machine within this microsecond detection window and captures the flip signal of the legal response state bit. The underlying communication controller overwrites the link recovery confirmation variable in place to the protocol header field of the data frame in the header. This state machine intervention link releases the logical resource contention in the multiple reuse channel and maintains the integrity of the data stream under the concurrent transmission of heterogeneous protocols.

[0035] Example 4: This embodiment combines Figures 1 to 2 This document describes an adaptive repair method for communication faults in a multi-protocol remote control test device. Figure 1 As shown, in step 101, the system polls to obtain the register status bit data of the underlying controller. Then, in step 102, the system sends a blocked transmission descriptor and locks the frame address. In step 103, the system parses the header of the delayed frame to extract the sequence number and synchronization feature word. Then, in step 104, the system constructs an intervention frame containing the status reference value in the bypass storage area. In step 105, the system modifies the descriptor pointer to redirect the target and sends the intervention frame. Finally, in step 106, the system updates the header and restores the descriptor pointer to restore the original order transmission.

[0036] like Figure 2As shown, the system's communication architecture mainly consists of a test host, physical transmission cables, a broadband radio frequency interference generator, and the device under test (DUT). The test host internally deploys a low-level monitoring daemon and an application-layer protocol stack in parallel, and is configured with a low-level communication controller and a single hardware port. The low-level monitoring daemon unidirectionally points to the low-level communication controller. The single hardware port integrates Gigabit Ethernet and multiple universal asynchronous transceiver interfaces. The low-level communication controller contains register status bit data and a direct memory access controller, and is divided into a main buffer storage area for storing header-residing data frames, a bypass storage area for storing protocol status intervention frames, and a protocol rule base or communication channel protocol priority mapping table. The read-only memory area internally directs the register status bit data unidirectionally to the main buffer memory area. At the same time, the main buffer memory area, the direct memory access controller, and the read-only memory area all unidirectionally direct to the bypass memory area. The output data of the underlying communication controller is transmitted to the outside via a single hardware port. In the physical environment where the broadband radio frequency interference generator applies an external unidirectional action to the physical transmission cable, the signal is unidirectionally input to the device under test via the physical transmission cable. The signal flow inside the device under test is sequentially transmitted unidirectionally upward through the receiving window to the state machine of the peer device and the control microprocessor of the device under test. At the same time, there is a dashed link in the system that leads out from the device under test and unidirectionally points to the direct memory access controller in the test host.

[0037] Example 5: In this embodiment, during the physical channel reuse transmission mode of the multimodal remote control test equipment, a communication deadlock occurs due to the interlocking of mixed backlogged test messages and protocol state machine data in the main buffer storage area of ​​the underlying communication controller. Before cleaning the read and write pointers, the underlying communication controller triggers a selective data evaluation procedure based on digital feature entropy. The underlying monitoring daemon locks the continuous memory block in the main buffer storage area from the starting address to the current write pointer offset, and divides the continuous memory block into multiple data blocks of a fixed length of 256 bytes. The underlying monitoring daemon extracts the occurrence probability of each byte value in the data block and calculates the digital feature entropy. The specific formula for calculating the digital feature entropy is as follows: ,in, The digital feature entropy of the data blocks. For the first The probability of a specific byte value appearing in a block of data. For an index of a specific byte value, the underlying communication controller extracts a standard data stream segment during full-load concurrent communication under fault-free conditions to calculate the baseline feature entropy. The baseline feature entropy is multiplied by a coefficient of 0.45 to determine the information entropy threshold. When the calculated digital feature entropy of the data block is lower than the information entropy threshold, the underlying communication controller determines that the data block is filled with low-information communication deadlock levels and resets the base address pointer and offset of the data block to zero to release memory space. When the digital feature entropy is greater than or equal to the information entropy threshold, the underlying communication controller determines that the data block contains normal protocol frame payload, locks its source memory address, and moves it into the bypass recovery queue.

[0038] Once the bypass recovery queue data distribution is established in the main buffer storage area, the underlying monitoring daemon parses the protocol header fields of the data frames stuck in the bypass recovery queue, extracts the current transmission sequence number and state machine synchronization feature, and, based on the protocol type identifier currently bound to the communication channel, assembles a protocol state intervention frame in the bypass storage area. The extracted current transmission sequence number, incremented by a step size constant, is written along with the state machine synchronization feature into the status identifier field of the protocol state intervention frame. The underlying communication controller suspends the primary direct memory access descriptor associated with the current communication channel, modifies the next node link pointer of this primary direct memory access descriptor to redirect its target address to the base address in the bypass storage area, and triggers a hardware enable signal to send the protocol state intervention frame via the direct memory access controller, bypassing the application layer transmission queue. Upon receiving the state machine reset confirmation signal from the peer device, the underlying communication controller extracts the link recovery confirmation variable and overwrites it in place to the header. Before the protocol header field of the delayed data frame is overwritten in place and the main buffer storage area has resumed flow, the underlying communication controller activates the first-level independent cyclic redundancy check (CRC) calculation engine built into the hardware link layer through the internal clock bus. This hardware engine directly reads the continuous memory segments of the delayed data frame after the header is updated through the parallel-mounted read-only bus, and immediately derives a new check bit sequence in the register according to the pre-configured polynomial generation rules. The hardware microcode takes over the write permission of the offset at the end of the source memory address to complete the in-place fixed-point filling of the new check sequence. This all-hardware operation link physically decouples the dependence on the computing power of the application layer software protocol stack, thereby ensuring the physical-level closed-loop self-consistency of the verification logic after the header data is tampered with. The underlying communication controller restores the link pointer of the main direct memory access descriptor to the source memory address of the main buffer storage area, so that the communication link can restore the original order and concurrent flow of heterogeneous protocol packets while retaining the high digital entropy test data.

[0039] Specifically, when constructing an intervention frame for the serial asynchronous protocol, the dominant level sequence that breaks the current timing synchronization is presented as a continuous logic low-level physical signal. The underlying communication controller forcibly pulls the physical transmit pin low, and its duration is longer than the transmission period of a single complete data frame at the current baud rate. Taking a single start bit, a single stop bit, and an eight-bit unchecked data format as an example, the low-level duration is set to be longer than ten bits. This continuous low-level signal triggers a frame error interrupt in the hardware controller of the peer device. Based on this interrupt mechanism, the peer device clears the residual level signal in the receive shift register, and the peer protocol state machine is reset to the initial line listening state.

[0040] When redirecting the target address of the direct memory access controller, the underlying communication controller driver writes a disable control word to the channel configuration register to suspend the high-performance bus request. The underlying monitoring daemon starts a microsecond-level spinlock to poll the hardware status register, monitors and captures the toggling level of the current data block transmission completion flag or the internal first-in-first-out buffer block empty interrupt flag. After confirming that the bus residual burst transmission is complete and releasing control, the driver overwrites the bypass memory area base address to the descriptor link pointer register. After the base address is updated, the driver writes an enable control word to the channel configuration register to restore the bus master device access permissions and sends a protocol status intervention frame through the hardware channel.

[0041] Example 6: In this embodiment, during the pre-deployment calibration scenario of introducing multi-protocol remote control testing equipment into a new testing production line, the underlying communication controller injects a scanned data stream containing various protocol headers and load boundaries into the test channel. The underlying monitoring daemon independently intercepts the underlying response level sequence returned by the peer device during the initial handshake and abnormal blocking phases, extracts the protocol type identifier and state machine synchronization feature word from the underlying response level sequence, and maps the extracted feature data to the intervention control bit set to generate a mapping relationship dictionary for assembling protocol state intervention frames. This dictionary is then stored in a read-only memory area to construct a protocol rule base. Specifically, the mapping relationship dictionary adopts a hash table data structure, using the intercepted protocol type identifier as the address pointer key, and includes the start synchronization header, payload length delimiter, and reserved... The set of intervention control bits in the status bitmask is used as the associated value. When assembling the protocol status intervention frame, the underlying communication controller retrieves the corresponding intervention control bit set from the dictionary, activates the hardware logic operation unit to perform a bitwise OR operation, and aligns and fills the state machine synchronization feature word into the blank offset address range defined by the reserved status bitmask. This realizes the physical-level memory splicing of the static payload and dynamic feature word of the protocol status intervention frame. During this data filling operation, the underlying communication controller blocks the system calls of the application layer and maintains the physical transmission cable in a one-way probe interaction state. The intervention frame structure parameters contained in the generated protocol rule base directly correspond to the hardware protocol stack characteristics of the target device under test. Based on this solidification operation, the underlying communication controller establishes the protocol type identifier bound to each communication channel and the fixed assembly path of the bypass intervention frame.

[0042] After the protocol rule base is built, the underlying monitoring daemon starts the calibration procedure for the baseline feature entropy. The underlying communication controller controls the active communication channel to continuously send the standard test payload under normal handshake state at the highest physical layer drive baud rate. It locks the continuous memory block carrying the standard test payload in the main buffer storage area. The underlying monitoring daemon extracts multiple calibration data blocks of a fixed length of 256 bytes and obtains the discrete feature entropy of each calibration data block according to the aforementioned digital feature entropy calculation rules. The underlying monitoring daemon removes the values ​​in the top 5% and bottom 5% of the discrete feature entropy set, calculates the arithmetic mean of the remaining discrete feature entropy, and solidifies the arithmetic mean as the baseline feature entropy. The underlying communication controller extracts the calibrated baseline feature entropy to set the information entropy threshold for triggering the selective data cleaning procedure. The test equipment outputs the buffer queue intervention judgment benchmark matching the current high-frequency concurrent working condition of the production line based on this calibration data.

[0043] Example 7: In this embodiment, when the multi-protocol remote control concurrent test equipment faces continuous radio frequency interference, the underlying communication controller initiates a baud rate adaptive frequency reduction procedure before sending the protocol status intervention frame. The underlying monitoring daemon reads the cumulative count value of the preceding communication errors recorded in the underlying hardware register. The underlying communication controller substitutes the cumulative count value of the preceding communication errors into a preset decrementing function to calculate the target baud rate. The specific baud rate calculation formula is as follows: ,in, For the target baud rate, The base physical layer drives the baud rate. For a specific down-frequency coefficient, As a cumulative count of pre-communication errors, the underlying communication controller extracts the minimum permissible communication rate corresponding to the protocol type identifier currently bound to the communication channel as a hard lower limit threshold. When the calculated target baud rate is lower than the hard lower limit threshold, the underlying communication controller sets the physical layer drive baud rate to the hard lower limit threshold. If the calculated target baud rate is greater than or equal to the hard lower limit threshold, the underlying communication controller writes the division ratio parameter of the corresponding target baud rate to the clock divider register. The clock divider outputs the down-frequency transmission clock signal to the physical transmission channel based on the updated division ratio parameter. The underlying communication controller extends the signal bit period time based on the down-frequency transmission clock signal and outputs a protocol status intervention frame.

[0044] In the process of establishing the bypass recovery queue data distribution status and constructing the protocol state intervention frame in the main buffer storage area, the underlying communication controller extracts the current stagnant state sequence variable from the protocol header field. The underlying monitoring daemon retrieves the protocol rule base stored in the read-only storage area based on the protocol type identifier currently bound to the communication channel, reads the maximum receive window size parameter that matches the protocol type identifier, multiplies the maximum receive window size parameter by a scaling factor of 0.5 and rounds down the product to obtain the offset constant parameter, adds the value of the current stagnant state sequence variable to the obtained offset constant parameter to obtain the state reference value, writes the state reference value into the state identifier field of the protocol state intervention frame, modifies the next node link pointer of the main direct memory access descriptor and triggers the hardware to send an enable signal, and sends the protocol state intervention frame carrying the state reference value to the peer device through the direct memory access controller, bypassing the application layer transmission queue. The peer device's state machine verifies the sequence variable located in the valid receive window and outputs a flip signal of the valid response state bit. The underlying communication controller receives the flip signal and restores the protocol synchronization interaction state of both devices.

[0045] Before initiating the underlying hardware status register polling procedure, the multi-protocol remote control test device triggers the first threshold dynamic extraction procedure. The underlying communication controller reads the protocol type identifier bound to the current communication channel and retrieves the communication channel protocol priority mapping table stored in the read-only memory area. The initial quantization assignment logic of the priority weight coefficient is constructed based on the physical bandwidth occupancy boundary and real-time response constraint level of heterogeneous protocols. For connection-oriented protocol types such as Ethernet transmission control protocol, which have retransmission handshake mechanisms and require strong end-to-end timing synchronization, the priority weight coefficient is statically set to a value greater than 1. For serial asynchronous protocols such as universal asynchronous transceiver transmitters, which are based on a best-effort transmission mechanism, their priority weight coefficient is constrained to a value less than or equal to 1. This forms a hard isolation boundary with a narrower timeout tolerance range for high-throughput channels. The underlying communication controller extracts the priority weight coefficient and the baseline timeout constant of the corresponding protocol type identifier in the communication channel protocol priority mapping table. The underlying communication controller divides the baseline timeout constant by the priority weight coefficient to calculate the dynamic timeout parameter. The specific dynamic timeout parameter calculation formula is as follows: ,in, The first threshold, As the baseline timeout constant, As a priority weighting coefficient, the underlying communication controller writes the dynamic timeout parameter into the timeout determination register and sets it as the first threshold. The underlying monitoring daemon monitors the time span for maintaining the blocking flag in the hardware status register based on the first threshold. The underlying hardware outputs a channel blocking determination signal based on this value boundary. After receiving the channel blocking determination signal, the underlying communication controller starts the concurrent scheduling weight and memory locking procedure. The underlying monitoring daemon reads the cumulative communication error count of the current communication channel and extracts the historical repair frequency of the channel. When the historical repair frequency exceeds the third threshold within a preset clock cycle, the underlying communication controller... The device sends a scheduling adjustment signaling message to the task scheduling engine to reduce the concurrent task scheduling weight of the current communication channel. The underlying communication controller suspends the current transfer descriptor of the direct memory access controller corresponding to the current communication channel. The driver of the underlying communication controller sends an interrupt masking instruction to the kernel memory management unit to disable the write protection interrupt for the source memory address of the header data frame in the main buffer. Based on the interrupt disabled state, the underlying communication controller locks the source memory address and maintains the current distribution state of the test data entities in the main buffer. Under this memory isolation state, the underlying hardware system blocks the external process from overwriting system calls to the source memory address.

Claims

1. A method for communication fault self-adaptive repair of a multi-protocol remote controller test device, characterized in that, Includes the following steps: Step 101: Poll to obtain the register status bit data in the underlying communication controller; Step 102: When the time for which the flag indicating transmission blockage in the register status bit data remains suspended exceeds the first threshold, suspend the current transmission descriptor of the direct memory access controller corresponding to the current communication channel, lock the source memory address of the header data frame in the main buffer storage area, and maintain the current distribution state of the data entities in the main buffer storage area. Step 103: Parse the protocol header fields of the data frame with the header still attached, and extract the current transmission sequence number and the state machine synchronization feature word; Step 104: Based on the preset protocol rule base and the protocol type identifier currently bound to the communication channel, construct a protocol state intervention frame in the bypass storage area, and write the extracted current transmission sequence number and state machine synchronization feature word as state reference quantities into the state identifier field of the protocol state intervention frame. Step 105: By modifying the next node link pointer of the current transport descriptor, the target address of the current transport descriptor is redirected to the base address of the bypass storage area, the underlying transmission enable signal is enabled, and the protocol status intervention frame is issued through the direct memory access controller. Step 106: After capturing the link confirmation signal returned by the peer device, extract the link recovery confirmation variable and update it in place to the protocol header field of the data frame with the header still pending. Restore the next node link pointer of the current transmission descriptor to the source memory address and cancel the suspended state of the direct memory access controller to restore the original order transmission of data in the main buffer storage area.

2. The communication fault self-adaptive repairing method of a multi-protocol remote controller testing device according to claim 1, characterized in that, After step 105, the following steps are also included: Step 1051, opening a detection window with a clock period of 10μs; Step 1052, if the flip signal of the status bit in the corresponding communication channel receive register is not captured within the second threshold period set in the detection window, a port reset signaling is issued.

3. The method of claim 1, wherein the method further comprises: In step 105, when issuing the protocol status intervention frame, the following steps are also included: Step 1053, read the cumulative count value of the previous communication error; Step 1054, based on the cumulative count value of the previous communication error, reduce the physical layer drive baud rate of the underlying communication controller through a preset decrement function.

4. The method of claim 1, wherein the method further comprises: In step 104, the protocol state intervention frame is constructed as follows: if the protocol type is identified as a connection-oriented transport protocol, the protocol state intervention frame is set as a state synchronization message with a reset flag; if the protocol type is identified as a serial asynchronous protocol, the protocol state intervention frame is set as a dominant level sequence that breaks the current timing synchronization.

5. The method of claim 1, wherein the method further comprises: In step 105, the redirection is achieved by tampering with the descriptor linked list of the direct memory access controller, which then bypasses the send queue of the application layer protocol stack based on the modified address pointer.

6. The method of claim 1, wherein the method further comprises: After step 106, the following steps are also included: Step 1061, re-verify the cyclic redundancy check code of the header-residual data frame; Step 1062, regenerate and fill the check sequence based on the updated protocol header field.

7. The method of claim 1, wherein the method further comprises: In step 101, the register status bit data includes the transmit buffer empty flag data and the receive buffer full flag data, and the first threshold is dynamically extracted according to the preset communication channel protocol priority mapping table.

8. The method of claim 1, wherein the method further comprises: In step 102, the lock is implemented by disabling write-protected interrupts for the source memory address through the driver of the underlying communication controller.

9. The method of claim 1, wherein the method further comprises: After step 106, the following steps are also included: Step 1063, accumulate the repair frequency of the current communication channel; Step 1064, when the repair frequency exceeds the preset third threshold within the preset period, reduce the concurrent task scheduling weight of the current communication channel to avoid continuous blocking caused by link performance degradation.

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