A software and hardware cooperative CSIG backward compatible implementation method and device, electronic equipment and computer readable medium

Abstract

This invention discloses a hardware-software co-operated CSIG backward compatibility implementation method, apparatus, electronic device, and computer-readable medium. The method includes the following: the CPU periodically collects statistical information of each port of the switch, and calculates the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] of each port based on the statistical information; the available bandwidth, normalized available bandwidth, and normalized queue depth are mapped to the corresponding quantization threshold M according to a preset mapping table. ABW M ABW / C M nQD[i] The quantization threshold is written into the threshold field of the corresponding ACL rule; the switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to the ACL rule; the CPU repeats the above steps at set time intervals to update the threshold field of the ACL rule, so that the comparison value in the ACL rule reflects the latest available bandwidth, normalized available bandwidth, and normalized queue depth of each port in real time. This invention enables older devices that do not support CSIG hardware updates to participate in local congestion signal correction.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method, apparatus, electronic device, and computer-readable medium for implementing CSIG backward compatibility through hardware and software collaboration. Background Technology

[0002] CSIG (Congestion Signaling) is a simple in-band network telemetry method where fine-grained measurements are collected at switches as packets traverse the network path. CSIG achieves low telemetry collection overhead by limiting the in-packet state to a single fixed-size CSIG tag (4 or 8 bytes), which stores the signal value measured at a single switch (regardless of the number of hops the packet has traversed). The UEC (Ultra Ethernet Consortium) supports three signal types for CSIG in its base profile: min(ABW), min(ABW / C), and max(Delay), and the max(nQD) signal type in its extended profile.

[0003] The main drawback is: CSIG implementation typically relies on real-time calculation and updates of the switch's hardware data plane. This means the switching chip directly reads information such as queue depth and bandwidth along the forwarding path and conditionally modifies the CSIG field in the packet. This purely hardware-based implementation suffers from poor backward compatibility; older switches or hardware that doesn't support CSIG cannot participate in the generation and updating of congestion signals. Consequently, CSIG only works in newly deployed networks and cannot be gradually rolled out in existing networks.

[0004] While Section 6.4 of the IETF draft (draft-ravi-ippm-csig-01) mentions achieving backward compatibility through software-assisted CSIG, it does not provide specific details of the solution. Therefore, a detailed hardware-software co-implementation scheme is needed. This scheme would utilize the CPU to assist in calculating available bandwidth and queue depth, and dynamically update ACL rules, enabling devices that do not support CSIG hardware updates to participate in local congestion signal correction and achieve backward compatibility. Summary of the Invention

[0005] According to a first aspect of the present invention, a CSIG backward compatibility implementation method with hardware and software collaboration is provided, comprising the following steps: The CPU periodically collects statistical information from each port of the switch and calculates the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] for each port based on the statistical information. The available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] are mapped to the corresponding quantization threshold M according to the preset mapping table. ABW M ABW / C M nQD[i] And write the quantization threshold into the threshold field of the corresponding ACL rule; The switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to ACL rules; The CPU repeats the above steps at set time intervals to update the threshold field of the ACL rules, so that the comparison values ​​in the ACL rules reflect the latest available bandwidth of each port in real time.

[0006] Furthermore, the statistical information includes: The number of bytes TX sent by the port within the time interval delta_t bytes and message count TX Packets And the depth of each queue at the port, Queue_depth[i]; The physical transmit bandwidth C of the port; Port preamble (including SFD) and inter-frame gap (IFG) length configuration.

[0007] Furthermore, the formulas for calculating available bandwidth, normalized available bandwidth, and normalized queue depth are as follows: Used bandwidth U = (8 * (TX) bytes +(Preamble+IFG)*TX Packets )) / delta_t, where U is an integer; Available bandwidth ABW=CU; Normalized available bandwidth ABW / C = 100*(1-U / C), where ABW / C is an integer; The normalized queue depth nQD[i] = Queue_depth[i] / C, where nQD[i] is an integer.

[0008] Furthermore, the used bandwidth U is smoothed using an exponentially weighted moving average algorithm.

[0009] Furthermore, the preset mapping table is divided into a compact CISG or a wide CISG mapping table.

[0010] Furthermore, in the compact CSIG tag, the csig.s field is 5 digits, and the ABW, ABW / C, and nQD[i] values ​​are assigned to specific regions according to a preset compact mapping table. The quantization threshold is obtained from each bucket; In the wide CSIG tag, the csig.s field is 20 bits, and the ABW, ABW / C, and nQD[i] values ​​are divided into regions using a uniform quantization method according to the preset wide mapping table. The quantization threshold is obtained from a number of quantized values; Quantization threshold M ABW M ABW / C M nQD[i] The values ​​are determined based on the quantization values ​​in the corresponding mapping tables.

[0011] Furthermore, the switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to ACL rules, specifically as follows: Parse the packet header using the custom offset of the ACL, extract the CSIG signal field, and extract the queue number i for forwarding within the packet. The CSIG signal field includes the signal type csig.t, signal value csig.s, do not modify bit csig.d, and locator metadata csig.lm. If the CSIG signal type is min(ABW), then the signal value csig.s > M. ABW If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. ABW And set csig.lm; If the CSIG signal type is min(ABW / C), then the signal value csig.s > M. ABW / C If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. ABW / C And set csig.lm; If the CSIG signal type is max(nQD), the message exit queue number is i, and the signal value is csig.s <M nQD[i] If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. nQD[i] And set csig.lm; If csig.d=0 and the message is truncated, then set csig.d to 1.

[0012] According to a second aspect of the present invention, a hardware-software co-operated CSIG backward compatibility implementation apparatus is provided, comprising: The data acquisition and calculation module is used by the CPU to periodically collect statistical information of each port of the switch, and calculate the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] of each port based on the statistical information. The mapping and writing module is used to map the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] to the corresponding quantization threshold M according to a preset mapping table. ABW MABW / C M nQD[i] And write the quantization threshold into the threshold field of the corresponding ACL rule; The matching and modification module is used by the switching chip to match and modify packets carrying CSIG signals passing through each port according to ACL rules; The repeat update module is used by the CPU to repeatedly execute the above steps at set time intervals to update the threshold field of the ACL rules, so that the comparison values ​​in the ACL rules reflect the latest available bandwidth of each port in real time.

[0013] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor executes the computer program to perform a hardware-software co-operation CSIG backward compatibility implementation method of the first aspect.

[0014] According to a fourth aspect of the present invention, a computer-readable medium having processor-executable non-volatile program code is provided, the program code causing the processor to perform a hardware-software co-operated CSIG backward-compatible implementation method of the first aspect.

[0015] According to an embodiment of the present invention, a hardware-software co-operated CSIG backward compatibility implementation method is provided to achieve backward compatibility. By utilizing the ACL function commonly supported by existing switches, and through CPU-assisted calculation and dynamic updating of ACL thresholds, older devices that do not support CSIG hardware updates can also participate in local correction of congestion signals, thereby realizing the gradual deployment of CSIG in the existing network.

[0016] It should be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further illustration of the claimed technology. Attached Figure Description

[0017] Figure 1 This is a flowchart of a CSIG backward compatibility implementation method for hardware and software collaboration according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of a compact CISG tag in a hardware-software co-operation CSIG backward compatibility implementation method according to an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of a wide CISG tag in a hardware-software co-operation CSIG backward compatibility implementation method according to an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of a hardware-software co-operation CSIG backward compatibility implementation device according to an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0022] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, further illustrating the present invention.

[0023] First, combine Figures 1-3 This invention describes a hardware-software co-operated CSIG backward compatibility implementation method for use in switches, which has a wide range of applications.

[0024] like Figures 1-3 As shown, an embodiment of the present invention provides a CSIG backward compatibility implementation method for hardware and software collaboration, comprising the following steps: like Figure 1 As shown, in S1, the CPU periodically collects statistical information from each port of the switch and calculates the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] for each port based on the statistical information. Specifically, on the switch, the CPU reads the hardware counters of each port at fixed time intervals (e.g., 1ms, 10ms, or according to policy configuration) to obtain the following information: The number of bytes TX sent by the port within the time interval delta_t bytes and message count TX Packets , and the depth of each queue at the port, Queue_depth[i] (i is the specified queue number).

[0025] The physical transmit bandwidth C of the port (i.e., the port speed, such as 10Gbps, 25Gbps, etc.).

[0026] The port's preamble (including SFD) and interframe gap (IFG) lengths are configured. The default preamble for an Ethernet frame is 8 bytes, and the interframe gap is 12 bytes.

[0027] The CPU calculates the port's used bandwidth, available bandwidth, normalized available bandwidth, and normalized queue depth using the following formulas: Used bandwidth U = (8 * (TX) bytes +(Preamble+IFG)*TX Packets )) / delta_t, where U is an integer; Available bandwidth ABW=CU; Normalized available bandwidth ABW / C = 100*(1-U / C), where ABW / C is an integer; The normalized queue depth nQD[i] = Queue_depth[i] / C, where nQD[i] is an integer and the queue depth Queue_depth[i] needs to be converted into bits based on the internal cell width of the switching chip.

[0028] To avoid instantaneous fluctuations, a smoothing algorithm (such as exponentially weighted moving average EWMA) can be used to smooth the used bandwidth U.

[0029] like Figures 1-3 As shown, in S2, the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] are mapped to the corresponding quantization threshold M according to the preset mapping table. ABW M ABW / C M nQD[i] The quantization threshold is then written into the threshold field of the corresponding ACL rule. Specifically, the CPU maps the calculated ABW, ABW / C, and nQD[i] values ​​to a new value M based on the mapping table of the compact CISG or wide CISG. ABW M ABW / C M nQD[i] These values ​​are then written to the threshold registers or comparison value fields of multiple specific ACL rule tables. In the compact CSIG tag, the csig.s field has only 5 bits, and the ABW, ABW / C, and nQD[i] values ​​are allocated according to the mapping table. In the wide CSIG tag, the csig.s field has 20 bits, and the ABW, ABW / C, and nQD[i] values ​​are uniformly quantized and divided into buckets. A quantized value.

[0030] ACL rules, based on the TPID of compact and wide CISG, extract packets carrying CSIG signals (csig.t, csig.s, csig.lm, csig.d) from the L2 header using a custom offset (based on the two CISG label formats) and a rule mask. The compact CISG label format is as follows: Figure 2 As shown, the wide CSIG tag format is as follows: Figure 3 As shown.

[0031] Specifically, ACL rules are designed as follows: 1) ACL rule 1 Matching criteria: Matches the TPID + CSIG signal type of the compact CISG in the message header as min(ABW) + CSIG signal value > M. ABW + CISG do not modify bit to 0 + The switching chip did not produce a truncation.

[0032] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. ABW Modify the CSIG locator metadata to the identifier of the current switch chip port.

[0033] 2) ACL rule 2 Matching criteria: Matches the TPID + CSIG signal type of the wide CISG in the message header as min(ABW) + CSIG signal value > M. ABW + CISG do not modify bit to 0 + The switching chip did not produce a truncation.

[0034] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. ABW Modify the CSIG locator metadata to the identifier of the current switch chip port.

[0035] 3) ACL rule 3 Matching criteria: Matches the TPID + CSIG signal type of the compact CISG in the message header as min(ABW / C) + CSIG signal value > M. ABW / C + CISG do not modify bit to 0 + The switching chip did not produce a truncation.

[0036] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. ABW / C Modify the CSIG locator metadata to the identifier of the current switch chip port.

[0037] 4) ACL rule 4 Matching criteria: Matches the TPID + CSIG signal type of the wide CISG in the message header as min(ABW) + CSIG signal value > M. ABW / C + CISG do not modify bit to 0 + The switching chip did not produce a truncation.

[0038] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. ABW / C Modify the CSIG locator metadata to the identifier of the current switch chip port.

[0039] 5) ACL rules 5~12 (taking an exit with 8 queues as an example, 0<=i<=7) Matching criteria: Matches the TPID + CSIG signal type of the compact CISG in the message header as max(nQD) + CSIG signal value. <M nQD[i] + CISG do not modify bit to 0 + Message exit queue number i + Switching chip did not generate truncation.

[0040] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. nQD[i] Modify the CSIG locator metadata to the identifier of the current switch chip port.

[0041] 6) ACL rules 13~20 (taking an exit with 8 queues as an example, 0<=i<=7) Matching criteria: Matches the TPID + CSIG signal type of the wide CISG in the message header as max(nQD) + CSIG signal value. <M nQD[i] + CISG do not modify bit to 0 + Message exit queue number i + Switching chip did not generate truncation.

[0042] Action: Modify the CSIG signal value field in the message to the current threshold, i.e., M. nQD[i] Modify the CSIG locator metadata to the identification information of the current switch chip port.

[0043] 7) ACL rule 21 Matching criteria: Match the TPID of the compact CISG in the message header + CISG (do not modify) bit to 0 + truncation caused by the switching chip.

[0044] Action: Change the CSIG do not modify bit in the message to 1.

[0045] 8) ACL rule 22 Matching conditions: Match the TPID of the wide CISG in the message header + CISG (do not modify the bit to 0) + truncation caused by the switching chip.

[0046] Action: Change the CSIG do not modify bit in the message to 1.

[0047] If the bit width limitation of the ACL's custom fields prevents the complete extraction of the csig.s signal value from a wide CSIG tag, you can extract only the high x bits of csig.s and compare them with the high x bits of the threshold. Simultaneously, the ACL action should still modify the 20 bits of csig.s to the threshold. This will introduce measurement bias, with a maximum bias of [value missing]. .

[0048] like Figures 1-3 As shown, in S3, the switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to ACL rules. Specifically, when a data packet arrives at the switch port, the switching chip's hardware data plane performs the following operations: 1) Use the custom offset of ACL to parse the packet header, extract the CSIG signal field (including signal type csig.t, signal value csig.s, do not modify bit csig.d), and extract the queue number i for internal forwarding of the packet.

[0049] 2) Match the packets with the ACL rules: If the CSIG signal type in the message is min(ABW), and the signal value of this type is greater than the threshold in the current ACL rule (i.e., the M value written by the CPU), then... ABW If the rule is met, and the internal pipeline of the switching chip is not interrupted, and csig.d is 0, then the rule is hit. Otherwise, the modification action is not executed.

[0050] If the CSIG signal type in the message is min(ABW / C), and the signal value of this type is greater than the threshold in the current ACL rule (i.e., the M value written by the CPU), then... ABW / C If the rule is met, and the internal pipeline of the switching chip is not interrupted, and csig.d is 0, then the rule is hit. Otherwise, the modification action is not executed.

[0051] If the CSIG signal type in the message is max(nQD), and the signal value of this type is greater than the threshold in the current ACL rule (i.e., the M value written by the CPU), then... nQD[i] If the queue number i matches, the pipeline inside the switching chip is not interrupted, and csig.d is 0, then the rule is hit. Otherwise, no modification action is performed. If the port has n queues, n ACLs matching signal type max(nQD) will be issued, where i takes values ​​in the range [0, n-1].

[0052] If the csig.d value of CSIG in the message is 0, and the pipeline inside the switching chip is truncated, then the rule is hit. Otherwise, no modification is performed.

[0053] 3) If the rule is matched, the hardware will overwrite the CSIG signal value field in the message with the threshold (M) configured in the ACL rule. ABW Or M ABW / C Or M nQD[i] Alternatively, you can replace the csig.lm field with the identification information of the port of this switch, or simply set the csig.d field to 1.

[0054] 4) The message continues to be forwarded normally.

[0055] like Figure 1 As shown, in S4, the CPU repeatedly executes the above steps at a set time interval (e.g., 1ms) to update the threshold field of the ACL rule and the csig.s signal value of the action, so that the comparison value in the ACL rule reflects the latest available bandwidth, normalized available bandwidth and normalized queue depth of each port in real time.

[0056] As described above, according to an embodiment of the present invention, a hardware-software co-operated CSIG backward compatibility implementation method achieves backward compatibility by utilizing the ACL function commonly supported by existing switches. Through CPU-assisted calculation and dynamic updating of ACL thresholds, older devices that do not support CSIG hardware updates can also participate in local correction of congestion signals, thus realizing the gradual deployment of CSIG in the existing network.

[0057] The above combined with the appendix Figures 1-3 A method for implementing CSIG backward compatibility through hardware and software collaboration according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to an apparatus for implementing CSIG backward compatibility through hardware and software collaboration.

[0058] like Figure 4 As shown, according to a second aspect of the present invention, a hardware-software co-operated CSIG backward compatibility implementation apparatus is provided, comprising: The data acquisition and calculation module 100 is used for the CAU to periodically collect statistical information of each port of the switch, and to calculate the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] of each port based on the statistical information. The mapping and writing module 200 is used to map the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] to the corresponding quantization threshold M according to a preset mapping table. ABW M ABW / C M nQD[i] And write the quantization threshold into the threshold field of the corresponding ACL rule; The matching and modification module 300 is used by the switching chip to match and modify packets carrying CSIG signals through each port according to ACL rules; The repeat update module 400 is used by the CPU to repeatedly execute the above steps at set time intervals to update the threshold field of the ACL rule, so that the comparison value in the ACL rule reflects the latest available bandwidth, normalized available bandwidth and normalized queue depth of each port in real time.

[0059] The above combined with the appendix Figure 4 A hardware-software co-operational CSIG backward compatibility implementation apparatus according to an embodiment of the present invention is described. Furthermore, the present invention can also be applied to an electronic device.

[0060] According to a third aspect of the present invention, an electronic device is provided, comprising: a memory 1, a processor 2, and a computer program 3, wherein the computer program 3 is stored in the memory 1, and the processor 2 executes the computer program 3 to perform a hardware-software co-operation CSIG backward compatibility implementation method of the first aspect.

[0061] According to a fourth aspect of the present invention, a computer-readable medium having processor-executable non-volatile program code is provided, the program code causing the processor to perform a hardware-software co-operated CSIG backward-compatible implementation method of the first aspect.

[0062] The readable storage medium can be a computer storage medium or a communication medium. A communication medium includes any medium that facilitates the transfer of a computer program from one location to another. A computer storage medium can be any available medium accessible to a general-purpose or special-purpose computer. For example, a readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the ASIC can reside within a device. Of course, the processor and the readable storage medium can also exist as discrete components in a communication device. The readable storage medium can be a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc. The present invention also provides a program product comprising executable instructions stored in the readable storage medium. At least one processor of the device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions, causing the device to implement a hardware-software co-operational CSIG backward-compatible implementation method provided by the various embodiments described above. In the embodiments of the above-described device, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0063] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for implementing CSIG backward compatibility in a hardware-software co-design, characterized in that, It includes the following steps: The CPU periodically collects statistical information from each port of the switch and calculates the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] for each port based on the statistical information. The available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] are mapped to the corresponding quantization threshold M according to the preset mapping table. ABW M ABW / C M nQD[i] And write the quantization threshold into the threshold field of the corresponding ACL rule; The switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to ACL rules; The CPU repeats the above steps at set time intervals to update the threshold field of the ACL rules, so that the comparison values ​​in the ACL rules reflect the latest available bandwidth, normalized available bandwidth and normalized queue depth of each port in real time.

2. The CSIG backward compatibility implementation method with hardware and software collaboration as described in claim 1, characterized in that, The statistical information includes: The number of bytes TX sent by the port in the time interval delta_t bytes The number of packets TX Packets and the queue depth of each queue of the port Queue_depth[i] The physical transmit bandwidth C of the port; Port preamble and inter-frame gap (IFG) length configuration.

3. The method of claim 2, wherein the CSIG backward compatible implementation of the software and hardware co-design is characterized by, The formulas for calculating available bandwidth, normalized available bandwidth, and normalized queue depth are as follows: Used bandwidth U = (8 * (TX bytes + (Preamble + IFG) * TX Packets )) / delta_t, U rounded up Available bandwidth ABW=CU; Normalized available bandwidth ABW / C = 100 * (1 - U / C), where ABW / C is an integer; The normalized queue depth nQD[i] = Queue_depth[i] / C, where nQD[i] is an integer.

4. The method of claim 3, wherein the CSIG backward compatible implementation of the software and hardware co-design is characterized by, The used bandwidth U is smoothed using an exponentially weighted moving average algorithm.

5. The method of claim 1, wherein the CSIG backward compatible implementation of the software and hardware co-design is characterized by, The preset mapping table is divided into a compact CISG or a wide CISG mapping table.

6. The CSIG backward compatibility implementation method with hardware and software collaboration as described in claim 5, characterized in that, In the compact CSIG tag, the csig.s field is 5 bits, and the ABW, ABW / C and nQD[i] values are divided into buckets according to a preset compact mapping table to obtain quantization thresholds; In the wide type CSIG tag, the csig.s field is 20 bits, and the ABW, ABW / C and nQD[i] values are divided into quantized threshold values according to a preset wide type mapping table in a uniform quantization manner. The quantization threshold M ABW M ABW / C M nQD[i] The values ​​are determined based on the quantization values ​​in the corresponding mapping tables.

7. The method of claim 1, wherein the CSIG backward compatible implementation of the software and hardware co-design is characterized by, The switching chip performs matching and modification on packets carrying CSIG signals passing through each port according to ACL rules, specifically as follows: Parse the packet header using the custom offset of the ACL, extract the CSIG signal field, and extract the queue number i for forwarding within the packet. The CSIG signal field includes the signal type csig.t, signal value csig.s, do not modify bit csig.d, and locator metadata csig.lm. If the CSIG signal type is min(ABW), then the signal value csig.s > M. ABW If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. ABW And set csig.lm; If the CSIG signal type is min(ABW / C), then the signal value csig.s > M. ABW / C If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. ABW / C And set csig.lm; If the CSIG signal type is max(nQD), the message exit queue number is i, and the signal value is csig.s <M nQD[i] If csig.d=0, the message is not truncated, then the signal value csig.s is modified to M. nQD[i] And set csig.lm; If csig.d=0 and the message is truncated, then set csig.d to 1.

8. A hardware-software co-operated CSIG backward compatibility implementation device, characterized in that, Include: The data acquisition and calculation module is used by the CPU to periodically collect statistical information of each port of the switch, and calculate the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] of each port based on the statistical information. The mapping and writing module is used to map the available bandwidth ABW, normalized available bandwidth ABW / C, and normalized queue depth nQD[i] to the corresponding quantization threshold M according to a preset mapping table. ABW M ABW / C M nQD[i] And write the quantization threshold into the threshold field of the corresponding ACL rule; The matching and modification module is used by the switching chip to match and modify packets carrying CSIG signals passing through each port according to ACL rules; The repeated update module is used by the CPU to repeatedly execute the above steps at set time intervals to update the threshold field of the ACL rules, so that the comparison values ​​in the ACL rules reflect the latest available bandwidth, normalized available bandwidth and normalized queue depth of each port in real time.

9. An electronic device, comprising: include: The system includes a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor executes the computer program to perform a hardware-software co-operation CSIG backward compatibility implementation method according to any one of claims 1 to 7.

10. A computer readable medium having non-transitory program code executable by a processor, the program code comprising instructions for: The program code causes the processor to run the CSIG backward compatibility implementation method of hardware and software collaboration as described in any one of claims 1-7.

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