A method for battery master-slave cluster address identification and allocation and a battery management system

Abstract

This invention proposes a battery master-slave cluster address identification and allocation method, comprising: each master control board determining the master cluster from multiple battery clusters by detecting the input signal of the previous master control board and the output signal of the current master control board, and combining random delay and weighted scoring of battery cluster control factor indicators, and designating the remaining battery clusters as slave clusters; the master control board of the master cluster broadcasts a reset command through the communication bus to restore the addresses of all slave cluster master control boards to default values; the master control board of the master cluster sequentially sends address encoding information to each slave cluster master control board through the communication bus, and controls the current slave cluster master control board to send an activation signal through its output signal terminal according to the unidirectional link sequence, so as to activate the input signal terminal of the next slave cluster master control board, until all slave clusters have completed address allocation. This method achieves fully automatic and highly robust battery cluster address identification and allocation without the need for a fixed master control module by dynamically electing the master cluster and a serial allocation mechanism that binds the address to the physical location.

Description

Technical Field

[0001] This invention relates to the field of battery cluster address allocation, and more particularly to a battery master-slave cluster address identification and allocation method and a battery management system. Background Technology

[0002] In large-scale energy storage systems such as industrial and commercial energy storage and containerized energy storage, the number of batteries is enormous, and a three-level battery cluster architecture is typically used for management: the first level is the slave control board, with each battery pack having its own BMS slave control board responsible for monitoring cell voltage, temperature, etc.; the second level is the master control board, with each battery cluster having its own BMS master control board responsible for managing the entire cluster and communicating with the upper layer; the third level is the master control board, which exchanges data with each master control board via a CAN bus, and the master control board assigns addresses to the master control boards. Within the cluster, address allocation between the master control board and the slave control board can be achieved using physical hard-coded DIP switches, CAN line daisy-chaining, or resistor voltage divider encoding.

[0003] Existing technologies rely on a fixed and pre-set master control module to complete the address allocation of all slave devices. The master control role cannot be dynamically changed according to the real-time status of battery health, temperature, etc. Once the performance of the fixed master control module degrades or fails, the address management of the entire system will be paralyzed, and it will be unable to automatically switch to a better slave device to take over as master control. This results in poor system robustness, high maintenance costs, and difficulty in adapting to the dynamic changes of battery clusters in the energy storage system. Summary of the Invention

[0004] In view of this, the present invention proposes a battery master-slave cluster address identification and allocation method and a battery management system. By dynamically electing the master cluster and using a serial allocation mechanism that binds the address to the physical location, fully automatic and robust battery cluster address identification and allocation can be achieved without a fixed master control module.

[0005] The technical solution of this invention is implemented as follows: Firstly, this invention provides a method for battery master-slave cluster address identification and allocation. The battery management system includes multiple battery clusters, each battery cluster having a master control board. The master control boards are interconnected via a communication bus, and the output signal terminals and input signal terminals of each master control board are sequentially connected in series to form a unidirectional link. The method includes the following steps: S1, each main control board determines the main cluster from multiple battery clusters by detecting the input signal of the previous main control board and the output signal of the current main control board, and combines the random delay and the weighted score of the battery cluster control factor index, and regards the remaining battery clusters as slave clusters. S2, the master control board of the main cluster broadcasts a reset command through the communication bus to restore the addresses of all slave master control boards to their default values; S3, the master control board of the master cluster sends address encoding information to each slave cluster master control board in sequence through the communication bus, and controls the current slave cluster master control board to send an activation signal through its output signal terminal according to the order of the unidirectional link, so as to activate the input signal terminal of the next slave cluster master control board, until all slave clusters have completed address allocation; S4. After the address allocation is completed, each slave cluster master board will save the allocated address to non-volatile memory.

[0006] Based on the above technical solutions, preferably, step S1 includes the following steps: Each main control board generates a random delay after power-on and continuously detects whether there is a valid activation signal at its input signal terminal during the delay period; After the random delay ends, if a valid activation signal has been detected at the input signal terminal, the current main control board is marked as a candidate for slave cluster and no activation signal is output; if no valid activation signal is detected at the input signal terminal, the current main control board sends an activation signal through the output signal terminal and performs output retrieval monitoring. The activation signal is a digital modulation signal. The amplitude and frequency of the digital modulation signal are detected simultaneously. When the amplitude is within a first preset range and the frequency is within a second preset range, the activation signal is determined to be valid. If the activation signal from the output acquisition monitoring is valid, and no valid activation signal is received at the input signal terminal within the subsequent preset time window, then the current main control board will be determined as the main cluster candidate. If a valid activation signal is detected at the input signal terminal after the output activation signal is output, the current master control board will be switched to slave cluster mode.

[0007] Based on the above technical solutions, preferably, step S1 further includes determining the number of primary cluster candidates: If there is only one candidate for master cluster, the current candidate will be directly elected as the master cluster and will broadcast a master cluster declaration message through the communication bus, and the remaining battery clusters will become slave clusters. If there are multiple candidate main clusters, the comprehensive score of each candidate main cluster is calculated based on the weighted average of the battery cluster control factor indicators. The battery cluster with the highest comprehensive score is selected as the main cluster. If the highest scores are tied, the main cluster is determined according to the preset rules.

[0008] Based on the above technical solutions, preferably, the step of calculating the comprehensive score of each candidate main cluster based on the weighted average of battery cluster control factor indicators, and selecting the battery cluster with the highest comprehensive score as the main cluster, and determining the main cluster according to preset rules if the highest scores are tied, includes the following sub-steps: Obtain the physical location sequence number of each main cluster candidate in the unidirectional link and the maximum number of clusters configured by the battery management system. Calculate the first difference by subtracting 1 from the physical location sequence number of each main cluster candidate in the unidirectional link. Divide the first difference by the maximum number of clusters to obtain the first quotient. Subtract the first quotient from 1 to obtain the physical location score corresponding to each main cluster candidate. Obtain the percentage value of cell health corresponding to each main cluster candidate, divide the percentage value of cell health by 100, and get the cell health score corresponding to each main cluster candidate. Obtain the average intra-cluster temperature of each candidate main cluster. Preset the optimal temperature baseline value and the temperature allowable deviation threshold. Calculate the absolute value of the difference between the average intra-cluster temperature of each candidate main cluster and the optimal temperature baseline value to obtain the second difference value. Divide the second difference value by the temperature allowable deviation threshold value to obtain the second quotient value. Subtract the second quotient value from 1 to obtain the preliminary temperature score. When the preliminary temperature score is less than zero, the temperature score of the current candidate main cluster is assigned to 0; otherwise, the temperature score is equal to the preliminary temperature score. Obtain the total cluster voltage and nominal cluster voltage of each candidate main cluster. Calculate the absolute value of the difference between the total cluster voltage and the nominal cluster voltage to obtain the third difference value. Divide the third difference value by the nominal cluster voltage to obtain the third quotient value. Subtract the third quotient value from 1 to obtain the voltage score. Obtain the cumulative running hours of each primary cluster candidate and the preset total reference running time for the entire life cycle. Divide the cumulative running hours of each primary cluster candidate by the total reference running time to obtain the fourth quotient. Subtract the fourth quotient from 1 to obtain the preliminary running time score. If the preliminary running time score is less than zero, the running time score is 0; otherwise, the running time score is equal to the preliminary running time score. Based on the preset weighting coefficients of each indicator, the scores for physical location, cell health, temperature, voltage, and runtime are weighted and summed to obtain the comprehensive score of the corresponding main cluster candidate. Compare the overall scores of all candidate main clusters and select the battery cluster with the highest overall score as the main cluster. If multiple candidates have the same highest overall score, prioritize comparing the cell health scores of the candidates with the same main cluster. The one with the higher cell health score is selected as the main cluster. If the cell health scores are tied, compare the physical location scores of the candidates with the same main cluster and select the one with the higher physical location score as the main cluster.

[0009] Based on the above technical solutions, preferably, step S3 includes the following sub-steps: S31, the master control board of the master cluster broadcasts a first address allocation command through the communication bus. The first address allocation command includes the first slave cluster address and requires only the slave cluster master control board that has not received a valid activation signal at the input signal terminal and whose current address is the default value to respond. S32, after the slave cluster master control board that meets the conditions receives the first address allocation command, it sets its own address to the first slave cluster address and replies with an acknowledgment message to the master cluster through the communication bus; S33, after receiving the confirmation, the master control board of the master cluster sends an activation enable command to the current slave master control board with the assigned address through the communication bus. The current slave master control board sends an activation signal through its output signal terminal according to the command to activate the input signal terminal of the next slave master control board. S34, the master control board of the master cluster broadcasts the next address allocation command through the communication bus. The next address allocation command includes the incremented address of the next slave cluster and requires the slave cluster master control board to respond when the input signal terminal has received a valid activation signal and the current address is still the default value. S35, repeat steps S33 to S34, sequentially assigning continuously increasing addresses to each slave cluster master control board until the master cluster master control board does not receive any slave cluster response to the address allocation command within a preset time, or determines that the link end has been reached by detecting the retrieval signal at its output signal terminal, or confirms that there are no more slave clusters through the CAN bus heartbeat mechanism, then the allocation is determined to be over.

[0010] Based on the above technical solutions, preferably, step S4 specifically includes: S41, after each slave cluster master control board obtains the assigned address, it performs XOR encryption on the assigned address and the dynamically generated key to generate an encrypted address, and calculates the CRC check code of the encrypted address. S42, write the encrypted address and the corresponding CRC checksum into the non-volatile memory; S43, when the system is powered on again after a power outage, each cluster master control board reads the encrypted address and CRC check code from the non-volatile memory, decrypts it using the same key to obtain the assigned address, and recalculates the check code; S44. If the recalculated checksum matches the stored checksum, the decrypted address is used to enter normal working state. If the checksums do not match, the address is restored to the default value and a new address is requested.

[0011] Based on the above technical solution, preferably, it also includes step S5, where each main control board periodically calculates its own comprehensive score. If the comprehensive score of the current main cluster is lower than the comprehensive score of any slave cluster and the difference exceeds a preset threshold, or if the current main cluster experiences communication loss or protection action failure, then a master-slave cluster switch is performed and the address is reassigned, including the following sub-steps: S51, when the main control board of the current main cluster detects that the switching conditions are met, it broadcasts a main cluster switching announcement message through the communication bus, releases control, and stops sending activation signals through its output signal terminal; S52: After all master control boards of the slave clusters hear the switchover announcement message, they pause the address allocation request, keep the current address unchanged, and wait for the new master cluster to be generated; S53, the master control board of each slave cluster calculates the comprehensive score of each candidate master cluster based on the weighted index of the battery cluster control factors, and broadcasts the score through the communication bus. The slave cluster with the highest comprehensive score automatically becomes the new master cluster, and the master control board of the new master cluster broadcasts the master cluster switching declaration message through the communication bus. S54, if the new master cluster can obtain the address mapping table stored in the original master cluster through the communication bus, it inherits the valid address allocation in the mapping table, compares the current physical link order, and identifies the newly added slave clusters, failed slave clusters, and slave clusters with address conflicts; it only allocates new addresses to the identified newly added slave clusters, reallocates unique addresses to slave clusters with address conflicts, and marks the addresses of failed slave clusters as empty, without interrupting slave clusters that are running normally and without conflicts; if the address mapping table of the original master cluster cannot be obtained, or if a failure occurs during the local readdressing process, the new master cluster performs address reallocation; After the address reassignment is completed, the main control board of the new primary cluster broadcasts the address completion message through the communication bus, and the system resumes normal operation.

[0012] Secondly, the present invention also provides a battery management system, including multiple battery clusters, each battery cluster having a main control board, the main control boards being interconnected via a communication bus, and the output signal terminals and input signal terminals of each main control board being connected in series to form a unidirectional link, the main control board integrating a DIO circuit, the DIO circuit including: The input interface is used to receive the activation signal sent by the previous main control board; The output interface is used to send an activation signal to the next-level main control board. The input terminal of the digital input detection circuit is electrically connected to the input interface, and the output terminal of the digital input detection circuit is electrically connected to the microcontroller of the main control board. It is used to detect the input activation signal and generate an input feedback signal to be sent to the microcontroller of the main control board. The input terminal of the digital output drive circuit is electrically connected to the PWM output terminal of the microcontroller on the main control board, and the output terminal of the digital output drive circuit is electrically connected to the output interface. It is used to output a PWM signal as an activation signal according to the instructions of the microcontroller. The input terminal of the output feedback circuit is electrically connected to the output interface, and the output terminal of the output feedback circuit is electrically connected to the microcontroller. It is used to collect the amplitude feedback signal and frequency feedback signal of the output activation signal and send them to the microcontroller.

[0013] Thirdly, the present invention also provides a terminal device, the terminal device comprising: a memory, a processor, and a battery cluster address identification and allocation method program stored in the memory and executable on the processor, the battery cluster address identification and allocation method program being configured to implement the steps of the battery cluster address identification and allocation method.

[0014] Fourthly, the present invention also provides a computer-readable storage medium storing a battery cluster address identification and allocation method and system program, wherein the battery cluster address identification and allocation method program is executed to implement the battery cluster address identification and allocation method.

[0015] The battery master-slave cluster address identification and allocation method and battery management system of the present invention have the following advantages over the prior art: (1) By combining a unidirectional link serial structure with a random delay competition and a weighted scoring mechanism of control factors, the battery cluster can complete the master-slave election autonomously and without conflict after power-on without the need for preset address, thus improving the accuracy of address allocation; the master cluster allocates addresses to the slave clusters in a chain activation manner according to the physical order of the unidirectional link, and the allocation process is deterministic and orderly, thus improving the reliability of address allocation; after the address allocation is completed, it is solidified to non-volatile memory to ensure that the address is not lost after power failure and can be used directly after power-on, thus improving the persistence of address allocation and system operating efficiency; (2) By simultaneously detecting the level amplitude and frequency of the activation signal, the validity of the signal is determined by digital modulation, effectively filtering out link noise interference, avoiding the main control board from incorrectly switching the master-slave mode due to false detection, and improving the accuracy of master cluster election; (3) By comprehensively considering five dimensions—physical location, cell health, cluster temperature, total cluster voltage, and cumulative operating time—the candidate main clusters are weighted and scored to ensure that the selected main cluster is the battery cluster with the best overall condition, which is conducive to balancing the load of each cluster and extending the overall lifespan of the system. (4) When the master cluster fails, it supports re-election among slave clusters and inheritance of the valid address mapping table. It only reassigns addresses to newly added or conflicting slave clusters without interrupting normally operating slave clusters, thus improving the fault tolerance and operational continuity of the system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the battery master-slave cluster address identification and allocation method of the present invention; Figure 2 This is a single DIO circuit diagram of the battery management system of the present invention; Figure 3 This is a circuit diagram of the overall architecture of the battery management system of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, the present invention provides a battery master-slave cluster address identification and allocation method applicable to large-scale energy storage systems such as industrial and commercial energy storage and containerized energy storage. The battery management system includes multiple battery clusters, each of which is equipped with a master control board. The master control boards are interconnected through a communication bus to realize data exchange and command broadcasting. At the same time, the output signal terminals and input signal terminals of each master control board are connected in series to form a unidirectional link. This link is used to transmit activation signals to determine the physical order and auxiliary address allocation.

[0020] The method includes the following steps: S1, each main control board determines the main cluster from multiple battery clusters by detecting the input signal of the previous main control board and the output signal of the current main control board, and by combining the random delay and the weighted score of the battery cluster control factor index, and regards the remaining battery clusters as slave clusters.

[0021] Step S1 includes the following steps: Each main control board generates a random delay after power-on and continuously detects whether there is a valid activation signal at its input signal terminal during the delay period; Specifically, after the system is powered on, all main control boards enter the initial state: stop outputting any activation signals, clear their own master / slave cluster identifiers, and start listening to their input signal terminals; each main control board independently generates a random delay, such as a random number evenly distributed in the range of 0~500ms. This random delay is used to stagger the preemption time of each main control board to avoid link conflicts caused by multiple main control boards sending activation signals at the same time. During the delay, each main control board continuously detects whether there is a valid activation signal at its input signal terminal.

[0022] After the random delay ends, if a valid activation signal has been detected at the input signal terminal, the current main control board is marked as a candidate for slave cluster and no activation signal is output; if no valid activation signal is detected at the input signal terminal, the current main control board sends an activation signal through the output signal terminal and performs output retrieval monitoring. Specifically, if a valid activation signal is detected at the input signal terminal, it indicates that during its waiting period, a cluster that is earlier or has a shorter delay has issued an activation signal. The main control board abandons the competition, automatically marks itself as a candidate for a slave cluster, enters a slave cluster standby state, and does not output any activation signal. This ensures that only one cluster is dominant on the link. If no valid activation signal is detected at the input signal terminal, the main control board assumes that it may be the earliest or the fastest to preempt, and thus issues an activation signal through its output signal terminal. At the same time, it starts output retrieval monitoring. Output retrieval refers to the real-time detection of the amplitude and frequency of the output signal through internal circuitry to ensure that the actual emitted signal meets expectations. If the retrieval is normal, it indicates that the output circuit and wiring harness are working well.

[0023] The activation signal is a digital modulation signal. The amplitude and frequency of the digital modulation signal are detected simultaneously. When the amplitude is within a first preset range and the frequency is within a second preset range, the activation signal is determined to be valid. It should be noted that the activation signal in this invention is a digital modulation signal, preferably a PWM signal. Unlike the simple high and low levels used in the prior art, this scheme simultaneously detects the amplitude and frequency of the activation signal. It is only considered valid when both fall within a preset range. This dual detection mechanism has the advantages of strong anti-interference capability, support for long-distance transmission and diagnostic functions. It is difficult for external noise to accurately imitate a specific amplitude and frequency at the same time. A certain degree of cable voltage drop can be tolerated by setting a reasonable amplitude range. If the amplitude or frequency deviates from the range, it can be determined that the wiring harness has poor contact, is open-circuited, or the upstream main control board is faulty.

[0024] Specifically, in one embodiment, the parameters of the activation signal are: amplitude 12V, frequency 1kHz, duty cycle 50%, first preset range of 10V~13V, and second preset range of 0.9kHz~1.1kHz. These parameters can be adjusted according to the actual link length and electromagnetic environment.

[0025] If the activation signal from the output acquisition monitoring is valid, and no valid activation signal is received at the input signal terminal within the subsequent preset time window, the current main control board is determined as a candidate for the main cluster; if a valid activation signal is detected at the input signal terminal after the output activation signal, the current main control board is switched to slave cluster mode.

[0026] It should be noted that after issuing the activation signal, the main control board continues to monitor its input signal terminal while maintaining the output activation signal. Within the specified time window, if the following two conditions are met: the output retrieval monitoring remains normal and no valid activation signal is received at the input signal terminal, then the main control board becomes a primary cluster candidate. Conversely, if a valid activation signal is detected at the input signal terminal within the preset time window after issuing the activation signal, it indicates that another candidate has appeared in the link. The main control board immediately withdraws from the competition and switches to slave cluster mode. This mechanism ensures that under any circumstances, at most one primary cluster candidate is active on the link.

[0027] Step S1 also includes determining the number of primary cluster candidates: If there is only one candidate for master cluster, the current candidate will be directly elected as the master cluster and will broadcast a master cluster declaration message through the communication bus, and the remaining battery clusters will become slave clusters. If there are multiple candidate main clusters, the comprehensive score of each candidate main cluster is calculated based on the weighted average of the battery cluster control factor indicators. The battery cluster with the highest comprehensive score is selected as the main cluster. If the highest scores are tied, the main cluster is determined according to the preset rules.

[0028] Specifically, it includes the following sub-steps: Obtain the physical location index of each primary cluster candidate within the unidirectional link and the maximum number of clusters configured by the battery management system. Calculate the first difference by subtracting 1 from the physical location index of each primary cluster candidate within the unidirectional link. Divide the first difference by the maximum number of clusters to obtain the first quotient. Subtract the first quotient from 1 to obtain the physical location score corresponding to each primary cluster candidate. The expression is: ; In the formula, N max The maximum number of clusters, n This represents the physical location number of the current primary cluster candidate within the unidirectional link. The earlier the location, the higher the score. This aligns with engineering experience that clusters closer to the power supply inlet or junction point in the energy storage system are more suitable to serve as primary clusters.

[0029] Obtain the percentage value of cell health corresponding to each main cluster candidate, divide the percentage value of cell health by 100, and get the cell health score corresponding to each main cluster candidate. It should be noted that the percentage value of cell health status (SOH) is directly divided by 100. SOH is a key indicator for measuring the degree of battery aging, with a value range of 0 to 1. The higher the health status of the cell, the better the long-term operational reliability, so it is given the highest weight.

[0030] Obtain the average intra-cluster temperature of each candidate main cluster. Preset an optimal temperature baseline and a temperature tolerance threshold. Calculate the absolute value of the difference between the average intra-cluster temperature of each candidate main cluster and the optimal temperature baseline to obtain a second difference value. Divide the second difference value by the temperature tolerance threshold to obtain a second quotient value. Subtract the second quotient value from 1 to obtain a preliminary temperature score. When the preliminary temperature score is less than zero, the temperature score of the current candidate main cluster is assigned a value of 0; otherwise, the temperature score equals the preliminary temperature score. The expression is: ; In the formula, T The average temperature within the candidate master cluster is 30, with 30 being the optimal baseline temperature and 50 being the allowable temperature deviation threshold. The unit "°C" has been removed; meaning the closer the temperature is to 30°C, the higher the score. A deviation exceeding 50°C results in a score of 0, preventing overheated or overcooled clusters from becoming master clusters. P temp A preliminary score is given for the temperature.

[0031] Obtain the total cluster voltage and nominal cluster voltage for each candidate main cluster. Calculate the absolute value of the difference between the total cluster voltage and the nominal cluster voltage to obtain the third difference value. Divide the third difference by the nominal cluster voltage to obtain the third quotient value. Subtract the third quotient value from 1 to obtain the voltage score. The expression is: ; In the formula, P volt Score for voltage. V total This represents the total voltage of the front cluster. V nom The nominal voltage of the cluster is used as the reference. The more stable the voltage is and the closer it is to the nominal value, the higher the score, which is beneficial for selecting the cluster with good voltage consistency as the master cluster.

[0032] Obtain the cumulative runtime of each primary cluster candidate and the preset total lifetime reference runtime. Divide the cumulative runtime of each primary cluster candidate by the total reference runtime to obtain the fourth quotient. Subtract the fourth quotient from 1 to obtain the preliminary runtime score. If the preliminary runtime score is less than zero, the runtime score is 0; otherwise, the runtime score equals the preliminary runtime score. The expression is: P time =max(0,1- t run / t all ); In the formula, P time The runtime score for the primary cluster candidate. t run The cumulative running hours of the primary cluster candidate t allThe preset total runtime of the primary cluster candidate is used as the reference for the entire lifecycle. The shorter the runtime, the higher the score. Newer clusters are selected as primary clusters, which can extend the overall lifecycle of the system.

[0033] Based on the preset weighting coefficients of each indicator, the scores for physical location, cell health, temperature, voltage, and runtime are weighted and summed to obtain the comprehensive score of the corresponding main cluster candidate. Specifically, the weighting coefficients of each indicator can be adjusted according to the actual application scenario. In a preferred embodiment, the weighting is as follows: weight of cell health score. w 2=30%, the weight of the initial temperature score w 3 = 20%, the weight of voltage score w 4 = 20%, the weight of the physical location score w 1 = 15%, weight of runtime score w 5 = 15%; this allocation reflects a strategy that prioritizes health while also considering location and duration.

[0034] The formula for calculating the overall score is: S = w 1 P pos + w 2 SOH + w 3 P temp + w 4 P volt + w 5 P time ; In the formula, P pos The score is the score of the physical location corresponding to the primary cluster candidate. SOH The cell health score corresponding to the main cluster candidate. P temp Preliminary temperature scores corresponding to the primary cluster candidates. P volt The voltage score corresponding to the primary cluster candidate. P time Runtime score for primary cluster candidates.

[0035] Compare the overall scores of all candidate main clusters and select the battery cluster with the highest overall score as the main cluster. If multiple candidates have the same highest overall score, prioritize comparing the cell health scores of the candidates with the same main cluster. The one with the higher cell health score is selected as the main cluster. If the cell health scores are tied, compare the physical location scores of the candidates with the same main cluster and select the one with the higher physical location score as the main cluster.

[0036] Step S1 achieves fully automatic and conflict-free master cluster election among multiple peer battery clusters under the condition of no master control unit by using a two-stage election mechanism that combines random delay preemption with multi-factor weighted scoring. This mechanism not only utilizes random delay to quickly stagger preemption time and avoid link signal conflicts, but also selects the most reliable and suitable master cluster by comprehensively evaluating key indicators such as cell health, temperature, voltage, physical location and running time. This improves the system's self-organization capability, robustness and maintainability in large-scale energy storage scenarios, while reducing hardware costs and manual debugging burden.

[0037] S2, the master control board of the main cluster broadcasts a reset command through the communication bus to restore the addresses of all slave master control boards to their default values; After the primary cluster is successfully elected in step S1, the system enters the address reset phase. The purpose of this step is to clear all old addresses that may remain in the slave cluster master control board and restore them to the preset default address values, creating a clean initial state for subsequent continuous address allocation. Step S2 is initiated by the master control board of the primary cluster and broadcast through the communication bus.

[0038] After confirming its own identity as the primary cluster, the primary cluster's control board constructs an address reset command. This command is a specially defined broadcast message whose message identifier uses the high-priority broadcast address in the system to ensure that all slave clusters can receive it in a timely manner. The payload of the reset command includes the command type, the default address value, and the check field. The command type indicates address reset, the default address value is a preset default address that does not conflict with any normally allocated valid address, and the check field is used for command integrity verification.

[0039] All slave cluster master boards continuously monitor the communication bus. Upon receiving an address reset broadcast command, each slave cluster performs the following operations: Check the command type and verification field, recalculate the verification code and compare it with the received verification field; if they do not match, discard the command. Regardless of whether an activation signal is currently being output, the cluster immediately sets its own output signal to a high-impedance or low-level state and stops emitting any activation signal to ensure that no unexpected signal interference occurs on the unidirectional link during address reset. The address currently stored on the cluster master board will be forcibly changed to the default address value specified in the reset command, and the default address will be written to the address variable at runtime. If the cluster maintains neighbor information or an address mapping table, clear it as well; To ensure that the master cluster knows that the reset operation has been completed, each slave cluster sends an acknowledgment message to the master cluster via the communication bus after successfully performing the address reset. The acknowledgment message contains the unique identifier of the slave cluster (such as the factory serial number or default, so that the master cluster can count it).

[0040] Because the communication bus may experience transient interference or individual slave cluster failures, the master control board of the master cluster will not wait indefinitely, but is designed with a retry mechanism and timeout protection.

[0041] After broadcasting the reset command, the master cluster starts a preset response waiting window. In this window, the master cluster receives acknowledgment messages from all slave clusters. The master cluster can determine whether it has received acknowledgments from all slave clusters based on the initial configuration or the online slave cluster list obtained by scanning the communication bus.

[0042] If not all acknowledgments are received within the specified time, the master cluster will repeatedly broadcast the reset command. A short random backoff time may be added between each retry to avoid bus congestion.

[0043] If some slave clusters still fail to acknowledge after the maximum number of retries has been reached, the master cluster will record the information of these unresponsive slave clusters and report a system fault. In this case, subsequent address allocation steps will only be performed on the acknowledged slave clusters. The unresponsive slave clusters are considered faulty nodes, and the system can continue to run but will issue an alarm.

[0044] To prevent malicious or accidental address resets, a dynamic token can be included in the reset command, or it can be valid only during the initial address allocation phase after power-on. Specifically, the master cluster only sends the reset command during the initial addressing phase after becoming the master cluster; if a slave cluster receives a reset command again during normal system operation, it should ignore it. Furthermore, the reset command uses a high-priority message identifier on the communication bus, dedicated to system management, which will not conflict with ordinary data packets.

[0045] Since the master cluster is dynamically elected, the initiator of the reset command may change at different times. Through acknowledgment messages and retry mechanisms, this invention ensures that the master cluster can grasp the status of all slave clusters in the system, providing a reliable basis for subsequent address allocation. At the same time, stopping the activation signal output action avoids the uncertainty of the link status during the reset period, ensuring a clear starting state of the unidirectional link.

[0046] S3, the master control board of the master cluster sends address encoding information to each slave cluster master control board in sequence through the communication bus, and controls the current slave cluster master control board to send an activation signal through its output signal terminal according to the order of the unidirectional link, so as to activate the input signal terminal of the next slave cluster master control board, until all slave clusters have completed address allocation; Step S3 includes the following sub-steps: S31, the master control board of the master cluster broadcasts a first address allocation command through the communication bus. The first address allocation command includes the first slave cluster address and requires only the slave cluster master control board that has not received a valid activation signal at the input signal terminal and whose current address is the default value to respond. S32, after the slave cluster master control board that meets the conditions receives the first address allocation command, it sets its own address to the first slave cluster address and replies with an acknowledgment message to the master cluster through the communication bus; S33, after receiving the confirmation, the master control board of the master cluster sends an activation enable command to the current slave master control board with the assigned address through the communication bus. The current slave master control board sends an activation signal through its output signal terminal according to the command to activate the input signal terminal of the next slave master control board. S34, the master control board of the master cluster broadcasts the next address allocation command through the communication bus. The next address allocation command includes the incremented address of the next slave cluster and requires the slave cluster master control board to respond when the input signal terminal has received a valid activation signal and the current address is still the default value. S35, repeat steps S33 to S34, sequentially assigning continuously increasing addresses to each slave cluster master control board until the master cluster master control board does not receive any slave cluster response to the address allocation command within a preset time, or determines that the link end has been reached by detecting the retrieval signal at its output signal terminal, or confirms that there are no more slave clusters through the CAN bus heartbeat mechanism, then the allocation is determined to be over.

[0047] Assuming the system has three slave clusters, with the physical order of slave cluster 1, slave cluster 2, and slave cluster 3, the execution flow is as follows: The primary cluster broadcast address is 0x02, and only cluster 1 responds by setting the address to 0x02 and replying with confirmation. The master cluster command outputs an activation signal from cluster 1, sends a PWM signal from the OUT of cluster 1, and receives the signal from the IN of cluster 2; The primary cluster broadcasts at address 0x03, and only cluster 2 responds by setting address 0x03 and replying with confirmation. The master cluster command outputs an activation signal from cluster 2, sends a PWM signal from the OUT of cluster 2, and receives the signal from the IN of cluster 3; The primary cluster broadcasts at address 0x04, and only cluster 3 responds. Set the address to 0x04 and reply with confirmation.

[0048] The master cluster command outputs an activation signal from cluster 3, then broadcasts to address 0x05. If there is no response within the preset timeout, the allocation ends.

[0049] The following abnormal situations may occur during the address allocation process: Cluster response timeout: If no acknowledgment is received within the timeout period after an address allocation command is issued, the primary cluster can resend the command. If there is still no response, the address will be skipped and the next address will be tried, or a fault will be reported.

[0050] Activation signal failure: If the master cluster commands a slave cluster to output an activation signal, and the output retrieval detects that the activation signal of the slave cluster is invalid, the master cluster determines that the slave cluster or link is faulty, records the fault information, and stops subsequent allocation.

[0051] Address conflict: If the master cluster finds that two slave clusters are using the same address in the acknowledgment message, the master cluster broadcasts a reset command and restarts address allocation.

[0052] This embodiment achieves strict binding between address and physical link order by actively broadcasting address allocation commands by the master cluster and combining them with the transmission mechanism of serial activation signals. This ensures that each slave cluster obtains a unique and location-related address, facilitating rapid fault location. At the same time, this mechanism employs multiple end-point judgment methods such as timeout no response, output retrieval, and heartbeat detection, which can adapt to different cluster sizes, support hot-swapping and dynamic expansion, and monitor link status in real time during the activation signal transmission process under the control of the master cluster. This effectively avoids address conflicts and allocation omissions, improving the reliability of address allocation.

[0053] S4. After the address allocation is completed, each slave cluster master board will save the allocated address to non-volatile memory.

[0054] After address allocation for all slave clusters is completed in step S3, the system enters the address persistence stage. The goal of this step is to securely store the address obtained by each slave cluster master board, ensuring that the address is not lost after power failure and preventing external tampering or accidental modification. Step S4 uses a combination of XOR encryption and CRC check to write the address into non-volatile memory, and automatically checks and restores it each time power is restored.

[0055] Specifically, step S4 includes the following sub-steps: S41, after each slave cluster master control board obtains the assigned address, it performs XOR encryption on the assigned address and the dynamically generated key to generate an encrypted address, and calculates the CRC check code of the encrypted address. It should be noted that the dynamically generated key can be a random number or calculated based on the unique identifier of the cluster. Each cluster can hold an independent key. XOR encryption is a lightweight symmetric encryption with fast operation speed, suitable for resource-constrained embedded systems. The CRC checksum is used to detect whether the stored data has bit errors due to power failure, electromagnetic interference, or storage media aging. Before writing, the cluster main control board calculates the CRC value of the encrypted data and stores it together with the encrypted data. When reading, the CRC is recalculated and compared with the stored value. If they match, the data is reliable.

[0056] S42, write the encrypted address and the corresponding CRC checksum into the non-volatile memory; S43, when the system is powered on again after a power outage, each cluster master control board reads the encrypted address and CRC check code from the non-volatile memory, decrypts it using the same key to obtain the assigned address, and recalculates the check code; S44. If the recalculated checksum matches the stored checksum, the decrypted address is used to enter normal working state. If the checksums do not match, the address is restored to the default value and a new address is requested.

[0057] It should be noted that after each system power-on, each slave cluster master control board first executes the address recovery process, which includes: reading the encrypted address and CRC checksum from the non-volatile memory; decrypting it using the local key to obtain the address to be verified; recalculating the CRC of the decrypted address and comparing it with the stored CRC; if they match, the address is used as its current address, and it directly enters the slave cluster working mode; if they do not match, it means that the stored address has been corrupted or tampered with. In this case, the master control board forces its own address to the default value and reports it to the master cluster through the communication bus, and then waits for the master cluster to re-execute the address allocation process.

[0058] In this embodiment, the address is securely stored in non-volatile memory through XOR encryption and CRC check, ensuring the persistent preservation of the address after power failure and preventing external tampering or accidental modification. The automatic verification and recovery mechanism at power-on enables the system to automatically return to the default state and re-apply for the address when encountering storage errors, improving the fault tolerance and security of the system. In addition, the lightweight encryption algorithm is suitable for embedded BMS systems and does not add significant computational overhead.

[0059] It also includes step S5, where each main control board periodically calculates its own comprehensive score. If the comprehensive score of the current main cluster is lower than that of any slave cluster and the difference exceeds a preset threshold, or if the current main cluster experiences communication loss or a protection action failure, then a master-slave cluster switch is performed and addresses are reallocated, including the following sub-steps: S51, when the main control board of the current main cluster detects that the switching conditions are met, it broadcasts a main cluster switching announcement message through the communication bus, releases control, and stops sending activation signals through its output signal terminal; S52: After all master control boards of the slave clusters hear the switchover announcement message, they pause the address allocation request, keep the current address unchanged, and wait for the new master cluster to be generated; S53, the master control board of each slave cluster calculates the comprehensive score of each candidate master cluster based on the weighted index of the battery cluster control factors, and broadcasts the score through the communication bus. The slave cluster with the highest comprehensive score automatically becomes the new master cluster, and the master control board of the new master cluster broadcasts the master cluster switching declaration message through the communication bus. S54, if the new master cluster can obtain the address mapping table stored in the original master cluster through the communication bus, it inherits the valid address allocation in the mapping table, compares the current physical link order, and identifies the newly added slave clusters, failed slave clusters, and slave clusters with address conflicts; it only allocates new addresses to the identified newly added slave clusters, reallocates unique addresses to slave clusters with address conflicts, and marks the addresses of failed slave clusters as empty, without interrupting slave clusters that are running normally and without conflicts; if the address mapping table of the original master cluster cannot be obtained, or if a failure occurs during the local readdressing process, the new master cluster performs address reallocation; After the address reassignment is completed, the main control board of the new primary cluster broadcasts the address completion message through the communication bus, and the system resumes normal operation.

[0060] In this embodiment, dynamic optimization of the primary cluster role is achieved through periodic comprehensive score evaluation and fault detection. The primary cluster can be automatically switched to a secondary cluster with higher battery health and a better operating environment, which improves the long-term reliability and self-healing capability of the system. At the same time, the use of address inheritance and local readdressing strategy reduces interference to normal secondary clusters during the switching process, avoids service interruption caused by full reset, and improves system availability. In addition, full reassignment as an alternative solution ensures system recoverability in extreme cases.

[0061] like Figure 2 and Figure 3 As shown, in a second aspect, the present invention also provides a battery management system, including multiple battery clusters, each battery cluster having a main control board, the main control boards being interconnected via a communication bus, and the output signal terminals and input signal terminals of each main control board being connected in series to form a unidirectional link, the main control board integrating a DIO circuit, the DIO circuit including: The input interface is used to receive activation signals from the previous main control board; The output interface is used to send an activation signal to the next-level main control board; The input terminal of the digital input detection circuit is electrically connected to the input interface, and the output terminal of the digital input detection circuit is electrically connected to the microcontroller of the main control board. It is used to detect the input activation signal and generate an input feedback signal to be sent to the microcontroller of the main control board. Specifically, the digital input detection circuit includes resistors R1, R2, and R3, and transistor Q1. One end of the input interface is grounded, and the other end is electrically connected to resistor R1. The other end of resistor R1 is electrically connected to one end of resistor R2 and the base of transistor Q1. The collector of transistor Q1 is connected to a +5V power supply, and the emitter of transistor Q1 is electrically connected to the input terminal IN_FB of the microcontroller on the main control board and resistor R3. The other end of resistor R3 and the other end of resistor R2 are grounded together.

[0062] The input terminal of the digital output drive circuit is electrically connected to the PWM output terminal of the microcontroller on the main control board, and the output terminal of the digital output drive circuit is electrically connected to the output interface, which is used to output a PWM signal as an activation signal according to the instructions of the microcontroller. Specifically, the digital output drive circuit includes resistors R4 and R5, transistors Q2 and Q3. The PWM output terminal DO_Ctr of the microcontroller on the main control board is electrically connected to the base of transistor Q2. The emitter of transistor Q2 is electrically connected to one end of the output interface. The collector of transistor Q2 is electrically connected to resistor R4. The other end of resistor R4 is electrically connected to resistor R5 and the base of transistor Q3. The other end of resistor R5 and the emitter of transistor Q3 are connected to a +12V power supply. The collector of transistor Q3 is electrically connected to the other end of the output interface.

[0063] In this embodiment, the activation signal is a PWM signal with an amplitude of 12V, a frequency of 1kHz, and a duty cycle of 50%. The activation enable command includes the duration of continuous output of the activation signal, or requires continuous output from the cluster main control board until a stop command is received.

[0064] The input terminal of the output feedback circuit is electrically connected to the output interface, and the output terminal of the output feedback circuit is electrically connected to the microcontroller. It is used to collect the amplitude feedback signal and frequency feedback signal of the output activation signal and send them to the microcontroller.

[0065] Specifically, the output feedback circuit includes resistors R6 and R7. The collector of the transistor Q3 is electrically connected to resistor R6. The other end of resistor R6 is electrically connected to resistor R7, amplitude feedback signal terminal DO_FB, and frequency feedback signal terminal DO_PWM, respectively. The other end of resistor R7 is grounded.

[0066] This DIO circuit uses discrete resistors and transistors to construct input detection, push-pull output, and feedback. The emitter follower at the input stage provides level isolation and conversion, ensuring reliable identification of the activation signal. The push-pull circuit at the output stage provides strong driving capability, ensuring steep edges and long transmission distances for the 12V PWM signal. The feedback circuit simultaneously acquires the amplitude and frequency of the output signal, enabling the microcontroller to diagnose the output status and link integrity in real time, effectively improving the system's anti-interference capability, fault detection capability, and long-term operational reliability.

[0067] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0068] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system and modules described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0069] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0070] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0072] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0073] Furthermore, it should be noted that in the system and method of the present invention, it is obvious that the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent solutions of the present invention. Moreover, the steps performing the above series of processes can naturally be executed in the order described, but are not necessarily required to be executed in chronological order; some steps can be executed in parallel or independently of each other. Those skilled in the art will understand that all or any step or component of the method and apparatus of the present invention can be implemented in any computing device (including processors, storage media, etc.) or network of computing devices, in hardware, firmware, software, or a combination thereof. This is something that those skilled in the art can achieve by using their basic programming skills after reading the description of the present invention.

[0074] Therefore, the object of the present invention can also be achieved by running a program or a set of programs on any computing system. The computing system can be a known general-purpose system. Therefore, the object of the present invention can also be achieved simply by providing a program product containing program code implementing the method or apparatus. That is, such a program product also constitutes the present invention, and the storage medium storing such a program product also constitutes the present invention. Obviously, the storage medium can be any known storage medium or any storage medium developed in the future. It should also be noted that in the apparatus and method of the present invention, it is obvious that the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent to the present invention. Furthermore, the steps performing the above series of processes can naturally be performed in the order described, but are not necessarily required to be performed in chronological order. Some steps can be performed in parallel or independently of each other.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for identifying and allocating master-slave cluster addresses in a battery, characterized in that, The battery management system includes multiple battery clusters, each battery cluster having a main control board. These main control boards are interconnected via a communication bus, and the output and input signal terminals of each main control board are connected in series to form a unidirectional link. The method includes the following steps: S1, each main control board determines the main cluster from multiple battery clusters by detecting the input signal of the previous main control board and the output signal of the current main control board, and combines the random delay and the weighted score of the battery cluster control factor index, and regards the remaining battery clusters as slave clusters. S2, the master control board of the main cluster broadcasts a reset command through the communication bus to restore the addresses of all slave master control boards to their default values; S3, the master control board of the master cluster sends address encoding information to each slave cluster master control board in sequence through the communication bus, and controls the current slave cluster master control board to send an activation signal through its output signal terminal according to the order of the unidirectional link, so as to activate the input signal terminal of the next slave cluster master control board, until all slave clusters have completed address allocation; S4. After the address allocation is completed, each slave cluster master board will save the allocated address to non-volatile memory.

2. The battery master-slave cluster address identification and allocation method as described in claim 1, characterized in that, Step S1 includes the following steps: Each main control board generates a random delay after power-on and continuously detects whether there is a valid activation signal at its input signal terminal during the delay period; After the random delay ends, if a valid activation signal has been detected at the input signal terminal, the current main control board is marked as a candidate for slave cluster and no activation signal is output; if no valid activation signal is detected at the input signal terminal, the current main control board sends an activation signal through the output signal terminal and performs output retrieval monitoring. The activation signal is a digital modulation signal. The amplitude and frequency of the digital modulation signal are detected simultaneously. When the amplitude is within a first preset range and the frequency is within a second preset range, the activation signal is determined to be valid. If the activation signal from the output acquisition monitoring is valid, and no valid activation signal is received at the input signal terminal within the subsequent preset time window, then the current main control board will be determined as the main cluster candidate. If a valid activation signal is detected at the input signal terminal after the output activation signal is output, the current master control board will be switched to slave cluster mode.

3. The battery master-slave cluster address identification and allocation method as described in claim 2, characterized in that, Step S1 also includes determining the number of primary cluster candidates: If there is only one candidate for master cluster, the current candidate will be directly elected as the master cluster and will broadcast a master cluster declaration message through the communication bus, and the remaining battery clusters will become slave clusters. If there are multiple candidate main clusters, the comprehensive score of each candidate main cluster is calculated based on the weighted average of the battery cluster control factor indicators. The battery cluster with the highest comprehensive score is selected as the main cluster. If the highest scores are tied, the main cluster is determined according to the preset rules.

4. The battery master-slave cluster address identification and allocation method as described in claim 3, characterized in that, The process involves calculating the comprehensive score of each candidate main cluster based on the weighted average of battery cluster control factor indicators, selecting the battery cluster with the highest comprehensive score as the main cluster, and determining the main cluster according to preset rules if the highest scores are tied. This includes the following sub-steps: Obtain the physical location sequence number of each main cluster candidate in the unidirectional link and the maximum number of clusters configured by the battery management system. Calculate the first difference by subtracting 1 from the physical location sequence number of each main cluster candidate in the unidirectional link. Divide the first difference by the maximum number of clusters to obtain the first quotient. Subtract the first quotient from 1 to obtain the physical location score corresponding to each main cluster candidate. Obtain the percentage value of cell health corresponding to each main cluster candidate, divide the percentage value of cell health by 100, and get the cell health score corresponding to each main cluster candidate. Obtain the average intra-cluster temperature of each candidate main cluster. Preset the optimal temperature baseline value and the temperature allowable deviation threshold. Calculate the absolute value of the difference between the average intra-cluster temperature of each candidate main cluster and the optimal temperature baseline value to obtain the second difference value. Divide the second difference value by the temperature allowable deviation threshold value to obtain the second quotient value. Subtract the second quotient value from 1 to obtain the preliminary temperature score. When the preliminary temperature score is less than zero, the temperature score of the current candidate main cluster is assigned to 0; otherwise, the temperature score is equal to the preliminary temperature score. Obtain the total cluster voltage and nominal cluster voltage of each candidate main cluster. Calculate the absolute value of the difference between the total cluster voltage and the nominal cluster voltage to obtain the third difference value. Divide the third difference value by the nominal cluster voltage to obtain the third quotient value. Subtract the third quotient value from 1 to obtain the voltage score. Obtain the cumulative running hours of each primary cluster candidate and the preset total reference running time for the entire life cycle. Divide the cumulative running hours of each primary cluster candidate by the total reference running time to obtain the fourth quotient. Subtract the fourth quotient from 1 to obtain the preliminary running time score. If the preliminary running time score is less than zero, the running time score is 0; otherwise, the running time score is equal to the preliminary running time score. Based on the preset weighting coefficients of each indicator, the scores for physical location, cell health, temperature, voltage, and runtime are weighted and summed to obtain the comprehensive score of the corresponding main cluster candidate. Compare the overall scores of all candidate main clusters and select the battery cluster with the highest overall score as the main cluster. If multiple candidates have the same highest overall score, prioritize comparing the cell health scores of the candidates with the same main cluster. The one with the higher cell health score is selected as the main cluster. If the cell health scores are tied, compare the physical location scores of the candidates with the same main cluster and select the one with the higher physical location score as the main cluster.

5. The battery master-slave cluster address identification and allocation method as described in claim 1, characterized in that, Step S3 includes the following sub-steps: S31, the master control board of the master cluster broadcasts a first address allocation command through the communication bus. The first address allocation command includes the first slave cluster address and requires only the slave cluster master control board that has not received a valid activation signal at the input signal terminal and whose current address is the default value to respond. S32, after the slave cluster master control board that meets the conditions receives the first address allocation command, it sets its own address to the first slave cluster address and replies with an acknowledgment message to the master cluster through the communication bus; S33, after receiving the confirmation, the master control board of the master cluster sends an activation enable command to the current slave master control board with the assigned address through the communication bus. The current slave master control board sends an activation signal through its output signal terminal according to the command to activate the input signal terminal of the next slave master control board. S34, the master control board of the master cluster broadcasts the next address allocation command through the communication bus. The next address allocation command includes the incremented address of the next slave cluster and requires the slave cluster master control board to respond when the input signal terminal has received a valid activation signal and the current address is still the default value. S35, repeat steps S33 to S34, sequentially assigning continuously increasing addresses to each slave cluster master control board until the master cluster master control board does not receive any slave cluster response to the address allocation command within a preset time, or determines that the link end has been reached by detecting the retrieval signal at its output signal terminal, or confirms that there are no more slave clusters through the CAN bus heartbeat mechanism, then the allocation is determined to be over.

6. The battery master-slave cluster address identification and allocation method as described in claim 1, characterized in that, Step S4 specifically includes: S41, after each slave cluster master control board obtains the assigned address, it performs XOR encryption on the assigned address and the dynamically generated key to generate an encrypted address, and calculates the CRC check code of the encrypted address. S42, write the encrypted address and the corresponding CRC checksum into the non-volatile memory; S43, when the system is powered on again after a power outage, each cluster master control board reads the encrypted address and CRC check code from the non-volatile memory, decrypts it using the same key to obtain the assigned address, and recalculates the check code; S44. If the recalculated checksum matches the stored checksum, the decrypted address is used to enter normal working state. If the checksums do not match, the address is restored to the default value and a new address is requested.

7. The battery master-slave cluster address identification and allocation method as described in claim 1, characterized in that, It also includes step S5, where each main control board periodically calculates its own comprehensive score. If the comprehensive score of the current main cluster is lower than that of any slave cluster and the difference exceeds a preset threshold, or if the current main cluster experiences communication loss or a protection action failure, then a master-slave cluster switch is performed and addresses are reallocated, including the following sub-steps: S51, when the main control board of the current main cluster detects that the switching conditions are met, it broadcasts a main cluster switching announcement message through the communication bus, releases control, and stops sending activation signals through its output signal terminal; S52: After all master control boards of the slave clusters hear the switchover announcement message, they pause the address allocation request, keep the current address unchanged, and wait for the new master cluster to be generated; S53, the master control board of each slave cluster calculates the comprehensive score of each candidate master cluster based on the weighted index of the battery cluster control factors, and broadcasts the score through the communication bus. The slave cluster with the highest comprehensive score automatically becomes the new master cluster, and the master control board of the new master cluster broadcasts the master cluster switching declaration message through the communication bus. S54, if the new master cluster can obtain the address mapping table stored in the original master cluster through the communication bus, it inherits the valid address allocation in the mapping table, compares the current physical link order, and identifies the newly added slave cluster, the failed slave cluster, and the slave cluster with address conflicts; it only assigns new addresses to the identified newly added slave clusters, reassigns unique addresses to the slave clusters with address conflicts, and marks the addresses of the failed slave clusters as empty, without interrupting the slave clusters that are running normally and without conflicts; If the address mapping table of the original primary cluster cannot be obtained, or if the local readdressing process fails, the new primary cluster will perform address reallocation. After the address reassignment is completed, the main control board of the new primary cluster broadcasts the address completion message through the communication bus, and the system resumes normal operation.

8. A battery management system, characterized in that, It includes multiple battery clusters, each with a main control board. These main control boards are interconnected via a communication bus, and their output and input signal terminals are connected in series to form a unidirectional link. Each main control board integrates a DIO circuit, which includes: The input interface is used to receive the activation signal sent by the previous main control board; The output interface is used to send an activation signal to the next-level main control board. The input terminal of the digital input detection circuit is electrically connected to the input interface, and the output terminal of the digital input detection circuit is electrically connected to the microcontroller of the main control board. It is used to detect the input activation signal and generate an input feedback signal to be sent to the microcontroller of the main control board. The input terminal of the digital output drive circuit is electrically connected to the PWM output terminal of the microcontroller on the main control board, and the output terminal of the digital output drive circuit is electrically connected to the output interface. It is used to output a PWM signal as an activation signal according to the instructions of the microcontroller. The input terminal of the output feedback circuit is electrically connected to the output interface, and the output terminal of the output feedback circuit is electrically connected to the microcontroller. It is used to collect the amplitude feedback signal and frequency feedback signal of the output activation signal and send them to the microcontroller.

9. A terminal device, characterized in that, The terminal device includes: a memory, a processor, and a battery cluster address identification and allocation method program stored in the memory and executable on the processor, the battery cluster address identification and allocation method program being configured to implement the steps of the battery cluster address identification and allocation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a battery cluster address identification and allocation method and system program. When the battery cluster address identification and allocation method program is executed, it implements the battery cluster address identification and allocation method as described in any one of claims 1-7.

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