Video transmission method, system, interface conversion device and electronic device

Abstract

This disclosure provides a video transmission method, system, interface conversion device, and electronic device. The method, applied to an interface conversion device, includes: receiving video data sent by an external camera through a first port of the interface conversion device to obtain multiple image frames; determining a target write area and a target read area based on the read / write states of a first buffer and a second buffer, respectively; for any current image frame among the multiple image frames, saving the current image frame to the target write area and obtaining the previous image frame from the target read area; sending the previous image frame to an external terminal through a second port of the interface conversion device; switching the read / write states of the first buffer and the second buffer, and rereading the image frame in the target read area and sending it to the external terminal based on the switched read / write states of the first buffer and the second buffer, thereby sending the video data to the external terminal.

Description

Technical Field

[0001] This application relates to the field of video transmission technology, and more specifically, to a video transmission method, a video transmission system, an interface conversion device, and an electronic device. Background Technology

[0002] With the rapid development of image sensor technology, high-resolution, high-frame-rate industrial cameras are widely used in machine vision, medical imaging, semiconductor inspection, and other fields. SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock), as an emerging high-speed serial interface standard, has advantages such as high speed, low power consumption, and fewer pins, and has become one of the mainstream interfaces for high-end image sensors. Cameras with SLVS-EC interface can achieve resolutions of 8192×8192 or even higher, frame rates of over 60fps, and single-channel data bandwidth exceeding 40Gbps.

[0003] However, in related technologies, connecting high-speed serial interface cameras to PCs for image evaluation typically requires dedicated image acquisition cards, which are expensive and have long procurement cycles during the R&D and evaluation phases. Furthermore, commercially available acquisition cards supporting new interface standards are scarce, limiting compatibility. In addition, the related solutions have complex hardware architectures, making them unsuitable for rapid prototyping and preliminary evaluation of camera module image performance. Summary of the Invention

[0004] One objective of this application is to provide a new technical solution for video transmission to solve the technical problems of high cost, complex implementation, and poor flexibility in image evaluation of SLVS-EC cameras in related technologies.

[0005] According to a first aspect of this application, a video transmission method is provided, applied to an interface conversion device, the method comprising: The video data sent by an external camera is received through the first port of the interface conversion device to obtain multiple image frames; Based on the read / write states of the first buffer and the second buffer respectively, the target write area and the target read area are determined; wherein, when the first buffer is the target write area, the second buffer is the target read area, and when the first buffer is the target read area, the second buffer is the target write area. For any current image frame among the plurality of image frames, the current image frame is saved to the target write area, and the previous image frame of the current image frame is obtained from the target read area; The previous image frame is sent to an external terminal through the second port of the interface conversion device; The read / write states of the first buffer and the second buffer are switched, and the image frames of the target reading area are reread and sent to the external terminal according to the read / write states of the first buffer and the second buffer after the switch, so as to send the video data to the external terminal.

[0006] Optionally, the first port includes multiple terminals, and the receiving of video data sent by an external camera through the first port of the interface conversion device to obtain multiple image frames includes: The video data sent by an external camera is received through the multiple terminals to obtain multiple serial bit sub-streams; Each serial bit substream is converted into a parallel codeword sequence according to a set time interval, thereby obtaining multiple parallel codeword sequences corresponding to the multiple serial bit substreams; The multiple parallel codeword sequences are aligned between channels to obtain multiple aligned codeword sequences; The multiple aligned codeword sequences are descrambled to obtain multiple descrambled codeword sequences. By parsing the multiple descrambled codeword sequences, multiple valid codeword sequences are obtained; Based on the bits belonging to the same pixel in the multiple valid codeword sequences, determine the pixel grayscale value corresponding to the pixel point, and obtain the pixel grayscale values ​​corresponding to the multiple pixels respectively. Based on the target pixel bit width, the pixel grayscale values ​​corresponding to the multiple pixels are organized into a row-arranged pixel sequence to obtain multiple row-arranged pixel sequences. The multiple row-arranged pixel sequences are concatenated to obtain a complete row sequence; Based on the frame synchronization signal, the line sequence is divided into independent video frames to obtain multiple image frames.

[0007] Optionally, determining the target write area and the target read area based on the read / write states corresponding to the first buffer and the second buffer respectively includes: When the first buffer is in the read state and the second buffer is in the write state, the first buffer is determined to be the target read area and the second buffer is determined to be the target write area. When the first buffer is in the write state and the second buffer is in the read state, the second buffer is determined to be the target read area and the first buffer is determined to be the target write area.

[0008] Optionally, switching the read / write states of the first buffer and the second buffer includes: When the current image frame is saved to the target write area and a frame completion interrupt signal is received, the read / write state of the first buffer and the second buffer is switched.

[0009] Optionally, switching the read / write states of the first buffer and the second buffer includes: When the target write area is the first buffer and the target read area is the second buffer, the read / write state of the first buffer is switched to the read state, and the read / write state of the second buffer is switched to the write state. When the target write area is the second buffer and the target read area is the first buffer, the read / write state of the second buffer is switched to the read state, and the read / write state of the first buffer is switched to the write state.

[0010] Optionally, sending the previous image frame to an external terminal through the second port of the interface conversion device includes: The previous image frame is divided into multiple data segments according to a set length; Metadata information is added to each of the multiple data segments to obtain multiple data packets; wherein, the metadata information includes the data packet sequence number; Arrange the multiple data packets in order of their sequence numbers to obtain a data packet sequence; The data packet sequence is sent to an external terminal through the second port of the interface conversion device.

[0011] Optionally, the first port is a high-speed serial interface, and the second port is a serial communication interface.

[0012] According to a second aspect of this disclosure, an interface conversion device is provided, comprising: a first port and a second port; The first port is used to connect to an external camera to receive video data sent by the external camera; The second port is used to connect to an external terminal to send the video data to the external terminal; The interface conversion device also includes a processor and a memory; The memory is used to store processor-executable instructions; The processor is configured to implement the method as described in the first aspect when executing instructions stored in the memory.

[0013] According to a third aspect of this disclosure, an electronic device is provided, comprising: an interface conversion device as described in the second aspect.

[0014] According to a fourth aspect of this disclosure, a video transmission system is provided, comprising: an external camera, an interface conversion device as described in the second aspect, and an external terminal, wherein the external camera is connected to a first port of the interface conversion device, and a second port of the interface conversion device is connected to the external terminal.

[0015] According to one embodiment of this disclosure, video data sent by an external camera is received through the first port of the interface conversion device. A first buffer and a second buffer are divided in memory to implement a ping-pong buffering mechanism. This allows the previous image frame to be read from the other buffer and sent to the external terminal through the second port while the current image frame is written to one buffer. This enables continuous acquisition and transmission of high-resolution, high-frame-rate video data, avoids frame loss, reduces hardware costs, and improves the efficiency and reliability of video transmission.

[0016] Other features and advantages of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present application and, together with their description, serve to explain the principles of the present application.

[0018] Figure 1 This is a schematic diagram of the hardware configuration of a video transmission system according to an embodiment of the present disclosure.

[0019] Figure 2 This is a schematic flowchart of a video transmission method according to an embodiment of the present disclosure.

[0020] Figure 3 This is a schematic diagram of the structure of an interface conversion device according to an embodiment of the present disclosure.

[0021] Figure 4 This is a schematic diagram of the structure of an FPGA chip according to an embodiment of the present disclosure.

[0022] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0023] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0024] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0026] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0028] With the rapid development of image sensor technology, Scalable LowVoltage Signaling with Embedded Clock (SLVS-EC) interface cameras can achieve resolutions of 8192×8192 or even higher, frame rates of over 60fps, and single-channel data bandwidth exceeding 40Gbps, making it one of the mainstream interfaces for high-end image sensors.

[0029] However, in related technologies, there are three main technical problems when connecting SLVS-EC interface cameras to personal computers (PCs) for image evaluation: First, dedicated image capture cards (such as Camera Link and CoaXPress capture cards) are usually required to receive and transmit video data. Dedicated image capture cards are expensive and have a long procurement cycle during the research and development evaluation stage. Second, there are few commercial data acquisition cards that support the new SLVS-EC interface standard, resulting in limited compatibility and extremely limited options. Third, the relevant solutions have complex hardware architectures, making them unsuitable for rapid prototyping and preliminary evaluation of camera module image performance, resulting in poor flexibility.

[0030] Therefore, the lack of a low-cost, high-efficiency solution for importing high-speed serial interface video into a PC based on a general-purpose platform and with flexible configuration has become an urgent problem to be solved.

[0031] To address the aforementioned technical problems, this disclosure provides a video transmission method based on an interface conversion device. This method achieves low-cost, high-efficiency continuous acquisition and transmission of video data through the following steps: First, video data sent by an external camera is received through the first port of the interface conversion device, resulting in multiple image frames. Second, a target write area and a target read area are determined based on the read / write states of a first buffer and a second buffer pre-divided in memory (e.g., DDR4 memory), wherein the read / write states of the first and second buffers are always complementary (i.e., when the first buffer is the target write area, the second buffer is the target read area, and vice versa). Then, for any current image frame, the current image frame is saved to the target write area, and simultaneously, the previous image frame is retrieved from the target read area and sent to an external terminal through the second port of the interface conversion device. After the current frame is written, the read / write states of the first and second buffers are switched, and the image frame in the target read area is reread according to the switched read / write state and sent to the external terminal. This process is repeated cyclically to continuously send video data to the external terminal. Through the aforementioned ping-pong buffering mechanism, while writing the current image frame to one buffer, the previous image frame can be read from another buffer and sent to an external terminal through a second port. This enables parallel writing and reading operations, avoiding inter-frame waiting, thereby achieving continuous acquisition and transmission of high-resolution, high-frame-rate video data, avoiding frame loss, reducing hardware costs, and improving system flexibility and evaluation efficiency.

[0032] <Hardware Implementation> Figure 1 This is a schematic diagram of the hardware configuration of a video transmission system according to an embodiment of the present disclosure.

[0033] like Figure 1 As shown, the video transmission system 10 includes an external camera 100, an interface conversion device 200, and an external terminal 300. The external camera 100 is connected to the first port of the interface conversion device 200, and the second port of the interface conversion device 200 is connected to the external terminal 300.

[0034] The external camera 100 is an image acquisition device that outputs video data through a high-speed serial interface.

[0035] In some examples, the external camera 100 can be an industrial camera with an SLVS-EC interface, a resolution of 8192×8192 or even higher, and a frame rate of 60fps or higher.

[0036] The external camera 100 is connected to the first port of the interface conversion device 200 through multiple data channels (e.g., 8 channels × 2 channels, a total of 16 data channels) to output high-speed serial video data. Each channel refers to a single data transmission channel in the SLVS-EC interface, and each channel can independently transmit serial data.

[0037] The SLVS-EC protocol uses differential signal transmission with an embedded clock, offering advantages such as high speed, low power consumption, and fewer pins. The single-channel rate can be configured from 2.01Gbps to 3.02Gbps depending on the pixel bit width, corresponding to 8-bit to 12-bit pixel depth.

[0038] For a video with a resolution of 8192×8192, a frame rate of 60fps, and a pixel width of 10bit, the total bandwidth requirement is approximately 40.3Gbps. After being distributed across 16 channels, the single-channel rate is approximately 2.52Gbps.

[0039] In one embodiment, the interface conversion device 200 is the core device for realizing protocol conversion between a high-speed serial interface and a serial port. For example... Figure 3 As shown, the interface conversion device 200 includes a first port, a second port, a processor, and a memory. The first port is a high-speed serial interface (e.g., an SLVS-EC interface) used to connect to an external camera 100 and receive high-speed serial video data sent by the external camera. The first port includes multiple terminals (e.g., 16 differential signal terminals), each terminal corresponding to one SLVS-EC data channel.

[0040] The second port is a serial communication interface (such as a UART interface or a USB interface), used to connect to the external terminal 300 and send the processed video data to the external terminal 300.

[0041] The processor executes instructions stored in memory to control the reception, buffering, and transmission of video data. The memory stores processor-executable instructions and is divided into a first buffer and a second buffer to implement a ping-pong buffering mechanism.

[0042] In one embodiment, the interface conversion device 200 can be implemented based on a field-programmable gate array (FPGA) chip.

[0043] like Figure 4 As shown, an FPGA chip includes a Programmable Logic (PL) module and a Processing System (PS) module.

[0044] The PL module includes a high-speed serial receiver module, a channel alignment and descrambling module, a pixel reconstruction module, a frame management and flow control module, and a write control module. The first port of the interface conversion device can be implemented based on the high-speed serial receiver module. The second port of the interface conversion device is implemented using the serial communication interface in the PS module. The memory of the interface conversion device can be implemented based on external DDR4 memory chips managed by the PS module of the FPGA chip.

[0045] The high-speed serial receiving module includes a gigabit high-speed transceiver or a gigabit ultra-high-speed transceiver. This module receives video data from an external camera via multiple terminals, obtaining multiple serial bit substreams. Each serial bit substream is then converted into a parallel codeword sequence at set time intervals, resulting in multiple parallel codeword sequences. The channel alignment and descrambling module aligns these parallel codeword sequences across channels, yielding aligned codeword sequences. These aligned codeword sequences are then descrambled, resulting in descrambled codeword sequences. The pixel reconstruction module parses these descrambled codeword sequences to obtain multiple valid codeword sequences. Based on the bits belonging to the same pixel within these valid codeword sequences, the corresponding pixel grayscale value is determined, resulting in the individual pixel grayscale values ​​for each pixel. The frame management and flow control module organizes the pixel grayscale values ​​corresponding to multiple pixels into a row-arranged pixel sequence according to the target pixel bit width, resulting in multiple pixel value sequences. These row-arranged pixel sequences are then concatenated to obtain a complete row sequence. Based on the frame synchronization signal, the row sequence is segmented into independent video frames, resulting in multiple image frames. The write control module writes the segmented image frames into DDR4 memory via the AXI high-performance bus, completing the transmission of video data from the PL module to the storage medium.

[0046] The PS module includes a processor and a serial communication interface. The processor is used to manage memory access, support ping-pong buffer management, and read image data from the DDR4 memory buffer, perform data encapsulation, and control transmission. The serial communication interface can be, for example, a Universal Asynchronous Receiver / Transmitter (UART) or a USB serial communication module, used to send the encapsulated image data to the external terminal 300.

[0047] In DDR4 memory, a first buffer and a second buffer are used to implement a ping-pong buffering mechanism. The two buffers take turns handling the roles of "writing the current image frame" and "reading the previous image frame," allowing write and read operations to be performed in parallel, thereby avoiding inter-frame waiting.

[0048] For example, for an image with a resolution of 8192×8192 and a pixel width of 16 bits, the data size of a single frame is approximately 128MB. Therefore, the first buffer and the second buffer are each configured to be 128MB, totaling 256MB. The two buffers have the same capacity to ensure that each can completely store a frame of image data and to prevent data overflow due to inconsistent capacity.

[0049] External terminal 300 is a computer device, such as a PC host, that receives, displays, or analyzes image data. External terminal 300 can receive image data through a serial communication interface (such as UART or USB to serial port) and perform image display, storage, and performance analysis through host computer software.

[0050] This video transmission system can be applied to fields such as machine vision, medical imaging, and semiconductor testing, and is used for rapid evaluation of the image performance of high-resolution industrial cameras.

[0051] This video transmission system enables low-cost, high-efficiency video data acquisition, transmission, and analysis, significantly shortening the camera module evaluation cycle.

[0052] In one embodiment, the video transmission system can also support adaptation to various SLVS-EC interface cameras. By flexibly configuring parameters (such as resolution, frame rate, pixel width, etc.), it can adapt to different models of SLVS-EC interface cameras. Furthermore, by replacing the corresponding high-speed serial receiver module in the FPGA chip, the video transmission system can also adapt to various high-speed serial interface standards such as Mobile Industry Processor Interface (MIPI), Low-Voltage Differential Signaling (LVDS), and Sub-LVDS, demonstrating good platform versatility.

[0053] As described above, this embodiment provides a video transmission system, which includes an external camera, an interface conversion device, and an external terminal. This system enables continuous acquisition and transmission of high-resolution, high-frame-rate video data, reduces hardware costs, and improves system flexibility and evaluation efficiency.

[0054] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Figure 5 As shown, electronic device 500 includes an interface conversion device.

[0055] The interface conversion device can be, for example, Figure 3 As shown or as Figure 4 The structure shown.

[0056] Electronic devices can be camera devices, personal computers, or other terminal devices with data processing capabilities that include interface conversion devices.

[0057] In some examples, the electronic device may take the form of a standalone conversion board integrated within the camera device, or as an expansion card for a PC. The electronic device may also include auxiliary modules such as a power module, clock module, and reset module to provide stable power, clock, and reset signals to the interface conversion device.

[0058] Electronic devices including the aforementioned interface conversion device can achieve a low-cost, high-efficiency video data transmission solution, suitable for rapid evaluation of the image performance of high-resolution industrial cameras.

[0059] <Method Implementation> This embodiment provides a video transmission method applied to an interface conversion device.

[0060] Figure 2 This is a schematic flowchart of a video transmission method according to an embodiment of this disclosure. Figure 2 As shown, the video transmission method includes the following steps S210 to S250.

[0061] In step S210, video data sent by an external camera is received through the first port of the interface conversion device to obtain multiple image frames.

[0062] In this embodiment, high-speed serial video data sent by an external camera is received through the first port of the interface conversion device, and multiple image frames are obtained after a series of processing steps.

[0063] The first port is the interface on the interface conversion device used to connect to an external camera. In some examples, the first port is a high-speed serial interface (such as the SLVS-EC interface), which includes multiple terminals (such as 16 differential signal terminals), each terminal corresponding to a data channel.

[0064] Video data refers to the high-speed serial video stream output by an external camera, containing pixel information, timing control information, etc. An image frame is an independent video frame segmented from this video stream; each frame contains complete image data.

[0065] In one embodiment, the first port includes multiple terminals. Step S210, which receives video data sent by an external camera through the first port of the interface conversion circuit to obtain multiple image frames, may include the following steps S2111 to S2119: Step S2111: Receive video data sent by an external camera through multiple terminals to obtain multiple serial bit sub-streams.

[0066] In this embodiment, the SLVS-EC differential signal output from an external camera is received through multiple terminals of the first port to obtain multiple serial bit substreams. A terminal refers to a physical connection interface on the first port, and each terminal corresponds to one SLVS-EC data channel. A serial bit substream refers to a continuous sequence of serial bits received from a single channel.

[0067] For example, for an SLVS-EC interface containing 16 channels, the first port includes 16 terminals, each terminal receiving serial data from one channel, resulting in 16 serial bit substreams. The rate of each serial bit substream can be from 2.01Gbps to 3.02Gbps, configured according to the pixel bit width.

[0068] Step S2112: Convert each serial bit substream into a parallel codeword sequence according to a set time interval to obtain multiple parallel codeword sequences corresponding to multiple serial bit substreams.

[0069] In this embodiment, the received serial bit substream is converted from serial to parallel to obtain a parallel codeword sequence. The set time interval refers to the sampling period of the serial-to-parallel conversion, for example, one 10-bit parallel codeword is output every 10 serial bit clock cycles. The parallel codeword sequence refers to a parallel data sequence in which the serial bit substream is organized according to a certain bit width, for example, the serial bit substream is organized into a 10-bit parallel codeword sequence with a bit width of 10 bits.

[0070] In one example, serial-to-parallel conversion can be achieved through the deserializer of the high-speed serial receiver module, converting high-speed serial data into low-speed parallel data for easier subsequent processing.

[0071] For a 16-bit serial substream, after serial-to-parallel conversion, 16 parallel codeword sequences are obtained.

[0072] Step S2113: Align multiple parallel codeword sequences across channels to obtain multiple aligned codeword sequences.

[0073] In this embodiment, since the transmission path lengths of different channels may differ, resulting in different data arrival times, it is necessary to use an alignment algorithm to perform inter-channel alignment of multiple parallel codeword sequences to eliminate delay deviations between different data channels and ensure that data from different data channels are aligned in time.

[0074] Channel alignment refers to eliminating delay discrepancies between different channels and ensuring that data from different channels are aligned in time.

[0075] Alignment algorithms can determine the delay differences between channels by detecting specific alignment codewords (such as K codewords) and make corresponding delay adjustments.

[0076] Aligned codeword sequences refer to parallel codeword sequences after inter-channel alignment processing. The data in each channel is aligned in time, but the data may still contain scrambling information, requiring further descrambling processing.

[0077] Step S2114: Descramble the multiple aligned codeword sequences to obtain multiple descrambled codeword sequences.

[0078] In this embodiment, the SLVS-EC protocol scrambles the original data to improve the signal spectral characteristics. This step, according to the descrambling polynomial specified in the protocol (such as x^23 + x^18 + 1), performs descrambling operations word by word on each aligned codeword sequence to recover the original data codewords. The descrambled codeword sequence may still contain control codewords used for synchronization, frame boundary marking, etc. (such as SOF, EOF, empty codewords, etc.), and the effective pixel data has not yet been separated.

[0079] Step S2115: parse the multiple descrambled codeword sequences to obtain multiple valid codeword sequences.

[0080] In this embodiment, control codewords (such as alignment padding, start of frame (SOF), end of frame (EOF), start of line, etc.) are identified and removed from the descrambled codeword sequence, and only valid data codewords carrying actual pixel information are retained.

[0081] For example, certain codewords in the SLVS-EC protocol (such as combinations of 0x00 and 0xFF) are used to identify frame or line boundaries. When these codewords are detected, boundary synchronization is performed, and they are not output as pixel data. The final result is a valid codeword sequence containing only pixel grayscale value information.

[0082] Step S2116: Based on the bits belonging to the same pixel in multiple valid codeword sequences, determine the pixel grayscale value corresponding to the pixel, and obtain the pixel grayscale values ​​corresponding to multiple pixels respectively.

[0083] In this embodiment, in the SLVS-EC protocol, the data of a pixel may be distributed in bits across multiple channels' valid codewords (for example, a 10-bit pixel may be distributed across codewords in different channels at the same or adjacent times). This step uses the pixel reconstruction module to extract all bits belonging to the same pixel from multiple valid codeword sequences according to the mapping relationship specified in the protocol, and combine them into a complete pixel grayscale value.

[0084] For example, in 10-bit RAW format, the pixel reconstruction module extracts the low-order and high-order bits from two adjacent codewords and concatenates them to form grayscale values ​​from 0 to 1023. After reconstructing the data from all channels, a continuous stream of pixel grayscale values ​​is output.

[0085] Step S2117: Based on the target pixel bit width, organize the pixel grayscale values ​​corresponding to multiple pixels into a pixel sequence arranged in rows to obtain multiple pixel value sequences.

[0086] In this embodiment, pixel grayscale values ​​are organized into a pixel value sequence according to the row order of the image. The target pixel bit width refers to the bit width of the pixel data, such as 8 bits, 10 bits, or 12 bits. A pixel value sequence is a data sequence in which the pixel grayscale values ​​of multiple pixels are organized according to the row order of the image. For an image with a resolution of 8192×8192, each row contains 8192 pixels, and there are a total of 8192 rows. The pixel value sequence is arranged from left to right and from top to bottom.

[0087] Based on the target pixel bit width, determine the bit width of each pixel grayscale value, and organize the pixel grayscale values ​​into a continuous pixel value sequence in row order. The pixel value sequence can be stored in a buffer for subsequent frame segmentation and transmission.

[0088] Step S2118: The multiple row-arranged pixel sequences are spliced ​​together to obtain a complete row sequence.

[0089] In this embodiment, multiple pixel value sequences are arranged in rows. However, due to the parallel processing architecture of the interface conversion device, the pixel sequences output by different channels or different processing units may correspond to different pixel segments in the same row, or they may correspond to different rows. Therefore, this step concatenates the multiple row-arranged pixel sequences according to the correct row order and pixel order within the row to form a continuous and complete row sequence, providing a complete row of image data for subsequent frame segmentation.

[0090] In the example where the interface conversion device is implemented using an FPGA chip, the stitching method depends on the data output organization of the pixel reconstruction module: If the pixel reconstruction module has already output a continuous data stream of all pixels in a row in order from left to right, this step does not require additional operation and can be implicitly completed in step S2117; if the pixel reconstruction module outputs multiple independent pixel segments in a multi-channel parallel processing architecture (for example, each of the 4 channels independently generates one row segment data, and different segments correspond to pixels in different intervals within the same row), then it is necessary to cache each segment through an on-chip FIFO or block random access memory (BRAM) and stitch them together row by row in the correct pixel order to ensure that the final output row sequence is completely consistent with the pixel scanning order of the image sensor.

[0091] The above splicing process ensures that the final generated row sequence data is complete and in the correct order, providing a reliable data foundation for subsequent frame synchronization and segmentation.

[0092] Step S2119: According to the frame synchronization signal, the line sequence is divided into independent video frames to obtain multiple image frames.

[0093] In this embodiment, a continuous sequence of pixel values ​​is segmented into independent video frames based on the frame synchronization signal. The frame synchronization signal is used to identify the start and end boundaries of a video frame. It originates from an external camera (embedded in the video data transmitted by the external camera) and is a protocol signal input to the interface conversion device. In the SLVS-EC protocol, the frame synchronization signal can be identified using specific K-codewords (e.g., the start of frame (SOF) and end of frame (EOF)). Based on the frame synchronization signal, a continuous sequence of pixel values ​​can be segmented into independent video frames.

[0094] For a video with a frame rate of 60fps, the time interval between each frame is 16.7ms. The video stream control module monitors the frame synchronization signal. When it detects the start of a frame codeword, it begins recording the pixel value sequence. When it detects the end of a frame codeword, it stops recording, forming a complete image frame. By repeatedly executing the above process, multiple independent image frames can be segmented from a continuous video stream.

[0095] Based on steps S2111 to S2119 above, multiple serial bit substreams output from the SLVS-EC interface camera are received through multiple terminals of the first port. The high-speed transceiver embedded in the FPGA sequentially performs clock data recovery, serial-to-parallel conversion, channel alignment, and descrambling, resulting in multiple aligned and descrambled parallel codeword sequences. Further analysis of the valid codeword sequences extracts bits belonging to the same pixel from multiple channels and combines them into complete pixel grayscale values. These are then organized into row-wise pixel sequences according to the target pixel bit width. Through row sequence concatenation and frame synchronization signal segmentation, independent video frames are accurately recovered from the continuous high-speed serial data stream. This method fully covers all parsing stages of the SLVS-EC protocol from the physical layer to the frame level, enabling efficient and frame-free processing of video data at resolutions up to 8192×8192, frame rates of 60fps, and single-channel rates of 3.02 Gbps. It ensures the integrity, timing correctness, and pixel accuracy of image data, meeting the requirements for high-resolution industrial camera image acquisition and real-time evaluation.

[0096] In other examples, receiving video data from an external camera can be achieved in other ways. For instance, a dedicated SLVS-EC receive IP core can be used for integrated processing. This IP core integrates serial-to-parallel conversion, inter-channel alignment, descrambling, pixel reconstruction, and frame segmentation, enabling a one-time conversion from serial bitstream to image frames. Alternatively, some functions can be implemented in software within the processor, such as using an ARM processor core for pixel reconstruction and frame segmentation. However, this method is slower and suitable for applications with low frame rates.

[0097] Step S220: Determine the target write area and the target read area according to the read / write states of the first buffer and the second buffer respectively; wherein, when the first buffer is the target write area, the second buffer is the target read area, and when the first buffer is the target read area, the second buffer is the target write area.

[0098] In this embodiment, the first buffer and the second buffer are storage areas divided in the memory (e.g., DDR4 memory).

[0099] In one example, the capacity of each buffer can be determined based on the size of a single frame image.

[0100] For example, for an image with a resolution of 8192×8192 and a pixel bit width of 16 bits, the size of a single frame is approximately 128MB, so each buffer is configured to be 128MB.

[0101] The read / write state refers to whether the buffer is currently in a write or read state. A write state indicates that data is being written to the buffer, while a read state indicates that data is being read from the buffer. At any given time, the read / write states of the first and second buffers are complementary; that is, when one buffer is in a write state, the other is in a read state.

[0102] The target write area refers to the buffer currently used to write image frame data. The target read area refers to the buffer currently used to read image frame data. Through a ping-pong buffering mechanism, while writing the current image frame, the previous image frame can be read simultaneously, enabling continuous data processing.

[0103] In one embodiment, step S220, which determines the target write area and the target read area based on the read / write states of the first buffer and the second buffer respectively, may include steps S2211 to S2212.

[0104] Step S2211: When the read / write state of the first buffer is in the read state and the read / write state of the second buffer is in the write state, the first buffer is determined to be the target read area and the second buffer is determined to be the target write area.

[0105] Step S2212: When the read / write state of the first buffer is in the write state and the read / write state of the second buffer is in the read state, determine that the second buffer is the target read area and the first buffer is the target write area.

[0106] In this embodiment, the target write area and target read area can be clearly determined by checking the read / write status of the first and second buffers. The read / write status can be recorded and queried using status flags, for example, by using registers or memory variables to store the current status of each buffer.

[0107] In one embodiment, the first and second buffers have the same capacity. Configuring the two buffers to have the same capacity ensures the symmetry of the ping-pong buffering mechanism and simplifies buffer management logic. Buffers of the same capacity can alternately handle write and read tasks, preventing uneven buffer utilization due to capacity differences.

[0108] Step S230: For any current image frame among multiple image frames, save the current image frame to the target write area and obtain the previous image frame from the target read area.

[0109] In this embodiment, the currently received image frame is written to the target write area, and the previously received image frame is read from the target read area. The current image frame refers to the image frame currently being processed, which can be any one of multiple image frames. The previous image frame refers to the image frame received before the current image frame, that is, the previous frame in time sequence.

[0110] In the example where the interface conversion device is implemented using an FPGA chip, saving the current image frame to the first or second buffer can be achieved through a write control module. Specifically, under the control of the PL module, the write control module writes the AXI4-Stream format image data output by the frame management and flow control module to the target buffer in DDR4 memory via the AXI high-performance bus (AXI HP). The AXI high-performance bus is a high-speed data path between the PL and PS modules, supporting high-bandwidth data transmission and ensuring that high-resolution video frames can be written to DDR4 memory in a timely manner to meet the bandwidth requirements of real-time acquisition. Retrieving the previous image frame from the first or second buffer can be achieved through the processor in the PS module. The processor accesses the currently readable target buffer through the DDR4 memory controller, reads the data of the previous image frame, and encapsulates the read image data in preparation for sending it to an external terminal via a serial communication interface.

[0111] By performing write and read operations simultaneously, parallel data processing can be achieved, avoiding the need for write operations to wait for read operations to complete, thereby improving system throughput.

[0112] For example, for a video with a frame rate of 60fps, the time interval between each frame is 16.7ms. Completing the writing of one frame and the reading of the previous frame within 16.7ms can ensure the continuous transmission of video data.

[0113] In step S240, the previous image frame is sent to the external terminal through the second port of the interface conversion device.

[0114] In the example where the interface conversion device is implemented using an FPGA chip, the processor in the PS module reads the complete data of the previous image frame from the currently readable target buffer (i.e., the buffer containing the previous image frame), encapsulates it into a data format suitable for serial port transmission, and then sends it to an external terminal (e.g., a PC host) through the serial communication interface. The serial communication interface supports Universal Asynchronous Receiver / Transmitter (UART) or USB serial communication protocols.

[0115] After receiving the data packet, the external terminal performs verification, packet assembly, and image reconstruction to achieve the final output and display of the video image.

[0116] In one embodiment, step S240, which sends the previous image frame to an external terminal through the second port of the interface conversion device, may include steps S2411 to S2414.

[0117] Step S2411: Divide the previous image frame into multiple data segments according to the set length.

[0118] In this embodiment, the previous image frame is divided into multiple data segments according to a set length to facilitate segmented transmission. A data segment refers to a data block obtained by dividing the previous image frame according to a set length (e.g., 1KB).

[0119] For example, an image with a single frame size of 128MB can be divided into 131,072 1KB data segments.

[0120] By transmitting data in segments, the amount of data transmitted in a single transmission can be reduced, thereby improving the flexibility and reliability of the transmission.

[0121] Step S2412: Add metadata information to each of the multiple data segments to obtain multiple data packets; wherein, the metadata information includes the data packet sequence number.

[0122] In this embodiment, metadata information is added to each data segment to form a complete data packet. Metadata information refers to the control information added to the data segment, which is used to identify the attributes and order of the data segment.

[0123] The metadata information may include packet sequence number, data length, and CRC (Cyclic Redundancy Check) value. The packet sequence number identifies the sequential position of the packet within the entire image frame, facilitating the receiving end's reassembly of the image frame in order. The data length identifies the number of valid bytes in the data segment. The CRC check value verifies the correctness of data transmission and detects data errors during transmission.

[0124] A data packet is a complete transmission unit containing data segments and metadata information. The format of a data packet may include a header (containing metadata information) and a payload (containing data segments). The header may include fields such as a start flag, packet sequence number, data length, and CRC checksum. The payload contains the actual image data.

[0125] Step S2413: Arrange multiple data packets in sequence according to their data packet numbers to obtain a data packet sequence.

[0126] In this embodiment, multiple data packets are arranged in sequence according to their sequence numbers to form a data packet sequence. A data packet sequence refers to the queue of data packets obtained by arranging multiple data packets in sequence according to their sequence numbers. By arranging them in order, it can be ensured that the receiving end can reassemble image frames in the correct order.

[0127] Step S2414: Send the data packet sequence to the external terminal through the second port of the interface conversion device.

[0128] In this embodiment, the data packet sequence is sent to the external terminal packet by packet through the second port.

[0129] The second port can be a serial communication interface. The serial communication interface can be configured with a baud rate (e.g., from 921600bps to 12Mbps), and the transmission time of a single packet can be calculated based on the baud rate and the data packet size.

[0130] For example, for a 1KB data packet and a 12Mbps baud rate, the transmission time for a single packet is approximately 0.67ms. Within a 16.7ms frame interval, about 25 data packets can be transmitted. For a 128MB image frame, multiple frame intervals are required to complete the transmission.

[0131] Based on the above steps S2411 to S2414, by dividing the previous image frame into multiple data segments, adding metadata information to each data segment to form a data packet, and sending the packets sequentially to the external terminal, reliable transmission of large-capacity image data can be achieved, and the correctness of data transmission can be ensured by CRC check.

[0132] In another embodiment, sending the previous image frame to the external terminal via the second port of the interface conversion device can be achieved in other ways. For example, the entire frame of image data can be sent directly to the external terminal via the second port without segmentation. However, this method requires high serial port bandwidth, and the entire frame needs to be retransmitted if an error occurs during transmission, resulting in low efficiency. Alternatively, compressed transmission can be used, compressing the image data before transmission to reduce the amount of data transmitted. However, this requires decompression at the external terminal, increasing processing complexity.

[0133] In step S250, the read / write state of the first buffer and the second buffer is switched, and the image frame of the target reading area is reread and sent to the external terminal according to the read / write state of the first buffer and the second buffer after the switch, so as to send the video data to the external terminal.

[0134] In this embodiment, switching the read / write state of the first buffer and the second buffer can be done by switching the current target write area to a new target read area, and vice versa. After the switching is complete, the processor reads the current image frame from the new target read area and sends the current image frame to the external terminal through the second port according to step S240. Simultaneously, the next image frame is written to the new target write area. By repeatedly executing steps S220 to S250, continuous acquisition and transmission of video data can be achieved.

[0135] In the example where the interface conversion device is implemented using an FPGA chip, two 128MB buffers are partitioned in the DDR4 memory: a first buffer and a second buffer. Each frame transmission cycle is 16.7ms (corresponding to a 60fps frame rate). During the time interval T0 to T1 (16.7ms), the PL module writes Frame N to the first buffer via the write control module, while the PS module reads Frame N-1 from the second buffer and sends it to the PC via the serial communication interface. At time T1, Frame N is written successfully, the PL module sends a frame completion interrupt signal, and the PS module switches the write control module to the second buffer. The frame completion interrupt signal is sent by the PL module to the PS module after a frame is completely written to the DDR4 memory, notifying the PS module to switch the read state; it is a control signal output to the PS module. During the time interval T1 to T2 (16.7ms), the PL module writes Frame N+1 to the second buffer, and the PS module reads Frame N from the first buffer and sends it to the PC via the serial communication interface. At time T2, Frame N+1 is written successfully, the switch occurs again, and the cycle repeats. This mechanism ensures that the PL module's write operation does not need to wait for the PS module to finish reading, enabling continuous, uninterrupted video stream acquisition at a frame rate of 60fps.

[0136] The ping-pong buffer mechanism operates cyclically by switching the read / write states of the first and second buffers.

[0137] In one embodiment, step S250, which switches the read / write state of the first buffer and the second buffer, may include step S2501.

[0138] Step S2501: When the current image frame is saved to the target write area and a frame completion interrupt signal is received, switch the read / write state of the first buffer and the second buffer.

[0139] In the example where the interface conversion device is implemented based on an FPGA chip, after the current image frame is written to the target write area, the frame management and flow control module or the write control module generates a frame completion interrupt signal. This interrupt signal is transmitted to the processor of the PS module via internal communication within the FPGA chip. The processor can register an interrupt service routine (ISR) to execute corresponding processing logic upon receiving the frame completion interrupt signal. Specifically, in the interrupt service routine, the processor reads the status information of the current buffer, determines that the current frame has been written to the target write area, then updates the read / write status flags of the first and second buffers, switches the target write area to the target read area, and vice versa. Simultaneously, the descriptor of the write control module can be updated to point to the new target write area address, preparing to receive the next image frame.

[0140] Based on this embodiment, switching the read / write state of the buffer via frame-driven interrupt signals ensures that the switching operation occurs at the frame boundary, avoiding data corruption caused by switching during frame transmission. The interrupt-driven approach improves the system's real-time performance and response speed.

[0141] In one embodiment, switching the read / write status of the first buffer and the second buffer in step S250 or step S2501 may include steps S2511 to S2512.

[0142] Step S2511: When the target write area is the first buffer and the target read area is the second buffer, switch the read / write state of the first buffer to the read state and switch the read / write state of the second buffer to the write state.

[0143] Step S2512: When the target write area is the second buffer and the target read area is the first buffer, switch the read / write state of the second buffer to the read state and switch the read / write state of the first buffer to the write state.

[0144] Based on steps S2511-S2512 above, the read / write state switching logic ensures that the read / write states of the two buffers remain complementary, preventing erroneous situations where both buffers are simultaneously in a write state or simultaneously in a read state. Thread safety can be guaranteed through atomic operations or mutex lock mechanisms during state switching.

[0145] Based on steps S210 to S250 above, this embodiment receives video data sent by an external camera through the first port of the interface conversion device to obtain multiple image frames. The target write area and target read area are determined according to the read / write status of the first buffer and the second buffer. The current image frame is written to the target write area, while the previous image frame is read from the target read area and sent to the external terminal through the second port. Then, the read / write status of the buffer is switched and the next frame is processed. This realizes high-speed continuous acquisition and transmission of video data based on the ping-pong buffer mechanism, avoids frame loss, improves the efficiency and reliability of video transmission, reduces hardware costs, and improves system flexibility.

[0146] In one embodiment, before receiving video data sent by an external camera through the first port of the interface conversion device in step S210 to obtain multiple image frames, the method further includes steps S110 to S120.

[0147] Step S110: Receive configuration parameters input by the user; wherein, the configuration parameters include the target pixel bit width.

[0148] In this embodiment, before receiving video data sent by an external camera, configuration parameters input by the user are received first to determine parameters such as the target pixel bit width. Configuration parameters refer to parameters used to configure the operating mode of the interface conversion device, including the target pixel bit width, resolution, frame rate, etc.

[0149] The target pixel bit width refers to the bit width of the pixel data, which can be 8 bits, 10 bits, or 12 bits, etc. Configuration parameters can be input via the host computer software on an external terminal and transmitted to the interface conversion device through the second port.

[0150] Step S120: Determine the target pixel bit width based on the configuration parameters.

[0151] In this embodiment, after receiving the configuration parameters, the interface conversion device determines the target pixel bit width according to the configuration parameters and configures the corresponding processing module (such as the pixel reconstruction module) to adapt to the target pixel bit width.

[0152] The target pixel bit width can be used in step S2117 to organize the pixel grayscale values ​​into a pixel value sequence according to the target pixel bit width.

[0153] By receiving configuration parameters before receiving video data, the interface conversion device can be flexibly configured to adapt to different models of SLVS-EC interface cameras.

[0154] For example, for a camera with an 8-bit pixel width, the target pixel width is configured to be 8 bits; for a camera with a 10-bit pixel width, the target pixel width is configured to be 10 bits. This flexible configuration improves the versatility of the interface conversion device and reduces hardware costs.

[0155] Configuration parameters can also include resolution, frame rate, and other parameters. By configuring these parameters, it is possible to adapt to cameras with different resolutions and frame rates.

[0156] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0157] This disclosure may be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement any of the methods in the foregoing embodiments of this disclosure.

[0158] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media may include, for example, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), compact disc-read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any combination thereof. The computer-readable storage medium used herein is not to be interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0159] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include one or more of copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to computer-readable storage media in the respective computing / processing device.

[0160] The computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source or object programs written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network (e.g., a local area network or a wide area network), or it may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays, or programmable logic arrays, can execute computer-readable program instructions to implement various aspects of the embodiments of this disclosure by utilizing state information from the computer-readable program instructions.

[0161] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0162] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0163] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0164] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It should be noted that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are all equivalent.

[0165] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.

Claims

1. A video transmission method, characterized in that, Applied to interface conversion devices, including: The video data sent by an external camera is received through the first port of the interface conversion device to obtain multiple image frames; Based on the read / write states of the first buffer and the second buffer respectively, the target write area and the target read area are determined; wherein, when the first buffer is the target write area, the second buffer is the target read area, and when the first buffer is the target read area, the second buffer is the target write area. For any current image frame among the plurality of image frames, the current image frame is saved to the target write area, and the previous image frame of the current image frame is obtained from the target read area; The previous image frame is sent to an external terminal through the second port of the interface conversion device; The read / write states of the first buffer and the second buffer are switched, and the image frames of the target reading area are reread and sent to the external terminal according to the read / write states of the first buffer and the second buffer after the switch, so as to send the video data to the external terminal.

2. The method according to claim 1, characterized in that, The first port includes multiple terminals. The first port of the interface conversion device receives video data sent by an external camera to obtain multiple image frames, including: The video data sent by an external camera is received through the multiple terminals to obtain multiple serial bit sub-streams; Each serial bit substream is converted into a parallel codeword sequence according to a set time interval, thereby obtaining multiple parallel codeword sequences corresponding to the multiple serial bit substreams; The multiple parallel codeword sequences are aligned between channels to obtain multiple aligned codeword sequences; The multiple aligned codeword sequences are descrambled to obtain multiple descrambled codeword sequences. By parsing the multiple descrambled codeword sequences, multiple valid codeword sequences are obtained; Based on the bits belonging to the same pixel in the multiple valid codeword sequences, determine the pixel grayscale value corresponding to the pixel point, and obtain the pixel grayscale values ​​corresponding to the multiple pixels respectively. Based on the target pixel bit width, the pixel grayscale values ​​corresponding to the multiple pixels are organized into a row-arranged pixel sequence to obtain multiple row-arranged pixel sequences. The multiple row-arranged pixel sequences are concatenated to obtain a complete row sequence; Based on the frame synchronization signal, the line sequence is divided into independent video frames to obtain multiple image frames.

3. The method according to claim 1, characterized in that, The step of determining the target write area and the target read area based on the read / write states corresponding to the first buffer and the second buffer respectively includes: When the first buffer is in the read state and the second buffer is in the write state, the first buffer is determined to be the target read area and the second buffer is determined to be the target write area. When the first buffer is in the write state and the second buffer is in the read state, the second buffer is determined to be the target read area and the first buffer is determined to be the target write area.

4. The method according to claim 1, characterized in that, Switching the read / write states of the first buffer and the second buffer includes: When the current image frame is saved to the target write area and a frame completion interrupt signal is received, the read / write state of the first buffer and the second buffer is switched.

5. The method according to claim 1 or 4, characterized in that, The switching of the read / write states of the first buffer and the second buffer includes: When the target write area is the first buffer and the target read area is the second buffer, the read / write state of the first buffer is switched to the read state, and the read / write state of the second buffer is switched to the write state. When the target write area is the second buffer and the target read area is the first buffer, the read / write state of the second buffer is switched to the read state, and the read / write state of the first buffer is switched to the write state.

6. The method according to claim 1, characterized in that, Sending the previous image frame to an external terminal through the second port of the interface conversion device includes: The previous image frame is divided into multiple data segments according to a set length; Metadata information is added to each of the multiple data segments to obtain multiple data packets; wherein, the metadata information includes the data packet sequence number; Arrange the multiple data packets in order of their sequence numbers to obtain a data packet sequence; The data packet sequence is sent to an external terminal through the second port of the interface conversion device.

7. The method according to claim 1, characterized in that, The first port is a high-speed serial interface, and the second port is a serial communication interface.

8. An interface conversion device, characterized in that, include: First port and second port; The first port is used to connect to an external camera to receive video data sent by the external camera; The second port is used to connect to an external terminal to send the video data to the external terminal; The interface conversion device also includes a processor and a memory; The memory is used to store processor-executable instructions; The processor is configured to implement the method of any one of claims 1 to 7 when executing instructions stored in the memory.

9. An electronic device, characterized in that, include: The interface conversion device according to claim 8.

10. A video transmission system, characterized in that, include: An external camera, an interface conversion device as described in claim 8, and an external terminal, wherein the external camera is connected to a first port of the interface conversion device, and a second port of the interface conversion device is connected to the external terminal.

Images