Image sensor, arrangement and control method

Abstract

This invention provides an image sensor, its arrangement structure, and a control method. The image sensor includes a plurality of pixel units arranged in an array. Each pixel unit includes: a conversion output module that outputs a first set of signals consisting of a first reset signal and pixel signals, and a second set of signals consisting of a second reset signal and an overflow signal; a first mode operating module connected to the conversion output module, which, in the first mode, stores and then reads out at least one of the first and second sets of signals; and a second mode operating module connected to the conversion output module, which, in the second mode, reads out at least one of the first and second sets of signals. This invention solves the problem in the prior art where multiple device terminals need to switch between different operating conditions to achieve image sensor fusion.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to an image sensor, its arrangement structure, and a control method. Background Technology

[0002] As image sensors continue to evolve, the fusion of different sensors is becoming increasingly frequent. For example, in some operating conditions, a rolling-type image sensor is needed to provide better image quality, while in others, a global-type image sensor is required to provide faster speed. Therefore, multiple device terminals need to work together, mainly achieved by switching between multiple device terminals under different operating conditions. In view of the above, how to reduce the switching of device terminals under different operating conditions has become a technical problem that those skilled in the art urgently want to solve.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an image sensor, an arrangement structure, and a control method to solve the problem in the prior art that different image sensors need to be fused by switching between multiple device terminals under different operating conditions.

[0005] To achieve the above and other related objectives, the present invention provides an image sensor comprising a plurality of pixel units arranged in an array, wherein the pixel units include:

[0006] The conversion output module outputs a first set of signals consisting of a first reset signal and a pixel signal, and outputs a second set of signals consisting of a second reset signal and an overflow signal.

[0007] The first mode working module is connected to the conversion output module. In the first mode, it stores and then reads out at least one of the first group of signals and the second group of signals respectively.

[0008] The second mode working module is connected to the conversion output module. In the second mode, at least one of the first group of signals and the second group of signals is read out respectively.

[0009] Optionally, the conversion output module includes:

[0010] The photosensitive part is coupled to a floating diffusion node, accumulates photogenerated electrons based on the photoelectric effect, and transfers the photogenerated electrons to at least the floating diffusion node to read out the pixel signal;

[0011] The overflow portion is coupled to the floating diffusion node or the photosensitive portion, and the photogenerated electrons overflowing from the floating diffusion node or the photosensitive portion are stored to read out the overflow signal;

[0012] The first reset section is coupled to the floating diffusion node and at least resets the floating diffusion node to read out the corresponding reset signal.

[0013] The output section is coupled to the floating diffusion node and is used to amplify and output the corresponding signal.

[0014] Optionally, the photosensitive portion includes a transmission transistor and a photosensitive element, wherein the control terminal of the transmission transistor receives a transmission control signal, the first terminal of the transmission transistor is coupled to the floating diffusion node, and the second terminal of the transmission transistor is coupled to a first potential via the photosensitive element;

[0015] And / or, the overflow portion includes an overflow transistor and an overflow capacitor, wherein the control terminal of the overflow transistor receives an overflow control signal, the first terminal of the overflow transistor is coupled to the floating diffusion node or the photosensitive portion, and the second terminal of the overflow transistor is coupled to a second potential via the overflow capacitor;

[0016] And / or, the first reset portion includes a first reset transistor, wherein the control terminal of the first reset transistor receives a first reset control signal, the first terminal of the first reset transistor is coupled to a third potential, and the second terminal of the first reset transistor is coupled to the floating diffusion node;

[0017] And / or, the output section includes a first source follower transistor, wherein the control terminal of the first source follower transistor is coupled to the floating diffusion node, the first terminal of the first source follower transistor is coupled to a fourth potential, and the second terminal of the first source follower transistor serves as the output terminal of the conversion output module.

[0018] Optionally, the conversion output module further includes:

[0019] The second reset part is coupled to the overflow part and at least resets the overflow part;

[0020] And / or, the gain portion, coupled to the floating diffusion node, is used for switching between different conversion gains.

[0021] Optionally, when the conversion output module includes a second reset section, the second reset section includes a second reset transistor, wherein the control terminal of the second reset transistor receives a second reset control signal, the first terminal of the second reset transistor is coupled to a fifth potential, and the second terminal of the second reset transistor is coupled to the overflow section; the second reset section resets the overflow section by cooperating with the first reset section.

[0022] When the conversion output module includes a gain section, the gain section includes a gain transistor, wherein the gain transistor is coupled between the first reset module and the floating diffusion node, or the first terminal of the gain transistor is coupled to the floating diffusion node and the second terminal is coupled to a sixth potential, and the control terminal of the gain transistor receives a gain control signal.

[0023] Optionally, the second mode operating module includes a third row selection transistor, wherein the control terminal of the third row selection transistor receives a third row selection control signal, the first terminal of the third row selection transistor is coupled to the output terminal of the conversion output module, and the second terminal of the third row selection transistor is coupled to the third column line.

[0024] Optionally, the first mode working module includes a first storage readout section; when the conversion output module includes a gain section, the first storage readout section stores and reads out the first reset signal and the pixel signal under any conversion gain corresponding to the gain section, respectively; or, the first mode working module further includes a second storage readout section, wherein the first storage readout section stores and reads out the first reset signal and the pixel signal under the first conversion gain corresponding to the gain section, respectively, and the second storage readout section stores and reads out the first reset signal and the pixel signal under the second conversion gain corresponding to the gain section, respectively.

[0025] Optionally, the first storage readout section includes a first storage transistor, a second storage transistor, a first storage capacitor, a second storage capacitor, a second source follower transistor, and a first row select transistor. The control terminal of the first storage transistor receives a first storage control signal. The first terminal of the first storage transistor is coupled to the output terminal of the conversion output module. The second terminal of the first storage transistor is coupled to a seventh potential via the first storage capacitor. The second terminal of the first storage transistor is also coupled to the first terminal of the second storage transistor. The control terminal of the second storage transistor receives a second storage control signal. The second terminal of the second storage transistor is coupled to an eighth potential via the second storage capacitor. The second terminal of the second storage transistor is also coupled to the control terminal of the second source follower transistor. The first terminal of the second source follower transistor is coupled to a ninth potential. The second terminal of the second source follower transistor is coupled to the first terminal of the first row select transistor. The control terminal of the first row select transistor receives a first row select control signal. The second terminal of the first row select transistor is coupled to a first column line. Alternatively, the first storage readout section further includes a third storage transistor. The control terminal of the third storage transistor receives a third storage control signal. The first terminal of the third storage transistor is coupled to the first terminal of the first storage transistor. The second terminal of the third storage transistor is coupled to the second terminal of the second storage transistor.

[0026] When the first mode operating module includes a second storage readout section, the second storage readout section includes a fourth storage transistor, a fifth storage transistor, a third storage capacitor, a fourth storage capacitor, a third source follower transistor, and a second row select transistor. The control terminal of the fourth storage transistor receives a fourth storage control signal. The first terminal of the fourth storage transistor is coupled to the output terminal of the conversion output module. The second terminal of the fourth storage transistor is coupled to a tenth potential via the third storage capacitor. The second terminal of the fourth storage transistor is also coupled to the first terminal of the fifth storage transistor. The control terminal of the fifth storage transistor receives a fifth storage control signal, and the second terminal of the fifth storage transistor is coupled to the first potential via the fourth storage capacitor. Connected to the eleventh potential, the second terminal of the fifth storage transistor is also coupled to the control terminal of the third source follower transistor, the first terminal of the third source follower transistor is coupled to the twelfth potential, the second terminal of the third source follower transistor is coupled to the first terminal of the second row select transistor, the control terminal of the second row select transistor receives the second row select control signal, and the second terminal of the second row select transistor is coupled to the second column line; or, the second storage readout portion further includes a sixth storage transistor, wherein the control terminal of the sixth storage transistor receives the sixth storage control signal, the first terminal of the sixth storage transistor is coupled to the first terminal of the fourth storage transistor, and the second terminal of the sixth storage transistor is coupled to the second terminal of the fifth storage transistor.

[0027] Optionally, when the first mode working module includes a second storage readout section, the second storage readout section and the first storage readout section multiplex the second source follower transistor and the first row select transistor. In this case, the first storage readout section or the second storage readout section also includes a readout transistor, wherein the control terminal of the readout transistor receives a readout control signal, the first terminal of the readout transistor is coupled to the second terminal of the second storage transistor or the second terminal of the fifth storage transistor, and the second terminal of the readout transistor is coupled to the control terminal of the second source follower transistor.

[0028] Optionally, when the conversion output module includes an overflow portion and the overflow portion includes an overflow capacitor: each storage capacitor and the overflow capacitor are implemented using MIM capacitors, and the capacitance value of each storage capacitor is greater than the capacitance value of the overflow capacitor.

[0029] Optionally, when the conversion output module includes an overflow portion, the overflow portion shares a first storage capacitor or a second storage capacitor with the first storage read portion; when the first mode operating module includes a second storage read portion, the overflow portion shares one of two corresponding storage capacitors with one of the first storage read portion and the second storage read portion; wherein, the second terminal of the overflow transistor in the overflow portion is coupled to the corresponding storage capacitor;

[0030] Alternatively, when the overflow portion and the first storage read portion share a second storage capacitor or the overflow portion and the second storage read portion share a fourth storage capacitor, the corresponding storage read portion further includes an auxiliary control transistor, wherein the auxiliary control transistor is coupled between the corresponding storage capacitor and the corresponding source follower transistor, and the control terminal of the auxiliary control transistor receives an auxiliary control signal.

[0031] The present invention also provides an image sensor arrangement structure as described in any one of the above claims, comprising:

[0032] The conversion output module includes a photosensitive part, an overflow part, a first reset part, and an output part. The overflow part and the first reset part are disposed on a first side of the photosensitive part, and the output part is disposed on a second side of the photosensitive part. The overflow part and the first reset part are offset from each other.

[0033] The first mode working module includes a first storage readout section, which is disposed on the second side of the photosensitive section;

[0034] The second mode operating module is located on the second side of the photosensitive portion.

[0035] Optionally, the conversion output module further includes a second reset section and / or a gain section, wherein the second reset section is disposed on the first side of the photosensitive section, and the gain section is disposed on the first side of the photosensitive section, wherein the second reset section and the first reset section are disposed along a first direction and the overflow section is disposed along a second direction, and the gain section and the overflow section are disposed along the first direction and the first reset section is disposed along the second direction.

[0036] Optionally, the first mode working module further includes a second storage readout section, disposed on the second side of the photosensitive section.

[0037] Optionally, each transistor and photosensitive element in the conversion output module, the first mode operating module, and the second mode operating module is formed in a semiconductor substrate, and each capacitor in the conversion output module and the first mode operating module is formed in an interconnect structure layer, wherein the interconnect structure layer is formed on the semiconductor substrate.

[0038] Optionally, the capacitors in the conversion output module and the first mode working module are formed in the same interconnect structure layer; and / or, the area of ​​the capacitor in the first mode working module is larger than the area of ​​the capacitor in the conversion output module; and / or, the capacitors in the first mode working module are arranged symmetrically with respect to the capacitors in the conversion output module; and / or, the capacitors in the first mode working module have recessed portions, and the recessed portions of different capacitors are arranged opposite each other to form a recessed region, and the capacitors in the conversion output module are arranged in the recessed region; and / or, the capacitors in the conversion output module and the capacitors in the first mode working module are located in adjacent first and second regions, respectively, and the projection of the capacitor in the first mode working module is located within the projection of the capacitor in the conversion output module in the adjacent direction.

[0039] The present invention also provides a control method for an image sensor as described in any one of the above claims, comprising:

[0040] In the first mode, the operation of storing and then reading out at least one of the first group of signals and the second group of signals is based on the conversion output module and the first mode working module.

[0041] In the second mode, the conversion output module and the second mode working module are used to read out at least one of the first group of signals and the second group of signals.

[0042] Optionally, the first mode and the second mode operate independently, wherein the operation of the image sensor includes:

[0043] In the first mode, the conversion output module and the first mode working module work to store and then read out one of the first group of signals and the second group of signals;

[0044] In the second mode, the conversion output module and the second mode working module operate to read out the first group of signals and the second group of signals;

[0045] Alternatively, the first mode and the second mode may operate in combination, wherein the operation of the image sensor includes:

[0046] During the reset phase, at least the floating diffusion node and the conversion output module are reset.

[0047] During the exposure stage, the conversion output module generates the pixel signal and the overflow signal based on photoelectric conversion;

[0048] During the transfer and storage phase, a first reset signal is generated based on the conversion output module and stored in the first mode working module, and the pixel signal is stored in the first mode working module based on the conversion output module;

[0049] During the readout phase, the first reset signal and the pixel signal are read out based on the first mode working module, and a second reset signal is formed based on the conversion output module, and the second reset signal and the overflow signal are read out based on the second mode working module.

[0050] Optionally, when the first mode and the second mode work together, the operation of the image sensor specifically includes:

[0051] After the exposure phase ends, first read out the overflow signal and the second reset signal in the second mode sequentially, then transfer and store the first reset signal and the pixel signal, and then read out the first reset signal and the pixel signal in the first mode sequentially; or,

[0052] After the exposure stage is completed, the first reset signal and the pixel signal are first transferred and stored. Then, the first reset signal and the pixel signal are read out in the first mode and the second reset signal and the overflow signal are read out in the second mode. The second reset signal is read out before the overflow signal or after the overflow signal is read out.

[0053] Optionally, the first storage readout portion in the first mode working module includes a first storage transistor, a second storage transistor, a first storage capacitor, and a second storage capacitor. When the overflow portion in the conversion output module reuses the first storage capacitor with the first storage readout portion, the operation of the image sensor specifically includes: in the second mode of independent operation, during the process of reading out the second group of signals, performing non-true correlation double sampling of the second group of signals based on the first storage capacitor, and / or, replacing the second mode working module with the first mode working module and performing correlation double sampling of the second group of signals based on the second storage capacitor;

[0054] The second storage readout section in the first mode working module includes a fourth storage transistor, a fifth storage transistor, a third storage capacitor, and a fourth storage capacitor. When the overflow section in the conversion output module reuses the third storage capacitor with the second storage readout section, the operation of the image sensor specifically includes: in the second mode of independent operation, during the readout of the second group of signals, performing non-true correlation double sampling of the second group of signals based on the third storage capacitor, and / or, replacing the second mode working module with the first mode working module and performing correlation double sampling of the second group of signals based on the fourth storage capacitor.

[0055] Optionally, when the conversion output module includes a gain section:

[0056] In the first mode, the conversion output module outputs a first reset signal and a pixel signal under different conversion gains, and the first mode working module performs storage and readout operations on the first reset signal and pixel signal under different conversion gains through different storage and readout sections; or, the conversion output module outputs a first reset signal and a pixel signal under arbitrary conversion gains, and the first mode working module performs storage and readout operations on the first reset signal and pixel signal respectively; and / or,

[0057] In the second mode, the conversion output module outputs a first reset signal and a pixel signal under different conversion gains, as well as a second reset signal and an overflow signal under the first conversion gain. The second mode working module reads out the first reset signal and the pixel signal under different conversion gains, as well as the second reset signal and the overflow signal under the first conversion gain.

[0058] As described above, the image sensor, layout structure, and control method of the present invention, through the design of the conversion output module, the first mode working module, and the second mode working module, can realize the switching between the first mode and the second mode in one image sensor, without the need to switch between different image sensors. Attached Figure Description

[0059] Figure 1 The diagram shown is a structural schematic of a pixel unit in an embodiment of the present invention.

[0060] Figure 2 Displayed as Figure 1 The diagram shows the structure of the overflow portion of the pixel unit and the first storage read portion sharing the first storage capacitor.

[0061] Figure 3 Displayed as Figure 1 The diagram shows the structure of the overflow portion of the pixel unit and the first storage read portion sharing the second storage capacitor.

[0062] Figure 4 This is a schematic diagram of another structure of the pixel unit in an embodiment of the present invention.

[0063] Figure 5 Displayed as Figure 4 The diagram shows a structural schematic of a pixel unit where the second storage readout portion and the first storage readout portion share the second source follower transistor and the first row select transistor.

[0064] Figure 6 Displayed as Figure 4 The diagram shows another structural schematic of the pixel unit where the second storage readout portion and the first storage readout portion reuse the second source follower transistor and the first row select transistor.

[0065] Figure 7 Displayed as Figure 6 The diagram shows the structure of the overflow portion of the pixel unit and the first storage read portion sharing the second storage capacitor.

[0066] Figure 8 Displayed as Figure 6 The diagram shows the structure of the overflow portion of the pixel unit and the second storage read portion sharing the fourth storage capacitor.

[0067] Figure 9 The diagram shows the arrangement of the image sensors in an embodiment of the present invention.

[0068] Figure 10 This is a schematic diagram showing one arrangement of the capacitors in an embodiment of the present invention.

[0069] Figure 11 This is a schematic diagram showing another arrangement of the capacitors in an embodiment of the present invention.

[0070] Figure 12 This is a schematic diagram showing another arrangement of the capacitors in an embodiment of the present invention.

[0071] Figure 13 This is a schematic diagram showing another arrangement of the capacitors in an embodiment of the present invention.

[0072] Figure 14 This is a schematic diagram showing another arrangement of the capacitors in an embodiment of the present invention.

[0073] Component designation explanation

[0074] 100 pixel unit

[0075] 110 Conversion Output Module

[0076] 111 Photosensitive part

[0077] 112 Overflow portion

[0078] 113 First Reset Part

[0079] 114 Output Section

[0080] 115 Second Reset Section

[0081] 116 Gain Section

[0082] 120 First Mode Working Module

[0083] 121 First storage read section

[0084] 122 Second storage read section

[0085] 130 Second Mode Working Module Detailed Implementation

[0086] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] Please see Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0088] like Figure 1 and Figure 4 As shown, this embodiment provides an image sensor, including a plurality of pixel units 100 arranged in an array; wherein, the pixel unit 100 includes a conversion output module 110, a first mode working module 120 and a second mode working module 130.

[0089] The conversion output module 110 outputs a first set of signals consisting of a first reset signal and a pixel signal, and outputs a second set of signals consisting of a second reset signal and an overflow signal. In one example, the conversion output module 110 includes a photosensitive part 111, an overflow part 112, a first reset part 113, and an output part 114, and further includes at least one of a second reset part 115 and a gain part 116.

[0090] The photosensitive portion 111 is coupled to a floating diffusion node FD, accumulates photogenerated electrons based on the photoelectric effect, and transfers the photogenerated electrons at least to the floating diffusion node FD to read out the pixel signal. In one embodiment, the photosensitive portion 111 includes a transmission transistor M1 and a photosensitive element PD; wherein, the control terminal of the transmission transistor M1 receives a transmission control signal TX, the first terminal of the transmission transistor M1 is coupled to the floating diffusion node FD, and the second terminal of the transmission transistor M1 is coupled to a first potential V1 (e.g., ground potential or negative potential) via the photosensitive element PD. It should be noted that in some embodiments, in the photosensitive portion 111, the transmission transistor M1 and the photosensitive element PD correspond one-to-one, and the number of them can be one or more, without limitation.

[0091] The overflow portion 112 is coupled to the floating diffusion node FD or the photosensitive portion 111, and stores the photogenerated electrons overflowing from the floating diffusion node FD or the photosensitive portion 111 to read out the overflow signal. It should be noted that if the charge of the photogenerated electrons does not exceed the storage capacity of the floating diffusion node FD or the photosensitive portion 111, no photogenerated electrons overflow from the floating diffusion node FD or the photosensitive portion 111, which is equivalent to no overflow signal being formed. In one embodiment, the overflow portion 112 includes an overflow transistor M2 and an overflow capacitor C0; wherein, the control terminal of the overflow transistor M2 receives an overflow control signal OF, the first terminal of the overflow transistor M2 is coupled to the floating diffusion node FD or the photosensitive portion 111, and the second terminal of the overflow transistor M2 is coupled to a second potential V2 (e.g., ground potential) via the overflow capacitor C0. In practical applications, the overflow capacitor C0 is implemented using a MIM capacitor. Figures 1 to 4 The diagram shows the overflow portion 112 coupled to the floating diffusion node FD.

[0092] The first reset section 113 is coupled to the floating diffusion node FD, and at least resets the floating diffusion node FD to read out the corresponding reset signal; further, the first reset section 113 also resets the photosensitive portion 111 and the overflow portion 112. In one embodiment, the first reset section 113 includes a first reset transistor M3; wherein, the control terminal of the first reset transistor M3 receives a first reset control signal RST1, the first terminal of the first reset transistor M3 is coupled to a third potential V3 (e.g., power supply potential), and the second terminal of the first reset transistor M3 is coupled to the floating diffusion node FD.

[0093] Output section 114 is coupled to a floating diffusion node FD for amplifying and outputting corresponding signals, such as amplifying and outputting a first reset signal and a pixel signal, and amplifying and outputting a second reset signal and an overflow signal. In one embodiment, output section 114 includes a first source follower transistor M4; wherein the control terminal of the first source follower transistor M4 is coupled to the floating diffusion node FD, the first terminal of the first source follower transistor M4 is coupled to a fourth potential V4 (e.g., a power supply potential or a variable potential), and the second terminal of the first source follower transistor M4 serves as the output terminal of the conversion output module 110.

[0094] When the conversion output module 110 further includes a second reset section 115, the second reset section 115 is coupled to the overflow section 112 for at least resetting the overflow section 112; in one example, the second reset section 115 cooperates with the first reset section 113 to quickly reset the overflow section 112. In one embodiment, the second reset section 115 includes a second reset transistor M5; wherein, the control terminal of the second reset transistor M5 receives a second reset control signal RST2, the first terminal of the second reset transistor M5 is coupled to a fifth potential V5, and the second terminal of the second reset transistor M5 is coupled to the overflow section 112 (e.g., coupled to the end of the overflow capacitor C0 in the overflow section 112 away from the overflow transistor M2). In the above embodiment, the fifth potential V5 and the third potential V3 are the same potential, for example, the power supply potential, so as to facilitate a quick reset of the overflow capacitor C0. Furthermore, the first terminal of the second reset transistor M5 and the first terminal of the first reset transistor M3 are connected to the same power supply voltage transmission line, thereby achieving a quick reset based on the second reset section 115 and the first reset section 113.

[0095] When the conversion output module 110 also includes a gain section 116, the gain section 116 is coupled to the floating diffusion node FD for switching between different conversion gains. In one embodiment, the gain section 116 includes a gain transistor M6 coupled between the first reset module 113 and the floating diffusion node FD. The control terminal of the gain transistor M6 receives a gain control signal DCG, the first terminal of the gain transistor M6 is coupled to the first reset module 113 (e.g., coupled to the second terminal of the first reset transistor M3 in the first reset module 113), and the second terminal of the gain transistor M6 is coupled to the floating diffusion node FD. In this case, in one implementation, the first terminal of the overflow transistor M2 in the overflow section 112 is no longer directly coupled to the floating diffusion node FD, but is directly coupled to the first terminal of the gain transistor M6. Of course, in other embodiments, the gain transistor M6 can also be directly coupled to the floating diffusion node FD, wherein the control terminal of the gain transistor M6 receives the gain control signal DCG, the first terminal of the gain transistor M6 is coupled to the floating diffusion node FD, and the second terminal of the gain transistor M6 is coupled to the sixth potential. At this time, the first reset module 113 is also directly coupled to the floating diffusion node FD.

[0096] The first-mode operating module 120 is connected to the conversion output module 110. In the first mode, it stores and then reads out at least one of the first group of signals and the second group of signals, respectively. In one example, the first-mode operating module 120 includes a first storage and readout section 121, such as... Figure 1 As shown; furthermore, it also includes a second storage readout section 122, as shown. Figure 4 As shown. In practical applications, when the conversion output module 110 does not include the gain section 116, the first mode working module 120 only includes the first storage read section 121; when the conversion output module 110 includes the gain section 116, the first mode working module 120 may only include the first storage read section 121, or it may include both the first storage read section 121 and the second storage read section 122.

[0097] The first storage readout section 121 is connected to the output terminal of the conversion output module 110. When the conversion output module 110 does not include the gain section 116, it stores and reads out at least the first reset signal and the pixel signal respectively. When the conversion output module 110 includes the gain section 116, it stores and reads out at least the first reset signal and the pixel signal under any conversion gain corresponding to the gain section 116 respectively. In one embodiment, such as Figure 1 As shown, the first storage readout section 121 includes a first storage transistor M7, a second storage transistor M8, a first storage capacitor C1, a second storage capacitor C2, a second source follower transistor M9, and a first row select transistor M10. Furthermore, it also includes a third storage transistor M11.

[0098] The control terminal of the first storage transistor M7 receives the first storage control signal CTL1. The first terminal of the first storage transistor M7 is coupled to the output terminal of the conversion output module 110 (e.g., coupled to the second terminal of the first source follower transistor M4 in the output section 114). The second terminal of the first storage transistor M7 is coupled to the seventh potential V7 (e.g., ground potential) via the first storage capacitor C1. The second terminal of the first storage transistor M7 is also coupled to the first terminal of the second storage transistor M8. The control terminal of the second storage transistor M8 receives the second storage control signal CTL2. The second terminal of the second storage transistor M8 is coupled to the eighth potential V8 via the second storage capacitor C2. The second terminal of the second storage transistor M8 is also coupled to the control terminal of the second source follower transistor M9. The first terminal of the second source follower transistor M9 is coupled to the ninth potential V9 (e.g., power supply potential or variable potential). The second terminal of the second source follower transistor M9 is coupled to the first terminal of the first row select transistor M10. The control terminal of the first row select transistor M10 receives the first row select control signal RS1. The second terminal of the first row select transistor M10 is coupled to the first column line BL1. In the above embodiments, when storing the first reset signal and the pixel signal respectively, by controlling the first storage transistor M7 and the second storage transistor M8 to turn on, the first reset signal is first stored in the second storage capacitor C2. By controlling the first storage transistor M7 to turn on and the second storage transistor M8 to turn off, the pixel signal is then stored in the first storage capacitor C1. When reading out the first reset signal and the pixel signal, by controlling the first row selection transistor M10 to turn on, the first reset signal in the second storage capacitor C2 is first read out. By controlling the second storage transistor M8 to turn on, the pixel signal in the first storage capacitor C1 is then read out. It should be noted that the above description of storage and reading out generally describes the storage and reading out of the first reset signal and the pixel signal, so as to facilitate understanding of signal acquisition and the implementation of correlated double sampling based on the difference obtained from the acquired signals. In fact, those skilled in the art will understand that when storing the first reset signal, it is also stored in the first storage capacitor C1 at the same time. Similarly, after reading out, the difference between the first reset signal and the corresponding pixel signal can be obtained to achieve correlated double sampling.

[0099] When the first storage readout section 121 also includes a third storage transistor M11, the control terminal of the third storage transistor M11 receives a third storage control signal CTL3. The first terminal of the third storage transistor M11 is coupled to the first terminal of the first storage transistor M7, and the second terminal of the third storage transistor M11 is coupled to the second terminal of the second storage transistor M8. By adding the third storage transistor M11, the first reset signal can be directly stored in the second storage capacitor C2 by controlling the third storage transistor M11 to be turned on, so that the first reset signal does not pass through the first storage capacitor C1, thus avoiding the influence on the first storage capacitor C1. At this time, the first storage transistor M7 and the second storage transistor M8 are in the off state.

[0100] In practical applications, the first storage capacitor C1 and the second storage capacitor C2 are implemented using MIM capacitors. Typically, the capacitance values ​​of the first storage capacitor C1 and the second storage capacitor C2 are designed to be relatively large to reduce noise in global shutter (GS) mode. In one implementation, the capacitance values ​​of both the first storage capacitor C1 and the second storage capacitor C2 are greater than the capacitance value of the overflow capacitor C0. As an alternative, the capacitance values ​​of the first storage capacitor C1 and the second storage capacitor C2 are designed to be equal. In one implementation, to reduce circuit area, the overflow portion 112 and the first storage readout portion 121 can share the first storage capacitor C1. In this case, the overflow portion 112 no longer includes the overflow capacitor C0, and the second terminal of the overflow transistor M2 is no longer coupled to the second potential V2 via the overflow capacitor C0, but is instead coupled to the seventh potential V7 via the first storage capacitor C1. Figure 2 As shown. Alternatively, the overflow portion 112 and the first storage read portion 121 can share the second storage capacitor C2. In this case, the overflow portion 112 no longer includes the overflow capacitor C0, and the second terminal of the overflow transistor M2 is no longer coupled to the second potential V2 via the overflow capacitor C0, but is coupled to the eighth potential V8 via the second storage capacitor C2, as shown. Figure 3 As shown; in a further design, the first storage readout section 121 also includes an auxiliary control transistor M12, which is coupled between the second storage capacitor C2 and the second source follower transistor M9. The control terminal of the auxiliary control transistor M12 receives the auxiliary control signal ACL. The first terminal of the auxiliary control transistor M12 is coupled to the end of the second storage capacitor C2 away from the eighth potential V8, and the second terminal of the auxiliary control transistor M12 is coupled to the control terminal of the second source follower transistor M9.

[0101] For the two alternative solutions mentioned above, when the conversion output module 110 also includes a second reset section 115, the coupling method of the second reset section 115 is adjusted as follows: In the scheme of reusing the first storage capacitor C1, the second terminal of the second reset transistor M5 in the second reset section 115 is no longer coupled to the end of the overflow capacitor C0 near the second potential V2, but is coupled to the end of the first storage capacitor C1 near the seventh potential V7, so as to facilitate the rapid reset of the first storage capacitor C1 by cooperating with the first reset section 113, such as... Figure 2 As shown; in the scheme of reusing the second storage capacitor C2, the second terminal of the second reset transistor M5 in the second reset section 115 is no longer coupled to the end of the overflow capacitor C0 near the second potential V2, but is coupled to the end of the second storage capacitor C2 near the eighth potential V8, so as to facilitate the rapid reset of the second storage capacitor C2 by cooperating with the first reset section 113, as shown. Figure 3 As shown.

[0102] When the first mode working module 120 further includes a second storage readout section 122, that is, when the first mode working module 120 simultaneously includes a first storage readout section 121 and a second storage readout section 122, the first storage readout section 121 stores and reads out at least the first reset signal and the pixel signal under the first conversion gain corresponding to the gain section 116, and the second storage readout section 122 stores and reads out at least the first reset signal and the pixel signal under the second conversion gain corresponding to the gain section 116. In one embodiment, as... Figure 4 As shown, the second storage readout section 122 includes a fourth storage transistor M13, a fifth storage transistor M14, a third storage capacitor C3, a fourth storage capacitor C4, a third source follower transistor M15, and a second row select transistor M16. Furthermore, it also includes a sixth storage transistor M17.

[0103] The control terminal of the fourth storage transistor M13 receives the fourth storage control signal CTL4. The first terminal of the fourth storage transistor M13 is coupled to the output terminal of the conversion output module 110 (e.g., coupled to the second terminal of the first source follower transistor M4 in the output section 114). The second terminal of the fourth storage transistor M13 is coupled to the tenth potential V10 (e.g., ground potential) via the third storage capacitor C3. The second terminal of the fourth storage transistor M13 is also coupled to the first terminal of the fifth storage transistor M14. The control terminal of the fifth storage transistor M14 receives the fifth storage control signal CTL5. The second terminal of the body transistor M14 is coupled to the eleventh potential V11 (e.g., ground potential) via the fourth storage capacitor C4. The second terminal of the fifth storage transistor M14 is also coupled to the control terminal of the third source follower transistor M15. The first terminal of the third source follower transistor M15 is coupled to the twelfth potential V12 (e.g., power supply potential or variable potential). The second terminal of the third source follower transistor M15 is coupled to the first terminal of the second row select transistor M16. The control terminal of the second row select transistor M16 receives the second row select control signal RS2. The second terminal of the second row select transistor M16 is coupled to the second column line BL2. It should be noted that the storage and readout operations of the second storage readout section 122 for the first reset signal and pixel signal under the second conversion gain corresponding to the gain section 116 are the same as those of the first storage readout section 121, and therefore will not be described again here.

[0104] When the second storage readout section 122 also includes a sixth storage transistor M17, the control terminal of the sixth storage transistor M17 receives the sixth storage control signal CTL6. The first terminal of the sixth storage transistor M17 is coupled to the first terminal of the fourth storage transistor M13, and the second terminal of the sixth storage transistor M17 is coupled to the second terminal of the fifth storage transistor M14. By adding the sixth storage transistor M17, the first reset signal under the second conversion gain can be directly stored in the fourth storage capacitor C4 by controlling the sixth storage transistor M17 to be turned on, so that the first reset signal under the second conversion gain does not pass through the third storage capacitor C3, thus avoiding the influence on the third storage capacitor C3. At this time, the fourth storage transistor M13 and the fifth storage transistor M14 are in the off state.

[0105] In practical applications, the first storage readout section 121 and the second storage readout section 122 can each use a set of source follower transistors and row select transistors as described above, or they can reuse a set of source follower transistors and row select transistors. For the reuse case, for example, the second source follower transistor M9 and the first row select transistor M10 can be reused. Of course, reusing the third source follower transistor M15 and the second row select transistor M160 is also feasible; the above alternatives are essentially the same. To read the corresponding signals in an orderly manner, the first storage readout section 121 or the second storage readout section 122 also includes a readout transistor M18. When the first storage readout section 121 includes a readout transistor M18, the control terminal of the readout transistor M18 receives the readout control signal RCL. The first terminal of the readout transistor M18 is coupled to the second terminal of the second storage transistor M8, and the second terminal of the readout transistor M18 is coupled to the control terminal of the second source follower transistor M9, such as... Figure 5 As shown; when the second storage readout section 122 includes a readout transistor M18, the control terminal of the readout transistor M18 receives the readout control signal RCL, the first terminal of the readout transistor M18 is coupled to the second terminal of the fifth storage transistor M14, and the second terminal of the readout transistor M18 is coupled to the control terminal of the second source follower transistor M9, as shown. Figure 6 As shown.

[0106] The first storage capacitor C1, the second storage capacitor C2, the third storage capacitor C3, and the fourth storage capacitor C4 are implemented using MIM capacitors. Typically, the capacitance value of each storage capacitor is designed to be greater than the capacitance value of the overflow capacitor C0; as an alternative, the capacitance values ​​of each storage capacitor are designed to be equal. To reduce circuit area, the overflow portion 112 and the first storage read portion 121 can share either the first storage capacitor C1 or the second storage capacitor C2, or the overflow portion 112 and the second storage read portion 122 can share either the third storage capacitor C3 or the fourth storage capacitor C4. In this case, the second terminal of the overflow transistor M2 is no longer coupled to the second potential V2 via the overflow capacitor C0, but is instead coupled to the corresponding potential via the corresponding storage capacitor, such as... Figure 7 and Figure 8As shown. The scheme of reusing the third storage capacitor C3 is similar to the scheme of reusing the first storage capacitor C1, and the scheme of reusing the fourth storage capacitor C4 is similar to the scheme of reusing the second storage capacitor C2. Related details can be found above and will not be repeated here. Furthermore, in a further design, for the scheme of reusing the second storage capacitor C2 or the fourth storage capacitor C4, when the first storage readout section 121 or the second storage readout section 122 includes a readout transistor M18, if the reused storage capacitor and the readout transistor M18 are in the same storage readout section, then there is no need to additionally set up an auxiliary control transistor M12; the readout transistor M18 can achieve the function of the auxiliary control transistor M12. If the reused storage capacitor and the readout transistor M18 are not in the same storage readout section, then an additional auxiliary control transistor M12 is still required. Related details can be found above and will not be repeated here.

[0107] For the above four alternative solutions, when the conversion output module 110 also includes a second reset section 115, the coupling method of the second reset section 115 is adjusted. The coupling methods of the second reset transistor M5 corresponding to the first two alternative solutions are detailed above. In the latter two alternative solutions, when the third storage capacitor C3 is reused, the second terminal of the second reset transistor M5 in the second reset section 115 is no longer coupled to the end of the overflow capacitor C0 near the second potential V2, but is instead coupled to the end of the third storage capacitor C3 near the tenth potential V10, so as to facilitate a rapid reset of the third storage capacitor C3 by cooperating with the first reset section 113. When the fourth storage capacitor C4 is reused, the second terminal of the second reset transistor M5 in the second reset section 115 is no longer coupled to the end of the overflow capacitor C0 near the second potential V2, but is instead coupled to the end of the fourth storage capacitor C4 near the eleventh potential V11, so as to facilitate a rapid reset of the fourth storage capacitor C4 by cooperating with the first reset section 113.

[0108] The second-mode operating module 130 is connected to the conversion output module 110. In the second mode, it reads at least one of the first group of signals and the second group of signals. In one embodiment, the second-mode operating module 130 includes a third row selection transistor M19; wherein, the control terminal of the third row selection transistor M19 receives a third row selection control signal RS3, the first terminal of the third row selection transistor M19 is coupled to the output terminal of the conversion output module 110 (for example, coupled to the second terminal of the first source follower transistor M4 in the output section 114), and the second terminal of the third row selection transistor M19 is coupled to the third column line BL3. In practical applications, the third column line BL3 and the first column line BL1 can be the same column line or different column lines, without limitation; while in the first-mode operating module 120, the first column line BL1 and the second column line BL2 can be the same column line or different column lines.

[0109] like Figure 9As shown, this embodiment also provides an image sensor layout structure, including the layout design of each device in the conversion output module 110, the first mode working module 120 and the second mode working module 130; wherein, the image sensor is implemented using the circuit structure described above.

[0110] The conversion output module 110 includes a photosensitive part 111, an overflow part 112, a first reset part 113, and an output part 114, and further includes at least one of a second reset part 115 and a gain part 116.

[0111] The photosensitive portion 111 includes a photosensitive element PD and a transmission transistor, formed in a semiconductor substrate; wherein the photosensitive element PD is rectangular and has a first side to a fourth side, and the transmission transistor M1 is disposed in the corner region adjacent to the first side and the second side of the photosensitive element PD. In practical applications, the transmission transistor M1 is usually disposed in the corner region at an inclined angle, and as an optional solution, the inclined angle is 45°.

[0112] An overflow portion 112 is disposed on the first side of the photosensitive portion 111. In one embodiment, the overflow portion 112 includes an overflow transistor M2 and an overflow capacitor C0, wherein the overflow transistor M2 is formed in a semiconductor substrate and the overflow capacitor C0 is formed in an interconnect structure layer. It should be noted that the overflow portion 112 being disposed on the first side of the photosensitive portion 111 mainly refers to the overflow transistor M2 being disposed on the first side of the photosensitive portion 111.

[0113] The first reset portion 113 is disposed on the first side of the photosensitive portion 111, and the first reset portion 113 and the overflow portion 112 are offset from each other. In one embodiment, the first reset portion 113 includes a first reset transistor M3 formed in a semiconductor substrate; wherein the first reset transistor M3 and the overflow transistor M2 are offset from each other, for example, the first reset transistor M3 and the overflow transistor M2 are disposed along a first direction, and the first reset transistor M3 and the transmission transistor M1 are disposed along a second direction. In this case, the first reset transistor M3 is disposed below the transmission transistor M1, and the overflow transistor M2 is disposed to the left of the first reset transistor M3.

[0114] The output portion 114 is disposed on the second side of the photosensitive portion 111. In one embodiment, the output portion 114 includes a first source follower transistor M4 formed in a semiconductor substrate; wherein the first source follower transistor M4 is disposed on the second side of the photosensitive element PD adjacent to the floating diffusion node FD.

[0115] When the conversion output module 110 further includes a second reset portion 115, the second reset portion 115 is disposed on the first side of the photosensitive portion 111, and the second reset portion 115 is offset from the overflow portion 112 and the first reset portion 113. For example, the second reset portion 115 and the first reset portion 113 are disposed along a first direction and the overflow portion 112 is disposed along a second direction. In one embodiment, the second reset portion 115 includes a second reset transistor M5 formed in a semiconductor substrate; wherein the second reset transistor M5 and the first reset transistor M3 are disposed along the first direction and the overflow transistor M2 is disposed along the second direction. In this case, the second reset transistor M5 is disposed to the left of the first reset transistor M3 and below the overflow transistor M2.

[0116] When the conversion output module 110 further includes a gain section 116, the gain section 116 is disposed on the first side of the photosensitive section 111, and the gain section 116 is offset from the overflow section 112, the first reset section 113, and the second reset section 115. For example, the gain section 116 and the overflow section 112 are disposed along a first direction and the first reset section 113 is disposed along a second direction. In one embodiment, the gain section 116 includes a gain transistor M6 formed in a semiconductor substrate; wherein the gain transistor M6 and the overflow transistor M2 are disposed along the first direction and the first reset transistor M3 is disposed along the second direction, in which case the gain transistor M6 is disposed to the right of the overflow transistor M2 and above the first reset transistor M3.

[0117] The first mode working module 120 includes a first storage readout section 121, and further includes a second storage readout section 122.

[0118] The first storage readout portion 121 is disposed on the second side of the photosensitive portion 111. In one embodiment, the first storage readout portion 121 includes a first storage transistor M7, a second storage transistor M8, a first storage capacitor C1, a second storage capacitor C2, a second source follower transistor M9, and a first row select transistor M10, and further includes a third storage transistor M11; wherein the transistors are formed in a semiconductor substrate, and the capacitors are formed in an interconnect structure layer. The first storage readout section 121 here is located on the second side of the photosensitive section 111. This mainly refers to the fact that the aforementioned transistors are located on the second side of the photosensitive section 111. For example, the first storage transistor M7, the second storage transistor M8, and the third storage transistor M11 are arranged along the second direction with the first source follower transistor M4. The second source follower transistor M9 and the first row select transistor M10 are arranged along the second direction and parallel to each other on the side away from the photosensitive element PD. The first storage transistor M7 is located above the first source follower transistor M4, the second storage transistor M8 is located above the first storage transistor M7, the third storage transistor M11 is located above the second storage transistor M8, the second source follower transistor M9 is located to the right of the third storage transistor M11, and the first row select transistor M10 is located below the second source follower transistor M9.

[0119] When the first mode operating module 120 further includes a second storage readout section 122, the second storage readout section 122 is disposed on the second side of the photosensitive section 111. In one embodiment, the second storage readout section 122 includes a fourth storage transistor M13, a fifth storage transistor M14, a third storage capacitor C3, a fourth storage capacitor C4, a third source follower transistor M15, and a second row select transistor M16, and further includes a sixth storage transistor M17; wherein each of the above transistors is formed in a semiconductor substrate, and each of the above capacitors is formed in an interconnect structure layer. To reduce the circuit area, the first storage readout section 121 and the second storage readout section 122 typically reuse a set of source follower transistors and row select transistors. In this case, the second storage readout section 122 is located on the second side of the photosensitive section 111, which mainly means that the fourth storage transistor M13, the fifth storage transistor M14, and the sixth storage transistor M17 are located on the second side of the photosensitive section 111. For example, the fourth storage transistor M13, the fifth storage transistor M14, and the sixth storage transistor M17 are arranged along the second direction and are located between the third storage transistor M11 and the second source follower transistor M9. The three can be arranged sequentially from bottom to top.

[0120] The second mode operating module 130 is disposed on the second side of the photosensitive portion 111. In one embodiment, the second mode operating module 130 includes a third row select transistor M19 formed in a semiconductor substrate; wherein the third row select transistor M19, the second source follower transistor M9, and the first row select transistor M10 are disposed along a second direction, for example, the third row select transistor M19 is disposed below the first row select transistor M10.

[0121] Interconnect layers are formed on the semiconductor substrate and can be a single layer or multiple layers. In practical applications, each capacitor can be formed in one interconnect layer, or at least two capacitors can be formed in one interconnect layer, but typically all capacitors are formed in the same interconnect layer. Furthermore, the area of ​​each storage capacitor is usually designed to be larger than the area of ​​the overflow capacitor; furthermore, the areas of each storage capacitor are designed to be equal. The layout design of each capacitor can be referenced from [reference needed]. Figures 10 to 14 Specifically, in one embodiment, the overflow capacitor C0 and each storage capacitor are located in adjacent first and second regions, respectively, and the projection of each storage capacitor lies within the projection of the overflow capacitor C0 in the adjacent direction, such as... Figure 10 As shown; in another embodiment, the storage capacitors are designed to be arranged symmetrically about the overflow capacitor C0, as follows. Figure 11 As shown; in other embodiments, each storage capacitor has a recessed portion, and the recessed portions of different capacitors are arranged opposite each other to form a recessed region, with the overflow capacitor C0 arranged in the recessed region, such as... Figures 12 to 14 As shown; of course, other layout designs are also feasible, and there are no restrictions on them.

[0122] This embodiment also provides a control method for an image sensor, including a first mode and a second mode; wherein the image sensor is implemented using the circuit structure described above. In practical applications, the first mode is typically a global shutter mode, and the second mode is typically a rolling shutter mode. The desired mode can be selected according to actual operation.

[0123] In the first mode, the conversion output module 110 and the first mode working module 120 are used to store and then read out at least one of the first group of signals and the second group of signals; in the second mode, the conversion output module 110 and the second mode working module 130 are used to read out at least one of the first group of signals and the second group of signals.

[0124] In one example, the first mode and the second mode operate independently; in this case, the operation of the image sensor includes:

[0125] In the first mode, the conversion output module 110 and the first mode working module 120 are working, while the second mode working module 130 is not working, so as to perform a storage and readout operation on one of the first group of signals and the second group of signals. For example, the storage and readout operation on the first reset signal and the pixel signal, or the storage and readout operation on the second reset signal and the overflow signal; wherein, the specific operation process includes a reset stage, an exposure stage, a transfer storage stage, and a readout stage.

[0126] When storing and reading the first reset signal and pixel signal, in order to Figure 1 For example, the operations performed in each stage are as follows: In the reset stage, at least the transmission transistor M1, the first reset transistor M3, and the gain transistor M6 are turned on. The first reset transistor M3 resets at least the floating diffusion node FD and the photosensitive element PD. Then, at least the transmission transistor M1 is turned off. Of course, turning off the gain transistor M6 is also feasible. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. In the transfer and storage stage, at least the first storage transistor M7 and the third storage transistor M11 are turned on. The first storage capacitor C1 and the second storage capacitor C2 are reset before transfer and storage. Then, the first storage transistor M7 is turned off. Afterwards, because the first source follower transistor M4 and the third storage transistor M11 are in the on state, the first reset signal is stored in the second storage capacitor C2. Then, the third storage transistor M11 is turned off. Afterwards, the transmission transistor M1 is turned on and then off to transfer photogenerated electrons to the floating diffusion node FD. The first storage transistor M7 is turned on and then off to store the pixel signal in the first storage capacitor C1. During the readout phase, the first row selection transistor M10 is turned on to read out the first reset signal, and then the second storage transistor M8 is turned on to read out the pixel signal. In this way, the correlation double sampling of the pixel signal is completed.

[0127] When the conversion output module 110 includes a gain section 116 but the first mode working module 120 only includes a first storage readout section 121, the conversion output module 110 outputs a first reset signal and a pixel signal at any conversion gain, and the first mode working module 120 stores and reads the first reset signal and the pixel signal respectively. When the conversion output module 110 includes a gain section 116 and the first mode working module 120 also includes a second storage readout section 122, in the first mode, the conversion output module 110 outputs a first reset signal and a pixel signal at different conversion gains, and the first mode working module 120 stores and reads the first reset signal and the pixel signal at different conversion gains respectively through different storage readout sections.

[0128] The operation of storing and reading the first reset signal and pixel signal under any conversion gain is the same as above, so it will not be repeated here. The following only describes the operation of storing and reading the first reset signal and pixel signal under different conversion gains. Figure 4 For example, the operations performed in each stage are as follows: In the reset stage, at least the transmission transistor M1, the first reset transistor M3, and the gain transistor M6 are turned on. The first reset transistor M3 resets at least the floating diffusion node FD and the photosensitive element PD, and then at least the transmission transistor M1 is turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. During the transfer storage stage, at least the first storage transistor M7, the third storage transistor M11, the fourth storage transistor M13, and the sixth storage transistor M17 are turned on to reset the first storage capacitor C1, the second storage capacitor C2, the third storage capacitor C3, and the fourth storage capacitor C4 before transfer storage. Then, the first storage transistor M7, the fourth storage transistor M13, and the sixth storage transistor M17 are turned off. Afterward, because the gain transistor M6 is turned on, the image sensor operates at the first conversion gain. The first source follower transistor M4 and the third storage transistor M11 are also turned on, storing the first reset signal at the first conversion gain in the second storage capacitor C2. Then, the gain transistor M6 and the third storage transistor M11 are turned off. Of course, it is also possible to control... When the first reset transistor M3 is turned off, the image sensor operates at the second conversion gain. The sixth storage transistor M17 is then turned on and off, storing the first reset signal at the second conversion gain in the fourth storage capacitor C4. Then, the transmission transistor M1 is turned on and off, transferring photogenerated electrons to the floating diffusion node FD. The fourth storage transistor M13 is then turned on and off, storing the pixel signal at the second conversion gain in the third storage capacitor C3. Next, the gain transistor M6 is turned on, switching the image sensor to the first conversion gain. The transmission transistor M1 is then turned on and off, transferring photogenerated electrons to the floating diffusion node FD. The first storage transistor M7 is then turned on and off, storing the pixel signal at the first conversion gain in the first storage capacitor C1. During the readout phase, the first row selection transistor M10 is turned on to read out the first reset signal under the first conversion gain. Then, the second storage transistor M8 is turned on to read out the pixel signal under the first conversion gain. The second row selection transistor M16 is turned on to read out the first reset signal under the second conversion gain. Then, the fifth storage transistor M14 is turned on to read out the pixel signal under the second conversion gain. In this way, the correlation double sampling of pixel signals under different conversion gains is completed.

[0129] When the first mode working module 120 only includes the first storage readout section 121, if the overflow section 112 and the first storage readout section 121 share the first storage capacitor C1, then during the process of storing and reading out the second reset signal and the overflow signal, the overflow signal is transferred and stored based on the second storage capacitor C2 (i.e., the overflow signal stored in the first storage capacitor C1 is transferred and stored in the second storage capacitor C2), and the second reset signal is transferred and stored based on the first storage capacitor C1, thereby performing a non-true correlation double sampling of the overflow signal; if the overflow section 112 and the first storage readout section 121 share the second storage capacitor C2, then during the process of storing and reading out the second reset signal and the overflow signal, the overflow signal is stored in the second storage capacitor C2, and the second reset signal is stored in the first storage capacitor C1. After the overflow signal is read out, the second reset signal is transferred and stored based on the second storage capacitor C2, thereby performing a non-true correlation double sampling of the overflow signal. Specifically, the process of storing and reading out the second reset signal and the overflow signal respectively includes a reset stage, an exposure stage, a transfer storage stage, and a readout stage.

[0130] When reusing the first storage capacitor C1, Figure 2 For example, the operations performed in each stage are as follows: In the reset stage, at least the transmission transistor M1, overflow transistor M2, first reset transistor M3, and gain transistor M6 are turned on. The first reset transistor M3 resets at least the floating diffusion node FD, the photosensitive element PD, and the first storage capacitor C1. Then, at least the transmission transistor M1 is turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the first storage capacitor C1 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. Afterward, the overflow transistor M2 is turned off. In the transfer storage stage, by turning on and then off the second storage transistor M8, the charge in the first storage capacitor C1 is transferred to the second storage capacitor C2. Then, by turning on and then off the first storage transistor M7, the second reset signal is stored in the first storage capacitor C1. During the readout phase, the first row selection transistor M10 is turned on to read out the overflow signal. Then, the second storage transistor M8 is turned on to read out the second reset signal. In this way, the non-true correlation double sampling of the overflow signal is completed.

[0131] When reusing the second storage capacitor C2, Figure 3For example, the operations performed in each stage are as follows: In the reset stage, at least the transmission transistor M1, overflow transistor M2, first reset transistor M3, and gain transistor M6 are turned on. The first reset transistor M3 resets at least the floating diffusion node FD, the photosensitive element PD, and the second storage capacitor C2. Then, at least the transmission transistor M1 is turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the second storage capacitor C2 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. Afterward, the overflow transistor M2 is turned off. In the transfer storage stage, the first storage transistor M7 is turned on and then turned off, storing the second reset signal in the first storage capacitor C1. In the readout stage, the first row selection transistor M10 and auxiliary control transistor M12 are turned on to read out the overflow signal. Then, the second storage transistor M8 is turned on to read out the second reset signal. This completes the non-true correlated double sampling of the overflow signal.

[0132] When the first mode working module 120 also includes a second storage readout section 122, if the overflow section 112 and the second storage readout section 122 reuse the third storage capacitor C3, the process of storing and reading the second reset signal and the overflow signal is the same as the case of reusing the first storage capacitor C1; if the overflow section 112 and the second storage readout section 122 reuse the fourth storage capacitor C4, the process of storing and reading the second reset signal and the overflow signal is the same as the case of reusing the second storage capacitor C2. Specifically, the process of storing and reading the second reset signal and the overflow signal includes a reset stage, an exposure stage, a transfer storage stage, and a readout stage. The case of reusing the third storage capacitor C3 is the same as the case of reusing the first storage capacitor C1, and the case of reusing the fourth storage capacitor C4 is the same as the case of reusing the second storage capacitor C2. For details, please refer to the above text; further elaboration is not provided here.

[0133] In the second mode, the conversion output module 110 and the second mode working module 130 are working, while the first mode working module 120 is not working, in order to perform readout operations on the first group of signals and the second group of signals, such as reading out the first reset signal and the pixel signal, and reading out the second reset signal and the overflow signal; wherein, the specific operation process includes a reset stage, an exposure stage and a readout stage.

[0134] by Figure 1For example, the operations performed in each stage are as follows: In the reset stage, the control transmission transistor M1, overflow transistor M2, first reset transistor M3, second reset transistor M5, and gain transistor M6 are turned on. The first reset transistor M3 resets the floating diffusion node FD and the photosensitive element PD. The first reset transistor M3 and the second reset transistor M5 work together to reset the overflow capacitor C0. Then, the control transmission transistor M1, first reset transistor M3, and second reset transistor M5 are turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the overflow capacitor C0 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. Afterward, the overflow transistor M2 is turned off. During the readout phase, the third row selection transistor M19 is turned on and then off to read the first reset signal. Then, the transmission transistor M1 is turned on and then off to transfer photogenerated electrons to the floating diffusion node FD. The third row selection transistor M19 is then turned on and then off to read the pixel signal. Next, the overflow transistor M2 is turned on and then off to read the overflow signal. Then, the first reset transistor M3 is turned on and then off to reset the floating diffusion node FD. The third row selection transistor M19 is then turned on and then off to read the second reset signal. In this way, correlated double sampling of the pixel signal and non-true correlated double sampling of the overflow signal are completed sequentially. During the readout process, the third row selection transistor M19 can also be kept on. Of course, in other examples, a reset operation can be performed before reading the overflow signal, and the second reset signal can be read out, thus completing the correlated double sampling of the overflow signal.

[0135] When the conversion output module 110 includes a gain section 116 and the gain section 116 performs conversion gain switching, in the second mode, the conversion output module 110 outputs a first reset signal and a pixel signal under different conversion gains, and outputs a second reset signal and an overflow signal under any conversion gain, such as a second reset signal and an overflow signal under the first conversion gain. At this time, the second mode working module 130 performs a readout operation on the first reset signal and pixel signal under different conversion gains, as well as the second reset signal and overflow signal under the first conversion gain.

[0136] by Figure 4For example, the operations performed in each stage are as follows: In the reset stage, the control transmission transistor M1, overflow transistor M2, first reset transistor M3, second reset transistor M5, and gain transistor M6 are turned on. The first reset transistor M3 resets the floating diffusion node FD and the photosensitive element PD. The first reset transistor M3 and the second reset transistor M5 work together to reset the overflow capacitor C0. Then, the control transmission transistor M1, first reset transistor M3, and second reset transistor M5 are turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the overflow capacitor C0 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. Afterward, the overflow transistor M2 is turned off. During the readout phase, with gain transistor M6 on, the image sensor operates at the first conversion gain. This controls the third row select transistor M19 to turn on, performing a readout operation on the first reset signal under the first conversion gain. Then, gain transistor M6 is turned off, causing the image sensor to operate at the second conversion gain, and the first reset signal under the second conversion gain is read out. The third row select transistor M19 is then turned off again. Afterward, the transmission transistor M1 is turned on and then off, transferring photogenerated electrons to the floating diffusion node FD. This then controls the third row select transistor M19 to turn on, performing a readout operation on the pixel signal under the second conversion gain. The control gain transistor M6 is turned on, switching the image sensor to the first conversion gain, and reading out the pixel signal at the first conversion gain. Then, the overflow transistor M2 is turned on and then off, reading out the overflow signal at the first conversion gain. Next, the first reset transistor M3 is turned on and then off, resetting the floating diffusion node FD. Finally, the third row select transistor M19 is turned on and then off, reading out the second reset signal at the first conversion gain. In this way, correlated double sampling of the pixel signal at different conversion gains and non-true correlated double sampling of the overflow signal at the first conversion gain are completed sequentially. Alternatively, a reset operation can be performed before reading out the overflow signal at the first conversion gain, and the second reset signal at the first conversion gain can be read out, thus completing the correlated double sampling of the overflow signal at the first conversion gain.

[0137] Of course, in the case of capacitor reuse, that is, the overflow portion 112 and the first storage read portion 121 reuse the first storage capacitor C1 or the second storage capacitor C2, or the overflow portion 112 and the second storage read portion 122 reuse the third storage capacitor C3 or the fourth storage capacitor C4, when the overflow signal is read out by the second mode working module 130, the corresponding storage transistor should also be turned on to achieve this.

[0138] In addition, for cases where capacitor reuse occurs, particularly where the overflow portion 112 reuses the first storage capacitor C1 with the first storage read portion 121, or where the overflow portion 112 reuses the third storage capacitor C3 with the second storage read portion 122, the first mode working module 120 can replace the second mode working module 130 to achieve at least one of correlated double sampling and non-true correlated double sampling of the overflow signal.

[0139] In the case of reusing the first storage capacitor C1, during the reading of the second group of signals in the second mode, the first mode working module 120 replaces the second mode working module 130. That is, the first mode working module 120 works while the second mode working module 130 does not work. At this time, non-true correlation double sampling of the second group of signals can be performed based on the first storage capacitor C1 (first, the overflow signal stored in the first storage capacitor C1 is transferred and stored in the second storage capacitor C2, and then the second reset signal is transferred and stored in the first storage capacitor C1. The overflow signal and the second reset signal are read out to achieve non-true correlation double sampling). Alternatively, correlation double sampling of the second group of signals can be performed based on the second storage capacitor C2 (the overflow signal is stored in the first storage capacitor C1, the second reset signal is obtained based on the second storage capacitor C2 and the third storage transistor M11, and after the second reset signal is read out, the overflow signal is transferred and stored based on the second storage capacitor C2 and then read out, thereby performing true correlation double sampling of the overflow signal).

[0140] In the case of reusing the third storage capacitor C3, during the reading of the second group of signals in the second mode, the first mode working module 120 replaces the second mode working module 130. That is, the first mode working module 120 works while the second mode working module 130 does not work. At this time, non-true correlation double sampling of the second group of signals can be performed based on the third storage capacitor C3 (first, the overflow signal stored in the third storage capacitor C3 is transferred and stored in the fourth storage capacitor C4, and then the second reset signal is transferred and stored in the third storage capacitor C3, and the overflow signal and the second reset signal are read out to achieve non-true correlation double sampling). Alternatively, correlation double sampling of the second group of signals can be performed based on the fourth storage capacitor C4 (the overflow signal is stored in the third storage capacitor C3, the second reset signal is obtained based on the fourth storage capacitor C4 and the sixth storage transistor M17, and after the second reset signal is read out, the overflow signal is transferred and stored based on the fourth storage capacitor C4 and then read out, thereby performing true correlation double sampling of the overflow signal).

[0141] In another example, the first mode and the second mode work together, in which the operation of the image sensor includes a reset phase, an exposure phase, a transfer storage phase, and a readout phase.

[0142] During the reset phase, at least the floating diffusion node FD and the conversion output module 110 are reset; during the exposure phase, the conversion output module 110 generates a pixel signal and an overflow signal based on photoelectric conversion; during the transfer and storage phase, a first reset signal is generated based on the conversion output module 110 and stored in the first mode working module 120, and the pixel signal is stored in the first mode working module 120 based on the conversion output module 110; during the readout phase, the first reset signal and the pixel signal are read out based on the first mode working module 120, and a second reset signal is generated based on the conversion output module 110, and the second reset signal and the overflow signal are read out based on the second mode working module 130.

[0143] In one implementation, after the exposure stage, the overflow signal and the second reset signal in the second mode are read out sequentially, then the first reset signal and the pixel signal are transferred and stored, and then the first reset signal and the pixel signal in the first mode are read out sequentially. Figure 1For example, the operations performed in each stage are as follows: In the reset stage, control transmission transistor M1, overflow transistor M2, first reset transistor M3, first source follower transistor M4, second reset transistor M5, gain transistor M6, first storage transistor M7, and third storage transistor M11 are turned on. The first reset transistor M3 resets the floating diffusion node FD, photosensitive element PD, first storage capacitor C1, and second storage capacitor C2. The first reset transistor M3 and second reset transistor M5 work together to reset the overflow capacitor C0. Then, control transmission transistor M1, first reset transistor M3, second reset transistor M5, first storage transistor M7, and third storage transistor M11 are turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the overflow capacitor C0 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. In the transfer storage and readout stages, firstly, overflow transistor M2 and gain transistor M6 are turned on. Then, the third row selection transistor M19 is turned on and then off to read out the overflow signal. After this, overflow transistor M2 is turned off. Next, the first reset transistor M3 is turned on and then off to reset the floating diffusion node FD. Then, the third row selection transistor M19 is turned on and then off to read out the second reset signal. This completes the non-true correlation double sampling of the overflow signal. Next, the third storage transistor M11 is turned on and then off to transfer the first reset signal to the second storage capacitor C2. Then, the transmission transistor M1 is turned on and then off to transfer photogenerated electrons to the floating diffusion node. Then, the first storage transistor M7 is turned on and then off to transfer the pixel signal to the first storage capacitor C1. Finally, the first row selection transistor M10 is turned on to read out the first reset signal. Then, the second storage transistor M8 is turned on and then off to read out the pixel signal. This completes the correlation double sampling of the pixel signal.

[0144] In another implementation, after the exposure stage, the first reset signal and pixel signal are first transferred and stored, followed by reading out the first reset signal and pixel signal in the first mode and reading out the second reset signal and overflow signal in the second mode, wherein the second reset signal is read out before or after the overflow signal. Figure 1For example, the operations performed in each stage are as follows: In the reset stage, the control transmission transistor M1, overflow transistor M2, first reset transistor M3, first source follower transistor M4, second reset transistor M5, gain transistor M6, first storage transistor M7, and third storage transistor M11 are turned on. The first reset transistor M3 resets the floating diffusion node FD, the photosensitive element PD, the first storage capacitor C1, and the second storage capacitor C2. The first reset transistor M3 and the second reset transistor M5 work together to reset the overflow capacitor C0. Then, the control transmission transistor M1, first reset transistor M3, second reset transistor M5, first storage transistor M7, and third storage transistor M11 are turned off. In the exposure stage, the photosensitive element PD accumulates photogenerated electrons based on the photoelectric effect. The portion exceeding the photosensitive element PD is stored in the overflow capacitor C0 via the floating diffusion node FD, gain transistor M6, and overflow transistor M2. Then, the overflow transistor M2 is turned off. In the transfer storage and readout stages, firstly, the third storage transistor M11 is turned on and then off to transfer the first reset signal to the second storage capacitor C2. Then, the transmission transistor M1 is turned on and then off to transfer the photogenerated electrons to the floating diffusion node. Next, the first storage transistor M7 is turned on and then off to transfer the pixel signal to the first storage capacitor C1. Then, the first row selection transistor M10 is turned on to read out the first reset signal. Then, the second storage transistor M8 is turned on and then off to read out the pixel signal, thus completing the correlation double sampling of the pixel signal. Finally, the first reset transistor M3 is turned on and then off to reset the floating diffusion node FD. The third row selection transistor M19 is turned on and then off to read out the second reset signal. Then, the overflow transistor M2 is turned on and the third row selection transistor M19 is turned on and then off to read out the overflow signal, thus completing the correlation double sampling of the overflow signal. Of course, it is also feasible to read out the overflow signal first and then read out the second reset signal through reset. In this case, the overflow signal is not a true correlation double sampling.

[0145] When the first mode working module 120 also includes a second storage readout section 122, during the transfer storage stage, based on the conversion output module 110, a first reset signal under different conversion gains is generated, the first reset signal under the first conversion gain is stored in the first storage readout section 121, and the first reset signal under the second conversion gain is stored in the second storage readout section 122. Similarly, based on the conversion output module 110, pixel signals under the first conversion gain are stored in the first storage readout section 121, and pixel signals under the second conversion gain are stored in the second storage readout section 122. During the readout stage, based on the first mode working module 120, the first reset signal and pixel signals under different conversion gains are read out, and based on the conversion output module 110, a second reset signal is generated, and based on the second mode working module 130, the second reset signal and overflow signal are read out. In one embodiment, after the exposure stage ends, the overflow signal and the second reset signal in the second mode are read out sequentially, then the first reset signal and pixel signals under different conversion gains are transferred and stored, and then the first reset signal and pixel signals under different conversion gains in the first mode are read out sequentially. In another implementation, after the exposure stage is completed, the first reset signal and pixel signal under different conversion gains are first transferred and stored, and then the first reset signal and pixel signal under different conversion gains in the first mode are read out, and the second reset signal and overflow signal in the second mode are read out, wherein the second reset signal is read out before the overflow signal or the second reset signal is read out after the overflow signal.

[0146] In summary, the image sensor, its arrangement structure, and control method of the present invention, through the design of a conversion output module, a first mode working module, and a second mode working module, enable the switching between the first and second modes within a single image sensor, eliminating the need for switching between different image sensors. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and possesses high industrial applicability.

[0147] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that, It includes a plurality of pixel units arranged in an array, wherein the pixel unit includes: The conversion output module outputs a first set of signals consisting of a first reset signal and a pixel signal, and outputs a second set of signals consisting of a second reset signal and an overflow signal. The first mode working module is connected to the conversion output module. In the first mode, it stores and then reads out at least one of the first group of signals and the second group of signals respectively. The second mode working module is connected to the conversion output module. In the second mode, at least one of the first group of signals and the second group of signals is read out respectively.

2. The image sensor according to claim 1, characterized in that, The conversion output module includes: The photosensitive part is coupled to a floating diffusion node, accumulates photogenerated electrons based on the photoelectric effect, and transfers the photogenerated electrons to at least the floating diffusion node to read out the pixel signal; The overflow portion is coupled to the floating diffusion node or the photosensitive portion, and the photogenerated electrons overflowing from the floating diffusion node or the photosensitive portion are stored to read out the overflow signal; The first reset section is coupled to the floating diffusion node and at least resets the floating diffusion node to read out the corresponding reset signal. The output section is coupled to the floating diffusion node and is used to amplify and output the corresponding signal.

3. The image sensor according to claim 2, characterized in that, The photosensitive part includes a transmission transistor and a photosensitive element, wherein the control terminal of the transmission transistor receives a transmission control signal, the first terminal of the transmission transistor is coupled to the floating diffusion node, and the second terminal of the transmission transistor is coupled to a first potential via the photosensitive element; And / or, the overflow portion includes an overflow transistor and an overflow capacitor, wherein the control terminal of the overflow transistor receives an overflow control signal, the first terminal of the overflow transistor is coupled to the floating diffusion node or the photosensitive portion, and the second terminal of the overflow transistor is coupled to a second potential via the overflow capacitor; And / or, the first reset portion includes a first reset transistor, wherein the control terminal of the first reset transistor receives a first reset control signal, the first terminal of the first reset transistor is coupled to a third potential, and the second terminal of the first reset transistor is coupled to the floating diffusion node; And / or, the output section includes a first source follower transistor, wherein the control terminal of the first source follower transistor is coupled to the floating diffusion node, the first terminal of the first source follower transistor is coupled to a fourth potential, and the second terminal of the first source follower transistor serves as the output terminal of the conversion output module.

4. The image sensor according to claim 2, characterized in that, The conversion output module also includes: The second reset part is coupled to the overflow part and at least resets the overflow part; And / or, the gain portion, coupled to the floating diffusion node, is used for switching between different conversion gains.

5. The image sensor according to claim 4, characterized in that, When the conversion output module includes a second reset section, the second reset section includes a second reset transistor, wherein the control terminal of the second reset transistor receives a second reset control signal, the first terminal of the second reset transistor is coupled to a fifth potential, and the second terminal of the second reset transistor is coupled to the overflow section; the second reset section resets the overflow section by cooperating with the first reset section. When the conversion output module includes a gain section, the gain section includes a gain transistor, wherein the gain transistor is coupled between the first reset module and the floating diffusion node, or the first terminal of the gain transistor is coupled to the floating diffusion node and the second terminal is coupled to a sixth potential, and the control terminal of the gain transistor receives a gain control signal.

6. The image sensor according to claim 1, characterized in that, The second mode operating module includes a third row selection transistor, wherein the control terminal of the third row selection transistor receives a third row selection control signal, the first terminal of the third row selection transistor is coupled to the output terminal of the conversion output module, and the second terminal of the third row selection transistor is coupled to the third column line.

7. The image sensor according to any one of claims 1 to 6, characterized in that, The first mode working module includes a first storage readout section; when the conversion output module includes a gain section, the first storage readout section stores and reads out the first reset signal and the pixel signal under any conversion gain corresponding to the gain section, respectively; or, the first mode working module further includes a second storage readout section, wherein the first storage readout section stores and reads out the first reset signal and the pixel signal under the first conversion gain corresponding to the gain section, respectively, and the second storage readout section stores and reads out the first reset signal and the pixel signal under the second conversion gain corresponding to the gain section, respectively.

8. The image sensor according to claim 7, characterized in that, The first storage readout section includes a first storage transistor, a second storage transistor, a first storage capacitor, a second storage capacitor, a second source follower transistor, and a first row select transistor. The control terminal of the first storage transistor receives a first storage control signal. The first terminal of the first storage transistor is coupled to the output terminal of the conversion output module. The second terminal of the first storage transistor is coupled to a seventh potential via the first storage capacitor. The second terminal of the first storage transistor is also coupled to the first terminal of the second storage transistor. The control terminal of the second storage transistor receives a second storage control signal. The second terminal of the second storage transistor is coupled to an eighth potential via the second storage capacitor. The second terminal of the second storage transistor is also coupled to the control terminal of the second source follower transistor. The first terminal of the second source follower transistor is coupled to a ninth potential. The second terminal of the second source follower transistor is coupled to the first terminal of the first row select transistor. The control terminal of the first row select transistor receives a first row select control signal. The second terminal of the first row select transistor is coupled to a first column line. Alternatively, the first storage readout section further includes a third storage transistor, wherein the control terminal of the third storage transistor receives a third storage control signal. The first terminal of the third storage transistor is coupled to the first terminal of the first storage transistor, and the second terminal of the third storage transistor is coupled to the second terminal of the second storage transistor. When the first mode operating module includes a second storage readout section, the second storage readout section includes a fourth storage transistor, a fifth storage transistor, a third storage capacitor, a fourth storage capacitor, a third source follower transistor, and a second row select transistor. The control terminal of the fourth storage transistor receives a fourth storage control signal. The first terminal of the fourth storage transistor is coupled to the output terminal of the conversion output module. The second terminal of the fourth storage transistor is coupled to a tenth potential via the third storage capacitor. The second terminal of the fourth storage transistor is also coupled to the first terminal of the fifth storage transistor. The control terminal of the fifth storage transistor receives a fifth storage control signal, and the second terminal of the fifth storage transistor is coupled to the first potential via the fourth storage capacitor. Connected to the eleventh potential, the second terminal of the fifth storage transistor is also coupled to the control terminal of the third source follower transistor, the first terminal of the third source follower transistor is coupled to the twelfth potential, the second terminal of the third source follower transistor is coupled to the first terminal of the second row select transistor, the control terminal of the second row select transistor receives the second row select control signal, and the second terminal of the second row select transistor is coupled to the second column line; or, the second storage readout portion further includes a sixth storage transistor, wherein the control terminal of the sixth storage transistor receives the sixth storage control signal, the first terminal of the sixth storage transistor is coupled to the first terminal of the fourth storage transistor, and the second terminal of the sixth storage transistor is coupled to the second terminal of the fifth storage transistor.

9. The image sensor according to claim 8, characterized in that, When the first mode working module includes a second storage readout section, the second storage readout section and the first storage readout section share the second source follower transistor and the first row select transistor. At this time, the first storage readout section or the second storage readout section also includes a readout transistor, wherein the control terminal of the readout transistor receives a readout control signal, the first terminal of the readout transistor is coupled to the second terminal of the second storage transistor or the second terminal of the fifth storage transistor, and the second terminal of the readout transistor is coupled to the control terminal of the second source follower transistor.

10. The image sensor according to claim 8, characterized in that, When the conversion output module includes an overflow portion and the overflow portion includes an overflow capacitor: each storage capacitor and the overflow capacitor are implemented using MIM capacitors, and the capacitance value of each storage capacitor is greater than the capacitance value of the overflow capacitor.

11. The image sensor according to claim 7, characterized in that, When the conversion output module includes an overflow portion, the overflow portion shares a first storage capacitor or a second storage capacitor with the first storage read portion; when the first mode working module includes a second storage read portion, the overflow portion shares one of two corresponding storage capacitors with one of the first storage read portion and the second storage read portion; wherein, the second terminal of the overflow transistor in the overflow portion is coupled to the corresponding storage capacitor; Alternatively, when the overflow portion and the first storage read portion share a second storage capacitor or the overflow portion and the second storage read portion share a fourth storage capacitor, the corresponding storage read portion further includes an auxiliary control transistor, wherein the auxiliary control transistor is coupled between the corresponding storage capacitor and the corresponding source follower transistor, and the control terminal of the auxiliary control transistor receives an auxiliary control signal.

12. An image sensor arrangement structure as described in any one of claims 1 to 11, characterized in that, include: The conversion output module includes a photosensitive part, an overflow part, a first reset part, and an output part. The overflow part and the first reset part are disposed on a first side of the photosensitive part, and the output part is disposed on a second side of the photosensitive part. The overflow part and the first reset part are offset from each other. The first mode working module includes a first storage readout section, which is disposed on the second side of the photosensitive section; The second mode working module is located on the second side of the photosensitive part.

13. The image sensor arrangement structure according to claim 12, characterized in that, The conversion output module further includes a second reset section and / or a gain section. The second reset section is disposed on a first side of the photosensitive section, and the gain section is disposed on a first side of the photosensitive section. The second reset section and the first reset section are disposed along a first direction and the overflow section is disposed along a second direction. The gain section and the overflow section are disposed along a first direction and the first reset section is disposed along a second direction.

14. The image sensor arrangement structure according to claim 12, characterized in that, The first mode working module also includes a second storage readout section, which is disposed on the second side of the photosensitive section.

15. The image sensor arrangement structure according to any one of claims 12 to 14, characterized in that, The transistors and photosensitive elements in the conversion output module, the first mode working module, and the second mode working module are formed in a semiconductor substrate, and the capacitors in the conversion output module and the first mode working module are formed in an interconnect structure layer, wherein the interconnect structure layer is formed on the semiconductor substrate.

16. The image sensor arrangement structure according to claim 15, characterized in that, The capacitors in the conversion output module and the first mode working module are formed in the same interconnect structure layer; and / or, the area of ​​the capacitor in the first mode working module is larger than the area of ​​the capacitor in the conversion output module. And / or, the capacitors in the first mode working module are arranged symmetrically with respect to the capacitors in the conversion output module; and / or, the capacitors in the first mode working module have recessed portions, and the recessed portions of different capacitors are arranged opposite each other to form a recessed region, and the capacitors in the conversion output module are arranged in the recessed region; and / or, the capacitors in the conversion output module and the capacitors in the first mode working module are located in adjacent first and second regions, respectively, and the projection of the capacitors in the first mode working module is located within the projection of the capacitors in the conversion output module in the adjacent direction.

17. A control method for an image sensor as described in any one of claims 1 to 11, characterized in that, include: In the first mode, the operation of storing and then reading out at least one of the first group of signals and the second group of signals is based on the conversion output module and the first mode working module. In the second mode, the conversion output module and the second mode working module are used to read out at least one of the first group of signals and the second group of signals.

18. The control method for an image sensor according to claim 17, characterized in that, The first mode and the second mode operate independently, wherein the operation of the image sensor includes: In the first mode, the conversion output module and the first mode working module work to store and then read out one of the first group of signals and the second group of signals; In the second mode, the conversion output module and the second mode working module operate to read out the first group of signals and the second group of signals; Alternatively, the first mode and the second mode may operate in combination, wherein the operation of the image sensor includes: During the reset phase, at least the floating diffusion node and the conversion output module are reset. During the exposure stage, the conversion output module generates the pixel signal and the overflow signal based on photoelectric conversion; During the transfer and storage phase, a first reset signal is generated based on the conversion output module and stored in the first mode working module, and the pixel signal is stored in the first mode working module based on the conversion output module; During the readout phase, the first reset signal and the pixel signal are read out based on the first mode working module, and a second reset signal is formed based on the conversion output module, and the second reset signal and the overflow signal are read out based on the second mode working module.

19. The control method for an image sensor according to claim 18, characterized in that, When the first mode and the second mode work together, the operation of the image sensor specifically includes: After the exposure phase ends, first read out the overflow signal and the second reset signal in the second mode sequentially, then transfer and store the first reset signal and the pixel signal, and then read out the first reset signal and the pixel signal in the first mode sequentially; or, After the exposure stage is completed, the first reset signal and the pixel signal are first transferred and stored. Then, the first reset signal and the pixel signal are read out in the first mode and the second reset signal and the overflow signal are read out in the second mode. The second reset signal is read out before the overflow signal or after the overflow signal is read out.

20. The control method for an image sensor according to claim 18, characterized in that, The first storage readout section in the first mode working module includes a first storage transistor, a second storage transistor, a first storage capacitor, and a second storage capacitor. When the overflow section in the conversion output module reuses the first storage capacitor with the first storage readout section, the operation of the image sensor specifically includes: in the second mode of independent operation, during the process of reading out the second group of signals, performing non-true correlation double sampling of the second group of signals based on the first storage capacitor, and / or, replacing the second mode working module with the first mode working module and performing correlation double sampling of the second group of signals based on the second storage capacitor; The second storage readout section in the first mode working module includes a fourth storage transistor, a fifth storage transistor, a third storage capacitor, and a fourth storage capacitor. When the overflow section in the conversion output module reuses the third storage capacitor with the second storage readout section, the operation of the image sensor specifically includes: in the second mode of independent operation, during the readout of the second group of signals, performing non-true correlation double sampling of the second group of signals based on the third storage capacitor, and / or, replacing the second mode working module with the first mode working module and performing correlation double sampling of the second group of signals based on the fourth storage capacitor.

21. The control method for an image sensor according to claim 17, characterized in that, When the conversion output module includes a gain section: In the first mode, the conversion output module outputs a first reset signal and a pixel signal under different conversion gains, and the first mode working module performs storage and readout operations on the first reset signal and pixel signal under different conversion gains through different storage and readout sections; or, the conversion output module outputs a first reset signal and a pixel signal under arbitrary conversion gains, and the first mode working module performs storage and readout operations on the first reset signal and pixel signal respectively; and / or, In the second mode, the conversion output module outputs a first reset signal and a pixel signal under different conversion gains, as well as a second reset signal and an overflow signal under the first conversion gain. The second mode working module reads out the first reset signal and the pixel signal under different conversion gains, as well as the second reset signal and the overflow signal under the first conversion gain.

Images