Image sensor circuit storage circuit, image sensor circuit and method

Abstract

This invention discloses a storage circuit, an image sensor circuit, and a method thereof for an image sensor circuit. The storage circuit includes a transmission gate switching transistor, a floating diffusion node, a signal storage circuit, and a reset storage circuit. A reference level located on the side of the first floating diffusion node varies between a low level and a high level. When the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset. Then, when the reference level changes from the low level to the high level, the voltage of the second floating diffusion node increases in response to the charge signal of the first floating diffusion node. The image sensor circuit can reduce circuit costs and provide a high dynamic range for pixel charge.

Description

Technical Field

[0001] This application relates to an image sensing mechanism, and more particularly to an image sensor circuit, a corresponding storage circuit, and a corresponding method. Background Technology

[0002] Generally, conventional image sensor devices inevitably require a bias current source and a gate-select transistor to transfer signal charge from a first floating diffusion node in the sensor circuitry to a second floating diffusion node coupled to a readout circuitry. In practice, this conventional circuitry undoubtedly leads to significantly higher costs. Furthermore, conventional image sensor devices cannot provide high dynamic range for signal charge. Summary of the Invention

[0003] Therefore, one of the purposes of this application is to disclose an image sensor circuit and its corresponding storage circuit to solve the above-mentioned problems.

[0004] According to an embodiment of this application, a storage circuit for an image sensor circuit is disclosed. The storage circuit is disposed between the sensor circuit and the readout circuit of the image sensor circuit. The storage circuit includes a transmission gate switching transistor, a second floating diffusion node, a signal storage circuit, and a reset storage circuit. A first node of the transmission gate switching transistor is coupled to a first floating diffusion node, and a second node of the transmission gate switching transistor is coupled to a second floating diffusion node. The second floating diffusion node is used to be read by the readout circuit. The signal storage circuit is coupled between the second floating diffusion node and a ground level. The reset storage circuit is coupled between the second floating diffusion node and the ground level. A reference level located on the first floating diffusion node side varies between a low level and a high level. When the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset, and then when the reference level changes from the low level to the high level, the voltage of the second floating diffusion node increases in response to the charge signal of the first floating diffusion node.

[0005] According to an embodiment of this application, a method for an image sensor circuit is also disclosed. The image sensor circuit has a storage circuit disposed between the sensor circuit and the readout circuit of the image sensor circuit. The method includes: raising a transmission gate switching transistor, a first node of which is coupled to a first floating diffusion node, and a second node of which is coupled to a second floating diffusion node; providing the second floating diffusion node for being read by the readout circuit; providing a signal storage circuit coupled between the second floating diffusion node and a ground level; providing a reset storage circuit coupled between the second floating diffusion node and the ground level; controlling a reference level located on the first floating diffusion node side to change between a low level and a high level; resetting the voltage of the second floating diffusion node when the reference level changes from the high level to the low level; and increasing the voltage of the second floating diffusion node in response to a charge signal of the first floating diffusion node when the reference level changes from the low level to the high level. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an image sensor circuit according to an embodiment of this application.

[0007] Figure 2 According to an embodiment of this application, it includes multiple Figure 1 The diagram shows a schematic of an image sensing device with an image sensor circuit.

[0008] Figure 3 According to an embodiment of this application Figure 1 The diagram shows waveforms of the corresponding control signals, charge dumping operations (e.g., global dumping), and readout operations (e.g., line readout) of the image sensor circuit shown.

[0009] Figure 4 This is another different embodiment according to this application. Figure 1 The diagram shows the waveforms of the corresponding control signals, charge dumping operations (e.g., global dumping), and readout operations (e.g., row readout) of the image sensor circuit.

[0010] Figure 5 This is a schematic diagram of an image sensor circuit according to another embodiment of this application.

[0011] Figure 6 According to an implementation of this application, for example Figure 5 The diagram shows the corresponding control signals of the image sensor circuit, as well as the waveforms of tilting operations (e.g., global tilting) and reading operations (e.g., line readout).

[0012] Figure 7 This is a schematic diagram of an image sensor circuit according to another embodiment of this application.

[0013] Figure 8 This is another embodiment according to this application. Figure 7 The diagram shows the waveforms of the control signals, tilting operations (e.g., global tilting), and reading operations (e.g., line reading operations) of the image sensor circuit.

[0014] The reference numerals in the attached figures are explained as follows:

[0015] 100, 500, 700 image sensor circuits

[0016] 105, 505, 705 sensor circuits

[0017] 110, 510 storage circuits

[0018] 115 and 515 readout circuits

[0019] 200 Image Sensing Devices

[0020] 205 Controller

[0021] 210 Image Sensor Device

[0022] 1101R, 5101R Reset Storage Circuit

[0023] 1101S, 5101L, 5101H signal storage circuit Detailed Implementation

[0024] This application aims to disclose a technical solution for an image sensor circuit and its corresponding storage circuit, so as to reduce circuit cost (e.g., save the cost of a bias current source and a gate selection transistor) and provide a high dynamic range for pixel charge.

[0025] For reference Figure 1 and Figure 2 . Figure 1 This is a schematic diagram of an image sensor circuit 100 according to an embodiment of this application. Figure 2 According to an embodiment of this application, it includes multiple Figure 1The image sensor circuit 100 shown is a schematic diagram of the image sensing device 200. The image sensor circuit 100 includes a sensor circuit 105, a storage circuit 110, and a readout circuit 115. For example, the image sensor circuit 100 is a pixel sensing circuit and is used as an image sensing pixel to sense and generate a pixel image signal and a pixel reset charge signal, thereby obtaining a sensed pixel value. The image sensing device 200 includes a controller 205 and an image sensor device 210. The image sensor device 210 includes multiple image sensor circuits 100 arranged in N rows and M columns (but not limited to this), and the controller 205 is used to control the image sensor circuits 100 to generate multiple pixel images to form an image.

[0026] exist Figure 1 In the sensor circuit 105, a photodiode PD, a first floating diffusion node FD, a transfer gate transistor TG, a reset transistor RST, and a specific transistor QN are included. A storage circuit 110 is coupled between the sensor circuit 105 and the readout circuit 115, and is disposed between the two. The storage circuit 110 includes a transfer gate switching transistor SW. TG The circuit includes a second floating diffusion node FDv, a signal storage circuit 1101S, and a reset storage circuit 1101R. The readout circuit 115 includes a first readout transistor Q1 (used as a source follower transistor) and a second readout transistor Q2.

[0027] A photodiode (PD) is a photosensitive circuit component that can generate multiple electron-hole pairs, thereby producing a charge signal proportional to the intensity of the light it receives (or senses).

[0028] A transfer gate transistor TG is coupled between a photodiode PD and a first floating diffusion node FD. It can be controlled by a transfer gate control signal S_TG (e.g., a voltage signal), which can be generated by controller 205. The transfer gate transistor TG is used to transfer or transmit the charge signal from the photodiode PD to the first floating diffusion node FD when it is turned on by the transfer gate control signal S_TG. In this way, the transferred charge signal is collected in the first floating diffusion node FD, then buffered by storage circuit 110, and finally read out by readout circuit 115. After the charge signal transfer is complete, the transfer gate transistor TG can be turned off, and the first floating diffusion node FD is reset to prepare for the next charge transfer cycle.

[0029] The reset transistor RST is coupled between the supply voltage level VDD and the first floating diffusion node FD. The reset transistor RST can be controlled by a reset control signal S_RST issued by the controller 205 and is used to perform an initialization operation by resetting the photodiode PD to a known state before capturing new photocharge data, such as discharging the photodiode PD to a reset voltage.

[0030] A control node of a specific transistor QN is coupled to a first floating diffusion node FD, and a first node (e.g., its source) of the specific transistor QN is coupled to a transmission gate switching transistor SW in the storage circuit 110. TG A second node (e.g., its drain) of a specific transistor QN is coupled to a reference level. This reference level is equivalent to a variable power supply voltage, the level of which varies between a low level VL and a high level VH and can be controlled by controller 205. For example (but not limited to), the low level VL is a ground level, and the high level VH is a supply voltage level VDD. In one embodiment (but not limited to), the first node of the specific transistor QN is directly coupled to the transmission gate switching transistor SW. TG However, this is not a limitation of this application. Furthermore, it should be noted that in this embodiment, the specific transistor QN simultaneously possesses the operation and function of a source follower transistor and the operation and function of charge discharge.

[0031] In terms of operation, before the voltage of the first floating diffusion node FD is transferred to the second floating diffusion node FDv, the reference level switches to a low level VL, causing the voltage of the second floating diffusion node FDv to drop to a lower level due to the low level VL. Then, when the voltage of the first floating diffusion node FD is transferred to the second floating diffusion node FDv, the reference level switches back to a high level VH, so that the voltage of the second floating diffusion node FDv can follow and approximately equal to the voltage of the first floating diffusion node FD.

[0032] Transmission gate switching transistor SW TG It is controlled by a control signal S_SWTG from controller 205, which controls the transmission gate switching transistor SW. TG One control node is coupled to the control signal S_SWTG, transmitting the gate switching transistor SW. TG A first node is coupled to a first floating diffuse node FD (or a reference level varying between VH / VL) via a specific transistor QN, and a transmission gate switching transistor SW. TG A second node is coupled to a second floating diffusion node FDv. The second floating diffusion node FDv is a node read out by the readout circuit 115. The reset storage circuit 1101R is coupled between the second floating diffusion node FDv and ground, and includes a reset switching transistor SW.RST (Controlled by a control signal S_SWRST issued by controller 205) and a reset storage capacitor C RST Reset switch transistor SW RST With reset storage capacitor C RST The two are connected in series. The signal storage circuit 1101S is coupled between the second floating diffusion node FDv and ground level, and includes a signal switching transistor SW. SIG (Controlled by a control signal S_SWSIG issued by controller 205) and a signal storage capacitor C SIG Signal switching transistor SW SIG With signal storage capacitor C SIG Both are connected in series.

[0033] A control node of transistor Q1 is coupled to the second floating diffusion node FDv, a first node of transistor Q1 is coupled to the supply voltage level VDD, and a second node of transistor Q1 is coupled to transistor Q2. A control node of transistor Q2 is coupled to a control signal RS (i.e., a row select signal) issued by controller 205, a first node of transistor Q2 is coupled to transistor Q1, and a second node of transistor Q2 is used to output one or more read charge signals.

[0034] Figure 3 According to an embodiment of this application Figure 1 The diagram shows waveforms of the corresponding control signals, charge dumping operations (e.g., global dumping), and readout operations (e.g., line readout) of the image sensor circuit 100. Figure 3 As shown, initially during the reset period of the photodiode PD from time t0 to t1, when the control signal S_RST is high during t0 to t0”' and turns on the reset transistor RST, the transmission gate transistor TG is turned on by a high level defined by a rising edge of the control signal S_TG at t0’ and a subsequent falling edge at t0”, and then turned off to reset the state of the photodiode PD before the exposure operation. In this case, the drain level (i.e., the reference level) of the specific transistor QN is at a high level VH, such as a supply voltage level VDD, while other control signals S_SWTG, S_SWRST, S_SWSIG, and RS are all low, such as a ground level.

[0035] During the exposure period from time t1 to t2, the control signals S_TG and S_RST are both kept at a low level, while the transmission gate transistor TG and the reset transistor RST are both in the off state, so that the photodiode PD can receive and accumulate multiple electron-hole pairs that are proportional to the light intensity.

[0036] During the reset of the floating diffusion node FD (or FDv) from time t2 to t3, when a rising edge in the control signal S_RST turns on the reset transistor RST at t2', the reference level of the drain of the specific transistor QN will switch from high level VH to low level VL. At the same time, all control signals S_SWTG, S_SWRST, and S_SWSIG will generate rising edges to turn on the transmission gate switching transistor SW. TG Reset switch transistor SW RST With signal switching transistor SW SIG This allows the states (e.g., residual charge) of the floating diffusion nodes FD and FDv to be reset, for example, by resetting the voltage of the second floating diffusion node FDv. In this case, the voltage of the second floating diffusion node FDv can be reset via the turned-on transfer gate switching transistor SW. TG The specific transistor QN is discharged to a low level VL. The reset transistor RST is turned off at t2", and then the signal switching transistor SW is switched on. SIG It is turned off at t2”'. The reset switch transistor SW RST It remains in the on state in preparation for entering the subsequent reset charge signal's dump period.

[0037] During the resetting charge signal dumping period (between times t3 and t4), the transmission gate transistor TG is turned off because the control signal S_TG is low, and the reset transistor RST is also turned off because the control signal S_RST is low. The reference level of the drain of this particular transistor QN switches from low level VL to high level VH at time t3, and then switches back to low level VL at t4. Meanwhile, the signal switching transistor SW... SIG It will be turned off because the control signal S_SWSIG is low. In this case, the transmission gate switching transistor SW... TG Before t3', it is in the on state, and at t3', it switches from the on state to the off state due to a falling edge of the control signal S_SWTG, and the reset switch transistor SW... RST Before t3", it was in the on state, and at t3", it switched from the on state to the off state due to the falling edge of S_SWRST. Therefore, when the reference level switches from low level VL to high level VH at t3, a reset charge signal buffered in the first floating diffusion node FD causes the voltage of the second floating diffusion node FDv to increase. Thus, when the reference level switches from low level VL to high level VH, the voltage of the second floating diffusion node FDv increases to store the reset charge signal buffered in the first floating diffusion node FD into the reset storage capacitor C.RST The reset charge signal can be transmitted from the first floating diffusion node FD to the second floating diffusion node FDv, and is dumped and stored in the reset storage capacitor C. RST middle.

[0038] During the transfer gate dump period from time t4 to t5, the reference level of a specific transistor QN switches from high level VH to low level VL at time t4, and then switches back to high level VH at t5. Since the control signal S_RST is low, the reset transistor RST is in the off state, and since the control signal S_SWRST is low, the reset switch transistor SW... RST It is also in the off state. In this case, the rising edge and subsequent falling edge of the control signal S_TG will cause the transfer gate transistor TG to turn on at t4' and turn off at t4" . Therefore, during the period from t4' to t4" , the charge signal stored in the photodiode PD will be transferred to the first floating diffusion node FD through the transfer gate transistor TG. Due to the transfer gate switching transistor SW TG With signal switching transistor SW SIG At time t4”, the second floating diffusion node FDv will be turned on simultaneously. The time of t4” is later than t4’ and t4. Therefore, during the period from t4 to t4”, the voltage of the second floating diffusion node FDv can be discharged again (or reset again).

[0039] Next, during the charge signal dump period from time t5 to t6, the reference level on the drain of a specific transistor QN immediately switches from low level VL to high level VH at time t5. During the period from time t5 to t5', the transmission gate switching transistor SW... TG The control signal S_SWTG is high and in the on state, and during time t5 to t5', this signal switches the transistor SW. SIG The control signal S_SWSIG is in the on state because it is high. At time t4, the reference level switches from high level VH to low level VL, resetting the voltage of the second floating diffusion node FDv. Then, at t5, when the reference level changes from low level VL to high level VH, the voltage of the second floating diffusion node FDv increases, thus storing a signal charge buffered in the first floating diffusion node FDv into the signal storage capacitor C. SIG In this way, the charge signal buffered in the first floating diffusion node FD can be transferred and dumped to the second floating diffusion node FDv (whose voltage follows the voltage of the first floating diffusion node FD), and then stored in the signal storage capacitor C. SIGFinally, at time t7', a rising edge appears on the control signal S_RST, turning on the reset transistor RST, at which point the entire global dump operation is completed.

[0040] During the row readout operation from time t8 to t13, the row selection transistor Q2, controlled by the control signal RS, is in the on state, the transfer gate transistor TG is in the off state because the control signal S_TG is low, the reset transistor RST is in the on state because the control signal S_RST is high, and the reference level of the drain of the specific transistor QN is held high and does not change. In this case, during the reset period of the second floating diffusion node FDv from time t8 to t9, the transfer gate switching transistor SW... TG During the period from t8' to t8", the transistor SW will be turned on due to the high level of the control signal S_SWTG, which switches the transistor SW. SIG With reset switch transistor SW RST It is then turned off, so that the level of the second floating diffusion node FDv can be reset by the turned-on reset transistor RST and the specific transistor QN.

[0041] Next, during the reset charge signal readout period from time t9 to t10, the reset switching transistor SW is reset. RST It will be turned on when the control signal S_SWRST is high, and the transmission gate switching transistor SW will be activated. TG and signal switching transistor SW SIG Then it is turned off, causing the buffer to reset the storage capacitor C. RST The reset charge signal can be transmitted through the turned-on reset switch transistor SW. RST Transistor Q1, used as a source follower, and transistor Q2, which is turned on, are transmitted and read out.

[0042] Then, similarly, during the reset period of the second floating diffusion node's FDv from time t10 to t11, the transmission gate switching transistor SW... TG During the period from time t10' to t10", the control signal S_SWTG will be turned on due to its high level, and the signal switching transistor SW will be activated. SIG With reset switch transistor SW RSTThen it is turned off, so that the level of the second floating diffusion node FDv is reset again through the already turned-on reset transistor RST and the specific transistor QN.

[0043] Similarly, during the charge signal readout period from time t11 to t12, the signal switching transistor SW... SIG It will be turned on due to the high level of the control signal S_SWSIG, and the transmission gate switching transistor SW TG and reset switch transistor SW SIG Then it is turned off, causing the buffer in the signal storage capacitor C to be closed. SIG The charge signal in the transistor SW can be switched by the already turned-on signal switch. SIG Transistor Q1, used as a source follower, and transistor Q2, which is already turned on, are transmitted and read out.

[0044] Figure 4 This is another different embodiment according to this application. Figure 1 The diagram shows waveforms of the corresponding control signals, charge dumping operations (e.g., global dumping), and readout operations (e.g., row readout) of the image sensor circuit 100. Figure 4 As shown, with Figure 3 The difference lies in the fact that, during the transfer gatedump period from time t4 to t5, the reference level of the drain of the specific transistor QN switches from high level VH to low level VL only at time t4” (later than t4). Furthermore, in Figure 4 During the reset period of the second floating diffusion node (FDv) from time t8 to t9, the reference level of the drain of a specific transistor QN switches from high level VH to level VL at t8', and then switches back to high level VH at t8''. When the transmission gate switching transistor SW... TG Turning on and resetting the switching transistor SW RST When turned off, the reference level switches from high level VH to low level VL at time t8' to reset the voltage of the second floating diffusion node FDv. Then, when the transmission gate switching transistor SW... TG The switching transistor SW is turned off and reset. RST When the circuit is turned on, the reference level switches from low level VL to high level VH at time t8”', and remains high at time t9 so that the buffer resets the storage capacitor C. RST A reset charge signal can be read by the readout circuit 115 of the image sensor circuit 100.

[0045] Similarly, during the reset of the second floating diffusion node FDv from time t10 to t11, the reference level on the drain of a specific transistor QN will switch from high level VH to low level VL at t10', and then switch back to high level VH at t10"'. When the transmission gate switching transistor SW... TG The conducting and signal switching transistor SW SIG When turned off, the reference level switches from high level VH to low level VL at t10' to reset the voltage on the second floating diffusion node FDv. Then, when the transmission gate switching transistor SW... TG The signal switching transistor SW is turned off at t10". SIG When t11 is turned on, the reference level will switch from low to high VH at t10”' and remain high at t11, so that the signal storage capacitor C is buffered. SIG The signal charge signal in the image sensor circuit 100 can be read out by the readout circuit 115.

[0046] This switching of the reference level can be used to reset or discharge the voltage of the second floating diffusion node FDv before reading out the charge signal (or resetting the charge signal). Furthermore, this also avoids current leakage in the first floating diffusion node FD caused by excessively high voltage. Thus, by appropriately switching the reference level between high level VH and low level VL, current leakage can be effectively avoided or mitigated.

[0047] Figure 5 This is a schematic diagram of an image sensor circuit 500 according to another embodiment of this application. The image sensor circuit 500 includes a sensor circuit 505, a storage circuit 510, and a readout circuit 515. The sensor circuit 505 includes a photodiode PD, a first floating diffusion node FD, a transmission gate transistor TG, a reset transistor RST, and a storage capacitor C. LCG and C HCG A switching transistor SG (controlled by the control signal S_SG) and a specific transistor QN. Storage capacitor C. HCG This is used to represent an inherent capacitance value in the circuit structure of the sensor circuit 505, while the storage capacitance C LCG This refers to a specific charge capacitor configured between ground level and an intermediate node, which is located between the reset transistor RST and the switching transistor SG. The switching transistor SG is located and coupled between the reset transistor RST and the first floating diffusion node FD. Storage capacitor C LCG The capacitance value is the inherent capacitance C. HCGSeveral times the capacitance value, and the storage capacitance C LCG It is used as a large capacitor to receive and store the charge overflowing from the photodiode PD to the first floating diffusion node FD when the photodiode PD is exposed to bright conditions and is fully loaded, so that more charge can be stored to provide a higher dynamic range for processing signal charge.

[0048] Storage circuit 510 includes a transmission gate switching transistor SW TG The image sensor circuit 500 includes a second floating diffusion node FDv, two signal storage circuits 5101L and 5101H, and a reset storage circuit 5101R. The readout circuit 515 includes a first readout transistor Q1 and a second readout transistor Q2. The operation and function of the image sensor circuit 500 are similar to those of the image sensor circuit 100. The difference is that the image sensor circuit 500 uses two signal storage circuits 5101L and 5101H to provide a high dynamic range for storing different charges (i.e., different charge signals). The capacitor C included in the storage circuit 5101L... SIGL The capacitance value is greater than the capacitance C included in the storage circuit 5101H. SIGH The capacitance value.

[0049] Figure 6 According to an implementation of this application, for example Figure 5 The diagram shows the corresponding control signals of the image sensor circuit 500, as well as the waveforms of tilting operations (e.g., global tilting) and reading operations (e.g., line readout operations). The tilting operations (e.g., global tilting) and reading operations (e.g., line readout operations) of the image sensor circuit 500 are similar to... Figure 3 The tilting and reading operations of the image sensor circuit 100 shown are described below. The relevant differences are described in the following sections.

[0050] During the photodiode's PD reset period from time t20 to t21, when the reset transistor RST is turned on by the high level of the signal S_RST during the period from time t20 to t20", the switching transistor SG is also turned on by the high level of the signal S_SG, so that the photodiode PD can be reset.

[0051] During the reset of the floating diffusion node FD (or FDv) from time t22 to t23, when the control signals S_RST and S_SG have rising edges at time t22' to turn on the reset transistor RST and the gate switching transistor SG, the reference level of the drain of the specific transistor QN will switch from high level VH to low level VL. At the same time, all control signals S_SWTG, S_SWRST, S_SIGH, and S_SIGL will also have rising edges to turn on the transmission gate switching transistor SW. TG Reset switch transistor SW RST and switching transistor SW SIGH and SW SIGL This allows the states (i.e., remaining charge) of the floating diffusion nodes FD and FDv to be reset. In this case, the voltage of the second floating diffusion node FDv can be controlled by the already turned-on transfer gate switching transistor SW. TG The specific transistor QN is discharged to a low level VL. The reset transistor RST and the switching transistor SG are turned off at time t22", followed by the switching transistor SW. SIGH and SW SIGL It will be turned off at t22”'.

[0052] During the reset charge signal dump period from time t23 to t24, the reference level of the drain of a specific transistor QN switches from low level VL to high level VH at t23, switching transistor SW. SIGH and SW SIGL The transmission gate switching transistor SW will be turned off by signals S_SIGH and S_SIGL with a low level. TG Before t23', the bit is in the on state, and at t23', it switches from the on state to the off state due to the falling edge of the control signal S_SWTG, and resets the switching transistor SW. RST The device is in the ON state before t23", and at t23", it switches from the ON state to the OFF state due to the falling edge of the control signal S_SWRST. In this way, the reset charge signal can be transmitted from the first floating diffusion node FD to the second floating diffusion node FDv, and then dumped and buffered in the reset storage capacitor C. RST middle.

[0053] During the transfer gate dump period from time t24 to t25, the transfer gate transistor TG is turned on at t24' due to the rising edge and subsequent falling edge of the control signal S_TG, and then turned off at t24”. The reference level of the drain of the specific transistor QN is at a high level VH before t24” and then switches to a low level VL at t24”. The transfer gate switching transistor SW TG At time t24", it will be turned on by the rising edge of the control signal S_SWTG, and the signal switching transistor SW will also be activated. SIGH At time t24", it will be turned on by the rising edge of the control signal S_SIGH. At this time, the signal switching transistor SW SIGL It is off. During the first charge signal's dump period from time t25 to t26, the reference level of the drain of the specific transistor QN will remain at a high level VH, and the transmission gate switching transistor SW will be off. TG At t25', it will be turned off by the falling edge of the control signal S_SWTG, and then the signal switching transistor SW will be activated. SIGH At t25", the control signal S_SIGH will be turned off on the falling edge. In this way, during the period from t24" to t25', a first charge signal (i.e., a first part of the signal charge) can be transferred from the photodiode PD and dumped to the first floating diffusion node FD, and then during the period from t24" to t25', it will be transferred and dumped to the second floating diffusion node FDv.

[0054] During the period from t26 to t27, the switching gate transistor SG is turned on by the rising edge of the control signal S_SG at t26', and the control signal S_SG remains at a high level VH. The reference level of the drain of the specific transistor QN is at a high level VH before t26", switches to a low level VL at t26", and then switches back to the high level VH at t27. The transmission gate switching transistor SW TG At time t26", it is turned on by the rising edge of the control signal S_SWTG, and the signal switching transistor SW SIGL It is turned on by the rising edge of the control signal S_SIGH at t24". At this time, the signal switching transistor SW SIGH It is turned off. During the second charge signal's dump period from time t27 to t28, the reference level of the drain of the specific transistor QN will remain at a high level VH, and the transmission gate switching transistor SW will be switched off. TG It is turned off by the falling edge of the control signal S_SWTG at t27', and then the signal switching transistor SW SIGLIt is turned off by the falling edge of the control signal S_SIGH at t27". Thus, during the period from t26" to t27', a second charge signal (i.e., a second portion of the signal charge) can be released from capacitor C. LCG The data is transferred and dumped to the first floating diffusion node FD, and then transferred and dumped to the second floating diffusion node FDv during the period from time t26” to t27’. Finally, at time t28’, the reset transistor RST is turned on by the rising edge of the control signal S_RST, and the global dumping operation is completed.

[0055] During the row read operation from time t29 to t35, the row selection transistor Q2, controlled by the control signal RS, will be in the ON state. The transmission gate switching transistor TG will be OFF when the control signal S_TG is low. The reset transistor RST and the gate switching transistor SG will be ON when the control signals S_RST and S_SG are high. The reference level of the drain of the specific transistor QN will remain at a low level VL and will not change. Similarly, the transmission gate switching transistor SW... TG It is on during the period from time t29' to t29" while the signal switching transistor SW is on. SIGH and SW SIGL and reset switch transistor SW RST It is off, allowing the level of the second floating diffusion node FDv to be reset or discharged. Next, the reset switching transistor SW... RST It is on during the period from time t30 to t31, while the transmission gate switching transistor SW is on. TG and signal switching transistor SW SIGH and SW SIGL It is off, so the buffer resets the storage capacitor C. RST The reset charge signal in the circuit can be transmitted through the activated reset switch transistor SW. RST The conducting transistors Q1 (used as a source follower) and Q2 are transferred and read out. Next, the transfer gate switching transistor SW... TG It will turn on again during the period from time t31' to t31" and the signal switching transistor SW SIGH SW SIGL and reset switch transistor SW RST This will be turned off, allowing the level of the second floating diffusion node FDv to be reset or discharged again. Next, the signal switching transistor SW... SIGH It is turned on during the period from time t32 to t33, while the transmission gate switching transistor SW is turned on. TG Signal switching transistor SW SIGL and reset switch transistor SW RSTThen it is turned off, allowing the buffered first charge signal to be transferred and read out. Next, the transmission gate switching transistor SW... TG It turns on again during the period from time t33' to t33" while the signal switching transistor SW SIGH SW SIGL and reset switch transistor SW RST This will be turned off, allowing the level of the second floating diffusion node FDv to be reset or discharged again. Next, the signal switching transistor SW... SIGL It will conduct during the period from time t34 to t35, while the transmission gate switching transistor SW TG Signal switching transistor SW SIGH and reset switch transistor SW RST This will then be turned off, allowing the buffered second charge signal to be transferred and read. Finally, at t35, the row read operation is complete.

[0056] In other embodiments, the switching transistor SG can be located at different positions in the sensor circuit, so the operation of the switching transistor SG and the reset transistor RST can be performed separately. Figure 7 This is a schematic diagram of an image sensor circuit 700 according to another embodiment of this application. The image sensor circuit 700 includes a sensor circuit 705, a storage circuit 510, and a readout circuit 515. Figure 7 The operation and function of the storage circuit 510 and the readout circuit 515 are the same as those of the storage circuit 510 and the readout circuit 515. Figure 5 The storage circuit 510 and the readout circuit 515 are included. Figure 5 and Figure 7 The difference between the embodiments is that, Figure 7 Storage capacitor C LCG This is a configured capacitor, which is positioned between ground and the first floating diffusion node FD via a specific switching gate transistor SG. The specific switching gate transistor SG is positioned between the first floating diffusion node FD and the storage capacitor C. LCG Between. In addition, the storage capacitor C LCG The capacitance value is the inherent capacitance C. HCG Several times the capacitance value, and the storage capacitance C LCG It is used as a large capacitor to receive and store the charge overflowing from the photodiode PD when it is exposed to bright conditions, allowing for the storage of more charge and thus improving the dynamic range for signal charge. In doing so, the image sensor circuit 700 is also able to provide a high dynamic range for storing different charges (i.e., different charge signals).

[0057] Figure 8 This is another embodiment according to this application. Figure 7The diagram illustrates the waveforms of the control signals, tilting operations (e.g., global tilting), and reading operations (e.g., line reading operations) of the image sensor circuit 700. The tilting operations (e.g., global tilting) and reading operations (e.g., line reading operations) of the image sensor circuit 700 are similar to... Figure 3 The tilting and reading operations of the image sensor circuit 100 shown are illustrated below. Detailed differences are described below.

[0058] During the photodiode's reset period (t20-t21) and the light exposure period (t21-t22), the switching transistor SG is turned on by the high level of the control signal S_SG and turned off by the falling edge of the control signal S_SG at t22, allowing the photodiode PD to be reset and subsequently storing the capacitor C. LCG It is used as a large capacitor to receive and store the overflowing charge when the photodiode (PD) is exposed to bright conditions, thus storing more charge and providing a high dynamic range for the signal charge.

[0059] Furthermore, in cases such as Figure 8 During the row read operation shown, the reference level of the drain of a specific transistor QN can also be rapidly switched from high level VH to low level VL at a point in time during the floating diffusion node reset (e.g., t29', t31', and t33'), and then switched back to high level VH at the next point in time (e.g., t29'', t31'', and t33''). Similarly, this voltage switching of the reference level is used to reset or discharge the voltage of the second floating diffusion node FDv before the charge signal (or reset charge signal) is read out. Furthermore, this avoids the problem of current leakage in the first floating diffusion node FD due to excessive voltage at the first floating diffusion node FD. This avoids or mitigates the current leakage problem.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A storage circuit of an image sensor circuit, the storage circuit being provided between a sensor circuit of the image sensor circuit and a readout circuit of the image sensor circuit, characterized in that, The storage circuit includes: A transmission gate switching transistor, wherein a first node of the transmission gate switching transistor is coupled to a first floating diffusion node, and a second node of the transmission gate switching transistor is coupled to a second floating diffusion node; The second floating diffusion node is used to be read by the readout circuit; A signal storage circuit is coupled between the second floating diffusion node and the ground level; and A reset storage circuit is coupled between the second floating diffusion node and the ground level; The reference level located at the first floating diffusion node varies between low and high levels; when the reference level changes from high to low, the voltage of the second floating diffusion node is reset; then, when the reference level changes from low to high, ... The voltage of the second floating diffusion node increases in response to the charge signal of the first floating diffusion node.

2. The storage circuit as described in claim 1, characterized in that, The low level is the ground level, while the high level is the supply voltage level.

3. The storage circuit as described in claim 1, characterized in that, The reset storage circuit includes a reset switch transistor and a reset storage capacitor, which are connected in series. When the transmission gate switch transistor and the reset switch transistor are turned on and the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset to reset the reset storage capacitor. Then, when the reference level changes from the low level to the high level, the voltage of the second floating diffusion node increases to store the reset charge signal buffered in the first floating diffusion node into the reset storage capacitor.

4. The storage circuit as described in claim 1, characterized in that, The signal storage circuit includes a signal switching transistor and a signal storage capacitor, which are connected in series. When the transmission gate switching transistor and the signal switching transistor are turned on and the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset to reset the signal storage capacitor. Then, when the reference level changes from the low level to the high level, the voltage of the second floating diffusion node increases to store the signal charge signal buffered in the first floating diffusion node into the signal storage capacitor.

5. The storage circuit as described in claim 1, characterized in that, The first node of the transmission gate switching transistor is directly coupled to the first node of a specific transistor in the sensor circuit, and the second node of the specific transistor is coupled to the reference level, which varies between the high level and the low level, and the control node of the specific transistor is coupled to the first floating diffusion node.

6. The storage circuit as claimed in claim 1, characterized in that, The reset storage circuit includes a reset switch transistor and a reset storage capacitor, which are connected in series. When the transmission gate switch transistor is turned on and the reset switch transistor is turned off, the reference level changes from the high level to the low level to reset the voltage of the second floating diffusion node. Then, when the transmission gate switch transistor is turned off and the reset switch transistor is turned on, the reference level changes from the low level to the high level so that the reset charge signal buffered in the reset storage capacitor is read out by the readout circuit of the image sensor circuit.

7. The storage circuit as claimed in claim 1, characterized in that, The signal storage circuit includes a signal switching transistor and a signal storage capacitor, which are connected in series. When the transmission gate switching transistor is turned on and the signal switching transistor is turned off, the reference level changes from the high level to the low level to reset the voltage of the second floating diffusion node. Then, when the transmission gate switching transistor is turned off and the signal switching transistor is turned on, the reference level changes from the low level to the high level so that the signal charge signal buffered in the signal storage capacitor is read out by the readout circuit of the image sensor circuit.

8. The storage circuit as claimed in claim 1, characterized in that, The storage circuit also includes: Another storage circuit is connected between the second floating diffusion node and the ground level; The signal storage circuit is used to store a first charge signal using a first storage capacitor, and the other signal storage circuit is used to store a second charge signal using a second storage capacitor, wherein the capacitance value of the second storage capacitor is greater than the capacitance value of the first storage capacitor.

9. An image sensor circuit, characterized in that, include: The storage circuit as described in claim 1; as well as A sensor circuit, coupled to the storage circuit, includes: A photodiode; The first floating diffusion node; A transmission gate transistor is coupled between the photodiode and the first floating diffusion node; a reset transistor is coupled between the first floating diffusion node and the supply voltage level; as well as A specific transistor, wherein a first node of the specific transistor is coupled to the first node of the transmission gate switching transistor of the storage circuit, a second node of the specific transistor is coupled to the reference level, and a control node of the specific transistor is coupled to the first floating diffusion node.

10. The image sensor circuit as described in claim 9, characterized in that, The sensor circuit also includes: A switching transistor, wherein a first node of the switching transistor is coupled to the first floating diffuse node, a second node of the switching transistor is coupled to the reset transistor, and the reset transistor is coupled between the supply voltage level and the switching transistor; and A specific charge capacitor is coupled to the ground level and the second node of the switching transistor; Specifically, when the reset transistor is turned off and the switching transistor is turned on, the first floating... A portion of the signal charge at the dynamic diffusion node is buffered into that specific charge capacitor.

11. The image sensor circuit as described in claim 9, characterized in that, The sensor circuit also includes: A switching transistor, wherein a first node of the switching transistor is coupled to a first floating diffusion node, and a second node of the switching transistor is coupled to a specific charge capacitor; and The specific charge capacitor is coupled between the ground level and the second node of the switching transistor; When the switching transistor is turned on, a portion of the signal charge signal on the first floating diffusion node is buffered into the specific charge capacitor.

12. A method for an image sensor circuit, wherein a storage circuit of the image sensor circuit is disposed between a sensor circuit and a readout circuit of the image sensor circuit, characterized in that, The method includes: A transmission gate switching transistor is provided, wherein a first node of the transmission gate switching transistor is coupled to a first floating diffusion node, and a second node of the transmission gate switching transistor is coupled to a second floating diffusion node; The second floating diffusion node is provided for being read by the readout circuit; A signal storage circuit is provided, which is coupled between the second floating diffusion node and the ground level; A reset storage circuit is provided, which is coupled between the second floating diffusion node and the ground level; The reference level located on the side of the first floating diffusion node is controlled to vary between low and high levels; When the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset; and When the reference level changes from the low level to the high level, the voltage of the second floating diffusion node is increased in response to the charge signal of the first floating diffusion node.

13. The method as described in claim 12, characterized in that, The low level is the ground level, and the high level is the supply voltage level.

14. The method as described in claim 12, characterized in that, The reset storage circuit includes a reset switching transistor and a reset storage capacitor, which are connected in series. The method further includes: When the transmission gate switching transistor and the reset switching transistor are turned on and the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset to reset the reset storage capacitor; and When the reference level changes from the low level to the high level, the voltage of the second floating diffusion node is increased to store the reset charge signal buffered in the first floating diffusion node into the reset storage capacitor.

15. The method as described in claim 12, characterized in that, The signal storage circuit includes a signal switching transistor and a signal storage capacitor, which are connected in series, and the method further includes; When the transmission gate switching transistor and the signal switching transistor are turned on and the reference level changes from the high level to the low level, the voltage of the second floating diffusion node is reset to reset the signal storage capacitor. as well as When the reference level changes from the low level to the high level, the voltage of the second floating diffusion node is increased to store the signal charge signal buffered at the first floating diffusion node into the signal storage capacitor.

16. The method as described in claim 12, characterized in that, The reset storage circuit includes a reset switching transistor and a reset storage capacitor, which are connected in series, and the method further includes; When the transmission gate switching transistor is turned on and the reset switching transistor is turned off, the reference level is changed from the high level to the low level to reset the voltage of the second floating diffusion node; as well as When the transmission gate switching transistor is turned off and the reset switching transistor is turned on, the reference level is changed from the low level to the high level so that the reset charge signal buffered in the reset storage capacitor is read out by the readout circuit of the image sensor circuit.

17. The method as described in claim 12, characterized in that, The signal storage circuit includes a signal switching transistor and a signal storage capacitor, which are connected in series. The method further includes: When the transmission gate switching transistor is turned on and the signal switching transistor is turned off, the reference level is changed from the high level to the low level to reset the voltage of the second floating diffusion node; and When the transmission gate switching transistor is turned off and the signal switching transistor is turned on, the reference level is changed from the low level to the high level, so that the signal charge signal buffered in the signal storage capacitor is read out by the readout circuit of the image sensor circuit.

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