A low-latency fast-switching optical switching system and method

Abstract

This invention proposes a low-latency, fast-switching optical switching system and method, belonging to the field of optical communication technology. The invention achieves fast switching by splitting a portion of the input optical signal and connecting it to a main control chip to regulate the switching of the optical switching chip. Specifically, a portion of the light is split from the main optical path and connected to a set of low-speed, high-sensitivity optoelectronic modules, i.e., the Rx terminal of the main control chip. The Rx terminal does not carry high-speed data but is dedicated to listening to and interpreting switching commands from the network interface card (NIC) carried by specific optical signals. After parsing these commands, the main control chip can immediately provide an optical response to the NIC through the same path, achieving rapid signaling interaction without going through the upper-layer switching network, greatly reducing scheduling latency. This invention can effectively adapt to the fast switching of optical switches, thereby enabling the fast-switching hardware unit to adapt to a fast control system.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology, specifically relating to a low-latency, fast-switching optical switching system and method. Background Technology

[0002] Driven by the surge in artificial intelligence and high-performance computing, data centers and computing clusters are placing unprecedentedly stringent demands on the bandwidth and latency of interconnect networks. Optical interconnects and switching technologies, with their inherent advantages of high bandwidth and low loss, are considered key to overcoming the bottlenecks of traditional electrical interconnects. Currently, the topology reconfiguration latency of optical switches based on technologies such as 3D Micro-Electro-Mechanical Systems (MEMS) micromirror arrays, piezoelectricity, and liquid crystals is generally on the order of tens of milliseconds. However, the traffic generated by tasks such as artificial intelligence (AI) training is highly bursty and dynamic, with communication patterns potentially changing within microseconds. This prevents existing optical switches from adaptively adjusting their topology according to real-time traffic demands, forcing them to adopt coarse-grained, task-level static or semi-static reconfiguration strategies. This inevitably leads to network inefficiency and fragmentation of cluster resources. Therefore, reducing the switching latency of optical switches to sub-millisecond or even microsecond levels is a core requirement for achieving high-performance, agile computing networks.

[0003] To achieve microsecond-level switching, on-chip optical switching solutions compatible with Complementary Metal Oxide Semiconductor (CMOS) technology have become the main technical approach, including thermo-optical, electro-optical, phase-change, and MEMS solutions. Although these advanced on-chip optical switching units possess the hardware potential to serve as fast switching configuration units with microsecond-level response, the "sensing-decision-execution" closed-loop performance of the entire system still faces fundamental bottlenecks when integrated into practical optical switching systems.

[0004] Current optical switching systems generally rely on traditional network control planes, such as Software Defined Networking (SDN) controllers, for control commands. These commands require processing and transmission through multiple protocol stacks, resulting in end-to-end topology reconstruction latency on the order of milliseconds. This creates a significant contradiction: fast-switching hardware units are constrained by a slow control system. Therefore, developing an ultra-low-latency control signaling interaction scheme that matches microsecond-level physical switching capabilities, enabling near-physical-layer speed command communication between optical switching equipment and terminal devices (such as smart network interface cards), has become a key challenge and a critical issue that urgently needs to be addressed to unleash the potential of fast-switching hardware and improve the overall agility and efficiency of optical switching systems. Summary of the Invention

[0005] To overcome the problems of high control command latency and complex paths in existing optical switching systems, this invention provides a low-latency, fast-switching optical switching system and method. This invention achieves fast switching by splitting a portion of the input optical signal and connecting it to a Field Programmable Gate Array (FPGA) to control the switching of the optical switching chip. Specifically, a portion of the light is split from the main optical path and connected to a set of low-speed, high-sensitivity optoelectronic modules, i.e., the Rx terminal of the FPGA main control chip. The Rx terminal does not carry high-speed data but is dedicated to listening to and interpreting switching commands from the network interface card (NIC) carried by specific optical signals. After parsing these commands, the FPGA main control chip can immediately provide an optical response to the NIC through the same path, achieving rapid signaling interaction without traversing the upper-layer switching network, greatly reducing scheduling latency. This invention can effectively adapt to the fast switching of optical switches, thereby enabling the fast-switching hardware unit to adapt to a fast control system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a low-latency, fast-switching optical switching system, comprising: N optical modules, two sets of input fiber arrays, two sets of output fiber arrays, two optical beam splitters, two optical switching chips, a main control chip, and two sets of GPIO control arrays, wherein N ≥ 2, and the input fiber arrays, output fiber arrays, optical beam splitters, optical switching chips, and GPIO control arrays correspond one-to-one; the N optical modules transmit input optical signals to the two sets of input fiber arrays, and the N ports of each set of input fiber arrays are respectively connected to the N optical modules; each set of input fiber arrays is connected to a corresponding optical beam splitter, and the optical beam splitter splits the input optical signal... The optical fiber array splits the optical signal, which is then transmitted through the input fiber array and connected to the Rx terminal of the main control chip. The remaining optical signal is input to the corresponding optical switching chip. The Rx terminal is used to capture the specific data packet headers transmitted by the input fiber array. The main control chip parses the headers and generates control commands. The main control chip uses the GPIO control array to control the corresponding optical switching chip, enabling the switching unit within the optical switching chip to switch links. The switched link transmits the optical signal input to the optical switching chip to the optical module through the corresponding output fiber array. The N ports of each output fiber array are connected to N optical modules respectively.

[0008] Optionally, it also includes 2N switching nodes, with each optical module connected to two sets of switching nodes.

[0009] Optionally, it also includes a power supply module for supplying power to the main control chip, optical switching chip and GPIO control array.

[0010] Optionally, it also includes a thermal management module for real-time monitoring of the temperature of the main control chip, optical switching chip, and GPIO control array.

[0011] Optionally, the optical switching chip consists of an N×N matrix of optical switching nodes with N inputs and N outputs. Each node includes an on-chip optical switch, and the on / off state of the optical switch is controlled by a GPIO control array.

[0012] Optionally, the on-chip optical switch is fabricated based on thin-film lithium niobate, thin-film lithium tantalate, silicon-on-insulator, silicon nitride, or silicon oxynitride platforms, and arranged using a non-blocking topology architecture such as PILOSS, Benes, CrossBar, or Torus.

[0013] Optionally, the optical signal split by the optical beam splitter is less than 10%.

[0014] In a second aspect, the present invention provides a low-latency, fast-switching optical switching method, implemented based on the optical switching system described in the first aspect, comprising the following steps: The switching node i to be communicated continuously sends switching and verification signals to the main control chip. The switching and verification signals are transmitted to the main control chip through the optical beam splitter and the input fiber array and are captured by the Rx end. At the same time, the switching node i waits for the response from the main control chip; where i represents the switching node number, i≤N; If the main control chip does not receive a switching and verification signal from the other switching node j to be communicated with, it will not perform a link switch and will continue to wait for a switching and verification signal from the switching node j; where j represents the switching node number, j≤N, i≠j; If the main control chip receives a switching and verification signal from switching node j, it generates a control command and controls the corresponding optical switching chip to perform link switching through the GPIO control array; After the link switch is completed, the verification signals of switching node i and switching node j are transmitted to each other through the input fiber array, optical switching chip and output fiber array. After the two switching nodes complete the verification, they continue to transmit data through the input fiber array, optical switching chip and output fiber array.

[0015] The beneficial effects of this invention are as follows: This invention achieves a fundamental breakthrough by creatively establishing an independent physical layer signal channel parallel to the high-speed data channel. It liberates the switching control commands from the complex network protocol stack, reducing processing latency from milliseconds (software control) to microseconds (hardware switching). Based on this channel, the optical switching chip and the smart network card can directly interact end-to-end at the optical physical layer, solving the large latency caused by multiple network interactions in traditional architectures. This design reduces end-to-end connection establishment time by orders of magnitude, which is the core advantage of this invention in achieving low-latency switching. This invention overcomes the signaling processing latency bottleneck caused by traditional control protocol stacks, achieving microsecond-level direct signaling interaction between the optical switch and terminal equipment, and based on this, realizing ultra-high-speed, high-reliability optical path switching. Attached Figure Description

[0016] Figure 1 This is an architectural framework diagram of the low-latency, fast-switching optical switching system of the present invention.

[0017] Figure 2 This is the working logic diagram of the low-latency, fast-switching optical switching system of the present invention. Detailed Implementation

[0018] The invention will now be described in further detail with reference to the accompanying drawings.

[0019] Example 1 This embodiment proposes a low-latency, fast-switching optical switching system. This architecture uses an optical beamsplitter at the data input end to couple a portion of the light from the data optical channel as an optical channel for signal switching commands. This channel is then connected to an FPGA main control chip used to control the switch and implement link switching, enabling the transmission of switching control commands between the optical switch and the access network interface card (NIC). This method of using the data plane to control optical switching achieves data switching at microsecond-level rates, significantly reducing switching scheduling latency and improving the system's responsiveness to dynamic traffic.

[0020] This microsecond-level fast switching system mainly consists of a power module, a thermal management module, and an optical switching section, all controlled by a single FPGA main control chip. The power module provides stable power to the FPGA main control chip, optical switching chip, and control circuitry. The thermal management module uses the FPGA main control chip to monitor the temperature of each unit in real time, providing active or passive heat dissipation solutions. The power module and thermal management module are primarily used to ensure the stable operation of the entire optical switch, ensuring the system remains in optimal working condition under complex load environments and guaranteeing the long-term reliability of the entire device.

[0021] The optical switching system, as the core of the optical switch, mainly includes optical switching chips, input / output fiber arrays, optical beam splitters, FPGA main control chips, optical modules, and other components. Through the coordinated operation of these components, microsecond-level optical switching is achieved. In this embodiment, the optical switch achieves fast switching through beam splitting control. The optical switching system framework diagram is shown below. Figure 1 As shown, the external interfaces of the entire machine are mainly divided into two parts: Ethernet ports and optical module interfaces. In a GPU cluster with an optical switch architecture, the optical switch serves as the networking core, connecting and transmitting data with the electrical switch through optical modules. This embodiment also retains the traditional control method of optical switches switching via Ethernet ports, and similarly supports millisecond-level low-speed switching on the control plane.

[0022] Figure 1 In this system, the power supply module provides stable power to the FPGA main control chip, optical switching chip, and their control circuits. The thermal management module, controlled by the FPGA main control chip, monitors the temperature of each unit in real time and provides active or passive heat dissipation solutions. The FPGA main control chip is the control core of the optical switch, analyzing the control commands received at the Rx end, issuing control commands to the control circuits of the optical switching chip, and also controlling various parameters such as power supply and temperature within the entire system. The optical beam splitter divides the light in the input fiber array into two parts. The fiber array uses a compact fiber arrangement for data transmission. The optical module is used for the conversion between electrical and optical signals, supporting data transmission in fiber optic communication. The Rx receiver uses a low-speed optical module, mainly used to parse the switching signals of the data plane transmission and interpret the data packet header. The optical switching chip mainly consists of an N×N matrix of optical switching nodes with N inputs and N outputs. Each node is mainly composed of an optical switch on a silicon substrate, and the switching is controlled by external circuitry. On-chip optical switches are primarily fabricated using platforms such as thin-film lithium niobate (LNOI), thin-film lithium tantalate (LTOI), silicon-on-insulator (SOI), silicon nitride (SiN), and silicon oxynitride (SiON). Switching is achieved by controlling changes in the refractive index or mechanical structure of the waveguide through the application of MEMS, phase transitions, thermo-optic effects, and electro-optic effects. These switches are arranged using non-blocking topologies such as PILOSS, Benes, CrossBar, and Torus to ensure that any idle input port can establish a path to any idle output port at any time, without being limited by existing connections within the network. Ethernet ports are used for Ethernet connections. Fiber optic interfaces are used for fiber optic patch cord connections.

[0023] The core of the optical switching system architecture is to overcome the millisecond-level latency required for data switching control on the control plane, reducing the overall latency to the microsecond level. To match the control chain with microsecond-level optical switching devices, controlling data switching on the data plane bypasses the complex multi-layer protocol stack processing and transmission, allowing direct hardware response to switching signals and completion of hardware switching. To achieve fast switching on the data plane, this embodiment connects an optical beam splitter after the input fiber array to split a portion of the light in the data optical channel for controlling link switching within the data optical channel. A very small portion of the light (<10%) split by the beam splitter is transmitted through the fiber array and connected to a receiver (Rx) end connected to the FPGA main control chip. The Rx end uses a low-speed optical module dedicated to listening to and parsing specific data packet headers transmitted from the fiber array. When the Rx end captures a specific switching command, the FPGA main control chip parses the received control signaling in real time and makes a switching decision within microseconds based on a preset fast scheduling algorithm. After making the decision, the FPGA main control chip directly sends the generated control commands to the drive control circuit inside the optical chip through the General Purpose Input / Output (GPIO) control array, controlling the corresponding switching unit to complete the switching state switching within microseconds.

[0024] Unlike electrical switches, which can achieve bidirectional transmission with a single wire, optical switches typically require two unidirectional optical fibers or a circulator to achieve bidirectional transmission. This embodiment provides a new architecture, namely, using a dual-chip design to achieve bidirectional transmission, such as... Figure 1 As shown, taking an 800G optical module as an example, the optical module contains four optical fiber channels: two inputs and two outputs. The input fibers (solid lines) are connected to the input ends of two optical switching chips, and the corresponding output fibers (dashed lines) are connected to the output ends of two optical switching chips. The left optical switching chip transmits to the right, while the right optical switching chip transmits to the left. Bidirectional transmission can be achieved by symmetrically configuring the two optical switching chips. In this embodiment, the optical beam splitter, optical switching chips, and Rx terminal can be integrated or used in a discrete device configuration.

[0025] Example 2 This embodiment proposes a low-latency, fast-handover optical switching method, implemented based on the optical switching system of Embodiment 1. The specific switching logic for data plane control during fast handover is as follows: Figure 2As shown in the diagram, the optical switch is connected to network interface cards (NICs) A through D. Initially, NICs A and B communicate bidirectionally, and NICs C and D communicate bidirectionally. At a certain point, after NIC A completes communication with NIC B, NIC A will communicate with NIC D. At this time, NIC A will continuously send switching commands and verification signals (e.g., "I am A") to the FPGA master control chip while waiting for its response. If NICs C and D have not yet completed communication, the FPGA master control chip will not receive the switching and verification signals (e.g., "I am D") from NIC D, and will not perform link switching but will continue to wait for the switching signal from NIC D. After NICs C and D complete communication, NIC D sends switching commands and verification signals to the FPGA master control chip. At this time, the FPGA master control chip receives switching commands and verification signals from both NICs A and D, and then issues a switching command to control the optical switch to perform link switching. After the link switch is completed, the authentication signal of network interface card A (e.g., "I am A") is transmitted to network interface card D, and at the same time, the authentication signal of network interface card D (e.g., "I am D") is also transmitted to network interface card A. At this point, the two network interfaces complete the authentication and begin data transmission. In this embodiment, the network interfaces can also be replaced by other types of switching nodes.

[0026] Based on the switching logic described above, in an N×N optical switching system, the system has N channels as input ports and N channels as output ports. Therefore, if the external optical module is 800G, then N external 800G optical modules are needed as connection ports. Furthermore, to fully utilize all connection port configurations, 2N network interface cards (NICs) are required for communication.

[0027] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A low-latency fast-switching optical switching system, characterized by, include: The system comprises N optical modules, two sets of input fiber optic arrays, two sets of output fiber optic arrays, two optical beam splitters, two optical switching chips, a main control chip, and two sets of GPIO control arrays, where N ≥ 2. The input fiber optic arrays, output fiber optic arrays, optical beam splitters, optical switching chips, and GPIO control arrays are in one-to-one correspondence. The N optical modules transmit the input optical signal to the two sets of input fiber optic arrays. Each set of input fiber optic arrays has N ports connected to the N optical modules. Each set of input fiber optic arrays is connected to a corresponding optical beam splitter, which splits the light from the input fiber optic arrays. The split optical signal... After transmission via the input fiber optic array, the optical signal is connected to the Rx terminal of the main control chip, and the remaining optical signal is input to the corresponding optical switching chip. The Rx terminal is used to capture the specific data packet header transmitted by the input fiber optic array, which is parsed by the main control chip and a control command is generated. The main control chip uses the GPIO control array to control the corresponding optical switching chip, so that the switching unit in the optical switching chip completes the link switching. The switched link transmits the optical signal input to the optical switching chip to the optical module through the corresponding output fiber optic array. The N ports of each output fiber optic array are connected to N optical modules respectively.

2. A low latency fast-switched optical switching system as claimed in claim 1, characterized in that: It also includes 2N switching nodes, with each optical module connecting to two sets of switching nodes.

3. The low-latency, fast-switching optical switching system as described in claim 1, characterized in that: It also includes a power module for supplying power to the main control chip, optical switching chip and GPIO control array.

4. The low latency fast-switched optical switching system of claim 1, wherein: It also includes a thermal management module for real-time monitoring of the temperature of the main control chip, optical switching chip, and GPIO control array.

5. A low latency fast-switched optical switching system as claimed in claim 1, characterized in that: The optical switching chip consists of an N×N matrix of optical switching nodes with N inputs and N outputs. Each node includes an on-chip optical switch, and the on / off state of the optical switch is controlled by a GPIO control array.

6. A low latency fast-switched optical switching system as claimed in claim 5, characterized in that: The on-chip optical switch is fabricated based on thin-film lithium niobate, thin-film lithium tantalate, silicon-on-insulator, silicon nitride, aluminum nitride, or silicon oxynitride platforms, and is arranged using a non-blocking topology architecture such as PILOSS, Benes, CrossBar, or Torus.

7. A low latency fast-switched optical switching system as claimed in claim 1, characterized in that: The optical beam splitter outputs less than 10% of the optical signal.

8. A low-latency fast-switching optical switching method, implemented based on the optical switching system as claimed in claim 2, characterized in that, Includes the following steps: The switching node i to be communicated continuously sends switching and verification signals to the main control chip. The switching and verification signals are transmitted to the main control chip through the optical beam splitter and the input fiber array and are captured by the Rx end. At the same time, the switching node i waits for the response from the main control chip; where i represents the switching node number, i≤N; If the main control chip does not receive a switching and verification signal from the other switching node j to be communicated with, it will not perform a link switch and will continue to wait for a switching and verification signal from the switching node j; where j represents the switching node number, j≤N, i≠j; If the main control chip receives a switching and verification signal from switching node j, it generates a control command and controls the corresponding optical switching chip to perform link switching through the GPIO control array; After the link switch is completed, the verification signals of switching node i and switching node j are transmitted to each other through the input fiber array, optical switching chip and output fiber array. After the two switching nodes complete the verification, they continue to transmit data through the input fiber array, optical switching chip and output fiber array.

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