Wireless communication terminal sleep wake-up stress test method, system and terminal

Abstract

This invention provides a method, system, and terminal for sleep and wake-up stress testing of wireless communication terminals. It involves clock synchronization calibration of log and power consumption acquisition devices, followed by multiple rounds of stress testing. Each round synchronously collects operating logs and current waveforms. Light sleep, deep sleep, and wake-up states are extracted from the logs through text recognition, generating a timing condition table. Based on this, characteristic parameters for each condition are extracted from segmented current waveforms. Threshold matching, timing synchronization, and glitches are then performed to obtain the round results. Finally, the reliability score is calculated by combining the results of each round, and a visual report is generated. This invention achieves automatic joint verification of logs and current waveforms, using AI algorithms to complete timing alignment, state matching, and feature recognition, reducing the probability of missed or false positives. It accurately distinguishes between light sleep, deep sleep, and wake-up working states, locating various faults such as standby leakage, sleep obstruction, and abnormal wake-up timing. A standardized quantitative evaluation system is established to ensure traceability and controllability of test results.

Description

Technical Field

[0001] This invention relates to the field of wireless communication terminal technology, and in particular to a method, system and terminal for testing sleep and wake-up stress in wireless communication terminals. Background Technology

[0002] The sleep and wake-up functions of wireless communication terminals rely on the collaborative operation of multiple subsystems, including the modem, power domain, clock, and peripherals. Their stability directly impacts battery life and user experience. Since hardware and software anomalies can cause low-probability intermittent faults such as high standby current and inability to wake up normally, high-frequency stress testing with multiple trigger sources is necessary to effectively reproduce and locate the problem. However, existing sleep and wake-up stress testing technologies that rely solely on logs or single current data to determine device status have significant flaws. They cannot accurately distinguish between light sleep, deep sleep, and wake-up states, and are unable to effectively identify hidden faults such as standby leakage, subsystem sleep obstruction, and wake-up lag. Currently, the industry-standard pure serial port log method triggers terminal sleep and wake-up via test scripts and collects UART (Universal Asynchronous Receiver / Transmitter) serial port status logs, judging device status solely based on log markers. While simple to implement and highly automated, this method suffers from timing discrepancies between log printing and actual hardware status, failing to identify underlying issues such as hardware leakage and unclosed power domains. Another method, based solely on current waveform, uses a power meter to collect the terminal's overall current waveform. It relies on the current magnitude and waveform changes to determine the device's sleep and wake-up states. While this method provides a direct view of the overall power consumption, it cannot distinguish between light sleep and deep sleep modes, nor can it identify software scheduling anomalies. Both of these single-data-source methods suffer from incomplete data dimensions, weak fault identification capabilities, and difficulty in detecting hidden defects.

[0003] Currently, the closest approach to fully meeting analytical needs is the manual log and current joint judgment method. Testers compare the timing and status of synchronously collected timestamped serial port logs and current waveforms segment by segment to manually identify anomalies. While this method can handle both log and current data, it relies entirely on manual operation. Faced with massive amounts of data generated from thousands or even tens of thousands of stress cycles, the workload is enormous and the testing cycle is lengthy, making it completely unsuitable for log-current comparison analysis in large-scale stress cycle testing. Furthermore, the human eye cannot accurately identify millisecond-level timing offsets, small current fluctuations, and occasional glitches, and cannot effectively handle complex situations such as glitches, fluctuations, and short-term pulses, leading to frequent missed and false positives. In summary, existing technologies using a single judgment method lack data dimensions and have insufficient fault location capabilities; while manual joint comparison lacks unified quantitative standards, resulting in highly subjective test results, inaccurate recording of fault locations and abnormal values, and difficulties in problem tracing, failing to meet the urgent needs of wireless communication terminal sleep-wake stress testing for automation, high precision, and standardization. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method, system and terminal for testing sleep and wake-up stress of wireless communication terminals, which solves the technical problems of insufficient accuracy of the single data source judgment method in the existing sleep and wake-up stress testing methods for wireless communication terminals, and low efficiency and heavy reliance on subjective experience of the manual multi-source data judgment method, which makes it difficult to balance test accuracy and automation.

[0005] To achieve the above and other related objectives, this invention provides a sleep-wake stress test method for a wireless communication terminal. The method includes: clock synchronization calibration of a log acquisition device and a power consumption detection device for the wireless communication terminal; performing sleep-wake stress tests and data analysis for all preset cycles of the test period; calculating a comprehensive sleep-wake reliability score based on the verification results of all cycles; and generating a visual stress test report. Each cycle of sleep-wake stress testing and data analysis includes: synchronously acquiring the device operation log and current waveform diagram for the current cycle through the log acquisition device and power consumption detection device based on a constructed trigger source; parsing the device operation status in the device operation log using a text recognition algorithm; and determining the status based on the data. The system divides continuous independent operating condition intervals and outputs a structured timing condition table carrying state transition times and state types. The device operating states include light sleep, deep sleep, and wake-up states. The collected current waveform is preprocessed and segmented using the structured timing condition table. The characteristic parameters of the current waveform for each operating condition segment in the current cycle are calculated. Current threshold matching, timing jump synchronization, and abnormal glitch statistical verification are performed on the current waveform characteristic parameters to obtain the verification results for each operating condition segment in the current cycle. It is determined whether the current cycle has reached the preset number of cycles. If not, the next cycle of sleep-wake stress test and data analysis is executed. If the preset number of cycles has been reached, the sleep-wake stress test and data analysis are terminated.

[0006] In one embodiment of the present invention, the method of synchronously collecting device operation logs and current waveforms for the current round based on the constructed trigger source through a log acquisition device and a power consumption detection device includes: constructing a trigger source through an automated test script, and synchronously collecting serial port logs with millisecond-level timestamps and current waveforms with a sampling rate not lower than a preset sampling rate for the current round through a UART serial port acquisition device and a power consumption detection device; the trigger source includes one or more of the following: WiFi disconnection, WiFi reconnection, UART command, USB plugging / unplugging, and log switch.

[0007] In one embodiment of the present invention, the preprocessing of the acquired current waveform, the segmentation of the current waveform in conjunction with the structured time-series operating condition table, and the calculation of the current waveform characteristic parameters of each operating condition segment in the current cycle include: using a filtering algorithm to remove waveform noise and random spikes in the current waveform, segmenting the current waveform into operating condition segments according to the structured time-series operating condition table, and calculating the measured current data, transition edge time, current spike amplitude and frequency of each operating condition segment in the current cycle; the measured current data includes: average current and base current.

[0008] In one embodiment of the present invention, the step of performing current threshold matching, timing jump synchronization, and abnormal glitch statistical verification on the current waveform characteristic parameters to obtain the verification result of the current round includes: comparing and verifying the measured current data of the operating condition segment with the standard current range of the corresponding operating condition to obtain the current verification result; comparing the state switching time and the jump edge time in the structured timing operating condition table to obtain the timing jump synchronization verification result; and statistically analyzing the current peak amplitude and frequency of the shallow sleep segment and the deep sleep segment to obtain the abnormal glitch verification result.

[0009] In one embodiment of the present invention, the measured current data of each operating condition segment is compared and verified with the standard current range of the corresponding operating condition to obtain the current verification result. This includes: based on a pre-trained standard current threshold library, the measured current data of each operating condition segment is matched and compared with the standard current range of the corresponding operating condition one by one; wherein, each operating condition segment includes: deep sleep segment, light sleep segment, and wake-up segment; if the measured current data of the deep sleep segment exceeds the standard, it is determined that there is a deep sleep leakage or subsystem sleep blocking fault; if the measured current data of the light sleep segment increases abnormally, it is determined that there is an early wake-up fault; if the measured current data of the wake-up segment is too low, it is determined that there is an incomplete wake-up fault; if the measured current data matches the standard current range completely, the timing jump synchronization verification is entered.

[0010] In one embodiment of the present invention, comparing the state switching time in the structured timing condition table with the transition edge time to obtain the timing transition synchronization verification result includes: calculating the time difference between the state switching time in the structured timing condition table and the transition edge time; if the time difference exceeds a preset threshold, it is determined that there is a timing offset or a hardware / software state switching asynchrony fault; if the time difference does not exceed the preset threshold, then proceeding to abnormal glitch statistical verification.

[0011] In one embodiment of the present invention, obtaining abnormal glitches verification results by statistically analyzing the current peak amplitude and frequency during the shallow sleep phase and the deep sleep phase includes: statistically analyzing the current peak amplitude and frequency during the shallow sleep phase and the deep sleep phase, and comparing them with a preset glitches threshold standard; if the current peak amplitude and frequency exceed the preset glitches threshold, it is determined that there is a fault such as peripheral device not being turned off or power domain control being abnormal; if the current peak amplitude and frequency do not exceed the preset glitches threshold, it is determined that the current operating condition is completely normal.

[0012] In one embodiment of the present invention, calculating the comprehensive sleep-wake reliability score based on the verification results of all rounds and generating a visual stress test report includes: according to the verification results of all rounds, counting the number of normal operating conditions, the number of various faults, the frequency of faults, and the average current deviation within the test cycle, calculating the comprehensive sleep-wake reliability score according to a preset algorithm, and generating a visual stress test report.

[0013] To achieve the above and other related objectives, this invention provides a sleep-wake stress testing system for wireless communication terminals. The system includes: a clock synchronization module for clock synchronization calibration of the log acquisition device and power consumption detection device of the wireless communication terminal; and a testing and data analysis module connected to the clock synchronization module for performing sleep-wake stress testing and data analysis for all preset cycles of the test period, calculating a comprehensive sleep-wake reliability score based on the verification results of all cycles, and generating a visualized stress test report. Each cycle of sleep-wake stress testing and data analysis includes: synchronously collecting the device operation log and current waveform diagram of the current cycle through the log acquisition device and power consumption detection device based on a constructed trigger source; and analyzing the device operation log based on a text recognition algorithm. The system records the device's operating status in the logs and segments the system into continuous independent operating condition intervals based on these statuses. It outputs a structured timing table of operating conditions, including state transition times and state types. The device operating statuses include light sleep, deep sleep, and wake-up states. The system preprocesses the collected current waveforms and segments them using the structured timing table, calculating the characteristic parameters of each operating condition segment in the current cycle. It then performs current threshold matching, timing jump synchronization, and abnormal glitches on the current waveform characteristic parameters to obtain the verification results for each operating condition segment in the current cycle. Finally, it determines whether the current cycle has reached the preset number of cycles. If not, it executes the next cycle of sleep-wake stress test and data analysis. If the cycle has reached the preset number of cycles, it terminates the sleep-wake stress test and data analysis.

[0014] To achieve the above and other related objectives, the present invention provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method.

[0015] As described above, this invention provides a method, system, and terminal for testing the sleep and wake-up stress of wireless communication terminals, offering the following advantages: This invention performs clock synchronization calibration on log and power consumption acquisition devices before executing multiple rounds of stress testing. Each round synchronously acquires operating logs and current waveforms. Through text recognition, it extracts the light sleep, deep sleep, and wake-up states from the logs and generates a timing condition table. Based on this, it extracts characteristic parameters for each condition from the current waveform segments. Then, through threshold matching, timing synchronization, and glitch verification, it obtains the round results. Finally, it calculates a reliability score by combining the results of each round and generates a visual report. This invention achieves automatic joint verification of logs and current waveforms, using AI algorithms to complete timing alignment, state matching, and feature recognition, reducing the probability of missed or false positives. It accurately distinguishes between light sleep, deep sleep, and wake-up working states, locating various faults such as standby leakage, sleep obstruction, and abnormal wake-up timing. It establishes a standardized quantitative evaluation system, enabling traceable and controllable test results. Attached Figure Description

[0016] Figure 1 The diagram shown is a flowchart illustrating a sleep-wake stress test method for a wireless communication terminal according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram illustrating the sleep-wake stress test and data analysis process for each round in an embodiment of the present invention.

[0018] Figure 3 The diagram shown illustrates current threshold matching, timing jump synchronization, and abnormal glitch statistical verification in one embodiment of the present invention.

[0019] Figure 4 The diagram shown is a structural schematic of a wireless communication terminal sleep-wake stress testing system according to an embodiment of the present invention.

[0020] Figure 5 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of the present invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0022] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0023] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0024] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0025] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0026] This invention provides a method for stress testing sleep and wake-up of wireless communication terminals. It involves clock synchronization calibration of log and power consumption acquisition devices, followed by multiple rounds of stress testing. Each round synchronously collects operating logs and current waveforms. Light sleep, deep sleep, and wake-up states are extracted from the logs through text recognition, generating a timing condition table. Based on this, characteristic parameters for each condition are extracted from the current waveform segments. Threshold matching, timing synchronization, and glitches are then performed to obtain the round results. Finally, the reliability score is calculated by combining the results of each round, and a visual report is generated. This invention achieves automatic joint verification of logs and current waveforms, using AI algorithms to complete timing alignment, state matching, and feature recognition, reducing the probability of missed or false positives. It accurately distinguishes between light sleep, deep sleep, and wake-up working states, locating various faults such as standby leakage, sleep obstruction, and abnormal wake-up timing. A standardized quantitative evaluation system is established to ensure traceability and controllability of test results.

[0027] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0028] like Figure 1 A flowchart illustrating the sleep-wake stress test method for a wireless communication terminal in an embodiment of the present invention is shown.

[0029] The method includes:

[0030] Step S1: Perform clock synchronization calibration on the log collection device and power consumption detection device of the wireless communication terminal.

[0031] In detail, before the official start of the testing cycle, a unified time base is first established between the log acquisition device and the power consumption detection device. The UART serial port acquisition device and the power consumption detector are connected to the same local area network or directly connected to a synchronization bus. The host computer acts as the clock source, broadcasting standard time synchronization protocol messages to both devices. Upon receiving the synchronization command, both devices reset their internal clock counters and perform phase-locked loop calibration based on the host computer's system clock.

[0032] Furthermore, to achieve precise alignment between the serial port log and the current waveform at the sub-millisecond level, a high-precision hardware timestamp is inserted into the log output stream of the UART serial port data acquisition device. This timestamp is generated by a timer inside the serial port data acquisition device the instant the data frame arrives, achieving a resolution at the microsecond level. Simultaneously, the power consumption detector records the corresponding absolute timestamp at each current sampling point, ensuring sufficiently fine temporal granularity of the current waveform.

[0033] Before the formal testing begins, a synchronization verification is performed. The main control computer simultaneously sends a status query command to the wireless communication terminal under test and monitors the timestamp of the response log returned by the UART serial port acquisition unit and the corresponding current fluctuation start timestamp on the power consumption detector. The time difference between the two is compared; if the difference remains consistently stable within the sub-millisecond range, the clock synchronization calibration is considered complete, and the system enters the test-ready state. Throughout the entire testing cycle, a clock daemon process runs continuously in the background, periodically correcting the clocks of both devices to prevent cumulative offsets caused by prolonged operation from affecting the accuracy of subsequent status determinations.

[0034] Step S2: Perform sleep-wake stress tests and data analysis for all preset cycles of the test period, calculate the comprehensive sleep-wake reliability score based on the verification results of all cycles, and generate a visual stress test report.

[0035] Among them, such as Figure 2 Each round of sleep-wake stress testing and data analysis includes:

[0036] Based on the constructed trigger source, the device operation log and current waveform diagram of the current round are collected synchronously through log collection device and power consumption detection device;

[0037] The system analyzes the device operating status from the device operation log using a text recognition algorithm, and divides the system into continuous independent operating condition intervals based on the status. It then outputs a structured timing table of operating conditions, carrying the state transition time and state type. The device operating states include light sleep, deep sleep, and wake-up states. In light sleep, the system only shuts down some clocks and peripherals, yet can still quickly respond to interrupts. In deep sleep, the system shuts down the main clock and power domain, entering a minimum power consumption state. In wake-up state, the system is awakened from sleep by an interrupt and resumes operation.

[0038] The collected current waveform is preprocessed, and the current waveform is segmented by combining the structured timing condition table. The characteristic parameters of the current waveform of each condition segment in the current cycle are calculated.

[0039] The current waveform characteristic parameters are matched with current threshold, synchronized with timing jumps, and statistically verified for abnormal glitches to obtain the verification results of each working condition segment in the current cycle.

[0040] Determine if the current round has reached the preset number of iterations;

[0041] If the target is not met, the next round of sleep-wake stress test and data analysis will be conducted.

[0042] If the target is achieved, a comprehensive sleep-wake reliability score will be calculated based on the verification results of all rounds, and a visual stress test report will be generated.

[0043] In one embodiment, the trigger source based on the constructed system synchronously collects the device operation logs and current waveforms for the current cycle through a log collection device and a power consumption detection device, including:

[0044] An automated test script is run to construct a trigger source and apply external stimulation to the wireless communication terminal under test. At the start of each test round, the script synchronously activates the log acquisition device and the power consumption detection device, enabling them to collect data for the current round in parallel, ensuring that the device operation log and current waveform remain synchronized in the time domain.

[0045] The trigger sources constructed by the automated test script include one or more of the following: WiFi disconnection, WiFi reconnection, UART commands, USB plugging / unplugging, and log switch. Each trigger source acts on the terminal under test sequentially according to the preset round configuration and timing logic, simulating various external events and command inputs in real application scenarios, causing the terminal to perform state transitions between light sleep, deep sleep, and wake-up states.

[0046] Log collection is performed by a UART serial port collector. This collector establishes a communication connection with the terminal under test via a physical serial port and captures the serial port log data output by the terminal in real time during the test. For each captured log line, the UART serial port collector uses its internal hardware timer to generate an absolute timestamp with millisecond precision at the moment the data frame arrives, and associates and stores this timestamp with the original log content to form a device operation log with precise timestamps, providing a time reference for subsequent status identification and operating condition segmentation.

[0047] Current waveform acquisition is performed by a power consumption detector. The device's current sampling probe is connected in series in the power supply circuit of the terminal under test, continuously sampling the terminal's operating current at a sampling rate of no less than 10 kS / s during the test. Each sample records the corresponding sampling time and current amplitude, thereby generating a high-resolution current waveform. This sampling rate setting ensures complete capture of rapid current jumps and subtle abnormal glitches during sleep-wake transitions.

[0048] During a single round of testing, the automated test script sends a synchronous acquisition start signal to the UART serial port data acquisition unit and the power consumption detector simultaneously with the trigger command. The two devices operate in parallel using a unified time base, based on the clock synchronization calibration results completed before the test. The millisecond-level timestamps of the serial port logs and the sampling timestamps of the current waveforms are aligned with each other within sub-millisecond precision, ensuring that the state transition records in the logs accurately correspond to the electrical response changes in the current waveforms. This eliminates data misalignment caused by acquisition start-up time differences or clock drift between devices.

[0049] In one embodiment, a text recognition algorithm is used to parse the device operation log to extract the device's operating status. This algorithm scans the log text line by line and performs pattern matching to identify three key operating states: light sleep, deep sleep, and wake-up. Specifically, when the character 'S' appears on a single line in the log, the system determines it to be in a light sleep state; when 'WFI@' appears, it is determined to be in a deep sleep state; and when 'R' appears, it is determined to be in a wake-up state. By capturing the positions of these state identifiers in the log, the algorithm can accurately locate state transition nodes.

[0050] Based on the identified state transition nodes, the system divides continuous log data into multiple continuous and independent operating condition intervals. Each operating condition interval corresponds to a single stable state maintained by the equipment within a specific time period. Subsequently, the system outputs a structured time-series operating condition table, which records in detail the start time, end time, and corresponding state type of each operating condition interval. The resulting structured time-series table not only carries accurate state transition time information but also clearly marks the state category to which each interval belongs, providing a standardized data foundation for subsequent time alignment and feature analysis with current waveforms.

[0051] In one embodiment, the acquired current waveform is preprocessed and its features are extracted. First, a filtering algorithm is used to process the original current waveform, effectively removing waveform noise and random spikes to improve the signal-to-noise ratio and purity of the waveform data. Then, based on the state switching time nodes recorded in the aforementioned structured time-series operating condition table, the filtered continuous current waveform is precisely segmented into operating condition segments, dividing the complete current waveform into independent operating condition intervals corresponding to the light sleep, deep sleep, and wake-up states.

[0052] The filtering process suppresses high-frequency noise and random interference spikes in the current waveform. By applying appropriate filtering algorithms, the system can smooth the current curve, eliminate non-physical fluctuations introduced by the measurement environment or equipment itself, and retain the true current change trend. This step provides a clean and reliable data foundation for subsequent accurate segmentation based on log timestamps, avoiding misjudgments or blurred boundaries caused by noise.

[0053] After filtering, the current waveform is aligned and segmented along the time axis based on the start and end times of each state marked in the structured time-series operating condition table. Each operating condition segment strictly corresponds to a single operating state of the equipment within a specific time period, ensuring complete consistency between the current data and the state semantics recorded in the log. This segmentation method based on precise time synchronization achieves accurate mapping from continuous current waveforms to discrete operating condition intervals.

[0054] For each independent operating condition segment, the system further calculates various current waveform characteristic parameters in that round of testing. Regarding the measured current data, the average current and base current within that segment are extracted to reflect the overall energy consumption level and steady-state current benchmark under that operating condition, respectively. Simultaneously, the system identifies and records the current transition edges, capturing the current change time points during state transitions. Furthermore, current spikes are statistically analyzed, calculating their amplitude and frequency of occurrence, thereby comprehensively quantifying the current behavior characteristics of each operating condition range and providing data support for subsequent threshold matching and timing synchronization verification.

[0055] In one embodiment, the step of performing current threshold matching, timing jump synchronization, and abnormal glitch statistical verification on the current waveform characteristic parameters to obtain the verification result of the current round includes:

[0056] The measured current data of the operating conditions are compared and verified with the standard current range of the corresponding operating conditions to obtain the current verification results. This step identifies abnormal current conditions such as deep sleep leakage, premature wake-up or incomplete wake-up by judging whether the measured current is within the standard range.

[0057] The state transition time in the structured timing condition table is compared with the current transition edge time to obtain the timing transition synchronization verification result. This step determines whether there is a timing offset or a lack of synchronization between the hardware and software state transitions by calculating the time difference between the state transition time and the current transition edge time.

[0058] The abnormal glitches are detected by statistically analyzing the amplitude and frequency of current spikes during the light and deep sleep phases. This step determines whether peripherals are not turned off or whether there are abnormalities in power domain control by monitoring current spikes during low-power states.

[0059] In one specific embodiment, such as Figure 3 The measured current data for each operating condition segment is compared and verified with the standard current range for the corresponding operating condition to obtain the current verification result. The process of obtaining the current verification result relies on a pre-trained standard current threshold library. This process matches and compares the measured current data for each operating condition segment, such as deep sleep, light sleep, and wake-up, with the standard current range for the corresponding operating condition one by one, thereby identifying current anomalies under different low-power states.

[0060] When the measured current data during deep sleep exceeds the upper limit of the standard current range, the system determines that the device has a deep sleep leakage fault or a subsystem sleep-blocking fault. This type of anomaly indicates that the device failed to effectively cut off unnecessary power supply circuits in deep sleep mode, or that a subsystem is preventing the device from entering the proper low-power deep sleep state.

[0061] When the measured current data during the light sleep phase shows an abnormal increase compared to the standard current range, the system determines that there is an early wake-up fault. This phenomenon means that the device experienced an undue increase in power consumption during the light sleep phase, which may correspond to some modules incorrectly restoring power or clock before the scheduled wake-up time.

[0062] When the measured current data of the wake-up segment is lower than the lower limit of the standard current range, the system determines that there is an incomplete wake-up fault. This indicates that the device failed to reach the current level required for normal full-speed operation during the wake-up process, which may reflect that the main control unit or key peripherals have not started normally, causing the system to be in an unexpected low-power stagnation state.

[0063] If the measured current data of each operating condition segment, such as deep sleep, light sleep, and wake-up, are completely matched with the corresponding standard current range and no abnormal situation occurs, the current threshold matching verification is passed, and the process automatically enters the timing jump synchronization verification stage to further verify the time consistency of state switching.

[0064] In one specific embodiment, such as Figure 3 The state transition times in the structured timing condition table are compared with the transition edge times to obtain the timing transition synchronization verification results, including:

[0065] First, calculate the time difference between the state transition time and the current waveform transition edge in the structured timing table. This time difference reflects the degree of deviation between the state transition time recorded by the software and the actual time when the hardware current changes.

[0066] If the aforementioned time difference exceeds a preset threshold, the device is determined to have a timing offset fault or a hardware / software state transition asynchrony fault. This type of anomaly indicates a significant delay or misalignment between the state transition commands at the software level and the actual power consumption state changes at the hardware level, which may lead to instability or functional abnormalities in the system during low-power transitions.

[0067] If the above time difference does not exceed the preset threshold, it means that the time consistency of the state transition meets the requirements, the timing jump synchronization verification is passed, and the process will enter the abnormal glitch statistical verification stage to continue to evaluate the stability of the current waveform.

[0068] In one specific embodiment, such as Figure 3 The abnormal glitches were detected by statistically analyzing the amplitude and frequency of current spikes during the light and deep sleep phases. The results included:

[0069] First, the current waveforms of the light and deep sleep phases are monitored, and the amplitude and frequency of current spikes are statistically analyzed. Then, the statistical results are compared with the preset glitch threshold standard.

[0070] If the amplitude and frequency of current spikes exceed the preset glitch threshold, the device is determined to have a peripheral device not being turned off or a power domain control malfunction. This type of malfunction indicates that some peripheral devices are not completely turned off in low-power mode, or that the switching control logic of the power domain is abnormal, resulting in unexpected instantaneous current pulses.

[0071] If the amplitude and frequency of current spikes do not exceed the preset glitch threshold, it indicates that the current waveform remains stable during the low-power phase and there is no abnormal glitch interference, thus determining that the current operating condition is completely normal.

[0072] In one embodiment, after completing all load testing rounds, the results of current threshold verification, timing jump synchronization verification, and abnormal glitches verification from each round are summarized. The system first categorizes and statistically analyzes the operating conditions within the test cycle, recording the total number of normal operating conditions, as well as the occurrence and frequency of various faults such as deep sleep leakage, blocked sleep, premature wake-up, incomplete wake-up, timing offset, hardware / software asynchrony, peripherals not turned off, and power domain control anomalies. Simultaneously, the system extracts the measured current values ​​from all abnormal operating conditions and calculates their average current deviation from the median of the corresponding standard interval.

[0073] Based on this, the testing system weights and integrates the above indicators according to a preset algorithm to generate a comprehensive sleep-wake reliability score. This preset algorithm can set differentiated weights for the proportion of normal operating conditions, failure frequency, average current deviation, and failure severity, so that the score results can quantitatively reflect the overall stability and reliability level of the device under test in low-power cycles.

[0074] Finally, the system automatically generates a visual stress test report based on the statistical results and comprehensive score. The report presents the status distribution of each round, current waveform trends, fault type proportions, and score change curves in chart form, making it easy for testers to intuitively locate weak points and evaluate the performance of the equipment under long-term sleep-wake stress tests.

[0075] Similar in principle to the above embodiments, the present invention provides a sleep-wake stress testing system for wireless communication terminals.

[0076] The following specific embodiments are provided in conjunction with the accompanying drawings:

[0077] like Figure 4 This diagram illustrates the structure of a wireless communication terminal sleep-wake stress testing system according to an embodiment of the present invention. The system includes:

[0078] Clock synchronization module 1 is used to perform clock synchronization calibration on the log collection device and power consumption detection device of the wireless communication terminal;

[0079] The testing and data analysis module 2 is connected to the clock synchronization module 1 and is used to perform sleep-wake stress tests and data analysis for all preset cycles of the test period. Based on the verification results of all cycles, it calculates the comprehensive score of sleep-wake reliability and generates a visual stress test report.

[0080] The sleep-wake stress test and data analysis for each round include:

[0081] Based on the constructed trigger source, the device operation log and current waveform diagram of the current round are collected synchronously through log collection device and power consumption detection device;

[0082] The device operation status in the device operation log is analyzed based on the text recognition algorithm, and continuous independent operating condition intervals are divided according to the status. A structured time-series operating condition table carrying the state switching time and state type is output. The device operation status includes light sleep state, deep sleep state and wake-up state.

[0083] The collected current waveform is preprocessed, and the current waveform is segmented by combining the structured timing condition table. The characteristic parameters of the current waveform of each condition segment in the current cycle are calculated.

[0084] The current waveform characteristic parameters are matched with current threshold, synchronized with timing jumps, and statistically verified for abnormal glitches to obtain the verification results of each working condition segment in the current cycle.

[0085] Determine if the current round has reached the preset number of iterations;

[0086] If the target is not met, the next round of sleep-wake stress test and data analysis will be conducted.

[0087] If the target is reached, the sleep-wake stress test and data analysis will then conclude.

[0088] Since the implementation principle of the wireless communication terminal sleep-wake stress test system has been described in the foregoing embodiments, it will not be repeated here.

[0089] The sleep-wake stress test method for wireless communication terminals provided in this embodiment of the invention can be implemented on the terminal side or the server side. Regarding the hardware structure of the electronic terminal, please refer to... Figure 5This is a schematic diagram of an optional hardware structure of an electronic terminal 1000 provided in an embodiment of the present invention. The terminal 1000 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It is understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 All buses are labeled as bus systems.

[0090] The user interface 1009 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0091] It is understood that memory 1002 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0092] In this embodiment of the invention, the memory 1002 is used to store various types of data to support the operation of the terminal 1000. Examples of this data include: any executable program for operation on the terminal 1000, such as the operating system 10021 and application program 10022; the operating system 10021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 10022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The sleep-wake stress test method for wireless communication terminals provided in this embodiment of the invention can be included in the application program 10022.

[0093] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 1001 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0094] In an exemplary embodiment, the terminal 1000 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0095] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0096] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact optical discs (CDs), laser optical discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0097] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to perform the method of any of the embodiments described above.

[0098] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to perform the method of any of the embodiments described above.

[0099] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0100] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0101] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0102] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0104] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0105] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] Compared with the prior art, the present invention has the following significant technical advantages:

[0107] 1. Test efficiency is improved by a huge margin: For the full data analysis of tens of thousands of cycle stress tests, the task that originally required several hours of manual work can be completed in minutes and is fully automated, which greatly reduces the cost of human resources and is fully adapted to the batch testing needs of industrial production lines.

[0108] 2. Comprehensive leap in detection accuracy: Relying on AI algorithms, it can accurately capture subtle abnormal features that cannot be identified by human vision and experience, such as millisecond-level timing deviations, micro-current fluctuations, and sporadic abnormal burrs, thereby significantly reducing the probability of missed and false detections from the root.

[0109] 3. Significantly improved fault location accuracy: By integrating two core data types, logs and current, the AI ​​algorithm can accurately distinguish different fault types such as software scheduling faults, hardware leakage, and peripheral abnormalities. At the same time, it automatically records the precise time of the fault occurrence and related parameters, supporting R&D personnel to quickly complete problem location and repair.

[0110] 4. Standardized and quantifiable test results: A unified quantitative scoring system is built through AI. The output test results are objective and neutral, and the data is completely retained throughout the entire process. It can be directly used for cross-batch quality comparison of products, full-process quality control, and retrospective tracing of historical issues.

[0111] 5. Excellent deployment convenience and data security: It adopts a lightweight AI model architecture, supports offline operation on the host computer, and does not require network data transmission throughout the process. This mechanism avoids the risk of leakage of original test data and can be quickly deployed in multiple scenarios such as laboratories and production workshops.

[0112] Compared to single methods such as pure serial port log judgment and pure current waveform judgment, this invention completely makes up for the information blind spots of a single data source by deeply integrating two types of core data, resulting in a wider range of fault identification coverage and significantly improved reliability and robustness of test results.

[0113] In summary, the wireless communication terminal sleep-wake stress test method, system, and terminal of this invention perform clock synchronization calibration on log and power consumption acquisition devices, and then execute multiple rounds of stress tests. Each round synchronously collects operating logs and current waveforms, extracts the light sleep, deep sleep, and wake-up states from the logs through text recognition, and generates a timing condition table. Based on this, segmented characteristic parameters of each condition are extracted from the current waveform. The round results are then obtained through threshold matching, timing synchronization, and glitch verification. Finally, the reliability score is calculated by combining the results of each round, and a visual report is generated. This invention achieves automatic joint verification of logs and current waveforms, using AI algorithms to complete timing alignment, state matching, and feature recognition, reducing the probability of missed or false positives; accurately distinguishing between light sleep, deep sleep, and wake-up working states, and locating various faults such as standby leakage, sleep obstruction, and abnormal wake-up timing; and establishing a standardized quantitative evaluation system to achieve traceable and controllable test results. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for stress testing sleep wake-up of a wireless communication terminal, the method comprising: The method includes: Clock synchronization calibration is performed on the log collection device and power consumption detection device of the wireless communication terminal; Perform sleep-wake stress tests and data analysis for all preset cycles of the test cycle, calculate the comprehensive sleep-wake reliability score based on the verification results of all cycles, and generate a visual stress test report; The sleep-wake stress test and data analysis for each round include: Based on the constructed trigger source, the device operation log and current waveform diagram of the current round are collected synchronously through log collection device and power consumption detection device; The device operation status in the device operation log is analyzed based on the text recognition algorithm, and continuous independent operating condition intervals are divided according to the status. A structured time-series operating condition table carrying the state switching time and state type is output. The device operation status includes light sleep state, deep sleep state and wake-up state. The collected current waveform is preprocessed, and the current waveform is segmented by combining the structured timing condition table. The characteristic parameters of the current waveform of each condition segment in the current cycle are calculated. The current waveform characteristic parameters are matched with current threshold, synchronized with timing jumps, and statistically verified for abnormal glitches to obtain the verification results of each working condition segment in the current cycle. Determine if the current round has reached the preset number of iterations; If the target is not met, the next round of sleep-wake stress test and data analysis will be conducted. If the target is reached, the sleep-wake stress test and data analysis will then conclude.

2. The wireless communication terminal sleep wake-up stress test method of claim 1, wherein, The constructed trigger source synchronously collects the device operation logs and current waveforms for the current round through log collection devices and power consumption detection devices, including: The trigger source is constructed by an automated test script, and the serial port log with millisecond-level timestamps and the current waveform with a sampling rate of not less than the preset sampling rate are collected synchronously by a UART serial port collector and a power consumption detection device. The trigger source includes one or more of the following: WiFi disconnection, WiFi reconnection, UART command, USB plugging / unplugging, and log switch.

3. The wireless communication terminal sleep wake stress test method of claim 1 wherein, The preprocessing of the acquired current waveform, the segmentation of the current waveform using a structured time-series operating condition table, and the calculation of the current waveform characteristic parameters for each operating condition segment in the current cycle include: A filtering algorithm is used to remove waveform noise and random spikes in the current waveform diagram. The current waveform is segmented into operating conditions based on a structured timing table. The measured current data, transition times, current spike amplitude and frequency of each operating condition segment in the current cycle are calculated. The measured current data includes: average current and base current.

4. The wireless communication terminal sleep wake-up stress test method of claim 3, wherein, The process of performing current threshold matching, timing jump synchronization, and abnormal glitch statistical verification on the current waveform characteristic parameters to obtain the verification results for the current round includes: The measured current data for each operating condition segment is compared and verified with the standard current range for the corresponding operating condition to obtain the current verification results. The state transition time in the structured timing condition table is compared with the transition edge time to obtain the timing transition synchronization verification result. The abnormal glitches were detected by statistically analyzing the amplitude and frequency of current spikes during the light and deep sleep phases.

5. The method for testing sleep-wake stress in a wireless communication terminal according to claim 4, characterized in that, The measured current data for each operating condition segment are compared and verified with the standard current range for the corresponding operating condition. The current verification results include: Based on a pre-trained standard current threshold library, the measured current data of each operating condition segment are matched and compared with the standard current range of the corresponding operating condition one by one; among them, each operating condition segment includes: deep sleep segment, light sleep segment and wake-up segment. If the measured current data of the deep sleep phase exceeds the standard, it is determined that there is a deep sleep leakage or a subsystem sleep blocking fault. If the measured current data during the light sleep phase increases abnormally, it is determined that there is an early wake-up fault. If the measured current data of the wake-up segment is low, it is determined that there is an incomplete wake-up fault. If the measured current data matches the standard current range perfectly, then proceed to the timing jump synchronization verification.

6. The method for testing sleep-wake stress in a wireless communication terminal according to claim 4, characterized in that, By comparing the state transition times in the structured timing condition table with the transition edge times, the timing transition synchronization verification results are obtained, including: Calculate the state transition time and the time difference between the transition edges in the structured timing table; If the time difference exceeds the preset threshold, it is determined that there is a timing offset or a lack of synchronization between software and hardware state switching. If the time difference does not exceed the preset threshold, then proceed to the abnormal spike statistical verification.

7. The method for testing sleep-wake stress in a wireless communication terminal according to claim 4, characterized in that, The results of abnormal glitches verification were obtained by statistically analyzing the amplitude and frequency of current spikes during the light and deep sleep phases, including: The amplitude and frequency of current spikes during light and deep sleep phases were statistically analyzed and compared with the preset glitch threshold standard. If the amplitude and frequency of the current spike exceed the preset glitch threshold, it is determined that there is a fault such as peripheral device not being turned off or power domain control being abnormal. If the current spike amplitude and frequency do not exceed the preset glitch threshold, the current operating condition is determined to be completely normal.

8. The method for testing sleep and wake-up stress in a wireless communication terminal according to claim 1, characterized in that, Based on the verification results of all rounds, a comprehensive sleep-wake reliability score is calculated, and a visual stress test report is generated, including: Based on the verification results of all rounds, the number of normal operating conditions, the number of various faults, the frequency of faults, and the average current deviation within the test cycle are statistically analyzed. The sleep-wake reliability comprehensive score is calculated according to the preset algorithm, and a visual stress test report is generated.

9. A sleep-wake stress testing system for a wireless communication terminal, characterized in that the system comprises: The clock synchronization module is used to perform clock synchronization calibration on the log collection device and power consumption detection device of the wireless communication terminal. The testing and data analysis module, connected to the clock synchronization module, is used to perform sleep-wake stress tests and data analysis for all preset cycles of the test period, calculate the comprehensive sleep-wake reliability score based on the verification results of all cycles, and generate a visual stress test report. The sleep-wake stress test and data analysis for each round include: Based on the constructed trigger source, the device operation log and current waveform diagram of the current round are collected synchronously through log collection device and power consumption detection device; The device operation status in the device operation log is analyzed based on the text recognition algorithm, and continuous independent operating condition intervals are divided according to the status. A structured time-series operating condition table carrying the state switching time and state type is output. The device operation status includes light sleep state, deep sleep state and wake-up state. The collected current waveform is preprocessed, and the current waveform is segmented by combining the structured timing condition table. The characteristic parameters of the current waveform of each condition segment in the current cycle are calculated. The current waveform characteristic parameters are matched with current threshold, synchronized with timing jumps, and statistically verified for abnormal glitches to obtain the verification results of each working condition segment in the current cycle. Determine if the current round has reached the preset number of iterations; If the target is not met, the next round of sleep-wake stress test and data analysis will be conducted. If the target is reached, the sleep-wake stress test and data analysis will then conclude.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 1 to 8.

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