Anti-warping chip embedded PCB

Abstract

This invention discloses an anti-warping chip-embedded PCB board. The anti-warping chip-embedded PCB board includes at least a chip embedding layer. At least one chip embedding area is provided in the central region of the chip embedding layer. Multiple auxiliary pattern structures are uniformly distributed in the peripheral region of the chip embedding layer. Each auxiliary pattern structure has an outer edge and an inner edge, the outer edge being parallel to the outer contour of its adjacent anti-warping chip-embedded PCB board. The inner edges of the multiple auxiliary pattern structures are sequentially connected to form a polygon, the center of which coincides with the center of the anti-warping chip-embedded PCB board. The at least one chip embedding area and the multiple auxiliary pattern structures are symmetrically distributed about the center of the anti-warping chip-embedded PCB board.

Description

Technical Field

[0001] This invention relates to the field of PCB technology, and in particular to an anti-warping chip embedded PCB board. Background Technology

[0002] As the heart of power electronic systems, the performance of power devices directly determines the energy efficiency and reliability of the entire system. Traditional packaging methods, when faced with wide-bandgap semiconductors (such as silicon carbide and gallium nitride), expose bottlenecks such as heat dissipation difficulties, excessive parasitic parameters, and limited integration density. Chip embedding technology, by directly embedding power chips inside the PCB substrate, achieves comprehensive optimization of electrical connections, heat dissipation paths, and mechanical structures, bringing significant performance improvements to fields such as electric vehicles, new energy, and industrial automation.

[0003] When power chips are directly embedded inside a PCB substrate, the significant difference in thermal expansion coefficients between the prepreg and the power chip generates substantial internal stress during the lamination process, leading to significant warping of the embedded PCB. This PCB warping prevents electronic components from adhering tightly to the solder pads, and the stress generated by warping can also cause solder joint breakage, all of which affect reliable electrical connections. If the warping cannot be corrected, the warped PCB must be scrapped. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides an anti-warping chip embedded PCB board. This anti-warping chip embedded PCB board includes a surface layer, an intermediate layer, a bottom layer, and a chip embedding layer.

[0005] The central region of the chip embedding layer has at least one chip embedding area.

[0006] The chip embedding layer has multiple auxiliary pattern structures evenly distributed around its perimeter.

[0007] Each of the auxiliary graphic structures has an outer edge and an inner edge, the outer edge being parallel to the outer contour of the adjacent anti-warping chip embedded PCB board.

[0008] The inner sides of multiple auxiliary graphic structures are connected sequentially to form a polygon, and the center of the polygon coincides with the center of the anti-warping chip embedded PCB board.

[0009] The at least one chip embedding area and the plurality of auxiliary graphic structures are symmetrically distributed about the center of the anti-warping chip embedded PCB board.

[0010] In one embodiment, the at least one chip embedding area is comprised of multiple blocks, which are symmetrically distributed in a grid pattern around the center of the anti-warping chip embedded PCB board.

[0011] In one embodiment, the number of the at least one chip embedding region is four, and the four chip embedding regions are arranged in a square array.

[0012] In one embodiment, the multiple auxiliary graphic structures are radially and uniformly distributed.

[0013] In one embodiment, the gap between any two adjacent auxiliary graphic structures is equal.

[0014] In one embodiment, the number of auxiliary graphic structures is eight, and the multiple auxiliary graphic structures are distributed in a star-shaped pattern, and the polygons are regular octagons.

[0015] In one embodiment, two adjacent auxiliary graphic structures are mirror-symmetric about the centerline of their adjacent sides.

[0016] In one embodiment, the inner side edge is either a broken line or a straight line.

[0017] In one embodiment, the edges of the auxiliary graphic structure are rounded.

[0018] In one embodiment, a power chip is embedded within the chip embedding layer.

[0019] In one embodiment, the auxiliary graphic structure is a graphic structure made of metallic material.

[0020] In one embodiment, the auxiliary graphic structure is a graphic structure made of non-metallic material.

[0021] In one embodiment, the auxiliary graphic structure is an auxiliary copper pour.

[0022] This invention employs a gridded design centered on the center point of the anti-warping chip-embedded PCB board in the chip embedding area, resulting in uniform stress distribution and reducing warpage in the central region of the anti-warping chip-embedded PCB board. Simultaneously, this invention designs multiple auxiliary graphic structures radially distributed around the chip embedding layer. The outer edges of these auxiliary graphic structures are parallel to the outer contours of adjacent anti-warping chip-embedded PCB boards, and their inner edges are sequentially connected to form polygons. The center point of each polygon coincides with the center point of the anti-warping chip-embedded PCB board. Adjacent auxiliary graphic structures are mirror-symmetrical about the center lines of their adjacent sides. The gaps between any two adjacent auxiliary graphic structures are equal, and the edges of the auxiliary graphic structures are rounded, further enhancing stress distribution and reducing warpage around the periphery of the anti-warping chip-embedded PCB board. Attached Figure Description

[0023] The above-described invention and the following detailed description will be better understood when read in conjunction with the accompanying drawings. It should be noted that the drawings are merely examples of the claimed invention. In the drawings, the same reference numerals represent the same or similar elements.

[0024] Figure 1 A schematic diagram of an anti-warping chip embedded PCB board according to an embodiment of the present invention is shown. Figure 2 A schematic diagram of a chip embedding layer in an anti-warping chip embedded PCB board according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of a chip embedding layer in an anti-warping chip embedded PCB board according to yet another embodiment of the present invention is shown. Figure 4 A schematic diagram of a chip embedding layer in an anti-warping chip embedded PCB board is shown according to another embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 1. Chip embedding layer; 2. Chip embedding area; 3. Auxiliary graphic structure; 4. Inner side of auxiliary graphic structure; 5. The outer edge of the auxiliary graphic structure; 6. Adjacent edges of auxiliary graphic structures; 7. Outer contour of the embedded PCB board for anti-warping chip Detailed Implementation

[0026] The following detailed description of the features and advantages of the present invention provides sufficient information for any person skilled in the art to understand and implement the invention. Furthermore, based on the specification, claims, and drawings disclosed herein, those skilled in the art can easily understand the related objectives and advantages of the invention. Although the description of the invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may arise based on the claims of the invention. To provide a thorough understanding of the invention, numerous specific details will be included in the following description. The invention may also be implemented without using these details. Moreover, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0029] It is understood that while terms such as "first," "second," and "third" may be used herein to describe various components, channels, assemblies, regions, layers, and / or parts, these components, channels, assemblies, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, channels, assemblies, regions, layers, and / or parts. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0031] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0032] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0033] This invention provides an anti-warping chip embedded PCB board, comprising a surface layer, an intermediate layer, a bottom layer, and a chip embedding layer.

[0034] The central region of the chip embedding layer has at least one chip embedding area.

[0035] The chip embedding layer has multiple auxiliary pattern structures evenly distributed around its perimeter.

[0036] Each of the auxiliary graphic structures has an outer edge and an inner edge, the outer edge being parallel to the outer contour of the adjacent anti-warping chip embedded PCB board.

[0037] The inner sides of multiple auxiliary graphic structures are connected sequentially to form a polygon, and the center of the polygon coincides with the center of the anti-warping chip embedded PCB board.

[0038] The at least one chip embedding area and the plurality of auxiliary graphic structures are symmetrically distributed about the center of the anti-warping chip embedded PCB board.

[0039] In one embodiment, the at least one chip embedding area is comprised of multiple blocks, which are symmetrically distributed in a grid pattern around the center of the anti-warping chip embedded PCB board.

[0040] In one embodiment, the number of the at least one chip embedding region is four, and the four chip embedding regions are arranged in a square array.

[0041] In one embodiment, the multiple auxiliary graphic structures are radially and uniformly distributed.

[0042] In one embodiment, the gap between any two adjacent auxiliary graphic structures is equal.

[0043] In one embodiment, the number of auxiliary graphic structures is eight, and the multiple auxiliary graphic structures are distributed in a star-shaped pattern, and the polygons are regular octagons.

[0044] In one embodiment, two adjacent auxiliary graphic structures are mirror-symmetric about the centerline of their adjacent sides.

[0045] In one embodiment, the inner side is zigzag-shaped.

[0046] In one embodiment, the edges of the auxiliary graphic structure are rounded.

[0047] In one embodiment, a power chip is embedded within the chip embedding layer.

[0048] In one embodiment, the auxiliary graphic structure is a graphic structure made of metallic material.

[0049] In one embodiment, the auxiliary graphic structure is a graphic structure made of non-metallic material.

[0050] In one embodiment, the auxiliary graphic structure is an auxiliary copper pour.

[0051] Figure 1 This diagram illustrates an overall schematic of an anti-warping chip-embedded PCB board according to an embodiment of the present invention. An anti-warping chip-embedded PCB board refers to a PCB board in which a chip is directly embedded inside a PCB substrate. The anti-warping chip-embedded PCB board of the present invention includes a surface layer, an intermediate layer, and a bottom layer identical to those of a conventional PCB board, as well as a chip embedding layer 1 unique to chip-embedded PCB boards.

[0052] Figure 2 A schematic diagram of the chip embedding layer of an anti-warping chip embedded PCB board according to an embodiment of the present invention is shown, wherein, Figure 2 for Figure 1 The top view direction.

[0053] The chip embedding layer 1 has four chip embedding areas 2 at its center. The four chip embedding areas 2 are symmetrically distributed in a centered manner, that is, arranged in a square array with the center point of the anti-warping chip embedded PCB board as the center. Eight auxiliary pattern structures 3 are evenly arranged around the chip embedding layer 1, and the auxiliary pattern structures 3 are distributed in a star-shaped pattern around the chip embedding layer 1.

[0054] In one embodiment, the auxiliary graphic structure 3 is a graphic structure made of metallic material.

[0055] In one embodiment, the auxiliary graphic structure 3 is a graphic structure made of non-metallic material.

[0056] In one embodiment, the auxiliary graphic structure 3 is an auxiliary copper pour.

[0057] Each auxiliary graphic structure 3 has an outer edge 5, an inner edge 4, and two adjacent edges 6. The inner edge 4 is a polygonal line.

[0058] The outer side 5 of the auxiliary graphic structure is parallel to the outer contour 7 of the adjacent anti-warping chip embedded PCB board. The inner side 4 of the auxiliary graphic structure 3 are connected in sequence to form a regular octagon. The center point of the regular octagon coincides with the center point of the anti-warping chip embedded PCB board.

[0059] The two adjacent auxiliary graphic structures 3 are mirror-symmetrical about the center line of the adjacent side 6 of the adjacent auxiliary graphic structure. The gap between any two adjacent auxiliary graphic structures 3 in the eight auxiliary graphic structures 3 is equal. This design helps to reduce the warpage of the embedded PCB board of the anti-warpage chip.

[0060] To prevent stress from concentrating excessively at a single point, the edges of auxiliary graphic structure 3 are rounded. After rounding, the edge stress of auxiliary graphic structure 3 acts over a wider range, and the stress distribution is more uniform, avoiding local warping of the PCB board and thus reducing the overall warping of the PCB board with the anti-warping chip embedded in it.

[0061] Figure 3 This diagram illustrates a chip embedding layer in an anti-warping chip embedded PCB board according to yet another embodiment of the present invention, wherein... Figure 3 for Figure 1 The top view direction.

[0062] The chip embedding layer has four chip embedding areas at its center. These four chip embedding areas are symmetrically distributed in a square array, centered on the center point of the anti-warping chip embedded PCB board.

[0063] Eight auxiliary pattern structures are evenly arranged around the chip embedding layer, and the auxiliary pattern structures are distributed in a star-shaped pattern around the chip embedding layer.

[0064] Each auxiliary graphic structure has one outer edge, one inner edge, and two adjacent edges.

[0065] The outer edges of the auxiliary graphic structures are parallel to the outer contours of the adjacent anti-warping chip embedded PCB board. The inner edges of each auxiliary graphic structure are connected in sequence to form a regular quadrilateral, and the center point of the regular quadrilateral coincides with the center point of the anti-warping chip embedded PCB board.

[0066] The two adjacent auxiliary graphic structures are mirror-symmetrical about the center line of the adjacent side of the auxiliary graphic structure. The gap between any two adjacent auxiliary graphic structures in the eight auxiliary graphic structures is equal. This design helps to reduce the warpage of the embedded PCB board of the anti-warpage chip.

[0067] To prevent excessive stress concentration at a single point, the edges of the auxiliary graphic structure are rounded. After rounding, the edge stress of the auxiliary graphic structure acts over a wider range, and the stress distribution is more uniform, avoiding local warping of the PCB board and thus reducing the overall warping of the PCB board with the anti-warping chip embedded in it.

[0068] Figure 4 This diagram illustrates a chip embedding layer in an anti-warping chip embedded PCB board according to yet another embodiment of the present invention, wherein... Figure 4 for Figure 1 The top view direction.

[0069] The chip embedding layer has six chip embedding areas at its center. These six chip embedding areas are symmetrically distributed vertically and horizontally, forming a rectangular array centered on the center point of the anti-warping chip embedded PCB board.

[0070] Ten auxiliary pattern structures are evenly arranged around the chip embedding layer, and the auxiliary pattern structures are radially distributed around the chip embedding layer.

[0071] Each auxiliary pattern structure has one outer edge, one inner edge, and two adjacent edges. The inner edges of the auxiliary pattern structures located at the four corners of the chip embedding layer are polygonal, while the inner edges of the remaining auxiliary pattern structures are straight lines.

[0072] The outer edges of the auxiliary graphic structures are parallel to the outer contours of the adjacent anti-warping chip embedded PCB board. The inner edges of each auxiliary graphic structure are connected in sequence to form an octagon, and the center point of the octagon coincides with the center point of the anti-warping chip embedded PCB board.

[0073] The gap between any two adjacent auxiliary graphic structures in the ten auxiliary graphic structures is equal. This design helps to reduce the warpage of the embedded PCB board of the anti-warpage chip.

[0074] To prevent excessive stress concentration at a single point, the edges of the auxiliary graphic structure are rounded. After rounding, the edge stress of the auxiliary graphic structure acts over a wider range, and the stress distribution is more uniform, avoiding local warping of the PCB board and thus reducing the overall warping of the PCB board with the anti-warping chip embedded in it.

[0075] It should be noted that the embodiments described or illustrated above are only some embodiments, not all embodiments. In other embodiments, the auxiliary graphic structure can also be other shapes, as long as the stress of the chip embedding layer is evenly distributed; the number of chip embedding areas can also be other, as long as they are evenly distributed around the center point of the chip embedding PCB board to prevent warping. Based on the embodiments in this document, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection.

[0076] The terminology and expressions used above are for descriptive purposes only, and the invention should not be limited to these terms and expressions. The use of these terms and expressions does not mean excluding any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

[0077] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims.

[0078] Similarly, it should be noted that although the present invention has been described with reference to the specific embodiments described above, those skilled in the art should recognize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions can be made without departing from the spirit of the present invention. Therefore, any changes or modifications to the above embodiments within the scope of the essential spirit of the present invention will fall within the scope of the claims of this application.

Claims

1. An anti-warping chip embedded PCB board, characterized in that, include: Chip embedding layer; The central region of the chip embedding layer is provided with at least one chip embedding area; Multiple auxiliary pattern structures are evenly distributed in the peripheral area of ​​the chip embedding layer; Each of the auxiliary graphic structures has an outer edge and an inner edge, the outer edge being parallel to the outer contour of the adjacent anti-warping chip embedded PCB board; The inner sides of multiple auxiliary graphic structures are connected sequentially to form a polygon, and the center of the polygon coincides with the center of the anti-warping chip embedded PCB board. The at least one chip embedding area and the plurality of auxiliary graphic structures are symmetrically distributed about the center of the anti-warping chip embedded PCB board.

2. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The at least one chip embedding area consists of multiple blocks, and the multiple chip embedding areas are symmetrically distributed in a grid pattern with the center of the anti-warping chip embedded PCB board as the center.

3. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The number of chip embedding areas is four, and the four chip embedding areas are arranged in a square array.

4. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The auxiliary graphic structures described herein are evenly distributed radially.

5. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The gaps between any two adjacent auxiliary graphic structures are equal.

6. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The number of auxiliary graphic structures is eight, and the multiple auxiliary graphic structures are distributed in a cross shape. The polygons are regular octagons.

7. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The auxiliary graphic structures of two adjacent blocks are mirror-symmetric about the center line of their adjacent sides.

8. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The inner side is zigzag-shaped.

9. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The edges of the auxiliary graphic structure are rounded.

10. The anti-warping chip embedded PCB board as described in claim 1, characterized in that, The chip embedding layer contains a power chip.

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