Blind hole processing method for flexible circuit board

Abstract

This invention discloses a method for processing blind vias in flexible circuit boards, relating to the field of circuit board processing. The processing method includes laser-forming blind vias with a first copper base on the substrate; laminating dry film on both sides of the substrate; exposing and developing the film to expose the hollowed-out circular holes and blind vias; electroplating to fill the holes; and then removing the film. Alternatively, dry film can be laminating on both sides of the substrate, followed by exposure, development, etching, and film removal to form circuitry. The substrate surface is then subjected to high-temperature pressing with hot-press adhesive, PI, and a second copper base, followed by laser-forming blind vias with circular holes at the bottom. This application's flexible circuit board, by setting electroplated circular holes on the inner first copper base surface as the bottom of the blind vias, can harmonize the color difference on the bottom surface of the blind vias, avoiding the color difference at the bottom of the blind vias affecting the accuracy of subsequent AOI scanning. This allows for further increases in AOI scanner parameters to improve detection accuracy.

Description

Technical Field

[0001] This invention relates to the field of circuit board processing, and more particularly to a method for processing blind vias in flexible circuit boards. Background Technology

[0002] As wearable electronic products rapidly evolve towards thinner, lighter, more flexible, and more reliable designs, the requirements for their supporting printed circuit boards (PCBs) are continuously increasing in terms of bending performance, interlayer conductivity stability, and appearance yield. To meet the high-frequency bending conditions of wearable products, the industry commonly uses high-performance HA copper foil as the base copper layer for four-layer stacked blind via PCBs. The inner core board employs a dot-filling electroplating process to complete the blind via plating, effectively ensuring the conductivity of the blind via walls and structural strength, thus adapting to the mass production needs of multilayer blind via boards.

[0003] However, during the mass production of circuit boards using HA copper foil, it was found that over 600 abnormal reports of outer-layer blind vias appeared on a single PNL after AOI scanning. These abnormal reports were concentrated on the blind via locations laser-processed on the HA copper foil surface, while no abnormal reports were found on the corresponding inner-layer blind via locations. The root cause of these abnormal reports is the optical color difference between HA copper foil and electrolytic copper. In non-overlapping via locations, the bottom surface of the blind via is HA copper, while in overlapping via locations, the bottom surface is electrolytic copper, leading to misidentification by the AOI scanning equipment.

[0004] The current conventional improvement method is to reduce the threshold of AOI scanning and recognition parameters to reduce the number of false alarms. However, this improvement method has great process risks. Lowering the parameters will reduce the accuracy of AOI detection and will easily cause the missed detection of real blind hole defects. It cannot balance the detection accuracy and the effect of good product screening, which seriously affects the accuracy of product quality control and mass production yield, and restricts the large-scale and stable application of HA copper foil in multilayer blind hole boards of highly flexible wearable electronic products. Summary of the Invention

[0005] This invention provides a method for processing blind vias on flexible circuit boards. By setting a circular hole on the inner copper layer of the circuit board that corresponds to the position of the blind via, the bottom of the blind via can be used to avoid abnormal point reporting during AOI scanning due to color difference of the inner copper layer, thereby improving the AOI detection accuracy.

[0006] To address the aforementioned technical problems, the present invention aims to provide a method for processing blind vias in flexible printed circuit boards, comprising the following steps: (1) Prepare a substrate for processing blind holes. The substrate for processing blind holes includes a PI layer and a first bottom copper on both sides. A blind hole is formed by UV laser blind hole forming with the first bottom copper as the bottom. After cleaning, the hole wall is treated by black shadow process and conductive material is adsorbed. (2) Dry film is applied to both sides of the substrate by hot pressing. After exposure, a dot-filling electroplating pattern is formed. The dot-filling electroplating pattern includes setting circular holes at corresponding positions on the substrate surface where blind holes are processed in the next stage. Unexposed areas are removed by development to expose the hollowed-out circular holes and blind holes. Electroplating is then performed to fill the circular holes and blind holes, and then the film is removed. (3) Dry film is applied to both sides of the substrate, and after exposure, a circuit pattern is formed. Unexposed areas are removed by development, and the first base copper not covered by dry film is etched away. Then the film is removed to form the circuit. (4) After browning the substrate surface, hot-press adhesive, PI and second bottom copper are attached in sequence. After high-temperature pressing, UV laser blind holes are used to form blind holes with a circular hole electroplated surface at the bottom.

[0007] In the blind via processing of the flexible circuit board of this application, in order to avoid the color difference between the first and second base copper layers causing too many abnormal reports during AOI scanning of blind vias, a circular hole formed by electroplating is provided on the surface of the inner first base copper layer. The hole corresponds to the position of the blind via on the outer second base copper layer and can serve as the bottom of the blind via on the second base copper layer. When using AOI to scan and detect blind vias, it can effectively avoid too many abnormal reports caused by the color difference at the bottom of the blind via, and the AOI scanner parameters can be improved to enhance the detection accuracy.

[0008] In some implementations, in step (2), the diameter of the circular hole is 3-10 mil larger than the diameter of the blind hole.

[0009] In the blind via processing of the flexible circuit board of this application, a circular hole formed by electroplating is set on the surface of the first bottom copper of the inner layer to serve as the bottom of the blind via on the outer copper layer. This can effectively reduce the excessive number of abnormal reports caused by color difference when scanning blind vias by AOI. The diameter of the circular hole is set to be slightly larger than the diameter of the blind via, so that the circular hole can completely cover the first bottom copper at the bottom of the blind via, avoiding the color difference caused by different copper surfaces at the bottom of the blind via from affecting the AOI scanning accuracy.

[0010] In some implementations, in step (1), the cleaning is performed using plasma cleaning.

[0011] In some embodiments, in step (1), the conductive material includes graphite.

[0012] In some embodiments, in step (1), the shadow etching process employs a micro-etching solution comprising 80-120 g / L sodium persulfate and 15-25 mL / L sulfuric acid, with a shadow line velocity of 1-1.5 m / min, a fixing mode of spraying, and a fixing pressure of 0.6-0.9 kg / cm². 2 The micro-etching pressure is 1.5-2 kg / cm². 2The micro-etching line velocity is 1.8-2.2 m / min, and the micro-etching amount is 0.5-0.8 μm.

[0013] In some embodiments, in step (2), electroplating is performed using direct current with a current density of 1-1.5 asd, copper plating time of 45-55 min, rectifier output ratio of 60%-120%, and spraying at 80-120 Hz.

[0014] In some embodiments, in step (2), the film removal is performed using a film removal solution comprising a hydroxide with an equivalent concentration of 0.3-0.9 N, wherein the hydroxide is potassium hydroxide and / or sodium hydroxide.

[0015] In some embodiments, in step (3), etching is performed using an etching solution comprising copper ions at a concentration of 120-160 g / L, sodium chlorate at a concentration of 20-45 g / L, and hydrochloric acid at an equivalent concentration of 1.7-2.2 N.

[0016] In some embodiments, in step (4), both the first and second base copper foils are HA copper foils.

[0017] Researchers in this application discovered that when HA copper foil is used as the first base copper, the optical color difference between HA copper foil and electrolytic copper causes discrepancies. HA copper foil, formed by physical rolling to alter the copper ingot shape, exhibits fibrous crystals, while electrolytic copper, deposited electrochemically, forms columnar crystals. AOI machines, utilizing high-resolution cameras and special light sources to scan the board surface, exhibit differences in crystal structure between HA copper foil and electrolytic copper. These differences result in variations in the copper content of the bottom surfaces of blind vias in non-overlapping and overlapping locations, leading to discrepancies in AOI imaging and causing excessive AOI detection when scanning HA copper foil. By creating electroplated circular holes on the surface of the inner first base copper layer, corresponding to the blind vias on the outer second base copper layer, these holes can serve as the bottom surfaces of the blind vias on the second base copper layer. This ensures that the bottom surfaces of the blind vias are all electrolytic copper, effectively preventing excessive AOI detection due to color differences at the bottom of the blind vias. Furthermore, the AOI scanner parameters can be improved to enhance detection accuracy.

[0018] In some embodiments, step (4) of the high-temperature pressing includes seven stages, with the first stage having a temperature of 130-150 °C, a time of 0.5-2 min, and a pressure of 5-10 kg / cm². 2 The second stage involves a temperature of 130-150℃, a time of 3-8 minutes, and a pressure of 5-10 kg / cm². 2 The third stage involves a temperature of 180-190 ℃, a time of 3-8 minutes, and a pressure of 40-50 kg / cm². 2 The fourth stage involves a temperature of 180-190 ℃, a time of 80-100 min, and a pressure of 40-50 kg / cm².2 The fifth stage involves a temperature of 180-190 ℃, a time of 20-40 min, and a pressure of 40-50 kg / cm². 2 The sixth stage involves a temperature of 110-130 ℃, a time of 12-18 min, and a pressure of 40-50 kg / cm². 2 The seventh stage involves a temperature of 90-110 ℃, a time of 12-18 min, and a pressure of 5-15 kg / cm². 2 .

[0019] Compared with the prior art, the present invention has the following beneficial effects: In the blind via processing of the flexible circuit board of this application, a circular hole formed by electroplating is provided on the surface of the first bottom copper layer of the inner layer. The hole corresponds to the position of the blind via on the second bottom copper layer of the outer layer. It can serve as the bottom of the blind via on the second bottom copper layer, maintaining the consistency of the copper on the bottom surface of the blind via. This avoids the color difference at the bottom of the blind via affecting the accuracy of subsequent AOI scanning and inspection, and the parameters of the AOI scanner can be increased to improve the inspection accuracy. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a blind via fabrication method for a flexible circuit board according to Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of the substrate prepared after point-filling electroplating in step (4) of Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the substrate structure prepared after the film is removed in step (5) of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the substrate prepared after browning, layout, and lamination in step (7) of Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the substrate fabricated after UV laser blind hole formation in step (8) of Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the substrate prepared after full-plate hole-filling electroplating in step (10) of Embodiment 1 of the present invention; Figure 7 This is the bottom of the blind hole on the substrate surface when using AOI scanning for blind holes in step (7) of Comparative Example 1 of the present invention; Figure 8 This is the substrate cross-section of the flexible circuit board processed in Embodiment 1 of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Any stated value or intermediate value within a stated range, as well as each smaller range between any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0023] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials have been described herein, any methods and materials similar or equivalent to those described herein may be used in the implementation or testing of this invention. All references to this specification are incorporated by way of citation to disclose and describe methods and / or materials associated with those references. In the event of any conflict with any incorporated reference, the content of this specification shall prevail.

[0024] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "top", "bottom", etc., indicating orientation or positional relationship are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0025] To further illustrate the present invention, the following detailed description is provided in conjunction with embodiments, but these should not be construed as limiting the scope of protection of the present invention. The sources of the raw materials used in the embodiments and comparative examples of this application are as follows. Unless otherwise specified, all raw materials used are commercially available, and the same raw materials were used in parallel experiments.

[0026] Example 1 A method for fabricating blind vias in a flexible circuit board, such as Figure 1 As shown, it includes the following steps: (1) Cutting and UV laser blind hole: Use a sheet cutting machine to cut the roll into the required sheets, such as Figure 2As shown, the roll material is a substrate with L2 and L3 copper layers on both sides of the PI layer L2 / 3. The L2 and L3 copper layers are HA copper foil. A high-frequency pulsed ultraviolet laser is used to emit high-frequency pulsed ultraviolet laser onto the substrate to process the required blind holes. The bottom of the blind holes is HA copper foil. Then, plasma cleaning is performed. The plasma machine ionizes the gas to form plasma to clean the substrate and wash away the residue in the blind holes after laser cleaning, achieving the cleaning effect of removing adhesive from the holes. (2) Using graphite as a conductive material, after the substrate L2 and L3 layers undergo a black shadow process, graphite is adsorbed onto the walls of the blind holes, forming a conductive layer on the hole walls. The black shadow process involves reacting a micro-etching solution with the copper layer. The micro-etching solution includes 100 g / L sodium persulfate and 20 mL / L sulfuric acid. The black shadow line speed is 1.2 m / min, the fixing mode is spraying, and the fixing pressure is 0.8 kg / cm². 2 The micro-etching pressure is 2 kg / cm². 2 The micro-etching line speed was 2 m / min, the micro-etching amount was 0.5 μm, the graphite adsorbed on the copper surface was washed away, and the number of points reported after AOI scanning was 32. (3) Dry film preparation of the dot-filling electroplating pattern: The dry film is applied to both sides of the substrate by hot pressing with a film laminating machine. The ultraviolet light of the exposure machine is used to irradiate the dry film to transfer the dot-filling electroplating pattern to the board surface. When designing the dot-filling electroplating pattern, circular holes are designed at the L2 and L3 layers corresponding to the blind holes in L1 and L4 layers. If the blind holes in L1 and 4 layers are at the same position as the blind holes in L2 and L3 layers, the circular holes at the blind hole positions are compensated by 3 mil on one side. If the blind holes in L1 and 4 layers are not overlapping with the blind holes in L2 and L3 layers, circular holes are designed at the L2 and L3 layers corresponding to the blind holes in L1 and L4 layers. The diameter of the circular holes is 6 mil larger than the diameter of the blind holes. After standing for 2 hours, the unexposed positions are washed away with developing solution to expose the blind holes to be electroplated in L2 and L3 layers and the circular holes on the surface. (4) Hole filling electroplating: Electroplating is performed to fill holes. Vertical VCP line electroplating uses DC current. The substrate is used as the negative electrode and the insoluble anode is used as the positive electrode. The rectifier outputs DC current. The copper tank is divided into 7 sections. When the copper tank is conductive, copper ions in the plating solution are deposited on the blind holes and circular holes of the negative electrode substrate to fill them. During the peak period of hole filling, the rectifier output ratio is set to 110%. The hole filling parameters are set as shown in Table 1 below. Copper plating layers are formed on the surfaces of L2 and L3 layers. Table 1 - Electroplating parameter settings for dot filling in step (4) of Example 1 (5) Spot removal: such as Figure 3 As shown, a potassium hydroxide stripping solution is used to remove the dry film. The stripping solution contains potassium hydroxide with an equivalent concentration of 0.5 N. The dry film decomposes in the alkaline solution, thereby peeling it off from the board surface to achieve the stripping effect. (6) Circuit fabrication: The laminator is used to apply dry film to both sides of the substrate by hot pressing. The ultraviolet light of the exposure machine is used to irradiate the dry film to transfer the circuit pattern to the board surface. After standing for 3 hours, the unexposed areas are washed away with developing solution. The copper layer not covered by the dry film is etched away with etching solution. The etching solution is a copper chloride system, which includes copper ions with a concentration of 140 g / L, sodium chlorate with a concentration of 30 g / L, and hydrochloric acid with an equivalent concentration of 2 N. Then, the dry film is expanded and decomposed with stripping solution. The stripping solution is a potassium hydroxide system, which includes potassium hydroxide with an equivalent concentration of 0.5 N to form the required circuit pattern. (7) Browning, layout, and lamination: After horizontal browning micro-etching of the L2 and L3 layers of the substrate to roughen the copper surface, hot-press adhesive is applied to the copper surfaces of the L2 and L3 layers of the substrate. Then, PI and HA copper foils are sequentially applied to the hot-press adhesive surface. Using a press machine, high-temperature lamination is performed for 3 hours. The 7-segment high-temperature lamination parameters are shown in Table 2 below. Figure 4 As shown, pure adhesive and PI are used to form L1 / 2 and L3 / 4 layers, and the base copper is used for L1 and L2 layers; Table 2 - High-temperature pressing parameter settings in step (7) of Example 1 (8) UV laser blind hole: such as Figure 5 As shown, a high-frequency pulsed ultraviolet laser is used to process the required blind holes. The bottom of the blind hole is a circular hole after electroplating. Then, plasma cleaning is performed. The plasma machine ionizes the gas to form plasma, which cleans the substrate and washes away the residue inside the blind hole after laser processing, achieving the cleaning effect of removing adhesive inside the hole. (9) Blind via shadowing production: Graphite is used as the conductive material. After the shadowing process, the graphite is adsorbed onto the non-conductive blind vias after laser etching on the substrate L1 and L4 layers, so that the graphite is adsorbed on the hole walls. The shadowing process uses a micro-etching solution to react with the copper layer. The micro-etching solution includes 100 g / L sodium persulfate and 20 mL / L sulfuric acid. The shadowing line speed is 1.2 m / min, the fixing mode is spray, and the fixing pressure is 0.8 kg / cm². 2 The micro-etching pressure is 2 kg / cm². 2 The micro-etching line speed was 2.5 m / min, the micro-etching amount was 0.5 μm, the graphite adsorbed on the copper surface was washed away, and the number of points reported after AOI scanning was 43. (10) Full-board hole-filling electroplating: such as Figure 6As shown, the substrate is electroplated to fill holes and form a copper plating layer on the entire board. The vertical VCP line electroplating uses DC current, with the substrate as the negative electrode and the insoluble anode as the positive electrode. The rectifier outputs DC current. The copper tank is divided into 7 sections. When the copper tank is conductive, copper ions in the plating solution are deposited on the negative electrode substrate. During the burst period, the rectifier output ratio is set to 120%. The specific electroplating parameter settings are shown in Table 3 below.

[0027] Table 3 - Full-plate hole-filling electroplating parameter settings in step (10) of Example 1 Comparative Example 1 A method for fabricating blind vias on a flexible printed circuit board includes the following steps: (1) Cutting and UV laser blind hole: The roll material is cut into the required sheet material using a sheet cutting machine. The roll material is a substrate with L2 layer bottom copper and L3 layer bottom copper on both sides of the L2 / 3 layer PI. The L2 layer bottom copper and L3 layer bottom copper are HA copper foil. The substrate is processed into the required blind hole by emitting high frequency pulse ultraviolet laser using a laser. The bottom of the blind hole is HA copper foil. Then, plasma cleaning is performed. The plasma machine ionizes the gas to form plasma to clean the substrate and wash away the residue in the blind hole after laser, achieving the cleaning effect of removing glue in the hole. (2) Using graphite as a conductive material, after the substrate L2 and L3 layers undergo a black shadow process, graphite is adsorbed onto the walls of the blind holes, forming a conductive layer on the hole walls. The black shadow process uses a micro-etching solution to react with the copper layer. The micro-etching solution includes 100 g / L sodium persulfate and 20 mL / L sulfuric acid. The black shadow line speed is 1.2 m / min, the fixing mode is spray, and the fixing pressure is 0.8 kg / cm². 2 The micro-etching pressure is 2 kg / cm². 2 The micro-etching line speed was 2.0 m / min, the micro-etching amount was 0.5 μm, the graphite adsorbed on the copper surface was washed away, and the number of points reported after AOI scanning was 31. (3) Hole filling electroplating: Electroplating is performed to fill holes. Vertical VCP line electroplating uses DC current, with the substrate as the negative electrode and the insoluble anode as the positive electrode. The rectifier outputs DC current. The copper tank is divided into 7 sections. When the copper tank is conductive, copper ions in the plating solution are deposited on the blind holes of the negative electrode substrate to fill them. During the peak period of hole filling, the rectifier output ratio is set to 110%. The specific hole filling parameters are set as shown in Table 4 below. Table 4 - Electroplating parameter settings for point filling in step (3) of Comparative Example 1 (4) Circuit fabrication: The laminator is used to apply dry film to both sides of the substrate by hot pressing. The ultraviolet light of the exposure machine is used to irradiate the dry film to transfer the circuit pattern to the board surface. After standing for 3 hours, the unexposed areas are washed away with developing solution. The copper layer not covered by the dry film is etched away with etching solution. The etching solution is a copper chloride system, which includes copper ions with a concentration of 140 g / L, sodium chlorate with a concentration of 30 g / L, and hydrochloric acid with an equivalent concentration of 2 N. Then, the dry film is expanded and decomposed with stripping solution. The stripping solution is a potassium hydroxide system, which includes potassium hydroxide with an equivalent concentration of 0.5 N to form the required circuit pattern. (5) Browning, layout and pressing: After the surface of the L2 and L3 layers of the substrate is browned by micro-etching, the copper surface is roughened. Then, hot press adhesive is attached to the copper surface of the L2 and L3 layers of the substrate. Then, PI and HA copper foil are attached to the hot press adhesive surface in sequence. Using a press machine, after 3 hours of high temperature pressing, the 7-segment high temperature pressing parameters are shown in Table 5 below to form pure adhesive and PI of L1 / 2 and L3 / 4 layers, as well as the bottom copper of L1 and L2 layers. Table 5 - High-temperature pressing parameter settings in step (5) of Comparative Example 1 (6) UV laser blind hole: The laser emits a high-frequency pulsed ultraviolet laser to process the required blind hole. The bottom of the blind hole is HA copper foil. Then, plasma cleaning is performed. The plasma machine ionizes the gas to form plasma to clean the substrate and wash away the residue in the blind hole after laser cleaning, achieving the cleaning effect of removing adhesive from the hole. (7) Blind via shadowing production: Graphite is used as the conductive material. After the shadowing process, the blind vias in the L1 and L4 layers of the substrate are adsorbed onto the non-conductive blind vias after laser etching, so that the via walls are adsorbed with graphite. The shadowing process uses a micro-etching solution to react with the copper layer. The micro-etching solution includes 100 g / L sodium persulfate and 20 mL / L sulfuric acid. The shadowing line speed is 1.2 m / min, the fixing mode is spray, and the fixing pressure is 0.8 kg / cm². 2 The micro-etching pressure is 2 kg / cm². 2 The micro-etching line speed was 2.0 m / min, the micro-etching amount was 0.5 μm, the graphite adsorbed on the copper surface was washed away, and the number of points reported after AOI scanning was 635. (8) Full-board hole-filling electroplating: Electroplating is performed on the substrate to fill holes and form a copper plating layer on the whole board. Vertical VCP line electroplating uses DC current, with the substrate as the negative electrode and the insoluble anode as the positive electrode. The rectifier outputs DC current. The copper tank is divided into 7 sections. When the copper tank is conductive, copper ions in the plating solution are deposited on the negative electrode substrate. During the burst period, the rectifier output ratio is set to 120%. The specific electroplating parameter settings are shown in Table 6 below.

[0028] Table 6 - Full-plate hole-filling electroplating parameter settings in step (8) of Comparative Example 1 Based on the blind via processing methods of flexible circuit boards in Embodiment 1 and Comparative Example 1, it can be seen that during AOI scanning inspection of the laser blind vias in layers L1 and L4, more than 600 blind via anomalies were found on the substrate of Comparative Example 1, while more than 40 blind via anomalies were found on the substrate of Embodiment 1. The number of blind via anomalies in Embodiment 1 is significantly lower than that in Comparative Example 1, proving that the AOI scanner error rate spikes due to color difference when the HA copper foil is used as the via bottom. Figure 8 As shown, in Embodiment 1 of this application, the bottom copper of layers L2 and L3 is made of HA copper foil. The inner layer is plated with patterned holes. If the blind holes of the outer layers L1 and L4 are laser-etched on the surface of the HA copper foil, then a circular hole is designed and electroplated at the corresponding position of the bottom copper of the inner layer. The size of the circular hole is 6 mil larger than the diameter of the blind hole, so that the laser-etched blind holes of the outer layer are on the electroplated layer of the inner layer, rather than on the surface of the HA copper foil. This improves the situation where the optical color difference between the bottom HA copper surface of the blind hole and the electrolytic copper causes abnormal color difference in the AOI scanning of the bottom blind hole during the patterned hole plating process of the multilayer blind hole board.

[0029] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for processing blind vias in a flexible circuit board, characterized in that, Includes the following steps: (1) Prepare a substrate for processing blind holes. The substrate for processing blind holes includes a PI layer and a first bottom copper on both sides. A blind hole is formed by UV laser blind hole forming with the first bottom copper as the bottom. After cleaning, the hole wall is treated by black shadow process and conductive material is adsorbed. (2) Dry film is applied to both sides of the substrate by hot pressing. After exposure, a dot-filling electroplating pattern is formed. The dot-filling electroplating pattern includes setting circular holes at corresponding positions on the substrate surface where blind holes are processed in the next stage. Unexposed areas are removed by development to expose the hollowed-out circular holes and blind holes. Electroplating is then performed to fill the circular holes and blind holes, and then the film is removed. (3) Dry film is applied to both sides of the substrate, and after exposure, a circuit pattern is formed. Unexposed areas are removed by development, and the first base copper not covered by dry film is etched away. Then the film is removed to form the circuit. (4) After browning the substrate surface, hot-press adhesive, PI and second bottom copper are attached in sequence. After high-temperature pressing, UV laser blind holes are used to form blind holes with a circular hole electroplated surface at the bottom.

2. The blind via fabrication method for flexible circuit boards as described in claim 1, characterized in that, In step (2), the diameter of the circular hole is 3-10 mil larger than the diameter of the blind hole.

3. The blind via processing method for flexible circuit boards as described in claim 1, characterized in that, In step (1), the cleaning is performed using plasma cleaning.

4. The blind via fabrication method for flexible circuit boards as described in claim 1, characterized in that, In step (1), the conductive material includes graphite.

5. The blind via processing method for flexible circuit boards as described in claim 1, characterized in that, In step (1), the shadow etching process uses a micro-etching solution comprising 80-120 g / L sodium persulfate and 15-25 mL / L sulfuric acid. The shadow etching line velocity is 1-1.5 m / min, the fixing mode is spraying, and the fixing pressure is 0.6-0.9 kg / cm². 2 The micro-etching pressure is 1.5-2 kg / cm². 2 The micro-etching line velocity is 1.8-2.2 m / min, and the micro-etching amount is 0.5-0.8 μm.

6. The blind via fabrication method for flexible circuit boards as described in claim 1, characterized in that, In step (2), the electroplating uses direct current with a current density of 1-1.5 asd, the copper plating time is 45-55 min, the rectifier output ratio is 60%-120%, and the spraying frequency is 80-120 Hz.

7. The blind via fabrication method for flexible circuit boards as described in claim 1, characterized in that, In step (2), the film removal is performed using a film removal solution, which includes a hydroxide with an equivalent concentration of 0.3-0.9 N, wherein the hydroxide is potassium hydroxide and / or sodium hydroxide.

8. The blind via processing method for flexible circuit boards as described in claim 1, characterized in that, In step (3), etching is performed using an etching solution comprising copper ions at a concentration of 120-160 g / L, sodium chlorate at a concentration of 20-45 g / L, and hydrochloric acid at an equivalent concentration of 1.7-2.2 N.

9. The blind via processing method for flexible circuit boards as described in claim 1, characterized in that, In step (4), both the first and second bottom copper foils are HA copper foils.

10. The blind via processing method for flexible circuit boards as described in claim 1, characterized in that, In step (4), the high-temperature pressing includes seven stages. The first stage has a temperature of 130-150 ℃, a time of 0.5-2 min, and a pressure of 5-10 kg / cm. 2 The second stage involves a temperature of 130-150 ℃, a time of 3-8 minutes, and a pressure of 5-10 kg / cm². 2 The third stage involves a temperature of 180-190 ℃, a time of 3-8 minutes, and a pressure of 40-50 kg / cm². 2 The fourth stage involves a temperature of 180-190 ℃, a time of 80-100 min, and a pressure of 40-50 kg / cm². 2 The fifth stage involves a temperature of 180-190 ℃, a time of 20-40 min, and a pressure of 40-50 kg / cm². 2 The sixth stage involves a temperature of 110-130 ℃, a time of 12-18 min, and a pressure of 40-50 kg / cm². 2 The seventh stage involves a temperature of 90-110 ℃, a time of 12-18 min, and a pressure of 5-15 kg / cm². 2 .

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