Semiconductor structure and method of forming, semiconductor device and memory system

Abstract

This disclosure provides a semiconductor structure and its formation method, a semiconductor device, and a memory system, relating to the field of memory technology. The semiconductor structure houses a memory cell array within a first semiconductor structure, and a first conductive pad and a second conductive pad are provided on the surface of the semiconductor structure. The memory cell array is connected to the first and second conductive pads respectively through at least different contact structures that at least partially penetrate the semiconductor structure along a first direction perpendicular to the surface of the semiconductor structure. The second conductive pad is a conductive pad for power supply with at least one wire connected to its surface. By using a first conductive pad with at least one shape selected from polygons, circles, or ellipses with more than four sides, and a quadrilateral second conductive pad, the area of ​​the first conductive pad is reduced to decrease the parasitic capacitance between the first conductive pad and the substrate, while maintaining the area of ​​the second conductive pad to increase the stability of the external power supply.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a semiconductor structure and its formation method, a semiconductor device, and a memory system. Background Technology

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. The process and manufacturing technology of planar memory cells have become challenging and costly, leading to the emergence of three-dimensional semiconductor structures. A three-dimensional semiconductor structure can include a memory cell array and a peripheral circuit structure. The peripheral circuit structure is used to control the signals input to the memory cell array and the signals output by the memory cell array.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure and a method for forming it, a semiconductor device, and a memory system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a first semiconductor structure including a memory cell array; a first conductive pad and a second conductive pad disposed on the surface of the semiconductor structure, the memory cell array being connected to the first conductive pad and the second conductive pad respectively through at least different contact structures, the contact structures at least partially penetrating the semiconductor structure along a first direction perpendicular to the surface of the semiconductor structure, wherein: the first conductive pad is at least one of a polygon, a circle, or an ellipse, the polygon having more than 4 sides; the surface of the second conductive pad is connected to at least one wire, the second conductive pad being a quadrilateral.

[0007] According to one embodiment of the present disclosure, the first conductive pad and the second conductive pad each have a first inner diameter and a second inner diameter that are perpendicular to each other, wherein: the length of the first inner diameter of the first conductive pad is equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad is equal to the length of the second inner diameter of the second conductive pad.

[0008] According to one embodiment of this disclosure, the area of ​​the first conductive pad is smaller than the area of ​​the second conductive pad.

[0009] According to one embodiment of the present disclosure, the semiconductor structure further includes a second semiconductor structure, the first surface of the second semiconductor structure being connected to the first semiconductor structure; the first conductive pad and the second conductive pad are both disposed on the second surface of the second semiconductor structure.

[0010] According to one embodiment of the present disclosure, the second semiconductor structure includes a peripheral circuit structure, which is connected to the memory cell array;

[0011] The contact structure includes a first through-substrate contact structure, which penetrates the substrate of the peripheral circuit structure. The peripheral circuit structure is connected to a corresponding first conductive pad or a second conductive pad at least through the first through-substrate contact structure.

[0012] According to one embodiment of the present disclosure, the contact structure further includes a second through-substrate contact structure, which penetrates the substrate of the peripheral circuit structure, and the memory cell array is connected to the corresponding first conductive pad or second conductive pad at least through the second through-substrate contact structure.

[0013] According to one embodiment of this disclosure, the semiconductor structure further includes a connection structure, and the contact structure is connected to a corresponding first conductive pad or a second conductive pad through the connection structure.

[0014] According to one embodiment of this disclosure, the semiconductor structure further includes a passivation layer disposed around the first conductive pad and / or the second conductive pad, wherein two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer are the first inner diameter and the second inner diameter, respectively.

[0015] According to one embodiment of this disclosure, the first conductive pad is a regular polygon.

[0016] According to one embodiment of this disclosure, the first conductive pad is octagonal or hexagonal.

[0017] According to one embodiment of this disclosure, the second conductive pad is rectangular, and the length and width of the second conductive pad are the first inner diameter and the second inner diameter, respectively.

[0018] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a first semiconductor structure, the first semiconductor structure including a memory cell array; forming a second semiconductor structure on a substrate, the second semiconductor structure including a peripheral circuit structure; bonding a first surface of the second semiconductor structure to the first semiconductor structure to connect the peripheral circuit structure to the memory cell array; forming a contact structure penetrating the substrate along a first direction, the first direction being perpendicular to the first surface; forming a first conductive pad and a second conductive pad respectively connected to different contact structures on a second surface of the second semiconductor structure to connect the memory cell array to the first conductive pad and the second conductive pad, the second surface being opposite to the first surface, wherein the first conductive pad is at least one of a polygon, a circle, or an ellipse, the polygon having more than 4 sides, and the second conductive pad being a quadrilateral; and forming at least one wire connected to the surface of the second conductive pad.

[0019] According to one embodiment of the present disclosure, the first conductive pad and the second conductive pad each have a first inner diameter and a second inner diameter that are perpendicular to each other, wherein: the length of the first inner diameter of the first conductive pad is equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad is equal to the length of the second inner diameter of the second conductive pad.

[0020] According to one embodiment of this disclosure, the area of ​​the first conductive pad is smaller than the area of ​​the second conductive pad.

[0021] According to one embodiment of the present disclosure, forming a second semiconductor structure on a substrate includes: forming the peripheral circuit structure on a first surface of the substrate; and forming a first connection structure connected to the peripheral circuit structure on a second surface of the substrate.

[0022] According to one embodiment of the present disclosure, the contact structure includes a first through-substrate contact structure; forming a contact structure through the substrate along a first direction includes: forming a first through-substrate contact structure through the substrate, wherein the first through-substrate contact structure is connected to the first connection structure; forming a first conductive pad and a second conductive pad respectively connected to different contact structures on a second surface of the second semiconductor structure includes: forming a first conductive pad or a second conductive pad connected to the first through-substrate contact structure on a second surface of the second semiconductor structure.

[0023] According to an embodiment of the present disclosure, the contact structure further includes a second through-substrate contact structure; forming a second semiconductor structure on the substrate further includes: forming a second connection structure connected to the memory cell array on a first surface of the substrate; the method further includes: forming a second through-substrate contact structure through the substrate, the second through-substrate contact structure being connected to the second connection structure; forming a first conductive pad and a second conductive pad respectively connected to different contact structures on a second surface of the second semiconductor structure, including: forming a first conductive pad or a second conductive pad that contacts the second through-substrate contact structure on the second surface of the second semiconductor structure.

[0024] According to one embodiment of this disclosure, the method further includes: forming a passivation layer on the surface of the first conductive pad and / or the second conductive pad; removing at least a portion of the passivation layer to expose a portion of the surface of the first conductive pad and / or the second conductive pad, wherein the two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer are the first inner diameter and the second inner diameter, respectively.

[0025] According to one embodiment of this disclosure, the first conductive pad is a regular polygon.

[0026] According to one embodiment of this disclosure, the first conductive pad is octagonal or hexagonal.

[0027] According to one embodiment of this disclosure, the second conductive pad is rectangular, and the length and width of the second conductive pad are the first inner diameter and the second inner diameter, respectively.

[0028] According to another aspect of this disclosure, a semiconductor device is provided, comprising any of the semiconductor structures described above.

[0029] According to another aspect of this disclosure, a storage system is provided, including a semiconductor device as described above and a controller coupled to said semiconductor device.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0031] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0032] Figure 1 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0033] Figure 2A A block diagram of a memory system is shown as an example.

[0034] Figure 2B A block diagram of another memory system is shown as an example.

[0035] Figure 3 A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment.

[0036] Figure 4A A schematic diagram of the shape of a first conductive pad is shown according to an exemplary embodiment.

[0037] Figure 4B A schematic diagram of the shape of another first conductive pad is shown according to an exemplary embodiment.

[0038] Figure 4C A schematic diagram of the shape of yet another first conductive pad is shown according to an exemplary embodiment.

[0039] Figure 4D A schematic diagram of the shape of another first conductive pad is shown according to an exemplary embodiment.

[0040] Figure 5 A schematic diagram of the shape of a second conductive pad is shown according to an exemplary embodiment.

[0041] Figure 6 A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment.

[0042] Figure 7 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0043] Figure 8 It shows Figure 7 The step S704 shown is a schematic diagram of the processing procedure in one embodiment.

[0044] Figure 9 It shows Figure 7 The steps S708 and S710 shown are schematic diagrams of the processing procedure in one embodiment.

[0045] Figure 10 It shows Figure 7 The steps S704, S708 and S710 shown are schematic diagrams of the processing in one embodiment.

[0046] Figure 11 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment.

[0047] Figure 12 A schematic cross-sectional view of a substrate of a first semiconductor structure is shown according to an exemplary embodiment.

[0048] Figure 13 A schematic cross-sectional view of a first semiconductor structure formed on a substrate is shown according to an exemplary embodiment.

[0049] Figure 14 A schematic cross-sectional view of a substrate of a second semiconductor structure is shown according to an exemplary embodiment.

[0050] Figure 15 A cross-sectional schematic diagram of a peripheral circuit structure formed on a substrate is shown according to an exemplary embodiment.

[0051] Figure 16 A schematic cross-sectional view of a bonding layer formed on a first semiconductor structure and a second semiconductor structure is shown according to an exemplary embodiment.

[0052] Figure 17 A cross-sectional schematic diagram of a bonded first semiconductor structure and a second semiconductor structure is shown according to an exemplary embodiment.

[0053] Figure 18 A schematic cross-sectional view of a conductive pad formed on the surface of a second semiconductor structure is shown according to an exemplary embodiment. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0055] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0056] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0057] It should be readily understood that the meanings of “on top of,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on top of” means not only “directly on something,” but also includes being on something with an intermediate feature or layer between them, and that “on top of” or “above” means not only being on or above something, but also includes the meaning of having no intermediate feature or layer between them (i.e., being directly on something).

[0058] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used in this disclosure to describe the relationship of one component or feature to one or more other components or features, as illustrated in the accompanying drawings. In addition to the directions depicted in the drawings, these spatial relative terms are intended to cover different orientations or directions of the device in use or operation. The device may be oriented in other ways (e.g., by a 90-degree rotation or in other directions) and can be interpreted accordingly using the spatially related descriptions used in this disclosure.

[0059] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0060] In this disclosure, the term "layer" refers to a portion of material having a thickness in a region. A layer may extend over the entire lower or upper layer structure, or its extent may be less than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes between the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0061] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0062] Figure 1 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0063] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to or receive data from the memory 104.

[0064] Memory 104 can be non-volatile memory, volatile memory, etc. Non-volatile memory can be NAND flash memory (e.g., 3D NAND flash memory). Volatile memory can be Dynamic Random Access Memory (DRAM).

[0065] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108.

[0066] In some embodiments, the memory controller 106 is configured to send commands to the memory 104 to cause the memory 104 to perform the memory operation methods provided in the embodiments of this disclosure.

[0067] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0068] In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0069] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0070] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0071] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0072] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a connector for connecting the memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0073] Figure 2B A block diagram of another memory system is shown as an example. Figure 2B As shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The multiple memories 104 may include, for example, multiple NAND flash memories 1042 and one DRAM 1044. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0074] Figure 3 A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment. The semiconductor structure provided in this disclosure can be a semiconductor device, for example, it can be... Figures 1 to 2B DRAM memory in [the context]. For example... Figure 3 The semiconductor structure shown may include a first semiconductor structure 302, and a memory cell array 3022 disposed in the first semiconductor structure 302.

[0075] Reference Figure 3 The first semiconductor structure 302 may include a memory cell array 3022 disposed on a substrate 3021. The memory cell array 3022 may include DRAM cells consisting of pairs of transistors and capacitors. Figure 3(Not shown in the image) An array is formed on the plane formed by the X and Z directions. Word lines (WL) and bit lines (BL) intersect on the plane formed by the X and Z directions. DRAM cells are formed at the intersection of WL and BL.

[0076] like Figure 3 The semiconductor structure shown may further include a first conductive pad 30442 and a second conductive pad 30444 disposed on the surface of the semiconductor structure. The memory cell array 3022 is constructed at least through different contact structures (e.g., Figure 3 The first through-substrate contact structure 3062 and the second through-substrate contact structure 3064 are respectively connected to the first conductive pad 30442 and the second conductive pad 30444, and the contact structures are along a first direction perpendicular to the surface of the semiconductor structure (e.g., Figure 3 The conductive pads 30442 and 30444 can both penetrate at least partially through the semiconductor structure in the Y direction. Both the first conductive pad 30442 and the second conductive pad 30444 can connect to internal connection structures within the semiconductor structure (e.g., including the first connection structure 3046). Figure 15 The second connection structure 1502, etc., is electrically connected, and the connection structure is then electrically connected to the contact structure, thereby electrically connecting the peripheral circuit structure 3042 and / or the memory cell array 3022 to the corresponding first conductive pad 30442 or second conductive pad 30444. The connection structure can be, for example, at least a portion of a metal layer. Both the first conductive pad 30442 and the second conductive pad 30444 can be made of metallic materials, such as one or more of copper, nickel, aluminum, silver, gold, etc.

[0077] The first conductive pad 30442 can be a conductive pad used for transmitting data from the outside to the memory cell array 3022 via the peripheral circuit structure 3042 and / or for transmitting data in the memory cell array 3022 to the outside via the peripheral circuit structure 3042. For example, it can be a conductive pad for transmitting clock signals, a conductive pad for transmitting data queues, a conductive pad for transmitting commands and addresses, or a conductive pad for transmitting signals that implement functions such as data masking and data bus inversion. The surface of the second conductive pad 30444 (i.e., the portion exposed on the surface of the semiconductor structure) is connected to at least one wire. Figure 3 (Not shown in the image), at least one wire extends from the metal surface of the second conductive pad 30444 into the interior of the semiconductor structure, and can extend to connect with the peripheral circuit structure 3042 and / or the memory cell array 3022 to provide power to the peripheral circuit structure 3042 and / or the memory cell array 3022. That is, the second conductive pad 30444 can be a conductive pad for external power supply to power the semiconductor structure.

[0078] The first conductive pad 30442 can be at least one of a polygon, a circle, or an ellipse with more than four sides. An exemplary embodiment of the shape of the first conductive pad 30442 can be found in [reference needed]. Figures 4A to 4D The second conductive pad 30444 can be quadrilateral.

[0079] According to the semiconductor structure provided in the embodiments of this disclosure, a memory cell array is disposed in a first semiconductor structure, and a first conductive pad and a second conductive pad are provided on the surface of the semiconductor structure. The memory cell array is connected to the first conductive pad and the second conductive pad respectively through at least different contact structures that at least partially penetrate the semiconductor structure along a first direction perpendicular to the surface of the semiconductor structure. The first conductive pad is used for data transmission, and the second conductive pad is a conductive pad for power supply with at least one wire connected to its surface. By using a first conductive pad with at least one shape among polygons, circles, or ellipses with more than 4 sides, and a quadrilateral second conductive pad, the area of ​​the first conductive pad can be reduced to reduce the parasitic capacitance between the first conductive pad and the substrate while ensuring the package size of the conductive pad, and the area of ​​the second conductive pad can be maintained to increase the stability of the external power supply.

[0080] In some embodiments, the semiconductor structure may further include a second semiconductor structure, in which a peripheral circuit structure is disposed. The first semiconductor structure and the second semiconductor structure can be bonded together via a bonding layer, thereby electrically connecting the memory cell array to the peripheral circuit structure. (Continuing to refer to...) Figure 3 The first semiconductor structure 302 and the second semiconductor structure 304 can be along Figure 3 The memory is formed by stacking the components together in the Y direction.

[0081] like Figure 3 As shown, the second semiconductor structure 304 may include a peripheral circuit structure 3042 disposed on the substrate 3041, which is connected to the memory cell array 3022. The peripheral circuit structure 3042 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating operation of the memory cell array 3022, and in some embodiments may include, for example, row decoder / word line (WL) drivers, page buffers / sensor amplifiers, column decoder / bit line (BL) drivers, address registers, control logic units, and input / output (I / O) circuitry, etc.

[0082] The first surface 30482 of the second semiconductor structure 304 is connected to the first semiconductor structure 302. The first conductive pad 30442 and the second conductive pad 30444 are both disposed on the second surface 30484 of the second semiconductor structure 304. The first surface 30482 and the second surface 30484 of the second semiconductor structure 304 are two opposing surfaces. The first surface 30482 can be, for example, the front side of the second semiconductor structure 304, and the second surface 30484 can be, for example, the back side of the second semiconductor structure 304.

[0083] The bonding layer 308 between the first semiconductor structure 302 and the second semiconductor structure 304 can be a bonding layer between two semiconductor structures formed by any suitable bonding technique described in detail below, such as one or more of hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding and eutectic bonding.

[0084] In some embodiments, the contact structure may include a through-substrate contact structure that penetrates the substrate of the peripheral circuit structure along a first direction. Figure 3 Two through-substrate contact structures are illustrated: a first through-substrate contact structure 3062 and a second through-substrate contact structure 3064. The peripheral circuit structure 3042 is connected to the corresponding first conductive pad 30442 or second conductive pad 30444 at least through the first through-substrate contact structure 3062. For example, the peripheral circuit structure 3042 is connected to the corresponding first conductive pad 30442 or second conductive pad 30444 through a metal layer in the second semiconductor structure 304 and the first through-substrate contact structure 3062. The memory cell array 3022 is connected to the corresponding first conductive pad 30442 or second conductive pad 30444 at least through the second through-substrate contact structure 3064. For example, the memory cell array 3022 is connected to the corresponding first conductive pad 30442 or second conductive pad 30444 sequentially through a metal layer in the first semiconductor structure 302, the second through-substrate contact structure 3064, and a metal layer in the second semiconductor structure 304.

[0085] According to the semiconductor structure provided in the embodiments of this disclosure, the semiconductor structure has a memory cell array disposed in a first semiconductor structure and a peripheral circuit structure disposed in a second semiconductor structure. The first conductive pad and the second conductive pad, which are connected to the memory cell array and / or the peripheral circuit structure, are disposed on the opposite side of the surface of the second semiconductor structure connected to the first semiconductor structure. Thus, the process of connecting the BL in the memory cell array to the peripheral circuit structure (e.g., the sense amplifier circuit) does not need to pass through the power supply metal layer, which reduces the winding length from BL to the sense amplifier circuit. On the other hand, it reduces the crosstalk between the power supply metal layer and other signal lines to the connection from BL to the sense amplifier circuit, and reduces the impact on the sense tolerance during memory operation.

[0086] In this embodiment of the present disclosure, when the semiconductor structure is formed by bonding the first semiconductor structure and the second semiconductor structure, and the conductive pad is disposed on the surface of the second semiconductor structure, the conductive pad is relatively close to the substrate of the second semiconductor structure (e.g., Figure 3 The distance h shown in the figure, especially for the first conductive pad used for data transmission, can generate parasitic capacitance that may affect the quality of data transmission. By using a first conductive pad with at least one shape among polygons, circles, or ellipses with more than 4 sides, the area of ​​the first conductive pad can be reduced while ensuring the package size of the conductive pad, thereby reducing the parasitic capacitance between the first conductive pad and the substrate and improving the quality of data transmission.

[0087] In this embodiment of the disclosure, Figure 3 The example described uses a first semiconductor structure and a second semiconductor structure bonded together, with the first and second conductive pads disposed on opposite surfaces of the surfaces connecting the second and first semiconductor structures. However, this is not a limitation. In other embodiments, peripheral circuitry may be disposed within the first semiconductor structure, and the first and second conductive pads may be disposed on the surface of the first semiconductor structure away from the substrate. In other embodiments, when the semiconductor structure includes both a first and a second semiconductor structure, the first and second conductive pads may also be disposed on the surface of the first semiconductor structure away from the substrate. Those skilled in the art can implement connections between the first and second conductive pads and the memory cell array and peripheral circuitry in these embodiments.

[0088] Figures 4A to 4D Examples of implementations of first conductive pads of different shapes are shown.

[0089] Figure 4A A schematic diagram of the shape of a first conductive pad is shown according to an exemplary embodiment. Figure 4A As shown, the first conductive pad 30442 can be octagonal.

[0090] Figure 4B A schematic diagram of the shape of another first conductive pad is shown according to an exemplary embodiment. For example... Figure 4B As shown, the first conductive pad 30442' can be a hexagon.

[0091] In some embodiments, the first conductive pad can be a regular polygon, for example... Figure 4A The center can be a regular octagon, for example... Figure 4B The center can be a regular hexagon.

[0092] Figure 4C A schematic diagram of the shape of yet another first conductive pad is shown according to an exemplary embodiment. For example... Figure 4C As shown, the first conductive pad 30442” can be circular.

[0093] Figure 4D A schematic diagram of the shape of another first conductive pad is shown according to an exemplary embodiment. Figure 4D As shown, the first conductive pad 30442”' can be elliptical.

[0094] Figure 5 A schematic diagram of the shape of a second conductive pad is shown according to an exemplary embodiment. Figure 5 As shown, the second conductive pad 30444 can be rectangular.

[0095] In some embodiments, both the first conductive pad and the second conductive pad have a first inner diameter and a second inner diameter that are perpendicular to each other. The inner diameter of the first conductive pad and the second conductive pad can be a line segment on the exposed conductive surface that passes through the center and has its two endpoints on the side, and the first inner diameter and the second inner diameter can be two mutually perpendicular lines therein.

[0096] Reference Figures 4A to 5 ,exist Figure 4A In the octagonal first conductive pad 30442, the first inner diameter a and the second inner diameter b are mutually perpendicular line segments passing through its center O and with their endpoints on opposite sides. Figure 4B In the diagram, for the first conductive pad 30442' of the hexagon, the first inner diameter a' and the second inner diameter b' are mutually perpendicular line segments passing through its center O' and with their endpoints on opposite sides. Figure 4C In the diagram, for the circular first conductive pad 30442", the first inner diameter a” is a diameter (passing through its center O”), and the second inner diameter ( Figure 4C (Not shown in the diagram) is another diameter perpendicular to "a". Figure 4D In the above, for the elliptical first conductive pad 30442”', the first inner diameter a”' can be the major axis (passing through its center O”'), and the second inner diameter b”' can be the minor axis. Figure 5 In the case of the rectangular second conductive pad 30444, the first inner diameter a1 and the second inner diameter b1 can be the length and width of the rectangle, respectively.

[0097] In some embodiments, when the first conductive pad is at least one of a polygon, circle, or ellipse with more than four sides, and the second conductive pad is a quadrilateral, the area of ​​the first conductive pad can be smaller than the area of ​​the second conductive pad by setting the length of the first inner diameter of the first conductive pad to be equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad to be equal to the length of the second inner diameter of the second conductive pad. In this configuration, the lengths of the first and second inner diameters can be greater than or equal to the minimum dimensions required by the packaging process.

[0098] In some embodiments, the minimum size required for the packaging process corresponding to the first inner diameter may be the same as or different from the minimum size required for the packaging process corresponding to the second inner diameter, and this disclosure does not impose any restrictions.

[0099] According to the semiconductor structure provided in the embodiments of this disclosure, when the first conductive pad is at least one of a polygon, a circle, or an ellipse with more than 4 sides, and the second conductive pad is a quadrilateral, by setting the length of the first inner diameter of the first conductive pad to be equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad to be equal to the length of the second inner diameter of the second conductive pad, the area of ​​the first conductive pad can be smaller than the area of ​​the second conductive pad while meeting the size requirements of the first and second conductive pads for packaging. This reduces the parasitic capacitance between the first conductive pad and the substrate, and also reduces the parasitic capacitance between the first conductive pad and other metal layers in the semiconductor structure.

[0100] In some embodiments, a passivation layer may also be provided around the surface of the first conductive pad and / or the second conductive pad to prevent oxidation at the edges of the conductive pad surfaces. The two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer may be a first inner diameter and a second inner diameter, respectively. In some embodiments, the passivation layer may include an insulating layer, a polymer layer, etc. The insulating layer may be a nitride layer, such as a metal nitride layer, and the polymer layer may be a nanopolymer, which can prevent scratches or damage to the edges of the conductive pad surfaces. (See again) Figures 4A to 5 ,exist Figure 4A In the first conductive pad 30442, which is octagonal, the passivation layer 30441 has an inner and outer octagonal ring structure. Figure 4B In the first conductive pad 30442', which is hexagonal, the passivation layer 30441' is a ring structure with both inner and outer hexagonal shapes. Figure 4C In the first conductive pad 30442", which is circular, its passivation layer 30441" is an annular ring. Figure 4D In the first elliptical conductive pad 30442”', its passivation layer 30441”' is an elliptical ring. Figure 5 In the middle, for the rectangular second conductive pad 30444, its passivation layer 30443 is a ring structure with both the inner and outer rectangles.

[0101] Figure 6 A schematic cross-sectional view of another semiconductor structure is shown according to an exemplary embodiment. The semiconductor structure provided in this disclosure can be a semiconductor device, for example, it can be... Figures 1 to 2B NAND memory in the system.

[0102] like Figure 6 The semiconductor structure shown may include a first semiconductor structure 302, and a memory cell array 3022' disposed in the first semiconductor structure 302. The memory cell array 3022' may be arranged in a vertical direction (e.g., Figure 6 The stacked structure (in the Y direction) provides the gate conductive layer of the transistor (including the select gate and WL), using a direction perpendicular to the stacking direction (e.g., in the Y direction). Figure 6 A channel structure (in the Y direction) penetrating the stacked structure provides the channel layer for transistors and also forms bit lines to connect the channel structure to the memory cells formed by the gate conductive layer. (See reference...) Figure 6 The gate conductive layer can extend on planes formed in the X and Z directions. The memory cell array 3022' can be formed in certain regions on the substrate 3021. In some embodiments, the memory cell array 3022' can also be formed as a plurality of memory blocks, which can be grouped into pages.

[0103] Figure 6 Zhongyu Figure 3 The same identifier can represent the same meaning. It will be understood by those skilled in the art that... Figure 6 Zhongyu Figure 3 The structures representing the same meaning can be adjusted in terms of connection, process, and number of elements according to the differences in actual operation between DRAM and NAND memory, and are not limited to being exactly the same.

[0104] Figure 7 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 7 The methods shown may include, for example, forming Figure 3 or Figure 6 The overall steps of the semiconductor structure are shown. (Refer to...) Figure 7 The method 70 provided in this embodiment may include the following steps S702 to S712. Figures 12 to 18 It shows Figure 3 The diagram shows cross-sectional views of some process nodes during the formation of the semiconductor structure. Figure 7 (as well as Figures 8 to 11 The formation method described in this paper will be illustrated in conjunction with these cross-sectional diagrams.

[0105] In step S702, a first semiconductor structure is formed, the first semiconductor structure including a memory cell array.

[0106] Figure 12 A schematic cross-sectional view of a substrate for a first semiconductor structure is shown according to an exemplary embodiment. Figure 12As shown, a substrate 3021 can be provided first. The substrate 3021 can be a single-layer substrate or a multi-layer substrate, such as a single-layer substrate of monocrystalline silicon, a single-layer substrate of polycrystalline silicon, or a multi-layer substrate of polycrystalline silicon and metal.

[0107] Figure 13 A schematic cross-sectional view of a first semiconductor structure formed on a substrate is shown according to an exemplary embodiment. For Figure 3 The semiconductor structure shown can be formed by forming transistors, bit line contact modules and bit lines, memory node contact modules, capacitors and other structures on the substrate 3021 during the process of forming the first semiconductor structure, thereby forming a DRAM memory cell array 3022 on the substrate 3021.

[0108] In other embodiments, for Figure 6 The semiconductor structure shown can be formed by stacking structures, channel structures, etc. on the corresponding substrate during the formation of the first semiconductor structure, thereby forming a NAND memory cell array on the substrate.

[0109] In step S704, a second semiconductor structure is formed on the substrate, the second semiconductor structure including a peripheral circuit structure.

[0110] Figure 14 A schematic cross-sectional view of a substrate for a second semiconductor structure is shown according to an exemplary embodiment. Figure 14 As shown, substrate 3041 can be provided first. Substrate 3041 can also be a single-layer substrate or a multi-layer substrate, such as a single-layer substrate of monocrystalline silicon, a single-layer substrate of polycrystalline silicon, or a multi-layer substrate of polycrystalline silicon and metal.

[0111] Figure 15 A cross-sectional schematic diagram of a peripheral circuit structure formed on a substrate is shown according to an exemplary embodiment. In some embodiments, the peripheral circuit structure may be formed on substrate 3041, for example, a plurality of peripheral circuit modules (3042 being an example of one of the peripheral circuit modules) may be formed on substrate 3041, and then a connection structure 1502 may be formed to achieve interconnection between the peripheral circuit modules.

[0112] In step S706, the first surface of the second semiconductor structure is bonded to the first semiconductor structure to connect the peripheral circuit structure to the memory cell array.

[0113] In some embodiments, bonding layers may be formed on the surfaces of the first semiconductor structure and the second semiconductor structure that are away from the substrate (e.g., the front side), so that the first semiconductor structure and the second semiconductor structure are bonded together through the bonding layers. Figure 16 A schematic cross-sectional view of a bonding layer formed on a first semiconductor structure and a second semiconductor structure is shown according to an exemplary embodiment. Figure 16As shown, bonding layers 308 can be formed on the surface of the first semiconductor structure 302 away from the substrate 3021 and on the surface of the second semiconductor structure 304 away from the substrate 3041, respectively. Bonding layer 308 can be an interconnect layer, which may include, for example, one or more bonding structures embedded in a dielectric layer. Bonding structures may include contacts, single / multilayer vias, wires, plugs, pads, and / or any other suitable conductive structure made of a conductive material including tungsten, cobalt, copper, aluminum, doped silicon, silicide, or any combination thereof. The dielectric layer may include a dielectric material including silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0114] In some embodiments, one or more bonding structures of the first semiconductor structure and one or more bonding structures of the second semiconductor structure may contact each other at the interface of the bonding layer to achieve electrical connection. Figure 17 A cross-sectional schematic diagram of a bonded first semiconductor structure and a second semiconductor structure is shown according to an exemplary embodiment. Figure 17 As shown, the bonding structure 1402 of the first semiconductor structure 302 and the bonding structure 1404 of the second semiconductor structure 304 are in contact at the interface of the bonding layer 308 to achieve electrical connection, thereby connecting the memory cell array 3022 and the peripheral circuit structure 3042.

[0115] In step S708, a contact structure is formed that penetrates the substrate along a first direction, the first direction being perpendicular to the first surface.

[0116] In some embodiments, after the first semiconductor structure and the second semiconductor structure are bonded, the substrate of the second semiconductor structure can be thinned to a certain thickness for subsequent manufacturing processes. For example, see reference to... Figure 16 and Figure 17 , Figure 17 The substrate of the second semiconductor structure 304 is thinner than the substrate of the first semiconductor structure 302.

[0117] Continue to refer to Figure 17 After thinning the substrate 3041 of the second semiconductor structure, a first through substrate contact structure 3062 and a second through substrate contact structure 3064 that penetrate the substrate 3041 along the Y direction can be formed, thereby leading out the peripheral circuit structure 3042 through the first through substrate contact structure 3062 and the second through substrate contact structure 3064.

[0118] In step S710, a first conductive pad and a second conductive pad are formed on the second surface of the second semiconductor structure, respectively connected to different contact structures, to connect the memory cell array with the first conductive pad and the second conductive pad. The second surface is opposite to the first surface. The first conductive pad is at least one of a polygon, a circle or an ellipse, the polygon has more than 4 sides, and the second conductive pad is a quadrilateral.

[0119] In some embodiments, after forming a contact structure that extends through the substrate in a first direction, a wiring layer including a connection structure may be formed on the exposed surface of the substrate of the second semiconductor structure.

[0120] Figure 18 A schematic cross-sectional view of a conductive pad formed on the surface of a second semiconductor structure is shown according to an exemplary embodiment. Figure 18 As shown, it is possible to Figure 17 A wiring layer including a first connection structure 3046 is formed on the surface of the substrate 3041 of the second semiconductor structure 304, and then a first conductive pad 30442 and a second conductive pad 30444 are formed on the second surface 30484 of the second semiconductor structure 304 outside the wiring layer.

[0121] In step S712, at least one wire is formed that is connected to the surface of the second conductive pad.

[0122] In some embodiments, during the formation of the wiring layer of the second semiconductor structure, at least one wire connected to the peripheral circuit structure and / or memory cell array may be extended to the second surface of the second semiconductor structure, thereby connecting the wire to the exposed surface of the second conductive pad to provide power to the peripheral circuit structure 3042 and / or memory cell array 3022.

[0123] Figure 8 It shows Figure 7 The diagram shown illustrates step S704 in one embodiment. Figure 8 As shown in the present embodiment, step S704 may further include step S802. Figure 8 Steps S802 and S804 describe the relevant steps in the process of forming the second semiconductor structure. The execution order can be designed according to actual needs, and this disclosure does not impose any restrictions.

[0124] Step S802: Form a peripheral circuit structure on the first surface of the substrate.

[0125] For example, continue to refer to Figure 15 A peripheral circuit structure 3042 can be formed on the first surface 30412 of the substrate 3041.

[0126] During the process of forming the second semiconductor structure in step S704, a structure connecting the peripheral circuit structure to other structures can also be formed. For example, step S804 may be included to form a first connection structure connected to the peripheral circuit structure on the second surface of the substrate.

[0127] For example, continue to refer to Figure 18 , can Figure 17 A wiring layer including a first interconnect structure 3046 is formed on the second surface 30414 of the (thinned) substrate 3041 of the second semiconductor structure 304. Step S804 may be performed, for example, between steps S708 and S710.

[0128] Figure 9 It shows Figure 7 The diagram illustrates steps S708 and S710 in one embodiment. Figure 9 As shown in the present embodiment, step S708 may further include step S902, and step S710 may further include step S904. Figure 9 Steps S902 and S904 illustrate the formation process of connecting the first conductive pad or the second conductive pad to the peripheral circuit structure through the first through-substrate contact structure. The execution order can be designed according to actual needs, and this disclosure does not limit it.

[0129] Step S902: A first through-substrate contact structure is formed, which penetrates the substrate, and the first through-substrate contact structure is connected to the first connection structure.

[0130] Continue to refer to Figure 18 After forming the first through-substrate contact structure 3062 that penetrates the substrate 3041 along the Y direction, during the process of forming a wiring layer including the first connection structure 3046 by performing step S804, the first connection structure 3046 is connected to the first through-substrate contact structure 3062.

[0131] Step S904: A first conductive pad or a second conductive pad that is connected to the first through-substrate contact structure is formed on the second surface of the second semiconductor structure.

[0132] Continue to refer to Figure 18 A wiring layer including a first connection structure 3046 can be formed on the second surface 30414 of the substrate 3041 of the second semiconductor structure 304. Then, a first conductive pad 30442 or a second conductive pad 30444 connected to the first through substrate contact structure 3062 via the wiring layer can be formed on the second surface 30484 of the second semiconductor structure 304 outside the wiring layer.

[0133] Figure 10 It shows Figure 7The diagram illustrates steps S704, S708, and S710 in one embodiment. Figure 10 As shown in the present embodiment, step S704 may further include step S1002, step S708 may further include step S1004, and step S710 may further include step S1006. Figure 1 Steps S1002 to S1006 illustrate the formation process of connecting the first conductive pad or the second conductive pad to the memory cell array through the second through-substrate contact structure. The execution order can be designed according to actual needs, and this disclosure does not limit it.

[0134] Step S1002: A second connection structure for connecting to the memory cell array is formed on the first surface of the substrate.

[0135] Continue to refer to Figure 15 After forming a peripheral circuit structure 3042 on the first surface 30412 of the substrate 3041 of the second semiconductor structure 304, a second connection structure 3046 can be formed. The second connection structure 3046 can be connected to the memory cell array 3022 through a bonding structure in the bonding layer. Step S1004 can be performed, for example, in step S704 and before step S706.

[0136] Step S1004: A second through-substrate contact structure is formed, which penetrates the substrate, and the second through-substrate contact structure is connected to the second connection structure.

[0137] Continue to refer to Figure 18 A second through-substrate contact structure 3064 is formed that penetrates the substrate 3041 along the Y direction, so that the second through-substrate contact structure 3064 is connected to the second connection structure 3046.

[0138] Step S1006: A first conductive pad or a second conductive pad that contacts the second through-substrate contact structure is formed on the second surface of the second semiconductor structure.

[0139] Continue to refer to Figure 18 A wiring layer can be formed on the second surface 30414 of the substrate 3041 of the second semiconductor structure 304, and then a first conductive pad 30442 or a second conductive pad 30444 connected to the second through substrate contact structure 306 via the wiring layer can be formed on the second surface 30484 of the second semiconductor structure 304 outside the wiring layer.

[0140] Figure 11 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment. Figure 11 The methods shown may include, for example, forming Figures 4A to 5The step of applying a passivation layer to the surface of the first conductive pad or the second conductive pad.

[0141] refer to Figure 11 The method 110 provided in this embodiment may include the following steps S1102 to S1104, for example, it may be executed during the execution of step S710, or for example, it may be executed after step S710.

[0142] In step S1102, a passivation layer is formed on the surface of the first conductive pad and / or the second conductive pad.

[0143] In some embodiments, a passivation layer may be deposited onto the exposed surfaces of the first conductive pad and / or the second conductive pad using a thin-film deposition technique.

[0144] In step S1104, at least a portion of the passivation layer is removed to expose a portion of the surface of the first conductive pad and / or the second conductive pad, wherein the two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer are the first inner diameter and the second inner diameter, respectively.

[0145] In some embodiments, etching techniques such as chemical mechanical polishing (CMP) can be used to remove the central portion of the surface of the first conductive pad and / or the second conductive pad covered with the passivation layer, for example, leaving the central portion intact. Figures 4A to 5 The passivation layer at the outer ring exposes a central portion with a first inner diameter and a second inner diameter to enable electrical connection between the memory cell array and / or peripheral circuitry structure and the outside.

[0146] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor structure, including a memory cell array; A first conductive pad and a second conductive pad are disposed on the surface of the semiconductor structure. The memory cell array is connected to the first conductive pad and the second conductive pad respectively through at least different contact structures. The contact structures at least partially penetrate the semiconductor structure along a first direction, which is perpendicular to the surface of the semiconductor structure, wherein: The first conductive pad is at least one of a polygon, a circle, or an ellipse, wherein the polygon has more than 4 sides; The surface of the second conductive pad is connected to at least one wire, and the second conductive pad is quadrilateral.

2. The semiconductor structure according to claim 1, characterized in that, Both the first conductive pad and the second conductive pad have a first inner diameter and a second inner diameter that are perpendicular to each other, wherein: The length of the first inner diameter of the first conductive pad is equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad is equal to the length of the second inner diameter of the second conductive pad.

3. The semiconductor structure according to claim 2, characterized in that, The area of ​​the first conductive pad is smaller than the area of ​​the second conductive pad.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, It also includes a second semiconductor structure, wherein the first surface of the second semiconductor structure is connected to the first semiconductor structure; Both the first conductive pad and the second conductive pad are disposed on the second surface of the second semiconductor structure.

5. The semiconductor structure according to claim 4, characterized in that, The second semiconductor structure includes a peripheral circuit structure, which is connected to the memory cell array; The contact structure includes a first through-substrate contact structure, which penetrates the substrate of the peripheral circuit structure. The peripheral circuit structure is connected to a corresponding first conductive pad or a second conductive pad at least through the first through-substrate contact structure.

6. The semiconductor structure according to claim 5, characterized in that, The contact structure further includes a second through-substrate contact structure, which penetrates the substrate of the peripheral circuit structure. The memory cell array is connected to the corresponding first conductive pad or second conductive pad at least through the second through-substrate contact structure.

7. The semiconductor structure according to claim 5 or 6, characterized in that, It also includes a connection structure, through which the contact structure connects to the corresponding first conductive pad or second conductive pad.

8. The semiconductor structure according to claim 2 or 3, characterized in that, It also includes a passivation layer disposed around the first conductive pad and / or the second conductive pad, wherein the two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer are the first inner diameter and the second inner diameter, respectively.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The first conductive pad is a regular polygon.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The first conductive pad is octagonal or hexagonal.

11. The semiconductor structure according to any one of claims 1 to 10, characterized in that, The second conductive pad is rectangular, and its length and width are the first inner diameter and the second inner diameter, respectively.

12. A method for forming a semiconductor structure, characterized in that, include: A first semiconductor structure is formed, the first semiconductor structure including a memory cell array; A second semiconductor structure is formed on a substrate, the second semiconductor structure including a peripheral circuit structure; The first surface of the second semiconductor structure is bonded to the first semiconductor structure to connect the peripheral circuit structure to the memory cell array; A contact structure is formed that penetrates the substrate along a first direction, the first direction being perpendicular to the first surface; A first conductive pad and a second conductive pad are formed on the second surface of the second semiconductor structure, respectively connected to different contact structures, to connect the memory cell array with the first conductive pad and the second conductive pad. The second surface is opposite to the first surface. The first conductive pad is at least one of a polygon, a circle or an ellipse, wherein the polygon has more than 4 sides, and the second conductive pad is a quadrilateral. At least one wire is formed that is connected to the surface of the second conductive pad.

13. The method according to claim 12, characterized in that, Both the first conductive pad and the second conductive pad have a first inner diameter and a second inner diameter that are perpendicular to each other, wherein: The length of the first inner diameter of the first conductive pad is equal to the length of the first inner diameter of the second conductive pad, and the length of the second inner diameter of the first conductive pad is equal to the length of the second inner diameter of the second conductive pad.

14. The method according to claim 13, characterized in that, The area of ​​the first conductive pad is smaller than the area of ​​the second conductive pad.

15. The method according to any one of claims 12 to 14, characterized in that, Forming a second semiconductor structure on a substrate includes: The peripheral circuit structure is formed on the first surface of the substrate; A first connection structure is formed on the second surface of the substrate to connect with the peripheral circuit structure.

16. The method according to claim 15, characterized in that, The contact structure includes a first through-substrate contact structure; Forming a contact structure penetrating the substrate along a first direction, comprising: A first through-substrate contact structure is formed that penetrates the substrate, and the first through-substrate contact structure is connected to the first connection structure; A first conductive pad and a second conductive pad, respectively connected to different contact structures, are formed on the second surface of the second semiconductor structure, including: A first conductive pad or a second conductive pad that is connected to the first through-substrate contact structure is formed on the second surface of the second semiconductor structure.

17. The method according to claim 15 or 16, characterized in that, The contact structure further includes a second through-substrate contact structure; Forming a second semiconductor structure on the substrate also includes: A second connection structure connected to the memory cell array is formed on the first surface of the substrate; The method further includes: A second through-substrate contact structure is formed that penetrates the substrate, and the second through-substrate contact structure is connected to the second connection structure; A first conductive pad and a second conductive pad, respectively connected to different contact structures, are formed on the second surface of the second semiconductor structure, including: The first conductive pad or the second conductive pad is formed on the second surface of the second semiconductor structure to contact the second through-substrate contact structure.

18. The method according to any one of claims 12 to 17, characterized in that, Also includes: A passivation layer is formed on the surface of the first conductive pad and / or the second conductive pad; At least a portion of the passivation layer is removed to expose a portion of the surface of the first conductive pad and / or the second conductive pad, wherein the two mutually perpendicular inner diameters of the surfaces of the first conductive pad and / or the second conductive pad exposed from the passivation layer are the first inner diameter and the second inner diameter, respectively.

19. The method according to any one of claims 12 to 18, characterized in that, The first conductive pad is a regular polygon.

20. The method according to any one of claims 12 to 18, characterized in that, The first conductive pad is octagonal or hexagonal.

21. The method according to any one of claims 12 to 20, characterized in that, The second conductive pad is rectangular, and its length and width are the first inner diameter and the second inner diameter, respectively.

22. A semiconductor device, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 11.

23. A storage system, characterized in that, Includes the semiconductor device as described in claim 22 and a controller coupled to said semiconductor device.

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