Semiconductor structure

Abstract

This disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, an upper structure, a vertical transistor, and a bonding pad. The upper structure is disposed on the substrate. The bonding pad is disposed on the vertical transistor. A peripheral portion of the bonding pad horizontally overlaps with an upper portion of the vertical transistor.

Description

Technical Field

[0001] This disclosure claims priority to U.S. Patent Application No. 19 / 050,858 (i.e., priority date “February 11, 2025”), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor structure and a method for fabricating the same. More particularly, it relates to a semiconductor structure including an electrical bonding pad and a method for fabricating the same. Background Technology

[0003] Semiconductor structures are used in a wide range of electronic applications, and their dimensions are constantly shrinking to meet current application requirements. However, various problems arise during this shrinking process, affecting the final electronic characteristics, quality, cost, and yield. Typical memory elements (such as dynamic random-access memory (DRAM) elements) include signal lines, such as word lines and bit lines that intersect with them. As DRAM element dimensions continue to shrink, signal line sizes and / or spacing become increasingly smaller, making complex manufacturing processes and high manufacturing costs critical issues.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0005] The purpose of this disclosure is to provide a semiconductor structure to solve at least one of the above-mentioned problems.

[0006] One embodiment of this disclosure provides a semiconductor structure including a substrate, an upper structure, a vertical transistor, and a bonding pad. The upper structure is disposed on the substrate. The vertical transistor is disposed on the upper structure. The bonding pad is disposed on the vertical transistor. A peripheral portion of the bonding pad horizontally overlaps with an upper portion of the vertical transistor.

[0007] Another embodiment of this disclosure provides a semiconductor structure including a substrate, an upper structure, a vertical transistor, and a bonding pad. The substrate includes a capacitor. The upper structure is disposed on the substrate. The vertical transistor is disposed in the upper structure and electrically connected to the capacitor. The vertical transistor extends beyond a top of the upper structure. The bonding pad is disposed on the vertical transistor.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a stacked structure including a substrate and an upper structure disposed on the substrate. The method also includes forming a hole extending through the upper structure. The method further includes forming a vertical transistor in the hole, wherein an upper portion of the vertical transistor extends beyond the upper structure. The method also includes forming a bonding pad on the vertical transistor.

[0009] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0011] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0012] Figure 2 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0013] Figure 3 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0014] Figure 4 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0015] Figure 5 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0016] Figure 6 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0017] Figure 7This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0018] Figure 8 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0019] Figure 9 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0020] Figure 10 This is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0021] Figure 11 Example Figure 10 An enlarged diagram of region "A".

[0022] The attached figures are labeled as follows:

[0023] 1: Semiconductor Structure

[0024] 2: Base

[0025] 3: Upper structure

[0026] 3a: First depression

[0027] 3a1: Inner surface

[0028] 3a2: Lower surface

[0029] 3b1: Inner surface

[0030] 3b2: Lower surface

[0031] 4: Vertical transistor

[0032] 5': First conductive layer

[0033] 6: Welding pad

[0034] 6': Second conductive layer

[0035] 7: Capacitor

[0036] 10: Stacked structure

[0037] 21: Upper surface

[0038] 22: Base

[0039] 22a: Basic Materials

[0040] 23: Conductive materials

[0041] 23a: Conductive materials

[0042] 24:lower part

[0043] 25: upper part

[0044] 26: Central Section

[0045] 27: Filling material

[0046] 31: Upper surface

[0047] 31': Upper surface

[0048] 32: Lower surface

[0049] 33: Lower insulation layer

[0050] 34: Conductive layer

[0051] 35: Upper insulation layer

[0052] 36: Hole

[0053] 37: Protrusion

[0054] 38: Top

[0055] 43: Main Materials

[0056] 44: Outer insulation layer

[0057] 44': Insulation layer

[0058] 45: upper part

[0059] 46: Upper surface

[0060] 48: Inclined surface

[0061] 51: Main body

[0062] 52: Peripheral Department

[0063] 53: Side surface

[0064] 54: Bottom

[0065] 55: Side surface

[0066] 61: Main body

[0067] 62: Peripheral Department

[0068] 63: Side surface

[0069] 64: Bottom

[0070] 71: First electrode

[0071] 72: Intermediate layer

[0072] 73: Second electrode

[0073] 74: Upper part

[0074] 75: lower part

[0075] 231: Upper surface

[0076] 232: Lower surface

[0077] 252: Lower surface

[0078] 263: Side surface

[0079] 441: Center Hole

[0080] 621: Upper part

[0081] 622: Lower part

[0082] 711: Upper surface

[0083] 721: Upper surface

[0084] 723: Side surface

[0085] 731: Upper surface

[0086] 733: Side surface

[0087] 900: Preparation Method

[0088] H: Height

[0089] S901: Steps

[0090] S902: Steps

[0091] S903: Steps

[0092] S904: Steps

[0093] T1: Thickness

[0094] T2: Thickness

[0095] T3: Thickness

[0096] T4: First thickness

[0097] T5: Second thickness

[0098] T6: Maximum Thickness

[0099] T7: Third Thickness Detailed Implementation

[0100] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0101] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0102] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, the terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0103] Figure 1 This is a flowchart illustrating a method 900 for preparing a semiconductor structure 1 according to an embodiment of the present disclosure. Figures 2 to 11 The various stages of a method for fabricating a semiconductor structure 1 according to an embodiment of this disclosure are illustrated. At least some of the figures have been simplified for a better understanding of the aspects of this disclosure.

[0104] Please refer to Figures 2 to 4 In step S901, a stacked structure 10 may be provided. The stacked structure 10 may include a base 2 and an upper structure 3 disposed on the base 2. Figure 2 This is a cross-sectional schematic diagram illustrating the stacked structure 10 of some embodiments of the present invention. Figure 3 This is a sectional view, illustrating along... Figure 2The upper part 74 of the capacitor 7 of the stacked structure 10 is cut off by section II. Figure 4 This is a sectional view, illustrating along... Figure 2 The lower part 75 of the capacitor 7 of the stacked structure 10 is cut off by section II-II.

[0105] In some embodiments, the substrate 2 may have an upper surface 21 and may include a base 22 and a conductive material 23 on the base 22. For example, the base 22 may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the base 22 may include an insulator-on-semiconductor substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0106] Depending on the IC manufacturing stage, the base 22 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof).

[0107] In some embodiments, the conductive material 23 may include a suitable conductive material. For example, the conductive material 23 may include tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof. In some embodiments, the conductive material 23 may include a transparent conductive oxide (TCO) material, such as indium tin oxide (ITO) and zinc oxide (ZnO).

[0108] In some embodiments, the substrate 2 may further include at least one capacitor 7 disposed therein. The capacitor 7 may be embedded in the substrate 2. In some embodiments, the capacitor 7 may be a vertical annular structure surrounding a central portion 26. The central portion 26 may be cylindrical in shape and may include a base material 22a and a conductive material 23a. The base material 22a of the central portion 26 may be part of the base 22 of the substrate 2. The conductive material 23a of the central portion 26 may be disposed on the base material 22a. The conductive material 23a of the central portion 26 may be part of the conductive material 23 of the substrate 2.

[0109] The capacitor 7 may include a first electrode 71 (e.g., a lower electrode), an intermediate layer 72, and a second electrode 73 (e.g., an upper electrode). It is conceivable that the number of capacitors 7 is unlimited. Multiple capacitors 7 may exist within the substrate 2. The substrate 2 may also include a filling material 27 between the capacitors 7.

[0110] The second electrode 73 can be a conductive layer, such as a titanium nitride (TiN) layer. The second electrode 73 can be disposed on and surround the side surface 263 of the central portion 26. Therefore, the second electrode 73 can be inserted between the central portion 26 and the intermediate layer 72. Furthermore, the intermediate layer 72 can be a high-k dielectric layer, such as a zirconium oxide (ZrO2) layer. The intermediate layer 72 can be disposed on and surround the side surface 733 of the second electrode 73. Therefore, the intermediate layer 72 can be inserted between the second electrode 73 and the first electrode 71. Furthermore, the first electrode 71 can be a conductive layer, such as a titanium nitride (TiN) layer. The first electrode 71 can be disposed on and surround the side surface 723 of the intermediate layer 72. Therefore, the first electrode 71 can be inserted between the intermediate layer 72 and the filler material 27.

[0111] The filler material 27 may include a lower portion 24 and an upper portion 25 disposed on the lower portion 24. The lower portion 24 may be a dielectric material or an insulating material, and may include silicon nitride (Si3N4, or SiN), silicon dioxide (SiO2), silicon nitride oxide (N2OSi2), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), strontium bismuth tantalum oxide (SrBi2Ta2O9, SBT), strontium barium titanate oxide (BaSrTiO3, BST), or combinations thereof. The upper part 25 can be a dielectric material or an insulating material, and may include silicon nitride (Si3N4, or SiN), silicon dioxide (SiO2), silicon nitride oxide (N2OSi2), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), strontium bismuth tantalum oxide (SrBi2Ta2O9, SBT), strontium barium titanate oxide (BaSrTiO3, BST), or combinations thereof. The material of the upper part 25 may be the same as or different from the material of the lower part 24.

[0112] In some embodiments, the conductive material 23a of the central portion 26 contacts the second electrode 73. For example... Figure 2As shown, an upper surface 231 of the conductive material 23a of the central portion 26 (or an upper surface 231 of the conductive material 23 of the substrate 2), an upper surface 731 of the second electrode 73, and an upper surface 721 of the intermediate layer 72 can be substantially coplanar or aligned with each other. Therefore, the upper surface 21 of the substrate 2 may include the upper surface 231 of the conductive material 23a of the central portion 26 (or the upper surface 231 of the conductive material 23 of the substrate 2), the upper surface 731 of the second electrode 73, and the upper surface 721 of the intermediate layer 72. Furthermore, the capacitor 7 may include an upper portion 74 and a lower portion 75 located below the upper portion 74, and the upper portion 74 of the capacitor 7 may be exposed from the upper surface 21 of the substrate 2.

[0113] Furthermore, the first electrode 71 may be disposed below the conductive material 23a of the central portion 26 and below the upper portion 25 of the filling material 27. That is, the height of an upper surface 711 of the first electrode 71 may be lower than the height of a lower surface 232 of the conductive material 23a of the central portion 26, and lower than the height of a lower surface 252 of the upper portion 25 of the filling material 27. The upper portion 74 of the capacitor 7 may not include the first electrode 71. In some embodiments, only the lower portion 75 may be designated as a capacitor.

[0114] The upper structure 3 may be disposed on the upper surface 21 of the base 2. The upper structure 3 may have an upper surface 31' and a lower surface 32 opposite to the upper surface 31'. The lower surface 32 of the upper structure 3 may contact the upper surface 21 of the base 2. The upper surface 31' of the upper structure 3 may be a generally flat plane. In cross-section, the entire upper surface 31' of the upper structure 3 may be at the same height.

[0115] The upper structure 3 may include a lower insulating layer 33, a conductive layer 34, and an upper insulating layer 35. The lower insulating layer 33 may be disposed on the upper surface 21 of the substrate 2. In some embodiments, the lower insulating layer 33 may include a dielectric material or an insulating material, such as a nitride, oxide, oxynitride, amorphous silicon, polycrystalline silicon, or other suitable material. The lower insulating layer 33 may have a thickness T1.

[0116] A conductive layer 34 may be disposed on the lower insulating layer 33. In some embodiments, the conductive layer 34 may include a suitable conductive material, such as tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof. In some embodiments, the conductive layer 34 may include multiple signal lines, such as multiple word lines. The conductive layer 34 may have a thickness T2.

[0117] An upper insulating layer 35 may be disposed on a conductive layer 34 (e.g., a character line). In some embodiments, the upper insulating layer 35 may include a dielectric material or an insulating material, such as a nitride, oxide, oxynitride, amorphous silicon, polycrystalline silicon, or other suitable material. The material of the upper insulating layer 35 may be the same as or different from the material of the lower insulating layer 33. The upper insulating layer 35 may have a uniform thickness T3. In some embodiments, the thickness T3 of the upper insulating layer 35 may be 70 nm.

[0118] Please refer to Figure 5 In step S902, for example, at least one hole 36 extending through the upper structure 3 can be formed by dry etching. Therefore, the hole 36 can extend between the upper surface 31' and the lower surface 32 of the upper structure 3, and can extend through the lower insulating layer 33, the conductive layer 34 (e.g., character lines), and the upper insulating layer 35. The hole 36 can be located directly above the conductive material 23a of the central portion 26. Therefore, the upper surface 231 of the conductive material 23a of the central portion 26 (or, the upper surface 231 of the conductive material 23 of the substrate 2) can be exposed from the hole 36. The hole 36 can be blocked by the conductive material 23a of the central portion 26. A width of the hole 36 can be smaller than a width of the conductive material 23a of the central portion 26. A central axis of the hole 36 can be aligned with a central axis of the conductive material 23a of the central portion 26. Therefore, a portion of the upper surface 231 of the conductive material 23a of the center portion 26 (or the upper surface 231 of the conductive material 23 of the substrate 2) can be a bottom wall of the hole 36.

[0119] Please refer to Figures 6 to 8 In step S903, at least one vertical transistor 4 may be formed in the hole 36, and an upper portion 45 of the vertical transistor 4 may extend beyond the upper structure 3.

[0120] Please refer to Figure 6 For example, an insulating layer 44' can be deposited on the upper surface 31' of the upper structure 3 and in the aperture 36. The insulating layer 44' may include an insulating material or a dielectric material, such as gate oxide (GOX).

[0121] Please refer to Figure 7 The portion of insulating layer 44' on the upper surface 31' of the upper structure 3 and on the bottom wall of the hole 36 is removed to form a peripheral insulating layer 44 on the sidewall of the hole 36. Then, a main material 43 can be formed in the central hole 441 defined by the peripheral insulating layer 44. The main material 43 may include a conductive material, such as indium gallium zinc oxide (IGZO). Simultaneously, a vertical transistor 4 (including the main material 43 and the peripheral insulating layer 44) can be formed in the hole 36.

[0122] The vertical transistor 4 can be disposed in the hole 36 and on the substrate 2. Therefore, the vertical transistor 4 can extend through the lower insulating layer 33, the conductive layer 34, and the upper insulating layer 35. Furthermore, a vertical projection of the vertical transistor 4 can be located within the central portion 26. Figure 7 As shown, the vertical transistor 4 may include a main material 43 and a peripheral insulating layer 44. The main material 43 may be a conductive material, such as indium gallium zinc oxide (IGZO). One bottom end of the main material 43 may contact the conductive material 23a of the central portion 26. Therefore, the vertical transistor 4 can be electrically connected to the capacitor 7 through the conductive material 23a of the central portion 26 surrounded by the second electrode 73 of the capacitor 7.

[0123] The vertical transistor 4 may include an upper portion 45 adjacent to the upper surface 31' of the upper insulating layer 35. The vertical transistor 4 may have an upper surface 46 that is substantially coplanar or aligned with the upper surface 31' of the upper insulating layer 35.

[0124] Please refer to Figure 8 For example, a portion of the upper insulating layer 35 of the upper structure 3 surrounding the upper portion 45 of the vertical transistor 4 can be removed by etching to define at least one first recess 3a around the vertical transistor 4. Thus, the vertical transistor 4 can extend beyond the upper insulating layer 35 of the upper structure 3.

[0125] A first recess 3a may be formed or disposed between two vertical transistors 4. The first recess 3a may taper gradually toward the substrate 2. The first recess 3a may be recessed from the upper surface 46 of the vertical transistor 4 and the upper surface 31' of the upper insulating layer 35. For example, the first recess 3a may be recessed from a top 38 of the upper structure 3. The first recess 3a may have an inner surface 3a1 and a lower surface 3a2. The inner surface 3a1 of the first recess 3a may be substantially coplanar or aligned with an inclined surface 48 of the vertical transistor 4. The upper portion 45 of the vertical transistor 4 may protrude from the lower surface 3a2 of the upper insulating layer 35 of the upper structure 3. The top of the upper portion 45 of the vertical transistor 4 may taper gradually from the substrate 2.

[0126] Simultaneously, the upper insulating layer 35 of the upper structure 3 may include a protrusion 37. The protrusion 37 may define a first recess 3a. The protrusion 37 may taper away from the substrate 2. The protrusion 37 may contact the vertical transistor 4. For example, the protrusion 37 may be defined by the inner surface 3a1 of the first recess 3a and one side surface of the vertical transistor 4. The protrusion 37 may protrude from the lower surface 3a2 of the first recess 3a. The protrusion 37 may include a top 38. The top 38 may contact the vertical transistor 4.

[0127] Meanwhile, the upper insulating layer 35 of the upper structure 3 may have a first thickness T4 and a second thickness T5. The first thickness T4 may be a vertical distance between the top 38 and an upper surface of the conductive layer 34. The second thickness T5 may be a vertical distance between the lower surface 3a2 of the first recess 3a and the upper surface of the conductive layer 34. The first thickness T4 is greater than the second thickness T5.

[0128] The upper structure 3 may have a maximum thickness T6, defined as a vertical distance between the lower surface 32 and the top 38 of the upper structure 3. The maximum thickness T6 of the upper structure 3 is the sum of the thickness T1 of the lower insulating layer 33, the thickness T2 of the conductive layer 34, and the first thickness T4 of the upper insulating layer 35. The vertical transistor 4 may have a height H. The height H of the vertical transistor 4 may be greater than the maximum thickness T6 of the upper structure 3. Therefore, the upper portion 45 of the vertical transistor 4 may extend beyond the top 38 of the upper structure 3.

[0129] Please refer to Figures 9 to 11 In step S904, a solder pad 6 may be formed or disposed on the vertical transistor 4.

[0130] Please refer to Figure 9 For example, a first conductive layer 5' may be formed or disposed on the vertical transistor 4 and in the first recess 3a by physical vapor deposition (PVD). The first conductive layer 5' may include a transparent conductive oxide (TCO) material, such as indium tin oxide (ITO) and zinc oxide (ZnO). The first conductive layer 5' may include a body portion 51, a peripheral portion 52 and a bottom portion 54 formed simultaneously.

[0131] The main body 51 can be disposed on the upper part 45 of the vertical transistor 4 and can contact the upper surface 46 of the vertical transistor 4. The main body 51 can be electrically connected to the vertical transistor 4. The thickness of the main body 51 can be 5 nm. The peripheral part 52 can be disposed on the inner surface 3a1 of the first recess 3a and can extend between the main body 51 and the bottom 54. The peripheral part 52 can have a side surface 53. The thickness of the peripheral part 52 can be 1 nm to 2 nm. Therefore, the thickness of the peripheral part 52 can be less than the thickness of the main body 51.

[0132] The bottom layer 54 can be disposed on the lower surface 3a2 of the first recess 3a. The thickness of the bottom layer 54 can be 1 nm to 2 nm. Therefore, the thickness of the bottom layer 54 can be equal to the thickness of the peripheral portion 52 and can be less than the thickness of the main body portion 51. The first conductive layer 5' can be substantially conformally aligned with the first recess 3a and the protruding upper portion 45 of the vertical transistor 4.

[0133] Then, for example, a second conductive layer 6' can be formed or disposed on the first conductive layer 5' (e.g., on the vertical transistor 4) and in the first recess 3a by physical vapor deposition (PVD). The second conductive layer 6' may include a suitable conductive material, such as tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof. The second conductive layer 6' may include a body portion 61, a peripheral portion 62, and a bottom portion 64 formed simultaneously.

[0134] The main body 61 can be disposed on or above the upper portion 45 of the vertical transistor 4 and can contact the main body 51 of the first conductive layer 5'. The main body 61 of the second conductive layer 6' can be electrically connected to the vertical transistor 4 through the main body 51 of the first conductive layer 5'. The thickness of the main body 61 can be 50 nm. The peripheral portion 62 can be disposed on the peripheral portion 52 of the first conductive layer 5' (e.g., on the inner surface 3a1 of the first recess 3a) and can extend between the main body 61 and the bottom 64. The peripheral portion 62 can have a side surface 63. The thickness of the peripheral portion 62 can be 20 nm to 30 nm. Therefore, the thickness of the peripheral portion 62 can be less than the thickness of the main body 61.

[0135] The bottom layer 64 can be disposed on the bottom 54 of the first conductive layer 5' (e.g., on the lower surface 3a2 of the first recess 3a). The thickness of the bottom layer 64 can be 20 nm to 30 nm. Therefore, the thickness of the bottom layer 64 can be equal to the thickness of the peripheral portion 62 and can be less than the thickness of the main body portion 61. The second conductive layer 6' can be substantially conformally aligned with the first conductive layer 5'. Therefore, the second conductive layer 6' can be substantially conformally aligned with the first recess 3a and the protruding upper portion 45 of the vertical transistor 4.

[0136] Please refer to Figure 10 and Figure 11 ,in Figure 11 Example Figure 10 An enlarged view of region "A" allows for a removal process. For example, at least a portion of the bottom 54 of the first conductive layer 5' and at least a portion of the bottom 64 of the second conductive layer 6' located in the first recess 3a can be removed by etching, thereby cutting off the first conductive layer 5' and the second conductive layer 6', forming a conductive structure 5 on the vertical transistor 4, and forming a solder pad 6 on the conductive structure 5 and the vertical transistor 4. That is, the first conductive layer 5' and the second conductive layer 6' can be patterned. Two adjacent conductive structures 5 may not be electrically connected to each other. Two adjacent solder pads 6 may not be electrically connected to each other.

[0137] Furthermore, for example, a portion of the upper insulating layer 35 of the upper structure 3 around the upper portion 45 of the vertical transistor 4 can be removed by etching to define at least one second recess 3b around the vertical transistor 4. The second recess 3b may be located between two vertical transistors 4. The second recess 3b may taper towards the substrate 2. The second recess 3b may be recessed from the lower surface 3a2 of the first recess 3a. The second recess 3b may have an inner surface 3b1 and a lower surface 3b2. The inner surface 3b1 of the second recess 3b may be substantially continuous and aligned with the side surface 63 of the peripheral portion 62 of the solder pad 6 and the side surface 55 of the remaining bottom 54 of the conductive structure 5.

[0138] Meanwhile, the lower surface 3b2 of the second recess 3b can be the upper surface 31 of the upper structure 3. The upper insulating layer 35 of the upper structure 3 can have a third thickness T7. The third thickness T7 can be a vertical distance between the lower surface 3b2 of the second recess 3b and the upper surface of the conductive layer 34. The third thickness T7 can be less than the first thickness T4 and the second thickness T5. In some embodiments, the third thickness T7 of the upper insulating layer 35 can be 35nm, 40nm, 45nm, 50nm, 55nm or 60nm.

[0139] The conductive structure 5 can be disposed between the vertical transistor 4 and the solder pad 6. The cross-section of the conductive structure 5 can be approximately inverted "U" shaped. The conductive structure 5 can include a cap-shaped structure in its cross-section. The conductive structure 5 can include a main body portion 51 and a peripheral portion 52. The main body portion 51 can be disposed on the vertical transistor 4. The main body portion 51 can gradually taper from the substrate 2.

[0140] The peripheral portion 52 may extend downward from the main body portion 51 and may have a side surface 53. The peripheral portion 52 may have a uniform thickness. Therefore, the side surface 53 of the peripheral portion 52 may not be parallel to the side surface 63 of the peripheral portion 62 of the solder pad 6. In some embodiments, the peripheral portion 52 of the conductive structure 5 may taper towards the substrate 2. The peripheral portion 52 of the conductive structure 5 may horizontally overlap with the upper portion 45 of the vertical transistor 4 and the peripheral portion 62 of the solder pad 6. In some embodiments, the conductive structure 5 may be omitted.

[0141] The soldering pad 6 can also be referred to as a "landing pad". The soldering pad 6 can be disposed on or above the conductive structure 5 (e.g., on the vertical transistor 4). The cross-section of the soldering pad 6 can be generally inverted "U" shaped. The cross-section of the soldering pad 6 can include a cap-like structure. The soldering pad 6 can include a main body portion 61 and a peripheral portion 62. The main body portion 61 can be disposed on the main body portion 51 of the conductive structure 5. The main body portion 61 can gradually taper from the substrate 2.

[0142] The peripheral portion 62 may extend downward from the main body portion 61 and may have a side surface 63. The peripheral portion 62 of the solder pad 6 may taper towards the substrate 2. Therefore, the thickness of an upper portion 621 of the peripheral portion 62 may be greater than the thickness of a lower portion 622 of the peripheral portion 62. In some embodiments, the peripheral portion 62 may have a uniform thickness. The peripheral portion 62 of the solder pad 6 may horizontally overlap with the upper portion 45 of the vertical transistor 4, the peripheral portion 52 of the conductive structure 5, and the top 38 of the upper structure 3. The peripheral portion 52 of the conductive structure 5 may be disposed between the inclined surface 48 (or a side surface of the vertical transistor 4) of the vertical transistor 4 and the peripheral portion 62 of the solder pad 6.

[0143] At the same time, a semiconductor structure 1 can be formed.

[0144] exist Figures 2 to 11 In the illustrated embodiment, during the manufacturing process, a first recess 3a can be formed between two adjacent vertical transistors 4. The upper portions 45 of the two adjacent vertical transistors 4 can be exposed in the first recess 3a. Therefore, the first recess 3a can have a self-aligned function. The upper portions 45 of the vertical transistors 4 can protrude from the upper structure 3. Therefore, the welding pad 6 (e.g., a landing pad) can be formed directly above the vertical transistors 4. In a comparative embodiment, the fabrication technique for a landing pad structure includes two self-aligned double patterning (SADP) processes, which results in a complex manufacturing process and high manufacturing costs. In contrast, a simplified... Figures 2 to 11 The manufacturing process of the semiconductor structure 1 in the illustrated embodiment results in low manufacturing costs.

[0145] Figure 10 This is a cross-sectional schematic diagram illustrating a semiconductor structure 1 of some embodiments of the present disclosure. Figure 11 Example Figure 10 An enlarged schematic diagram of region "A". In some embodiments, semiconductor structure 1 may be a semiconductor element containing a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

[0146] Furthermore, the semiconductor structure 1 may be or include part of an integrated circuit (IC) wafer comprising various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0147] The semiconductor structure 1 may include a substrate 2 (e.g., a semiconductor substrate), an upper structure 3, a vertical transistor 4, a conductive structure 5, and an electric bonding pad 6.

[0148] Figure 1 The base 2 can be with Figure 2 The substrate 2 is the same as or similar to the substrate 2. In some embodiments, the substrate 2 may have an upper surface 21 and may include a base 22, a conductive material 23 on the base 22, and at least one capacitor 7. The capacitor 7 may be embedded in the substrate 2. In some embodiments, the capacitor 7 may be a vertical ring structure surrounding a central portion 26. The central portion 26 may be cylindrical and may include a base material 22a and a conductive material 23a. The base material 22a of the central portion 26 may be a part of the base 22 of the substrate 2. The conductive material 23a of the central portion 26 may be a part of the conductive material 23 of the substrate 2.

[0149] Figure 10 Capacitor 7 can be with Figure 2 The capacitors 7 are the same as or similar to those in the substrate 2, and may include a first electrode 71 (e.g., a lower electrode), an intermediate layer 72, and a second electrode 73 (e.g., an upper electrode). It is conceivable that the number of capacitors 7 is unlimited. Multiple capacitors 7 may exist within the substrate 2. The substrate 2 may also include a filling material 27 between the multiple capacitors 7. The filling material 27 may include a lower portion 24 and an upper portion 25 disposed on the lower portion 24.

[0150] In some embodiments, the conductive material 23a of the central portion 26 contacts the second electrode 73. For example... Figure 10 As shown, the upper surface 21 of the substrate 2 may include the upper surface 231 of the conductive material 23a of the central portion 26 (or the upper surface 231 of the conductive material 23 of the substrate 2), the upper surface 731 of the second electrode 73, and the upper surface 721 of the intermediate layer 72. Furthermore, the capacitor 7 may include an upper portion 74 and a lower portion 75 located below the upper portion 74, and the upper portion 74 of the capacitor 7 may be exposed from the upper surface 21 of the substrate 2. In some embodiments, only the lower portion 75 may be designated as a capacitor.

[0151] Figure 10 The upper structure 3 can be with Figure 2 The upper structure 3 is the same as or similar to the lower structure 33, and may include a lower insulating layer 33, a conductive layer 34, and an upper insulating layer 35. The lower insulating layer 33 may be disposed on the upper surface 21 of the substrate 2. The conductive layer 34 may be disposed on the lower insulating layer 33. In some embodiments, the conductive layer 34 may include multiple signal lines, such as word lines. The upper insulating layer 35 may be disposed on the conductive layer 34 (e.g., word lines).

[0152] Figure 10The upper structure 3 may define at least one hole 36 extending through the upper structure 3. Therefore, the hole 36 may extend through the lower insulating layer 33, the conductive layer 34 (e.g., character lines), and the upper insulating layer 35. The hole 36 may be located directly above the conductive material 23a of the central portion 26. Therefore, the upper surface 231 of the conductive material 23a of the central portion 26 (or the upper surface 231 of the conductive material 23 of the substrate 2) may be exposed through the hole 36. The width of the hole 36 may be smaller than the width of the conductive material 23a of the central portion 26.

[0153] A vertical transistor 4 may be formed or disposed in the aperture 36. The vertical transistor 4 may include a main material 43 and a peripheral insulating layer 44. The peripheral insulating layer 44 may be formed or disposed on the sidewall of the aperture 36. The main material 43 may be formed or disposed in a central aperture 441 defined by the peripheral insulating layer 44. The main material 43 may include a conductive material, such as indium gallium zinc oxide (IGZO).

[0154] The vertical transistor 4 may include an upper portion 45 adjacent to the upper surface 31 of the upper insulating layer 35. The vertical transistor 4 may have an upper surface 46. The upper insulating layer 35 of the upper structure 3 may define at least one first recess 3a around the vertical transistor 4. Therefore, the vertical transistor 4 may extend beyond the upper insulating layer 35 of the upper structure 3.

[0155] A first recess 3a may be formed or disposed between two vertical transistors 4. The first recess 3a may taper gradually toward the substrate 2. The first recess 3a may be recessed from the upper surface 46 of the vertical transistor 4. For example, the first recess 3a may be recessed from a top 38 of the upper structure 3. The first recess 3a may have an inner surface 3a1 and a lower surface 3a2. The inner surface 3a1 of the first recess 3a may be substantially coplanar or aligned with the inclined surface 48 of the vertical transistor 4. The upper portion 45 of the vertical transistor 4 may protrude from the lower surface 3a2 of the upper insulating layer 35 of the upper structure 3. The top of the upper portion 45 of the vertical transistor 4 may taper gradually from the substrate 2.

[0156] The upper insulating layer 35 of the upper structure 3 may include a protrusion 37. The protrusion 37 may define a first recess 3a. The protrusion 37 may taper away from the substrate 2. The protrusion 37 may contact the vertical transistor 4. For example, the protrusion 37 may be defined by the inner surface 3a1 of the first recess 3a and one side surface of the vertical transistor 4. The protrusion 37 may protrude from the lower surface 3a2 of the first recess 3a. The protrusion 37 may include a top 38. The top 38 may contact the vertical transistor 4.

[0157] The upper insulating layer 35 of the upper structure 3 also defines at least one second recess 3b around the vertical transistor 4. The second recess 3b may be located between two vertical transistors 4. The second recess 3b may taper towards the substrate 2. The second recess 3b may be recessed from the lower surface 3a2 of the first recess 3a. The second recess 3b may have an inner surface 3b1 and a lower surface 3b2. The inner surface 3b1 of the second recess 3b may be substantially continuous and aligned with the side surface 63 of the peripheral portion 62 of the solder pad 6 and the side surface 55 of the remaining bottom 54 of the conductive structure 5.

[0158] The lower surface 3b2 of the second recess 3b can be the upper surface 31 of the upper structure 3.

[0159] The upper insulating layer 35 of the upper structure 3 may have a first thickness T4, a second thickness T5, and a third thickness T7. The first thickness T4 may be a vertical distance between the top 38 and an upper surface of the conductive layer 34. The second thickness T5 may be a vertical distance between the lower surface 3a2 of the first recess 3a and the upper surface of the conductive layer 34. The third thickness T7 may be a vertical distance between the lower surface 3b2 of the second recess 3b and the upper surface of the conductive layer 34. The first thickness T4 may be greater than the second thickness T5. The third thickness T7 may be less than the first thickness T4 and the second thickness T5. In some embodiments, the third thickness T7 of the upper insulating layer 35 may be 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm.

[0160] The upper structure 3 may have a maximum thickness T6, defined as a vertical distance between the lower surface 32 and the top 38 of the upper structure 3. The maximum thickness T6 of the upper structure 3 is the sum of the thickness T1 of the lower insulating layer 33, the thickness T2 of the conductive layer 34, and the first thickness T4 of the upper insulating layer 35. The vertical transistor 4 may have a height H. The height H of the vertical transistor 4 may be greater than the maximum thickness T6 of the upper structure 3. Therefore, the upper part 45 of the vertical transistor 4 may extend beyond the top 38 of the upper structure 3.

[0161] A conductive structure 5 may be disposed between the vertical transistor 4 and the solder pad 6. The cross-section of the conductive structure 5 may be approximately inverted "U" shaped. The conductive structure 5 may include a cap-shaped structure in its cross-section. The conductive structure 5 may include a main body 51 and a peripheral body 52. ​​The main body 51 may be disposed on the vertical transistor 4. The main body 51 may gradually taper from the substrate 2.

[0162] The peripheral portion 52 may extend downward from the main body portion 51 and may have a side surface 53. The peripheral portion 52 may have a uniform thickness. Therefore, the side surface 53 of the peripheral portion 52 may not be parallel to the side surface 63 of the peripheral portion 62 of the solder pad 6. In some embodiments, the peripheral portion 52 of the conductive structure 5 may taper towards the substrate 2. The peripheral portion 52 of the conductive structure 5 may horizontally overlap with the upper portion 45 of the vertical transistor 4 and the peripheral portion 62 of the solder pad 6. In some embodiments, the conductive structure 5 may be omitted.

[0163] The soldering pad 6 can also be referred to as a "landing pad". The soldering pad 6 can be disposed on or above the conductive structure 5 (e.g., on the vertical transistor 4). The cross-section of the soldering pad 6 can be generally inverted "U" shaped. The cross-section of the soldering pad 6 can include a cap-like structure. The soldering pad 6 can include a main body portion 61 and a peripheral portion 62. The main body portion 61 can be disposed on the main body portion 51 of the conductive structure 5. The main body portion 61 can gradually taper from the substrate 2.

[0164] The peripheral portion 62 may extend downward from the main body portion 61 and may have a side surface 63. The peripheral portion 62 of the solder pad 6 may taper towards the substrate 2. Therefore, the thickness of the upper portion 621 of the peripheral portion 62 may be greater than the thickness of the lower portion 622 of the peripheral portion 62. In some embodiments, the peripheral portion 62 may have a uniform thickness. The peripheral portion 62 of the solder pad 6 may horizontally overlap with the upper portion 45 of the vertical transistor 4, the peripheral portion 52 of the conductive structure 5, and the top 38 of the upper structure 3. The peripheral portion 52 of the conductive structure 5 may be disposed between the inclined surface 48 (or a side surface of the vertical transistor 4) of the vertical transistor 4 and the peripheral portion 62 of the solder pad 6.

[0165] One embodiment of this disclosure provides a semiconductor structure including a substrate, an upper structure, a vertical transistor, and a bonding pad. The upper structure is disposed on the substrate. The vertical transistor is disposed on the upper structure. The bonding pad is disposed on the vertical transistor. A peripheral portion of the bonding pad horizontally overlaps with an upper portion of the vertical transistor.

[0166] Another embodiment of this disclosure provides a semiconductor structure including a substrate, an upper structure, a vertical transistor, and a bonding pad. The substrate includes a capacitor. The upper structure is disposed on the substrate. The vertical transistor is disposed in the upper structure and electrically connected to the capacitor. The vertical transistor extends beyond a top of the upper structure. The bonding pad is disposed on the vertical transistor.

[0167] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a stacked structure including a substrate and an upper structure disposed on the substrate. The method also includes forming a hole extending through the upper structure. The method further includes forming a vertical transistor in the hole, wherein an upper portion of the vertical transistor extends beyond the upper structure. The method also includes forming a bonding pad on the vertical transistor.

[0168] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0169] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor structure, comprising: One base; The upper structure is set on this base; A vertical transistor is disposed in the upper structure; as well as A solder pad is disposed on the vertical transistor, wherein a peripheral portion of the solder pad horizontally overlaps with an upper portion of the vertical transistor.

2. The semiconductor structure of claim 1, wherein the substrate includes a capacitor disposed therein.

3. The semiconductor structure of claim 2, wherein the capacitor is a ring structure surrounding a central portion, and the central portion includes a base material and a conductive material, wherein the conductive material is disposed on the base material and electrically connected to the vertical transistor.

4. The semiconductor structure of claim 3, wherein the capacitor includes a first electrode, an intermediate layer and a second electrode, wherein the second electrode is disposed on one side surface of the central portion, the intermediate layer is disposed on one side surface of the second electrode, and the first electrode is disposed on the side surface of the intermediate layer.

5. The semiconductor structure of claim 4, wherein the conductive material at the center contacts the second electrode.

6. The semiconductor structure of claim 5, wherein an upper surface of the conductive material at the center, an upper surface of the second electrode, and an upper surface of the intermediate layer are substantially coplanar with each other.

7. The semiconductor structure of claim 4, wherein the first electrode is disposed below the conductive material at the center.

8. The semiconductor structure of claim 3, wherein a vertical projection of the vertical transistor is located within the central portion.

9. The semiconductor structure of claim 1, wherein the upper structure comprises a lower insulating layer, a conductive layer and an upper insulating layer, wherein the lower insulating layer is disposed on the substrate, the conductive layer is disposed on the lower insulating layer and the upper insulating layer is disposed on the conductive layer.

10. The semiconductor structure of claim 1, wherein the vertical transistor extends beyond the upper structure.

11. The semiconductor structure of claim 1, wherein the solder pad is generally inverted "U" shaped in cross-section.

12. The semiconductor structure of claim 11, wherein the solder pad further comprises a main portion disposed above the vertical transistor, wherein the peripheral portion of the solder pad extends from the main portion of the solder pad.

13. The semiconductor structure of claim 1, wherein the peripheral portion of the solder pad tapers towards the substrate.

14. The semiconductor structure of claim 1, wherein the upper structure includes a top that contacts the vertical transistor, wherein the vertical transistor extends beyond the top of the upper structure.

15. The semiconductor structure of claim 1, wherein a height of the vertical transistor is greater than a maximum thickness of the upper structure.

16. The semiconductor structure of claim 1, wherein the upper structure defines a first recess and a second recess, wherein the first recess is recessed from a top of the upper structure, and the second recess is recessed from the first recess.

17. The semiconductor structure of claim 16, wherein both the first recess and the second recess taper towards the substrate.

18. The semiconductor structure of claim 16, wherein an inner surface of the second recess is continuous and aligned with one side surface of the peripheral portion of the solder pad.

19. The semiconductor structure of claim 16, wherein the upper structure includes a protrusion defining the first recess, wherein the protrusion tapers away from the substrate.

20. The semiconductor structure of claim 19, wherein the protrusion contacts the vertical transistor.

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