semiconductor devices

Abstract

A semiconductor device includes: a substrate; a semiconductor pattern extending on the substrate in a first direction parallel to an upper surface of the substrate; word lines extending on the semiconductor pattern in a second direction intersecting the first direction; bit lines connected to one end of the semiconductor pattern and extending upward in a third direction perpendicular to the upper surface of the substrate; and a data storage element connected to the other end of the semiconductor pattern. The bit lines include a first portion connected to the semiconductor pattern and a second portion extending from the first portion in the first direction. The width of the first portion in the second direction is greater than the width of the second portion in the second direction. The configuration of the bit lines provides sufficient contact area with the semiconductor pattern and reduces electrical coupling between adjacent bit lines.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] There is a need for technologies to improve the integration density of semiconductor devices. For two-dimensional semiconductor devices, the integration density is mainly determined by the area occupied by a unit memory cell, and this aspect of the integration density can be affected by the level of fine patterning technology.

[0003] However, the integration density of two-dimensional semiconductor devices, while continuously increasing, remains limited due to the expensive equipment required for fine patterning techniques. Therefore, three-dimensional semiconductor devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0004] This disclosure attempts to provide a semiconductor device with high reliability.

[0005] In addition, this disclosure attempts to provide a semiconductor device with improved electrical characteristics.

[0006] Embodiments of this disclosure provide a semiconductor device comprising: a substrate; a semiconductor pattern positioned on the substrate and extending in a first direction parallel to an upper surface of the substrate; a word line positioned on the semiconductor pattern and extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a bit line connected to one end of the semiconductor pattern and extending upward in a third direction perpendicular to the upper surface of the substrate; and a data storage element connected to the other end of the semiconductor pattern, the other end of the semiconductor pattern being opposite to one end of the semiconductor pattern, wherein the bit line includes a first portion connected to the semiconductor pattern and a second portion extending from the first portion in the first direction, and the width of the first portion in the second direction is greater than the width of the second portion in the second direction.

[0007] Embodiments of this disclosure provide a semiconductor device, comprising: a substrate; a first semiconductor pattern and a second semiconductor pattern positioned on the substrate and extending in a first direction parallel to an upper surface of the substrate; a first word line and a second word line extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction, and positioned to overlap the first semiconductor pattern and the second semiconductor pattern, respectively; a first bit line connected to the first semiconductor pattern and the second semiconductor pattern on opposite sides in the first direction; a second bit line positioned separately from the first bit line in the second direction; and a pair of first intermediate insulating patterns positioned between the first bit line and the second bit line; and a second intermediate insulating pattern positioned between the pair of first intermediate insulating patterns.

[0008] Embodiments of this disclosure provide a semiconductor device comprising: a substrate; a semiconductor pattern positioned on the substrate and extending in a first direction parallel to an upper surface of the substrate; word lines positioned on the semiconductor pattern and extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a pair of bit lines connected to one end of the semiconductor pattern, extending upward in a third direction perpendicular to the upper surface of the substrate, and spaced apart from each other in the second direction; and a data storage element connected to the other end of the semiconductor pattern, the other end of the semiconductor pattern being opposite to one end of the semiconductor pattern, wherein each bit line includes a first portion and a second portion, the first portion being positioned on one side of the bit line and connected to the semiconductor pattern stacked upward in a third direction, the second portion extending from the first portion in the first direction, and the width of the first portion in the second direction being greater than the width of the second portion in the second direction.

[0009] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a first trench between semiconductor patterns spaced apart from each other in a first direction; forming a first intermediate insulating layer in the first trench; forming a second intermediate insulating layer on the first intermediate insulating layer; patterning the first and second intermediate insulating layers to form a second trench including a first intermediate insulating pattern, a second intermediate insulating pattern, a first region located between the first intermediate insulating patterns, and a second region located between the second intermediate insulating patterns; and forming bit lines in the second trench, wherein the width of the first region in a second direction is greater than the width of the second region in a second direction.

[0010] In the method for manufacturing a semiconductor device according to an embodiment, the first intermediate insulating layer and the second intermediate insulating layer have different etching selectivity.

[0011] In the method for manufacturing a semiconductor device according to an embodiment, the first intermediate insulating layer and the second intermediate insulating layer have different component ratios.

[0012] In the method for manufacturing a semiconductor device according to an embodiment, the first intermediate insulating layer and the second intermediate insulating layer comprise the same insulating material.

[0013] In the method for manufacturing a semiconductor device according to an embodiment, the second trench has an H-shaped structure in a plan view.

[0014] In a method for manufacturing a semiconductor device according to an embodiment, the first region is located on the opposite side of the second trench.

[0015] In a method for manufacturing a semiconductor device according to an embodiment, a bit line includes a first portion formed in a first region and a second portion formed in a second region, wherein the width of the first portion in a second direction is greater than the width of the second portion in the second direction.

[0016] In a method for manufacturing a semiconductor device according to an embodiment, the second trench has a T-shaped structure in a plan view.

[0017] In a method for manufacturing a semiconductor device according to an embodiment, a first region is positioned on one side of a second trench.

[0018] In the method for manufacturing a semiconductor device according to an embodiment, the step of patterning a first intermediate insulating layer and a second intermediate insulating layer to form a second trench further includes forming a shielding pattern on the second intermediate insulating layer.

[0019] In a method for manufacturing a semiconductor device according to an embodiment, a first region of a second trench extends upward in a third direction, thereby exposing the end portion of a semiconductor pattern.

[0020] According to the implementation method, a semiconductor device with high reliability can be provided.

[0021] Furthermore, according to the embodiments, a semiconductor device with improved electrical characteristics can be provided. Attached Figure Description

[0022] Figure 1 This is a perspective view schematically showing a portion of a semiconductor device according to an embodiment.

[0023] Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0024] Figure 3 It is the edge of the semiconductor device according to the implementation method Figure 2 The planar diagram intercepted by line A-A'.

[0025] Figure 4 and Figure 5 It is a semiconductor device according to other embodiments. Figure 2 The planar diagram intercepted by line A-A'.

[0026] Figures 6 to 19 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0027] Figure 20 This is a cross-sectional view of a semiconductor device according to another embodiment.

[0028] Figure 21 It is a semiconductor device according to another embodiment. Figure 20 The planar diagram intercepted by line A-A'.

[0029] Figure 22 This is a cross-sectional view of a semiconductor device according to another embodiment.

[0030] Figure 23 It is a semiconductor device according to another embodiment. Figure 22 The planar diagram intercepted by line A-A'.

[0031] Figures 24 to 33 This is a diagram illustrating a method for manufacturing a semiconductor device according to another embodiment. Detailed Implementation

[0032] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the invention. The invention can be implemented in many different forms, and is not limited to the embodiments described herein.

[0033] To clearly illustrate the invention, parts irrelevant to the description have been omitted, and the same or similar components are referred to by the same reference numerals throughout the specification.

[0034] Furthermore, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated for ease of explanation, and therefore the invention is not necessarily limited to what is shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0035] Furthermore, when a portion such as a layer, membrane, region, or plate is described as being "above" or "on" another portion, this includes not only cases where the portion is "directly above" the other portion, but also cases where there are other portions between the portion and the other portion. In contrast, when an element is described as being "directly above" another element, there is no intermediate element. Moreover, being "above" or "on" a reference portion means being located above or below the reference portion, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity.

[0036] Furthermore, unless explicitly stated otherwise, the word “contains” and its variations shall be understood to imply inclusion of the stated element but not exclusion of any other element.

[0037] Additionally, throughout the instruction manual, when "in a plane" is mentioned, it means when the target part is viewed from above, and when "in a cross-section" is mentioned, it means when the target part is viewed from the side in a vertically cut cross-section.

[0038] Figure 1 This is a perspective view schematically showing a portion of a semiconductor device according to an embodiment. Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment. Figure 3 It is along the semiconductor device according to the implementation method Figure 2 The planar diagram intercepted by line A-A'.

[0039] Reference Figure 1 and Figure 2 A semiconductor device according to one embodiment may include a substrate 100, a bit line BL, a semiconductor pattern SP, and a word line WL.

[0040] For ease of explanation, Figure 1 Only the bit line BL, word line WL, and semiconductor pattern SP are shown; some components included in the semiconductor device are omitted.

[0041] The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may have a shape extending in a first direction DR1 and a second direction DR2. The second direction DR2 may be a direction intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. For example, the first direction DR1 and the second direction DR2 may be directions parallel to the upper surface of the substrate 100. Although not shown, additional peripheral circuitry may be provided on the substrate 100.

[0042] The bit line BL extending on the third direction DR3 can be located on the upper surface of the substrate 100. The bit line BL can have a shape extending on the third direction DR3 perpendicular to the upper surface of the substrate 100. The third direction DR3 can be a direction intersecting the first direction DR1 and the second direction DR2. For example, the second direction DR2 and the third direction DR3 can be orthogonal to each other. The third direction DR3 and the first direction DR1 can be orthogonal to each other. For example, the third direction DR3 can be a direction perpendicular to the upper surface of the substrate 100.

[0043] A field insulating layer 105 may be located on the substrate 100. The field insulating layer 105 may be located between the bit line BL and the substrate 100. The field insulating layer 105 may be located within the substrate 100. The upper surface of the field insulating layer 105 may be located at the same level as the upper surface of the substrate 100, but is not limited thereto. The upper surface of the field insulating layer 105 may be located above the upper surface of the substrate 100. For example, the field insulating layer 105 may be located above the upper surface of the substrate 100. Semiconductor patterns SP may be stacked on a third-direction DR3. Due to the field insulating layer 105, some of the semiconductor patterns SP positioned at the bottom on the third-direction DR3 may not be connected to the bit line BL.

[0044] The field insulating layer 105 may have a shape extending in the second direction DR2. The field insulating layer 105 may be connected to a plurality of bit lines BL spaced apart from each other in the second direction DR2. For example, the field insulating layer 105 may be positioned below the plurality of bit lines BL.

[0045] The field insulating layer 105 can serve to block the electrical connection between the substrate 100 and the bit line BL. The field insulating layer 105 may include an insulating material. As an example, the field insulating layer 105 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxide nitride (SiON), but is not limited thereto.

[0046] Bit lines BL can be positioned on substrate 100. Multiple bit lines BL can be positioned on substrate 100. Bit lines BL can be positioned on field insulating layer 105. For example, multiple bit lines BL can be positioned on one field insulating layer 105. Multiple bit lines BL can be positioned spaced apart along the second direction DR2.

[0047] Bit line BL can be connected to a semiconductor pattern SP positioned on the opposite side. For example, bit line BL can be connected to a semiconductor pattern SP positioned on the opposite side of a first direction DR1. Bit line BL can be connected to a semiconductor pattern SP stacked on a third direction DR3.

[0048] The bit line BL can be positioned to overlap with the semiconductor pattern SP in the first direction DR1. The bit line BL can overlap with the end of the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the bit line BL can be positioned not to overlap with the semiconductor pattern SP in the second direction DR2.

[0049] Bit line BL may include a first portion BL_a connected to a semiconductor pattern SP positioned on opposite sides and a second portion BL_b located between the first portions BL_a. Bit line BL may include a pair of first portions BL_a positioned spaced apart in a first direction DR1 and a second portion BL_b positioned between the pair of first portions BL_a. For example, bit line BL may have an "H" shape in a plan view. For example, corner portions of bit line BL may have an angular shape, but are not limited thereto.

[0050] The first portion BL_a can be connected to a semiconductor pattern SP. The first portion BL_a can cover a side surface of the semiconductor pattern SP and a portion of its upper and lower surfaces. The first portion BL_a can contact a side surface of the semiconductor pattern SP and a portion of its upper and lower surfaces. The first portion BL_a can be connected to multiple semiconductor patterns SP stacked on a third direction DR3. For example, a bit line BL can include a pair of first portions BL_a positioned spaced apart on a first direction DR1.

[0051] The first portion BL_a can have a shape extending in the third direction DR3. Alternatively, as an example, the first portion BL_a can have a shape extending in the second direction DR2. Compared to the second portion BL_b, the first portion BL_a can have a relatively larger width in the second direction DR2. For example, a bit line BL can include a second portion BL_b positioned between a pair of first portions BL_a spaced apart in the first direction DR1.

[0052] The first portion BL_a of the bit line BL can be positioned to overlap with the semiconductor pattern SP in the first direction DR1. The first portion BL_a can also be positioned to overlap with the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the first portion BL_a can be positioned so as not to overlap with the semiconductor pattern SP in the second direction DR2. The width of the first portion BL_a in the second direction DR2 can be greater than the width of the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the width of the first portion BL_a in the second direction DR2 can be equal to or less than the width of the semiconductor pattern SP in the second direction DR2.

[0053] The second part BL_b can be positioned between the first part BL_a. The second part BL_b can be connected to the first part BL_a positioned on the opposite side.

[0054] The second part BL_b can have a shape extending in the third direction DR3. Alternatively, as an example, the second part BL_b can have a shape extending in the first direction DR1. Compared to the first part BL_a, the second part BL_b can have a relatively smaller width in the second direction DR2.

[0055] The second part BL_b of the bit line BL can be positioned to overlap with the semiconductor pattern SP in the first direction DR1.

[0056] Bit line BL may include a conductive material. The first portion BL_a and the second portion BL_b of bit line BL may include conductive materials. The conductive material may be, for example, a doped semiconductor material (such as doped silicon (doped Si) or doped germanium (doped Ge)), a conductive metal nitride (such as titanium nitride (TiN) or tantalum nitride (TaN)), a metal (such as tungsten (W), titanium (Ti), or tantalum (Ta)) or a metal semiconductor compound (such as tungsten silicide (WSi)). x ), cobalt silicide (CoSi) x ) or titanium silicide (TiSi) x One of them.

[0057] exist Figure 1 In the middle, three bit lines BL are positioned on the substrate 100. Figure 3 In this embodiment, four bit lines BL are positioned on the substrate 100, but the invention is not limited thereto. Multiple bit lines BL can be positioned on the substrate 100 at intervals from each other in the first direction DR1 and the second direction DR2.

[0058] A semiconductor pattern SP can be positioned on the substrate 100. The semiconductor pattern SP can have a shape extending in the first direction DR1. For example, the semiconductor pattern SP can have a strip shape extending in the first direction DR1. The semiconductor pattern SP can partially protrude from the second insulating layer 230 toward the data storage element DS.

[0059] A semiconductor pattern SP can be connected to a bit line BL. One end of the semiconductor pattern SP can be connected to the bit line BL. The semiconductor pattern SP can be positioned to penetrate the first insulating layer 210. For example, one end of the semiconductor pattern SP can be covered by the bit line BL, but is not limited thereto. For example, one end of the semiconductor pattern SP can be in contact with one end of the bit line BL.

[0060] For example, a semiconductor pattern SP may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). A semiconductor pattern SP may include a channel region, a first impurity region, and a second impurity region.

[0061] The first and second impurity regions can represent regions of a semiconductor pattern SP that are doped with impurities. The first and second impurity regions can have either n-type or p-type conductivity. For example, the first and second impurity regions can be located at each end of the semiconductor pattern SP.

[0062] One end of the semiconductor pattern SP can be connected to the bit line BL. The semiconductor pattern SP can be connected to the bit line BL in a manner that partially protrudes into the bit line BL, but is not limited to this. For example, one side surface of one end of the semiconductor pattern SP may not protrude, but may instead contact the side surface of the bit line BL.

[0063] The other end of the semiconductor pattern SP can be connected to the data storage element DS. For example, a first impurity region of the semiconductor pattern SP can be connected to the bit line BL, and a second impurity region of the semiconductor pattern SP can be connected to the data storage element DS. A channel region can be located between the first and second impurity regions.

[0064] Multiple semiconductor patterns SP can be positioned on substrate 100, and the multiple semiconductor patterns SP can be stacked to be spaced apart from each other along a third direction DR3. For example, multiple semiconductor patterns SP connected to a bit line BL can be positioned to be spaced apart from each other along a third direction DR3. Alternatively, multiple semiconductor patterns SP can be positioned along a bit line BL that is positioned to be spaced apart from each other in a first direction DR1 and a second direction DR2.

[0065] The word line WL can be positioned on the semiconductor pattern SP. The word line WL can have a shape extending along the second direction DR2. For example, the word line WL can have a strip shape extending along the second direction.

[0066] For example, a word line WL can be positioned to surround a semiconductor pattern SP. The word line WL can cover a central region of the semiconductor pattern SP. The word line WL can cover a channel region located between a first impurity region and a second impurity region of the semiconductor pattern SP. The word line WL can extend in a second direction DR2, and the semiconductor pattern SP can be positioned to penetrate the word line WL in a first direction DR1. In some embodiments, a pair of word lines can be positioned above and below each semiconductor pattern SP, respectively. Multiple word lines WL can be positioned on the substrate 100, and multiple word lines WL can be stacked while being spaced apart from each other in a third direction DR3.

[0067] The word line (WL) may include a conductive material. The conductive material may be any of a semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0068] A semiconductor device according to one embodiment may further include a first insulating layer 210, a gate insulating pattern 220, a second insulating layer 230, a first spacer 242, a second spacer 244, and an interlayer insulating layer 250.

[0069] The first insulating layer 210 may be disposed on one side surface of the bit line BL. The first insulating layer 210 may be positioned between the bit line BL and the first spacer 242. Alternatively, the first insulating layer 210 may be positioned between the bit line BL and the interlayer insulating layer 250.

[0070] A gate insulating pattern 220 may be positioned between a word line WL and a semiconductor pattern SP. The semiconductor pattern SP and the word line WL may be positioned spaced apart on a third direction DR3, with the gate insulating pattern 220 interposed therebetween. The gate insulating pattern 220 may be further positioned between a first spacer 242 and the semiconductor pattern SP. Alternatively, as an example, the gate insulating pattern 220 may be further positioned between the word line WL and a second spacer 244. For example, the gate insulating pattern 220 may have an "L" shape in its cross-section on the first direction DR1 and the third direction DR3, but is not limited thereto. For example, the gate insulating pattern 220 may have a straight line shape extending along the semiconductor pattern SP in its cross-section on the first direction DR1 and the third direction DR3.

[0071] The gate insulating pattern 220 may include an insulating material. The gate insulating pattern 220 may include a silicon oxide film, a silicon oxide nitride film, a high-k film having a higher dielectric constant than a silicon oxide film, or a combination thereof. The high-k dielectric film may be made of a metal oxide or a metal oxide nitride. For example, high-k dielectric films that can be used as the gate insulating pattern 220 may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or combinations thereof.

[0072] The second insulating layer 230 may be positioned between the second spacer 244 and the semiconductor pattern SP. The second insulating layer 230 may also be positioned between the second spacer 244 and the data storage element DS. For example, the second insulating layer 230 may have an "L" shape in the cross-section on the first direction DR1 and the third direction DR3, but is not limited thereto.

[0073] The first spacer 242 may be positioned between the word line WL and the bit line BL. The first spacer 242 may have a shape that surrounds the portion of the semiconductor pattern SP between the word line WL and the bit line BL. The first spacer 242 may be positioned between the first insulating layer 210 and the word line WL.

[0074] The second spacer 244 can be positioned between the word line WL and the data storage element DS. The first spacer 242 and the second spacer 244 can be positioned on opposite sides of the word line WL. The second spacer 244 can be in the form of a portion surrounding the semiconductor pattern SP between the word line WL and the data storage element DS. The second spacer 244 can be positioned between the second insulating layer 230 and the interlayer insulating layer 250.

[0075] The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise insulating materials. The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise the same insulating material. Optionally, at least one of the first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise different insulating materials. For example, the first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise at least one of silicon oxide (SiO), silicon nitride (SiN), or silicon nitride oxide (SiON), but are not limited thereto. The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may be formed simultaneously or separately.

[0076] Interlayer insulating layer 250 can be disposed between multiple semiconductor patterns SP. The multiple semiconductor patterns SP can be positioned spaced apart on a third-direction DR3, and interlayer insulating layer 250 can be positioned between the multiple semiconductor patterns SP spaced apart on the third-direction DR3.

[0077] Interlayer insulating layer 250 can be positioned above word lines WL. Interlayer insulating layer 250 can be positioned above first spacer 242. Additionally, interlayer insulating layer 250 can be positioned between multiple word lines WL. The multiple word lines WL can be positioned spaced apart on a third-direction DR3, and interlayer insulating layer 250 can be positioned between the multiple word lines WL spaced apart on the third-direction DR3. Interlayer insulating layer 250 can be positioned between second spacer 244 and bit line BL. Interlayer insulating layer 250 can be positioned between second spacer 244 and first insulating layer 210. For example, one side surface of interlayer insulating layer 250 can contact first insulating layer 210, and the other side surface of interlayer insulating layer 250 can contact second spacer 244.

[0078] The interlayer insulating layer 250 may include an insulating material. As an example, the interlayer insulating layer 250 may include, but is not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxide nitride (SiON).

[0079] A semiconductor device according to one embodiment may include a data storage element DS.

[0080] Data storage element DS can be connected to semiconductor pattern SP. The other end of semiconductor pattern SP can be connected to data storage element DS. Multiple data storage elements DS can be positioned to be stacked on a third-party DR3.

[0081] The data storage element DS may include a first electrode 310, a dielectric layer 320, and a second electrode 330.

[0082] The first electrode 310 may be connected to the other end of the semiconductor pattern SP. One end of the first electrode 310 may be connected to the semiconductor pattern SP. The first electrode 310 may cover the other side surface of the semiconductor pattern SP, as well as a portion of the upper and lower surfaces. The first electrode 310 may have a shape surrounding the other end of the semiconductor pattern SP. The first electrode 310 may be positioned at substantially the same level as the semiconductor pattern SP. The first electrode 310 may be aligned parallel to the semiconductor pattern SP in a first direction DR1.

[0083] The first electrode 310 may have a shape extending in the first direction DR1. The first electrode 310 may have a strip or column shape extending in the first direction DR1, but is not limited thereto. For example, the first electrode 310 may have a cylindrical shape with a hollow center. The width of the first electrode 310 in the second direction DR2 and / or the third direction DR3 may be substantially the same as the width of the semiconductor pattern SP in the second direction DR2 and / or the third direction DR3, but is not limited thereto. For example, the width of the first electrode 310 in the second direction DR2 and / or the third direction DR3 may be different from the width of the semiconductor pattern SP in the second direction DR2 and / or the third direction DR3.

[0084] A dielectric layer 320 may be positioned on the first electrode 310. The dielectric layer 320 may be positioned between the first electrode 310 and the second electrode 330. The dielectric layer 320 may cover the upper surface, lower surface, and side surface of the first electrode 310. For example, the side surface of the first electrode 310 may refer to a surface perpendicular to the upper surface of the substrate 100. Additionally, the dielectric layer 320 may cover a portion of another side surface of the first electrode 310. The other side surface of the first electrode 310 may refer to a surface opposite to one side surface of the first electrode 310, at which the first electrode 310 and the semiconductor pattern SP are connected. The other side surface of the first electrode 310 may be covered by the dielectric layer 320. The dielectric layer 320 may be conformally disposed on the first electrode 310. The dielectric layer 320 may be disposed on the second insulating layer 230. The first spacer 242 and the second spacer 244 may be placed on the interlayer insulating layer 250, the second insulating layer 230 may be placed on the second spacer 244, and the dielectric layer 320 may be placed on the second insulating layer 230. For example, the second spacer 244 may be placed on the side surface of the interlayer insulating layer 250.

[0085] The dielectric layer 320 may include an insulating material. The dielectric layer 320 may include a silicon oxide film, a silicon oxide nitride film, a high-k dielectric film having a higher dielectric constant than a silicon oxide film, or a combination thereof. The high-k dielectric film may be made of a metal oxide or a metal oxide nitride. For example, high-k dielectric films that can be used as the dielectric layer 320 may include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or combinations thereof.

[0086] The second electrode 330 can be positioned on the dielectric layer 320. The second electrode 330 can fill the space between multiple first electrodes 310. Multiple data storage elements DS stacked on the third-direction DR3 can share a single second electrode 330.

[0087] The second electrode 330 may include a conductive material. The second electrode 330 may include, for example, metallic materials (such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru)), conductive metal nitrides (such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN)), and conductive metal oxides (such as ruthenium oxide (RuO)). x ), iridium oxide (IrO), indium tin oxide (ITO), molybdenum oxide (MoO) x ) and vanadium oxide (VO x At least one of the following: doped semiconductor materials (such as doped silicon (doped Si) or doped germanium (doped Ge)).

[0088] A semiconductor device according to one embodiment may include a first intermediate insulating pattern 261, a second intermediate insulating pattern 271, a protective layer 410, pad spacers 420, and pad electrodes 430.

[0089] The first intermediate insulating pattern 261 can be positioned between multiple bit lines BL. The first intermediate insulating pattern 261 can be positioned between multiple bit lines BL in the second direction DR2. The first intermediate insulating pattern 261 can be positioned on the opposite side of the second intermediate insulating pattern 271 in the first direction DR1, and the width of the first intermediate insulating pattern 261 on the opposite side of the second intermediate insulating pattern 271 in the first direction is the same. A pair of first intermediate insulating patterns 261 can be positioned on the opposite side of the second intermediate insulating pattern 271 in the first direction DR1. The first intermediate insulating pattern 261 can contact the other end of the semiconductor pattern SP. The first intermediate insulating pattern 261 can contact the bit line BL. The first intermediate insulating pattern 261 can contact the first portion BL_a of the bit line BL. The first intermediate insulating pattern 261 can be positioned so as not to overlap with the bit line BL in the first direction DR1, but is not limited thereto. The first intermediate insulating pattern 261 can be positioned to overlap with the bit line BL in the second direction DR2. The first intermediate insulating pattern 261 can be positioned to overlap with the first portion BL_a in the second direction DR2. The first intermediate insulating pattern 261 can be positioned to overlap with the end of the semiconductor pattern SP in the second direction DR2. The first intermediate insulating pattern 261 can be positioned on the opposite side of the first portion BL_a in the second direction DR2. The first intermediate insulating pattern 261 can be positioned between a plurality of first portions BL_a.

[0090] The first intermediate insulation pattern 261 may extend along the bit line BL in the third direction DR3. The width of the first intermediate insulation pattern 261 in the second direction DR2 may be smaller than the width of the second intermediate insulation pattern 271 in the second direction DR2. The width of the first intermediate insulation pattern 261 in the first direction DR1 may be smaller than the width of the second intermediate insulation pattern 271 in the first direction DR1, but is not limited thereto.

[0091] The second intermediate insulating pattern 271 can be positioned between multiple bit lines BL. The second intermediate insulating pattern 271 can be positioned between multiple bit lines BL in the second direction DR2. The second intermediate insulating pattern 271 can be positioned between first intermediate insulating patterns 261. The second intermediate insulating pattern 271 can be positioned between a pair of first intermediate insulating patterns 261 in the first direction DR1. The second intermediate insulating pattern 271 can contact the bit line BL. The second intermediate insulating pattern 271 can contact the second portion BL_b of the bit line BL. The second intermediate insulating pattern 271 can be positioned to overlap with the second portion BL_b in the second direction DR2. The second intermediate insulating pattern 271 can be positioned to overlap with the bit line BL in the first direction DR1. The second intermediate insulating pattern 271 can be positioned to overlap with the first portion BL_a in the first direction DR1. The second intermediate insulating pattern 271 can be positioned on the opposite side of the second portion BL_b in the second direction DR2. The second intermediate insulating pattern 271 can be positioned between multiple second portions BL_b.

[0092] The second intermediate insulation pattern 271 may extend along the bit line BL in the third direction DR3. The width of the second intermediate insulation pattern 271 in the second direction DR2 may be greater than the width of the first intermediate insulation pattern 261 in the second direction DR2. The width of the second intermediate insulation pattern 271 in the first direction DR1 may be greater than the width of the first intermediate insulation pattern 261 in the first direction DR1, but is not limited thereto.

[0093] The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may include insulating materials. For example, the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may include at least one of silicon oxide (SiO), silicon nitride (SiN) and silicon nitride oxide (SiON), but are not limited thereto.

[0094] The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may include, but are not limited to, the same insulating material, and may include different insulating materials. The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may have different etching rates. The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may have different etching rates under the same conditions. For example, the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may have different etching rates depending on conditions such as the formation method, formation temperature, post-heat treatment method, and post-heat treatment temperature.

[0095] The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can have different composition ratios. The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can comprise the same material, but the composition ratios of the materials can be different. The first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can exhibit different etching rates due to the difference in composition ratios. The first intermediate insulating pattern 261 can have a higher etching rate than the second intermediate insulating pattern 271. Compared to the second intermediate insulating pattern 271, the first intermediate insulating pattern 261 can have a higher etching rate under the same conditions. For example, the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can comprise silicon oxide (SiO2) with different etching rates. x Additionally, the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 may have silicon oxide (SiO2) as a component. x The different ratios of silicon (Si) and oxygen (O) in the material. However, this is not the only possibility. For example, when the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 are mixtures of various insulating materials, differences in etching rates may occur depending on the content ratio of the insulating materials.

[0096] Protective layer 410 may be positioned on top of multiple semiconductor patterns SP stacked on third-direction DR3. Protective layer 410 may be positioned on top of multiple word lines WL stacked on third-direction DR3. Protective layer 410 may be positioned on top of data storage elements DS stacked on third-direction DR3. For example, protective layer 410 may be positioned at the top layer of a semiconductor device.

[0097] The protective layer 410 may have the form of extending in the first direction DR1 and the second direction DR2.

[0098] The protective layer 410 serves to protect the semiconductor pattern SP, word line WL, and data storage element DS. As an example, the protective layer 410 may include silicon (Si), but is not limited to this. For instance, the protective layer 410 may include materials such as silicon oxide (SiO2). x Insulating materials made of silicon nitride (SiN).

[0099] The pad spacer 420 can be positioned above the bit line BL. The pad spacer 420 can be positioned between the protective layer 410 and the pad electrode 430.

[0100] The pad spacer 420 can be positioned on the opposite side of the pad electrode 430. The pad spacer 420 can have a shape surrounding the sidewall of the pad electrode 430.

[0101] The pad spacers 420 may include an insulating material. For example, the pad spacers 420 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxide nitride (SiON), but are not limited thereto.

[0102] The pad electrode 430 can be positioned above the bit line BL. The pad electrode 430 can be connected to the bit line BL. The pad electrode 430 can be positioned to penetrate the protective layer 410.

[0103] In the planar view, the pad electrode 430 can have a shape substantially the same as that of the bit line BL. For example, the bit line BL can have an "H" shape in the planar view, and the pad electrode 430 can have an "H" shape in the planar view, but is not limited to this. For example, the pad electrode 430 can have a polygonal shape such as a circle, ellipse, rectangle, etc. in the planar view, and can be modified in various ways as needed.

[0104] The pad electrode 430 may include a conductive material. For example, the pad electrode 430 may include a metallic material (such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru)), a conductive metal nitride (such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN)), or a conductive metal oxide (such as ruthenium oxide (RuO)). x ), iridium oxide (IrO), indium tin oxide (ITO), molybdenum oxide (MoO) x ) and vanadium oxide (VO x At least one of the following: doped semiconductor materials (such as doped silicon (doped Si) or doped germanium (doped Ge)).

[0105] Figure 4 and Figure 5 It is a semiconductor device according to other embodiments. Figure 2 The planar diagram intercepted by line A-A'.

[0106] Descriptions of parts that are essentially the same as in the previous example will be omitted, and the explanations will focus on the differences.

[0107] Reference Figure 4 The semiconductor device may include a bit line BL, which includes a first portion BL_a and a second portion BL_b. The corners of the bit line BL may have a rounded shape rather than an angular shape. The corners of the first portion BL_a and the second portion BL_b of the bit line BL may have a rounded shape. Therefore, the corners of the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 that contact the bit line BL may also have a rounded shape.

[0108] Reference Figure 5 The semiconductor device may further include a first intermediate insulating pattern 261 in contact with a first portion BL_a of the bit line BL, a second intermediate insulating pattern 271 in contact with a second portion BL_b, and a third intermediate insulating pattern 272 positioned between the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271.

[0109] The third intermediate insulating pattern 272 may contact a portion of the bit line BL. The third intermediate insulating pattern 272 may be positioned on the opposite side of the second intermediate insulating pattern 271 in the first direction DR1. The third intermediate insulating pattern 272 may simultaneously contact the first portion BL_a and the second portion BL_b of the bit line BL. The third intermediate insulating pattern 272 may have the form of extending in the third direction DR3.

[0110] The third intermediate insulation pattern 272 may include an insulating material. As an example, the third intermediate insulation pattern 272 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon nitride oxide (SiON), but is not limited thereto.

[0111] The third intermediate insulating pattern 272 may include, but is not limited to, the same insulating material as the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271, and may include different insulating materials. The third intermediate insulating pattern 272 may have an etching rate different from that of the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271.

[0112] For example, the third intermediate insulating pattern 272 can be used as an etching stop film.

[0113] Figures 6 to 19 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0114] Reference Figure 6 and Figure 7 A first trench TRC1 can be formed between semiconductor patterns SP that are spaced apart from each other on the first direction DR1 and stacked on the third direction DR3. The first trench TRC1 can be located between interlayer insulating layers 250 that are spaced apart from each other on the first direction DR1. The first trench TRC1 can be located between word lines WL that are spaced apart from each other on the first direction DR1. The first trench TRC1 can be located on the substrate 100.

[0115] The bottom surface of the first trench TRC1 can be positioned below the upper surface of the substrate 100. For example, the first trench TRC1 can be formed by removing a portion of the substrate 100. A semiconductor pattern SP can partially protrude from the first insulating layer 210 toward the first trench TRC1. The first trench TRC1 can have a shape extending in a second direction DR2 and a third direction DR3.

[0116] A first intermediate insulating layer 260 may be formed within the first trench TRC1. The first intermediate insulating layer 260 may be formed on the first insulating layer 210. The first intermediate insulating layer 260 may be formed on the substrate 100. The first intermediate insulating layer 260 may cover the ends of the semiconductor pattern SP. The first intermediate insulating layer 260 may be formed on the side surface of the protective layer 410.

[0117] The first intermediate insulating layer 260 may include an insulating material. As an example, the first intermediate insulating layer 260 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxide nitride (SiON), but is not limited thereto.

[0118] Next, refer to Figure 8 and Figure 9 A second intermediate insulating layer 270 can be formed on the first intermediate insulating layer 260. The second intermediate insulating layer 270 can be positioned within the first trench TRC1. The second intermediate insulating layer 270 can fill the first trench TRC1.

[0119] The second intermediate insulating layer 270 may not be in contact with the semiconductor pattern SP. The second intermediate insulating layer 270 may be formed at a distance from the semiconductor pattern SP, and the first intermediate insulating layer 260 may be interposed therebetween.

[0120] The second intermediate insulating layer 270 may include an insulating material. As an example, the second intermediate insulating layer 270 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon nitride oxide (SiON), but is not limited thereto.

[0121] The first intermediate insulating layer 260 and the second intermediate insulating layer 270 may include, but are not limited to, the same insulating material, and may include different insulating materials. The first intermediate insulating layer 260 and the second intermediate insulating layer 270 may have different etch rates. The first intermediate insulating layer 260 and the second intermediate insulating layer 270 may have different composition ratios. The first intermediate insulating layer 260 and the second intermediate insulating layer 270 may have different etch rates due to different composition ratios. The first intermediate insulating layer 260 may have a higher etch rate than the second intermediate insulating layer 270. For example, the first intermediate insulating layer 260 and the second intermediate insulating layer 270 may include silicon oxide (SiO) with different etch rates. For example, even if the first intermediate insulating layer 260 and the second intermediate insulating layer 270 contain the same insulating material, they may have different etch rates due to different formation process conditions, etc. For example, the first intermediate insulating layer 260 and the second intermediate insulating layer 270 may include silicon oxide (SiO), and the first intermediate insulating layer 260 and the second intermediate insulating layer 270 may have different silicon (Si) and oxygen (O) composition ratios.

[0122] Next, refer to Figure 10 and Figure 11 Patterning of the first intermediate insulating layer 260 and the second intermediate insulating layer 270 can be performed.

[0123] The patterning of the first intermediate insulating layer 260 can be performed by removing a portion of it. The field insulating layer 105 and the first intermediate insulating pattern 261 can be formed by patterning the first intermediate insulating layer 260. The second intermediate insulating pattern 271 can be formed by patterning the second intermediate insulating layer 270. The second trench TRC2 can be formed by patterning the first intermediate insulating layer 260 and the second intermediate insulating layer 270.

[0124] The second trench TRC2 may include a first region TRC2_a and a second region TRC2_b.

[0125] The first region TRC2_a can be located on the opposite side of the second trench TRC2. The first region TRC2_a can be located between the first intermediate insulating patterns 261. The first region TRC2_a can be formed to overlap with the first intermediate insulating patterns 261 in the second direction DR2. The other end of the semiconductor pattern SP can be exposed by the first region TRC2_a. The width of the first region TRC2_a in the second direction DR2 can be greater than the width of the second region TRC2_b in the second direction DR2.

[0126] The first region TRC2_a can be positioned to overlap with the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the first region TRC2_a can be positioned to not overlap with the semiconductor pattern SP in the second direction DR2. The width of the first region TRC2_a in the second direction DR2 can be greater than the width of the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the width of the first region TRC2_a in the second direction DR2 can be equal to or less than the width of the semiconductor pattern SP in the second direction DR2.

[0127] The second region TRC2_b can be located between the first regions TRC2_a. The second region TRC2_b can be located between the second intermediate insulation patterns 271. The second region TRC2_b can be formed to overlap with the second intermediate insulation pattern 271 in the second direction DR2. The width of the second region TRC2_b in the second direction DR2 can be smaller than the width of the first region TRC2_a in the second direction DR2.

[0128] The first region TRC2_a and the second region TRC2_b can have the form of extending onto DR3 in a third direction.

[0129] The second groove TRC2 can have an "H" shape in the plan view, but is not limited to this. For example, the second groove TRC2 can have shapes such as "T", circle, ellipse, square or polygon in the plan view.

[0130] A field insulating layer 105 can be positioned on the bottom surface of the second trench TRC2. The field insulating layer 105 can be positioned on the substrate 100. The field insulating layer 105 can have a form extending along the second trench TRC2 in a second direction DR2. A first intermediate insulating pattern 261 can be positioned on the substrate 100. The first intermediate insulating pattern 261 can be positioned on the field insulating layer 105. The first intermediate insulating pattern 261 can have a form extending in a third direction DR3. A second intermediate insulating pattern 271 can be positioned on the substrate 100. The second intermediate insulating pattern 271 can be positioned on the field insulating layer 105. The second intermediate insulating pattern 271 can have a form extending in a third direction DR3.

[0131] For example, the upper surfaces of the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can be positioned at the same level as the upper surface of the protective layer 410.

[0132] The first intermediate insulation pattern 261 can be positioned such that it is spaced apart in the second direction DR2 by the second groove TRC2. The second groove TRC2 can be positioned in the second direction DR2 between the first intermediate insulation patterns 261.

[0133] The ends of the semiconductor pattern SP can be exposed by the second trench TRC2.

[0134] The second trench TRC2 can be formed without using an additional mask. For example, the difference in width between the first region TRC2_a and the second region TRC2_b of the second trench TRC2 in the second direction DR2 can be caused by the difference in etching rates of the first intermediate insulating layer 260 and the second intermediate insulating layer 270. However, it is not limited to this; for example, photoresist material and an additional mask can be used to pattern the first intermediate insulating layer 260 and the second intermediate insulating layer 270. The photoresist layer and the additional mask can be used to form the second trench TRC2.

[0135] Wet etching processes can be used to pattern the first intermediate insulating layer 260 and the second intermediate insulating layer 270, but are not limited thereto.

[0136] Next, refer to Figure 12 and Figure 13 Bit line BL can be formed within the second trench TRC2. Bit line BL can have a shape corresponding to the shape of the second trench TRC2. Bit line BL can have an "H" shape in a plan view.

[0137] Bit line BL may include a first portion BL_a and a second portion BL_b. The first portion BL_a may cover the end of the semiconductor pattern SP. The first portion BL_a may be positioned between the first intermediate insulating patterns 261. For example, the first portion BL_a may be formed to overlap with the semiconductor pattern SP in the first direction DR1 and the third direction DR3, but may be formed not to overlap with the semiconductor pattern SP in the second direction DR2.

[0138] The second part BL_b can be positioned between the first parts BL_a located on the opposite side. The second part BL_b can be positioned between the second intermediate insulating patterns 271.

[0139] The first part BL_a and the second part BL_b can have a shape that extends in the third direction DR3. The width of the first part BL_a in the second direction DR2 can be greater than the width of the second part BL_b in the second direction DR2.

[0140] Next, refer to Figure 14 and Figure 15 The upper portion of the bit line BL can be removed to form the third trench TRC3.

[0141] The third trench TRC3 can be formed on the bit line BL. The protective layer 410 can be positioned on the opposite side of the third trench TRC3. The third trench TRC3 can be positioned between a plurality of first intermediate insulation patterns 261 and a plurality of second intermediate insulation patterns 271.

[0142] The upper surfaces of the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can be positioned at substantially the same level as the upper surface of the protective layer 410. The planar shape of the third trench TRC3 can be substantially the same as the planar shape of the bit line BL. The third trench TRC3 can be formed using the first intermediate insulating pattern 261, the second intermediate insulating pattern 271, and the protective layer 410 as a mask, and can be formed without using an additional mask.

[0143] Next, refer to Figure 16 and Figure 17 Pad spacers 420 can be formed within the third trench TRC3. Pad spacers 420 can be positioned on bit lines BL. Pad spacers 420 can be formed in a shape surrounding the sidewalls of the third trench TRC3. Pad spacers 420 can be conformally formed along the sidewalls of the third trench TRC3.

[0144] For example, the pad spacer 420 can be formed by depositing insulating material in the third trench TRC3 and then removing the portion positioned on the bottom surface, but is not limited thereto.

[0145] The process of forming pad spacers 420 can use a first intermediate insulating pattern 261, a second intermediate insulating pattern 271, and a protective layer 410 formed in a previous process as a mask.

[0146] Next, refer to Figure 18 and Figure 19 The pad electrode 430 can be filled within the third trench TRC3. The pad electrode 430 can be positioned on the bit line BL. The pad electrode 430 can be electrically connected to the bit line BL. The pad electrode 430 can have a planar shape substantially the same as the planar shape of the bit line BL. The pad spacer 420 can be positioned between the pad electrode 430 and the protective layer 410.

[0147] The process of forming the pad electrode 430 can use the first intermediate insulating pattern 261, the second intermediate insulating pattern 271 and the protective layer 410 formed in the previous process as a mask.

[0148] Figure 20 This is a cross-sectional view of a semiconductor device according to another embodiment. Figure 21 It is a semiconductor device according to another embodiment. Figure 20The plan view intercepted by line A-A'. Descriptions of parts substantially the same as those previously described will be omitted, and the differences will be the main focus.

[0149] Reference Figure 20 and Figure 21 Bit lines BL can be connected to semiconductor patterns SP stacked on a third direction DR3. Multiple bit lines BL can be positioned spaced apart along a first direction DR1 and a second direction DR2. Bit lines BL can be connected to semiconductor patterns SP positioned on one side rather than both sides based on the first direction DR1. A second intermediate insulating pattern 271 can be positioned between the multiple bit lines BL. A pair of bit lines BL can be positioned spaced apart from each other along the first direction DR1, and a second intermediate insulating pattern 271 can be positioned between the pair of bit lines BL. A pair of bit lines BL spaced apart along the first direction DR1 can be positioned facing each other. Bit lines BL can have a "T" shape in a plan view, but are not limited to this.

[0150] A second intermediate insulating pattern 271 may be positioned between a plurality of pad electrodes 430. The second intermediate insulating pattern 271 may extend from the field insulating layer 105 to the upper surface of the pad electrodes 430 on a third direction DR3. A pair of pad electrodes 430 may be positioned spaced apart from each other on a first direction DR1, and the second intermediate insulating pattern 271 may be positioned between the pair of pad electrodes 430. The pad electrodes 430 spaced apart along the first direction DR1 may be positioned facing each other. The pad electrodes 430 may have a "T" shape in a plan view, but are not limited thereto.

[0151] Bit line BL may include a first portion BL_a and a second portion BL_b. Unlike the previous implementation, bit line BL may include a first portion BL_a and a second portion BL_b connected to the first portion BL_a.

[0152] The first part BL_a may have a shape extending on the third direction DR3. The first part BL_a may be connected to a plurality of semiconductor patterns SP stacked on the third direction DR3. The first part BL_a may be positioned between the first intermediate insulating patterns 261. The first part BL_a may have a wider width on the second direction DR2 than the second part BL_b.

[0153] The first portion BL_a of the bit line BL can be positioned to overlap with the semiconductor pattern SP in the first direction DR1. The first portion BL_a can also be positioned to overlap with the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the first portion BL_a can be positioned not to overlap with the semiconductor pattern SP in the second direction DR2. The width of the first portion BL_a in the second direction DR2 can be greater than the width of the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the width of the first portion BL_a in the second direction DR2 can be equal to or less than the width of the semiconductor pattern SP in the second direction DR2.

[0154] The second portion BL_b may have a shape extending in the third direction DR3. The second portion BL_b may have a width smaller than that of the first portion BL_a in the second direction DR2. The second portion BL_b may have a shape extending from the first portion BL_a along the first direction DR1. A second intermediate insulating pattern 271 may be positioned between the plurality of second portions BL_b. The sidewalls of the second portions BL_b may be covered by the second intermediate insulating pattern 271.

[0155] Figure 22 This is a cross-sectional view of a semiconductor device according to another embodiment. Figure 23 It is a semiconductor device according to another embodiment. Figure 22 The plan view intercepted by line A-A'. Descriptions of parts substantially the same as those previously described will be omitted, and the differences will be the main focus.

[0156] Reference Figure 22 and Figure 23 A shielding pattern 440 can be positioned between bit lines BL spaced apart from each other along the first direction DR1. The shielding pattern 440 can be positioned on the substrate 100. The shielding pattern 440 can be positioned on the field insulating layer 105. The shielding pattern 440 can be positioned on the second intermediate insulating pattern 271. The shielding pattern 440 can be positioned spaced apart from the bit lines BL. The shielding pattern 440 can be positioned spaced apart from the bit lines BL and has a shielding insulating layer 442 therebetween.

[0157] A shielding pattern 440 may be positioned between a plurality of pad electrodes 430. A second intermediate insulating pattern 271 may extend from the field insulating layer 105 to the upper surface of the pad electrodes 430 on a third direction DR3. A pair of pad electrodes 430 may be positioned spaced apart from each other in a first direction DR1, and the shielding pattern 440 may be positioned between the pair of pad electrodes 430. The pad electrodes 430 spaced apart along the first direction DR1 may be positioned facing each other. The pad electrodes 430 may have a "T" shape in a plan view, but are not limited thereto.

[0158] The shielding pattern 440 serves to prevent electrical interference between bit lines BL. The shielding pattern 440 may include a conductive material. For example, the shielding pattern 440 may include a metal. For example, the shielding pattern 440 may include metallic materials such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru), but is not limited thereto.

[0159] The shielding insulating layer 442 can be positioned on the shielding pattern 440. The shielding insulating layer 442 can be conformally disposed on the shielding pattern 440. The shielding insulating layer 442 can be positioned between the shielding pattern 440 and the bit line BL. The shielding insulating layer 442 can be positioned between the shielding pattern 440 and the second portion BL_b of the bit line BL. Furthermore, the shielding insulating layer 442 can be positioned between the shielding pattern 440 and the pad electrode 430.

[0160] The shielding insulation layer 442 may include an insulating material. As an example, the shielding insulation layer 442 may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon nitride oxide (SiON), but is not limited thereto.

[0161] The second intermediate insulating pattern 271 can be positioned between the shielding pattern 440 and the field insulating layer 105. The second intermediate insulating pattern 271 can be positioned between bit lines BL spaced apart in the second direction DR2. The portion of the second intermediate insulating pattern 271 positioned below the shielding pattern 440 can have a form that extends in the second direction DR2, and the portion positioned between the bit lines BL can have a form that extends in the third direction DR3.

[0162] Figures 24 to 33 This is a diagram illustrating a method for manufacturing a semiconductor device according to another embodiment. Descriptions of parts that are substantially the same as the manufacturing method of the previously described embodiment will be omitted, and the description will focus on the differences.

[0163] Reference Figure 24 and Figure 25 A first intermediate insulating layer 260 can be formed within the first trench TRC1.

[0164] Next, refer to Figure 26 and Figure 27 A second intermediate insulating layer 270 can be formed on the first intermediate insulating layer 260. The second intermediate insulating layer 270 can be conformally formed on the first intermediate insulating layer 260 without filling the first trench TRC1. Therefore, empty spaces can be left in the first trench TRC1.

[0165] Next, refer to Figure 28 and Figure 29A shielding pattern 440 and a shielding insulating layer 442 can be formed on the second intermediate insulating layer 270. The shielding pattern 440 and the shielding insulating layer 442 can fill the first trench TRC1.

[0166] For example, a shielding insulating layer 442 can be conformally formed within the first trench TRC1 and on the second intermediate insulating layer 270, and then a shielding pattern 440 can be formed to fill the first trench TRC1.

[0167] Next, refer to Figure 30 and Figure 31 Patterning of the first intermediate insulating layer 260 and the second intermediate insulating layer 270 can be performed.

[0168] The patterning of the first intermediate insulating layer 260 can be performed by removing a portion of it. The field insulating layer 105 and the first intermediate insulating pattern 261 can be formed by patterning the first intermediate insulating layer 260. The second trench TRC2 can be formed by patterning the first intermediate insulating layer 260 and the second intermediate insulating layer 270.

[0169] The second trench TRC2 may include a first region TRC2_a and a second region TRC2_b.

[0170] The first region TRC2_a can be located on one side of the second trench TRC2. The first region TRC2_a can be located between the first intermediate insulating patterns 261. The first region TRC2_a can be formed to overlap with the first intermediate insulating patterns 261 in the second direction DR2. The other end of the semiconductor pattern SP can be exposed by the first region TRC2_a. The width of the first region TRC2_a in the second direction DR2 can be greater than the width of the second region TRC2_b in the second direction DR2.

[0171] The first region TRC2_a can be positioned to overlap with the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the first region TRC2_a can be positioned to not overlap with the semiconductor pattern SP in the second direction DR2. The width of the first region TRC2_a in the second direction DR2 can be greater than the width of the semiconductor pattern SP in the second direction DR2. However, this is not a limitation; in some embodiments, the width of the first region TRC2_a in the second direction DR2 can be equal to or less than the width of the semiconductor pattern SP in the second direction DR2.

[0172] The second region TRC2_b may have a shape that extends from the first region TRC2_a in the first direction DR1. The second region TRC2_b may be positioned between the second intermediate insulation patterns 271. The second region TRC2_b may be formed to overlap with the second intermediate insulation pattern 271 in the second direction DR2. The width of the second region TRC2_b in the second direction DR2 may be smaller than the width of the first region TRC2_a in the second direction DR2.

[0173] The first region TRC2_a and the second region TRC2_b can have the form of extending onto DR3 in a third direction.

[0174] The second trench TRC2 can have a "T" shape in the plan view.

[0175] A field insulating layer 105 can be positioned on the bottom surface of the second trench TRC2. The field insulating layer 105 can be positioned on the substrate 100. The field insulating layer 105 can have a shape extending in the second direction DR2. A first intermediate insulating pattern 261 can be positioned on the substrate 100. The first intermediate insulating pattern 261 can be positioned on the field insulating layer 105. The first intermediate insulating pattern 261 can have a form extending in the third direction DR3. A second intermediate insulating pattern 271 can be positioned on the substrate 100. The second intermediate insulating pattern 271 can be positioned on the field insulating layer 105. The second intermediate insulating pattern 271 can have a form extending in the third direction DR3.

[0176] For example, the upper surfaces of the first intermediate insulating pattern 261 and the second intermediate insulating pattern 271 can be positioned at the same level as the upper surface of the protective layer 410.

[0177] The first intermediate insulating pattern 261 can be positioned to be spaced apart in the second direction DR2 via the second trench TRC2. The second intermediate insulating pattern 271 can be positioned to be spaced apart in the second direction DR2 via the second trench TRC2. The ends of the semiconductor pattern SP can be exposed by the second trench TRC2.

[0178] The second trench TRC2 can be formed without using an additional mask. For example, the difference in width between the first region TRC2_a and the second region TRC2_b of the second trench TRC2 in the second direction DR2 can be caused by the difference in etching rates of the first intermediate insulating layer 260 and the second intermediate insulating layer 270. However, it is not limited to this; for example, photoresist material and a separate mask can be used to pattern the first intermediate insulating layer 260 and the second intermediate insulating layer 270. For example, a photoresist layer and a separate mask can be used to form the second trench TRC2. Wet etching processes can be used to pattern the first intermediate insulating layer 260 and the second intermediate insulating layer 270, but are not limited to this.

[0179] Next, refer to Figure 32 and Figure 33 Bit line BL can be formed within the second trench TRC2. Bit line BL can have a shape corresponding to the shape of the second trench TRC2. Bit line BL can have a "T" shape in a plan view.

[0180] Bit line BL may include a first portion BL_a and a second portion BL_b. The first portion BL_a may cover the end of the semiconductor pattern SP. The first portion BL_a may be covered by a first intermediate insulating pattern 261. For example, the first portion BL_a may be formed to overlap with the semiconductor pattern SP in the first direction DR1 and the third direction DR3, but may be formed not to overlap with the semiconductor pattern SP in the second direction DR2. The second portion BL_b may have a shape extending from the first portion BL_a in the first direction DR1. The second portion BL_b may be positioned between the second intermediate insulating patterns 271. The first portion BL_a and the second portion BL_b may have a shape extending in the third direction DR3. The width of the first portion BL_a in the second direction DR2 may be greater than the width of the second portion BL_b in the second direction DR2.

[0181] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention as defined in the claims also fall within the scope of the present invention.

[0182] Cross-reference to related applications

[0183] This application claims priority and benefit to Korean Patent Application No. 10-2025-0016915, filed with the Korean Intellectual Property Office on February 10, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Substrate; A semiconductor pattern is positioned on the substrate and extends in a first direction parallel to the upper surface of the substrate; The letter line is positioned on the semiconductor pattern and extends in a second direction, which is parallel to the upper surface of the substrate and intersects the first direction; Bit lines are connected to one end of the semiconductor pattern and extend upward on a third side perpendicular to the upper surface of the substrate; as well as A data storage element is connected to the other end of the semiconductor pattern, the other end of which is opposite to the first end of the semiconductor pattern. The bit line includes a first portion connected to the semiconductor pattern and a second portion extending from the first portion in the first direction, wherein the width of the first portion in the second direction is greater than the width of the second portion in the second direction.

2. The semiconductor device of claim 1, further comprising a first intermediate insulating pattern in contact with the first portion of the bit line and a second intermediate insulating pattern in contact with the second portion of the bit line.

3. The semiconductor device of claim 2, wherein, The first intermediate insulation pattern and the second intermediate insulation pattern have different component ratios.

4. The semiconductor device of claim 1, further comprising a field insulating layer positioned between the substrate and the bit line.

5. The semiconductor device of claim 1, wherein, The bit line includes a plurality of first portions located on the opposite side of the second portion, and the bit line has an H-shaped structure in a plan view.

6. The semiconductor device of claim 1, further comprising a shielding pattern positioned on one side of the bit line.

7. The semiconductor device of claim 6, further comprising a shielding insulating layer positioned between the shielding pattern and the bit line.

8. The semiconductor device of claim 6, wherein, The shielding pattern extends upward in the second direction and the third direction.

9. The semiconductor device according to claim 1, wherein, The bit line has a T-shaped structure in the plan view.

10. The semiconductor device according to claim 1, The system further includes pad electrodes, which are disposed above the bit line and electrically connected to the bit line. wherein The pad electrode has a planar shape that is substantially the same as the planar shape of the bit line.

11. A semiconductor device, comprising: Substrate; A first semiconductor pattern and a second semiconductor pattern are positioned on the substrate and extend in a first direction parallel to the upper surface of the substrate; The first word line and the second word line extend in a second direction parallel to the upper surface of the substrate and intersecting the first direction, and are positioned to overlap with the first semiconductor pattern and the second semiconductor pattern, respectively. The first bit line and the second bit line are connected to the first bit line on opposite sides of the first semiconductor pattern in the first direction, and the second bit line is positioned separately from the first bit line in the second direction. as well as A pair of first intermediate insulation patterns and a second intermediate insulation pattern, wherein the pair of first intermediate insulation patterns are positioned between the first bit line and the second bit line, and the second intermediate insulation pattern is positioned between the pair of first intermediate insulation patterns.

12. The semiconductor device of claim 11, wherein, The width of the first intermediate insulating pattern in the second direction is smaller than the width of the second intermediate insulating pattern in the second direction.

13. The semiconductor device of claim 11, wherein, The first bit line and the second bit line each include a first portion that contacts the first intermediate insulation pattern and a second portion that contacts the second intermediate insulation pattern.

14. The semiconductor device of claim 11, wherein, The first bit line and the second bit line are positioned to overlap with the second intermediate insulation pattern in the first direction.

15. The semiconductor device of claim 11, wherein, The widths of the first intermediate insulating patterns located on opposite sides of the second intermediate insulating pattern are the same in the first direction.

16. A semiconductor device, comprising: Substrate; A semiconductor pattern is positioned on the substrate and extends in a first direction parallel to the upper surface of the substrate; The letter line is positioned on the semiconductor pattern and extends in a second direction, which is parallel to the upper surface of the substrate and intersects the first direction; A pair of bit lines, connected to one end of the semiconductor pattern, extending upward in a third direction perpendicular to the upper surface of the substrate, and spaced apart from each other in the second direction; as well as A data storage element is connected to the other end of the semiconductor pattern, the other end of which is opposite to the first end of the semiconductor pattern. Each bit line includes a first portion and a second portion, the first portion being located on one side of the bit line and connected to the semiconductor pattern stacked upwards on the third side, the second portion extending from the first portion in the first direction, and the width of the first portion in the second direction being greater than the width of the second portion in the second direction.

17. The semiconductor device of claim 16, wherein, Each bitline has a T-shaped structure in the planar diagram.

18. The semiconductor device of claim 16, further comprising a shielding pattern positioned between the pair of bit lines.

19. The semiconductor device of claim 18, further comprising a shielding insulating layer positioned between the shielding pattern and each bit line.

20. The semiconductor device of claim 16, further comprising a first intermediate insulating pattern contacting the first portion of each bit line and a second intermediate insulating pattern contacting the second portion of each bit line.

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