Semiconductor device and method of manufacturing the same, storage system

Abstract

This application discloses a semiconductor device and its manufacturing method, as well as a memory system, to simplify the manufacturing process of semiconductor devices. The semiconductor device includes a channel structure, word lines, a capacitor structure, and a dielectric structure. The channel structure includes a first channel portion and a second channel portion interconnected; the first channel portion extends along a first direction, and the second channel portion is disposed around the first channel portion. The word lines surround at least a portion of the second channel portion. The capacitor structure is connected to the second channel portion. The dielectric structure includes a first dielectric portion and a second dielectric portion interconnected; the first dielectric portion is located between the word lines and the second channel portion, and the second dielectric portion surrounds at least a portion of the second channel portion and is located between the word lines and the capacitor structure; the dimension of the second dielectric portion along the first direction is larger than the dimension of the first dielectric portion along the first direction.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a semiconductor device and its manufacturing method, and a storage system. Background Technology

[0002] With the development of semiconductor process technology, the manufacturing process of Dynamic Random Access Memory (DRAM) will evolve from planar processes to three-dimensional (3D) structure processes to increase storage capacity. Currently, 3D stacked DRAM faces the problem of complex manufacturing processes. Summary of the Invention

[0003] This application provides a semiconductor device and its manufacturing method, as well as a storage system, to at least partially solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a semiconductor device is provided, including a channel structure, a word line, a capacitor structure, and a dielectric structure. The channel structure includes a first channel portion and a second channel portion interconnected; the first channel portion extends along a first direction, and the second channel portion is disposed around the first channel portion. The word line surrounds at least a portion of the second channel portion. The capacitor structure is connected to the second channel portion. The dielectric structure includes a first dielectric portion and a second dielectric portion interconnected; the first dielectric portion is located between the word line and the second channel portion, and the second dielectric portion surrounds at least a portion of the second channel portion and is located between the word line and the capacitor structure, wherein the dimension of the second dielectric portion along the first direction is larger than the dimension of the first dielectric portion along the first direction.

[0005] According to a second aspect of this application, a method for manufacturing a semiconductor device is provided, comprising: A multilayer structure is formed, the multilayer structure including an insulating layer and a sacrificial layer stacked along a first direction. A first initial word line portion and a sacrificial fill structure are formed in the stacked structure. The sacrificial fill structure includes a first sacrificial portion and a second sacrificial portion. The first sacrificial portion penetrates the stacked structure along the first direction. The second sacrificial portion is disposed around the first sacrificial portion. The second sacrificial portion and the first initial word line portion are located between adjacent insulating layers. The first initial word line portion surrounds the second sacrificial portion. A capacitor groove is formed in the stacked structure, and a portion of the first initial word line portion is removed through the capacitor groove, with the remaining first initial word line portion constituting the first word line portion; wherein, the capacitor groove is located on one side of the sacrificial filler structure and includes a first capacitor groove and a second capacitor groove that are interconnected, the first capacitor groove penetrates the stacked structure along the first direction, and the second capacitor groove is located between adjacent insulating layers and exposes the first word line portion. An isolation dielectric structure and a capacitor structure are formed in the capacitor groove. The capacitor structure is located in the capacitor groove and is in contact with the second sacrificial portion. The isolation dielectric structure is located between the capacitor structure and the first word line portion.

[0006] According to a third aspect of this application, a storage system is also provided, the storage system comprising the semiconductor devices described in any of the above embodiments. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a planar structure of a semiconductor device provided in an exemplary embodiment of this application; Figure 2 The exemplary embodiments provided in this application are along Figure 1 A schematic diagram of a cross-sectional structure of the semiconductor device shown, taken by the A-A' tangent line. Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor device provided in an exemplary embodiment of this application; Figures 4-14 The figure is a schematic diagram of the process of manufacturing a semiconductor device provided in an exemplary embodiment of this application; Figure 15 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application.

[0008] Explanation of reference numerals in the attached figures: 100. Semiconductor devices; 11. Channel structure; 111. First channel section; 112. Second channel section; 12. Character line; 120. First initial character line section; 121. First character line section; 121A. First character line end face; 121B. Second character line end face; 122. Second character line section; 13. Capacitor structure; 131. First electrode structure; 1311. Common part; 1312. Extension part; 132. Second electrode structure; 133. Capacitor dielectric layer; 13A. Capacitor structure group; 14. Dielectric structure; 141. First dielectric section; 142. Second dielectric section; 143. Third dielectric section; 15. Bit line; 161. Word line isolation structure; 162. Isolation structure; 17. Substrate; 18. Laminated structure; 181. Sacrificial layer; 182. Insulating layer; 19. Sacrificial filling structure; 191. First sacrificial part; 192. Second sacrificial part; 211. First through opening; 212. First lateral opening; 22. Gate oxide layer; 23. Second opening; 231. Second through opening; 232. Second lateral opening; 24. Capacitor slot; 241. First capacitor slot; 242. Second capacitor slot; 25. Initial dielectric layer; 251. Isolation dielectric structure; Z, first direction; X, second direction; Y, third direction; 200, Controller; 300, Storage System. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0010] Please see Figure 1 and Figure 2 As shown, this application provides a semiconductor device 100, which includes a channel structure 11, a word line 12, a capacitor structure 13, and a dielectric structure 14.

[0011] The channel structure 11 includes a first channel section 111 and a second channel section 112.

[0012] Each first channel portion 111 extends along a first direction Z. A plurality of first channel portions 111 are arranged along a second direction X and a third direction Y. Each first channel portion 111 can be an internally hollow columnar structure, but is not limited thereto. The shape of the cross-section of the first channel portion 111 can include at least one of a circle and a rectangle, and the cross-section of the first channel portion 111 can be perpendicular to the first direction Z.

[0013] Any two of the first direction Z, the second direction X, and the third direction Y intersect each other. In one example, any two of the first direction Z, the second direction X, and the third direction Y are perpendicular to each other, but this is not a limitation. In another example, the angle between any two of the first direction Z, the second direction X, and the third direction Y can be acute or obtuse.

[0014] Multiple second channel portions 112 are arranged in an array along a first direction Z, a second direction X, and a third direction Y. A second channel portion 112 is disposed around a corresponding first channel portion 111 and connected to a corresponding first channel portion 111 and a capacitor structure 13. Word lines 12 surround at least a portion of the second channel portions 112. At least two second channel portions 112 spaced apart along the first direction Z are connected to a first channel portion 111. Therefore, the second channel portions 112 with multiple transistors disposed along the first direction Z share a single first channel portion 111, thereby enabling the semiconductor device 100 to achieve a three-dimensional stacked design to improve the storage density of the semiconductor device 100. Furthermore, different second channel portions 112 along each of the second direction X and the third direction Y are respectively connected to different corresponding first channel portions 111. The cross-sectional shape of each second channel portion 112 is annular, and the cross-section of each second channel portion 112 may be perpendicular to the first direction Z.

[0015] In some embodiments, the second channel portion 112 includes a channel top surface, a channel bottom surface, and a channel side surface. The channel top surface and the channel bottom surface are disposed opposite to each other along a first direction Z and surround the first channel portion 111. The channel side surface connects between the channel top surface and the channel bottom surface and contacts the capacitor structure 13.

[0016] The channel structure 11 includes a semiconductor material. The semiconductor material may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline germanium, and oxide semiconductors. The oxide semiconductors include, but are not limited to, at least one of indium gallium zinc oxide (In-Ga-Zn-O, abbreviated as IGZO), indium gallium oxide (IGO), zinc oxide (ZnO), and indium zinc oxide. In one example, the channel structure 11 includes silicon.

[0017] In some embodiments, the semiconductor device 100 further includes a plurality of bit lines 15, each bit line 15 extending along a first direction Z. Each first channel portion 111 is disposed around and in contact with a corresponding bit line 15, that is, the first channel portion 111 surrounds and contacts a corresponding bit line 15. The bit line 15 includes a conductive material, which includes at least one of a metal nitride and a metal element.

[0018] In a memory cell (including a transistor and a capacitor structure 13), the capacitor structure 13 and the word line 12 are located on different sides of a corresponding channel structure 11. In some embodiments, along the third direction Y, the capacitor structure 13 and the word line 12 are located on opposite sides of the corresponding channel structure 11.

[0019] Multiple capacitor structures 13 are arranged along a first direction Z, a second direction X, and a third direction Y. Each capacitor structure 13 includes a first electrode structure 131, a second electrode structure 132, and a capacitor dielectric layer 133. The first electrode structure 131 includes a common portion 1311 and an extension portion 1312. The common portion 1311 extends along the first direction Z, and the extension portion 1312 extends along the third direction Y toward the second channel portion 112. The second electrode structure 132 extends along the third direction Y, surrounds the extension portion 1312, and contacts the second channel portion 112. The capacitor dielectric layer 133 is located between the first electrode structure 131 and the second electrode structure 132. One common portion 1311 is connected to multiple extension portions 1312 arranged along the first direction Z, the second direction X, and the third direction Y. This reduces the overall number of first electrode structures 131 in the semiconductor device 100 and simplifies the manufacturing process of the first electrode structures 131. Furthermore, the first electrode structure 131 of the multiple capacitor structures 13 arranged along the first direction Z, the second direction X, and the third direction Y can be connected to the same potential.

[0020] In some embodiments, the plurality of capacitor structures 13 may include a plurality of capacitor structure groups 13A arranged at intervals along a third direction Y. A capacitor structure group 13A may be located between adjacent word lines 12 in the third direction Y and may include two capacitor structure subgroups arranged symmetrically along the third direction Y. Each capacitor structure subgroup includes a plurality of capacitor structures 13 arranged in an array along a first direction Z and a second direction X. The extensions 1312 of all capacitor structures 13 in a capacitor structure group 13A are connected to a common portion 1311, that is, all capacitor structures 13 in a capacitor structure group 13A share a common portion 1311.

[0021] Both the first electrode structure 131 and the second electrode structure 132 include a conductive material, which includes at least one of a metal nitride and a metallic element. The metal nitride includes at least one of titanium nitride, tantalum nitride, and tungsten nitride, and the metallic element may include tungsten, etc. In one example, the first electrode structure 131 may include a stack of a titanium nitride layer and a tungsten layer, and the second electrode structure 132 may include a titanium nitride layer.

[0022] The capacitor dielectric layer 133 may include an insulating material having a high dielectric constant. The insulating material having a high dielectric constant may include at least one of hafnium oxide, aluminum oxide, zirconium oxide, titanium dioxide, hafnium zirconium oxide, and barium strontium titanate.

[0023] Multiple word lines 12 are arranged at least along a first direction Z and a third direction Y. In one example, multiple word lines 12 are arranged along the first direction Z and a third direction Y. In another example, multiple word lines 12 are arranged along the first direction Z, a second direction X, and a third direction Y.

[0024] Each word line 12 includes a first word line portion 121, which serves as the gate of a transistor. At least two first word line portions 121 of a word line 12 are arranged at intervals along a second direction X.

[0025] In some embodiments, the first character line portion 121 surrounds the second channel portion 112 and is disposed around the first channel portion 111. In this case, the first character line portion 121 is a fully enclosed gate to improve the control capability of the first character line portion 121 over the second channel portion 112.

[0026] In some embodiments, the first word line portion 121 includes a first word line end face 121A, which is located on the side of the first word line portion 121 closer to the capacitor structure 13 and is recessed inward relative to the second channel portion 112 towards the first channel portion 111, thereby reducing the risk of a short circuit between the first word line end face 121A and the capacitor structure 13 when the second channel portion 112 contacts the capacitor structure 13. In some embodiments, the first word line end face 121A may include a curved surface.

[0027] In some embodiments, a word line 12 further includes a second word line portion 122, which provides gate signals for the gates of a plurality of transistors. The second word line portion 122 extends along a second direction X and is located on the side of the channel structure 11 opposite to the capacitor structure 13. A second word line portion 122 connects to at least two first word line portions 121 spaced apart along the second direction X, so as to provide gate signals for the gates of at least two transistors spaced apart along the second direction X through the second word line portion 122.

[0028] In some embodiments, the first character line portion 121 further includes a second character line end face 121B, which is disposed opposite to the first character line end face 121A along a third direction Y and contacts the second character line portion 122. The second character line end face 121B includes an arc-shaped surface to increase the contact area between the first character line portion 121 and the second character line portion 122 and reduce the contact resistance between the first character line portion 121 and the second character line portion 122.

[0029] Both the first word line portion 121 and the second word line portion 122 include a conductive material, which includes at least one selected from polycrystalline silicon, elemental metal, and metal nitride. In some embodiments, the material of the first word line portion 121 may be different from the material of the second word line portion 122. In one example, the first word line portion 121 may include a tungsten layer, and the second word line portion 122 may include a stack of a tungsten layer and titanium nitride. In some embodiments, the first word line portion 121 and the second word line portion 122 may include the same material to simplify the manufacturing process of the semiconductor device 100 by using the same material to fabricate the first word line portion 121 and the second word line portion 122.

[0030] In some embodiments, the semiconductor device 100 further includes a plurality of word line isolation structures 161, which are spaced apart along a third direction Y. Each word line isolation structure 161 extends along a first direction Z and a second direction X and is located on the side of the first word line portion 121 facing away from the capacitor structure 13. Two second word line portions 122 are located opposite to a word line isolation structure 161 along the third direction Y and are in contact with the word line isolation structure 161. Thus, for each layer in the multilayer structure spaced apart along the first direction Z, the word line isolation structures 161 can achieve electrical isolation between adjacent second word line portions 122 in the third direction Y.

[0031] In some embodiments, the word line isolation structure 161 may include an insulating material. The insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0032] In some embodiments, the semiconductor device 100 further includes a plurality of isolation structures 162. The plurality of isolation structures 162 are arranged along a second direction X and a third direction Y. Each isolation structure 162 extends along a first direction Z and a third direction Y, and is located between an adjacent second word line portion 122 and a second electrode structure 132 along the second direction X, so as to isolate the adjacent second word line portion 122 and the capacitor structure 13 along the second direction X.

[0033] In some embodiments, the isolation structure 162 may include an insulating material. The insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the isolation structure 162 may be made of the same material as the word line isolation structure 161, for example, both being silicon dioxide.

[0034] The medium structure 14 includes a first medium section 141 and a second medium section 142 that are interconnected.

[0035] The first dielectric portion 141 is located between the character line 12 and the second channel portion 112 to isolate the character line 12 from the second channel portion 112. The first dielectric portion 141 is also located between the character line 12 and the first channel portion 111 to isolate the character line 12 from the first channel portion 111.

[0036] The second dielectric portion 142 surrounds at least a portion of the second channel portion 112 and is located between the first word line portion 121 of the word line 12 and the capacitor structure 13, thereby isolating the word line 12 and the capacitor structure 13 and reducing the risk of short circuit between the word line 12 and the capacitor structure 13. In some embodiments, the dimension D2 of the second dielectric portion 142 along the first direction Z is larger than the dimension D1 of the first dielectric portion 141 along the first direction Z. This improves the reliability of the second dielectric portion 142 electrically isolating the word line 12 and the capacitor structure 13.

[0037] In some embodiments, the second dielectric portion 142 is located between the adjacent first word line end face 121A and the capacitor structure 13 and is disposed around the second channel portion 112 to effectively isolate the first word line end face 121A from the capacitor structure 13.

[0038] In some embodiments, the dielectric surface of the second dielectric portion 142 in contact with the second electrode structure 132 of the capacitor structure 13 may include a curved surface, which is beneficial to form an initial dielectric layer covering the first word line end face 121A and then obtain the second dielectric portion 142 through a back-etching process, so that the multiple second dielectric portions 142 are the same to improve the uniformity of the isolation performance of the multiple second dielectric portions 142.

[0039] In some embodiments, the dielectric structure 14 further includes third dielectric portions 143, and a plurality of third dielectric portions 143 are spaced apart along a first direction Z, a second direction X, and a third direction Y. The third dielectric portions 143 are located between adjacent capacitor structures 13, adjacent word lines 12, and adjacent second channel portions 112 in the first direction Z. Thus, the third dielectric portions 143 provide isolation for the adjacent capacitor structures 13, adjacent word lines 12, and adjacent second channel portions 112 in the first direction Z.

[0040] In some embodiments, each of the first dielectric portion 141, the second dielectric portion 142, and the third dielectric portion 143 may include an insulating material. The insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first dielectric portion 141, the second dielectric portion 142, and the third dielectric portion 143 may include the same material. In one example, the first dielectric portion 141, the second dielectric portion 142, and the third dielectric portion 143 may all include silicon dioxide.

[0041] In some embodiments, the semiconductor device 100 further includes a substrate 17. The channel structure 11, bit line 15, word line 12, capacitor structure 13, and dielectric structure 14 are all located on the substrate 17. The first channel portion 111 and the bit line 15 extend in directions perpendicular to the plane of the substrate 17. In some embodiments, the substrate 17 may include a semiconductor layer, which may include at least one of single-crystal silicon, single-crystal germanium, gallium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. In one example, the substrate 17 includes single-crystal silicon.

[0042] Please see Figure 3 This application also provides a method for manufacturing a semiconductor device 100, including steps S100, S101, S105 and S106.

[0043] Please see Figure 4Step S100 is executed, which forms a stacked structure 18, the stacked structure 18 including a sacrificial layer 181 and an insulating layer 182 stacked along the first direction Z.

[0044] The stacked structure 18 is formed on the substrate 17. In one example, the sacrificial layer 181 may include silicon nitride. In one example, the insulating layer 182 may include silicon oxide.

[0045] Please see Figures 5-8 Perform the above step S101, that is, form a first initial word line portion 120 and a sacrificial fill structure 19 in the stacked structure 18. The sacrificial fill structure 19 includes a first sacrificial portion 191 and a second sacrificial portion 192 that are connected to each other. The first sacrificial portion 191 penetrates the stacked structure 18 along the first direction Z. The second sacrificial portion 192 is disposed around the first sacrificial portion 191. The second sacrificial portion 192 and the first initial word line portion 120 are located between adjacent insulating layers 182. The first initial word line portion 120 surrounds the second sacrificial portion 192.

[0046] In some embodiments, forming a first initial word line portion 120 and a sacrificial fill structure 19 in the stacked structure 18 includes steps S1011, S1012, S1013 and S1015.

[0047] Please see Figure 5 In step S1011, a first through opening 211 is formed in the laminated structure 18. The first through opening 211 penetrates the insulating layer 182 and the sacrificial layer 181 along the first direction Z.

[0048] In some embodiments, a plurality of first through openings 211 may be arranged at intervals along a third direction Y. In some embodiments, a plurality of first through openings 211 may be arranged at intervals along both a second direction X and a third direction Y. The cross-section of the first through opening 211 may include at least one of a rectangle, an ellipse, and a circle, and the cross-section of the first through opening 211 is perpendicular to the first direction Z.

[0049] Please see Figure 6 In step S1012, the sacrificial layer 181 around the first through opening 211 is removed through the first through opening 211 to form a first lateral opening 212, which is located between adjacent insulating layers 182.

[0050] In some embodiments, each first through opening 211 is connected to a plurality of first lateral openings 212 which are spaced apart along a first direction Z. Adjacent first lateral openings 212 in a third direction Y also have a portion of a sacrificial layer 181.

[0051] Please see Figure 7In step S1013, a first initial character line portion 120 is formed on the side wall of the first lateral opening 212.

[0052] In some embodiments, word line conductive layers can be formed on the sidewalls of the first lateral opening 212 and the groove wall of the first through opening 211. The word line conductive layers on the groove wall of the first through opening 211 are removed to disconnect the word line conductive layers in the plurality of first lateral openings 212, thereby forming a plurality of first initial word line portions 120. The material of the first initial word line portions 120 may include conductive materials such as tungsten.

[0053] Please continue reading. Figure 7 After step S1013 and before step S1015, the method for manufacturing semiconductor device 100 further includes step S1014, namely forming a gate oxide layer 22, which covers the first initial word line portion 120 and the sidewall of the first through opening 211.

[0054] The gate oxide layer 22 serves to isolate the first word line portion 121 formed by the first initial word line portion 120 from the subsequently formed channel structure 11. The gate oxide layer 22 comprises an insulating material. In one example, the gate oxide layer 22 comprises silicon oxide.

[0055] Please see Figure 8 Step S1015 is executed, in which sacrificial filling structure 19 is filled into the first lateral opening 212 and the first through opening 211.

[0056] In some embodiments, the sacrificial filler structure 19 may include, but is not limited to, at least one of silicon nitride, silicon germanium, and polycrystalline silicon.

[0057] In some embodiments, please refer to Figure 9 Before step S105, the method of manufacturing semiconductor device 100 further includes step S102, namely forming a second opening 23. The second opening 23 is located between adjacent sacrificial fill structures 19 and includes a second through opening 231 and a second lateral opening 232. The second through opening 231 penetrates the stacked structure 18 along the first direction Z, and the second lateral opening 232 is located between adjacent insulating layers 182 and exposes the first initial word line portion 120.

[0058] In some embodiments, the second opening 23 is located between the adjacent sacrificial fill structure 19 and the first initial letter line portion 120 along the third direction Y. A second through opening 231 communicates with at least two second lateral openings 232 spaced apart along the first direction Z.

[0059] In some embodiments, please refer to Figure 10After step S102 and before step S105, the manufacturing method of semiconductor device 100 further includes step S103, that is, forming a second word line portion 122 in the second lateral opening 232, the second word line portion 122 contacting the first initial word line portion 120.

[0060] In some embodiments, please refer to Figure 10 The process of forming a second character line portion 122 in a second lateral opening 232 includes: forming a second initial character line portion (not shown in the figure), the second initial character line portion filling the second through opening 231 and the second lateral opening 232; and removing the second initial character line portion in the second through opening 231, the remaining second initial character line portion including a plurality of second character line portions 122 located on the opposite side of the second through opening 231. Thus, after forming the second initial character line portion, by removing the second initial character line portion in the second through opening 231, the second initial character line portions in the plurality of second lateral openings 232 are disconnected to form a plurality of second character line portions 122.

[0061] In some embodiments, each second word line portion 122 extends along a second direction X. Multiple second word line portions 122 on the same layer are spaced apart along a third direction Y. Adjacent second word line portions 122 on different layers are spaced apart along a first direction Z. The second initial word line portion may include a conductive material. In one example, the second word line portion 122 includes a stack of a tungsten layer and a titanium nitride layer, the titanium nitride layer being located between the tungsten layer and the first initial word line portion 120.

[0062] In some embodiments, please continue reading Figure 10 After step S103 and before step S105, the method for manufacturing semiconductor device 100 further includes step S104, which involves forming a word line isolation structure 161 in the second through opening 231. The word line isolation structure 161 is located between adjacent second word line portions 122 and is in contact with the adjacent second word line portions 122.

[0063] In some embodiments, the word line isolation structure 161 is located between adjacent second word line portions 122 in the third direction Y, and extends along the first direction Z and the second direction X.

[0064] In some embodiments, please also refer to Figure 10 and Figure 11 Perform the above step S105, that is, form a capacitor groove 24 in the stacked structure 18, and remove part of the first initial word line portion 120 through the capacitor groove 24, the remaining first initial word line constitutes the first word line portion 121; wherein, the capacitor groove 24 is located on one side of the sacrificial filler structure 19 and includes a first capacitor groove 241 and a second capacitor groove 242 that are interconnected, the first capacitor groove 241 penetrates the stacked structure 18 along the first direction Z, and the second capacitor groove 242 is located between adjacent insulating layers 182 and exposes the first word line portion 121.

[0065] In some embodiments, please refer to Figure 10 Along the third direction Y, the capacitor groove 24 is located on the side of the sacrificial filling structure 19 opposite to the second letter line portion 122. The method of forming the capacitor groove 24 may include first removing a portion of the sacrificial layer 181 and the insulating layer 182 to form a first capacitor groove 241, and then removing a portion of the sacrificial layer 181 from the first capacitor groove 241 to form a second capacitor groove 242.

[0066] In some embodiments, please refer to Figure 11 The removal of a portion of the first initial word line portion 120 by means of capacitor slot 24 includes: removing at least a portion of the first initial word line portion 120 by means of second capacitor slot 242 to at least expose the gate oxide layer 22 on the sidewall of the second sacrificial portion 192.

[0067] In some embodiments, please refer to Figures 12-14 By performing the above step S106, an isolation dielectric structure 251 and a capacitor structure 13 are formed in the capacitor groove 24. The capacitor structure 13 is located in the capacitor groove 24 and is in contact with the second sacrificial part 192. The isolation dielectric structure 251 is located between the capacitor structure 13 and the first word line part 121.

[0068] In some embodiments, please refer to Figure 12 and Figure 13 An isolation dielectric structure 251 is formed in a capacitor trench 24, including: forming an initial dielectric layer 25, which covers the first word line portion 121 and the gate oxide layer 22 and is located on the sidewall of the second capacitor trench 242; and removing a portion of the initial dielectric layer 25 and a portion of the gate oxide layer 22 through the capacitor trench 24 to expose the sidewall of the second sacrificial portion 192, while retaining the portion of the initial dielectric layer 25 in contact with the first word line portion 121 to form the isolation dielectric structure 251. Thus, the initial dielectric layer 25 is formed in a single film deposition process, and then a portion of the initial dielectric layer 25 and the gate oxide layer 22 are removed in a single pushback process to form the isolation dielectric structure 251. The formation process of the isolation dielectric structure 251 is simple, simplifying the semiconductor device fabrication process, shortening the semiconductor device manufacturing cycle, and also improving the process window.

[0069] It should be noted that the first dielectric portion 141 mentioned above includes an isolation dielectric structure 251. In some embodiments, the first dielectric portion 141 may further include the remaining gate oxide layer 22 between the isolation dielectric structure 251 and the second channel portion 112. The second dielectric portion 142 mentioned above includes the gate oxide layer between the first word line portion 121 and the second word line portion 122 and the channel structure 11. The third dielectric portion 143 mentioned above includes the remaining insulating layer 182.

[0070] In some embodiments, please refer to Figure 14 The formation of capacitor structure 13 in capacitor tank 24 includes: forming a second electrode structure 132 on the tank wall of the second capacitor tank 242; forming a capacitor dielectric layer 133 covering the second electrode structure 132 and the tank wall of the first capacitor tank 241; and forming a first electrode structure 131, which is located in the remaining first capacitor tank 241 and the remaining second capacitor tank 242.

[0071] In some embodiments, please refer to Figure 1 and Figure 2 The method of manufacturing semiconductor device 100 further includes: removing sacrificial fill structure 19 to form a first opening; and forming a channel structure 11 in the first opening, the channel structure 11 being in contact with capacitor structure 13.

[0072] In some embodiments, please refer to Figure 1 and Figure 2 The method of manufacturing semiconductor device 100 further includes: forming a bit line 15 in the remaining first opening, the bit line 15 extending along a first direction Z, and a channel structure 11 disposed around the bit line 15.

[0073] Based on the same inventive concept, please refer to Figure 15 This application also provides a storage system 300. The storage system 300 may include a semiconductor device 100 and a controller 200 as described in any of the above embodiments. The controller 200 is connected to the semiconductor device 100 and is used to control the semiconductor device 100 to store data.

[0074] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0076] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0077] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: The channel structure includes a first channel portion and a second channel portion that are interconnected; the first channel portion extends along a first direction, and the second channel portion is disposed around the first channel portion. The letter line surrounds at least a portion of the second channel portion; A capacitor structure is connected to the second channel portion; A dielectric structure includes a first dielectric portion and a second dielectric portion interconnected; the first dielectric portion is located between the word line and the second channel portion, the second dielectric portion surrounds at least a portion of the second channel portion and is located between the word line and the capacitor structure, and the dimension of the second dielectric portion along the first direction is greater than the dimension of the first dielectric portion along the first direction.

2. The semiconductor device according to claim 1, characterized in that, The character line includes a first character line portion, which is disposed around the first channel portion and surrounds the second channel portion; The first character line portion includes a first character line end face, which is located on the side of the first character line portion near the capacitor structure and is recessed inward relative to the second channel portion in a direction closer to the first channel portion. The second dielectric portion is located between the adjacent first character line end face and the capacitor structure and is disposed around the second channel portion.

3. The semiconductor device according to claim 2, characterized in that, The word line also includes a second word line portion, which extends along a second direction and is located on the side of the channel structure opposite to the capacitor structure. One second word line portion connects at least two first word line portions spaced apart along the second direction, and the first direction intersects the second direction.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a word line isolation structure that extends along the first direction and the second direction, and two second word line portions along a third direction contact one of the word line isolation structures, the third direction intersecting the first direction and the second direction.

5. The semiconductor device according to claim 1, characterized in that, A plurality of second channel portions are arranged along the first direction, the second direction and the third direction, and at least two second channel portions arranged at intervals along the first direction are connected to one first channel portion; The character lines are arranged along the first direction and the third direction; The dielectric structure further includes a third dielectric portion, which is located between adjacent capacitor structures, adjacent word lines, and adjacent second channel portions along the first direction.

6. The semiconductor device according to claim 1, characterized in that, The plurality of said capacitor structures are arranged along the first direction, the second direction and the third direction respectively, and one said capacitor structure includes: A first electrode structure includes a common portion and an extension portion. The common portion extends along a first direction, and the extension portion extends toward the second channel portion along a third direction. The third direction intersects with the first direction and the second direction. The second electrode structure extends along the third direction, surrounds the extension portion, and contacts the second channel portion; A capacitor dielectric layer is located between the first electrode structure and the second electrode structure; One of the common portions is connected to a plurality of the extension portions arranged along the first direction, the second direction, and the third direction.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device further includes a bit line, and the first channel portion surrounds and contacts the bit line.

8. A method for manufacturing a semiconductor device, characterized in that, include: A multilayer structure is formed, the multilayer structure including an insulating layer and a sacrificial layer stacked along a first direction; A first initial word line portion and a sacrificial fill structure are formed in the stacked structure. The sacrificial fill structure includes a first sacrificial portion and a second sacrificial portion. The first sacrificial portion penetrates the stacked structure along the first direction. The second sacrificial portion is disposed around the first sacrificial portion. The second sacrificial portion and the first initial word line portion are located between adjacent insulating layers. The first initial word line portion surrounds the second sacrificial portion. A capacitor groove is formed in the stacked structure, and a portion of the first initial word line portion is removed through the capacitor groove, with the remaining first initial word line portion constituting the first word line portion; wherein, the capacitor groove is located on one side of the sacrificial filler structure and includes a first capacitor groove and a second capacitor groove that are interconnected, the first capacitor groove penetrates the stacked structure along the first direction, and the second capacitor groove is located between adjacent insulating layers and exposes the first word line portion. An isolation dielectric structure and a capacitor structure are formed in the capacitor groove. The capacitor structure is in contact with the second sacrificial portion, and the isolation dielectric structure is located between the capacitor structure and the first word line portion.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The method further includes: Remove the sacrificial fill structure to form the first opening; A channel structure is formed in the first opening, and the channel structure is in contact with the capacitor structure.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The method further includes: A bit line is formed in the first opening, the bit line extends along the first direction, and the channel structure is arranged around the bit line.

11. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of the first initial word line portion and the sacrificial fill structure in the stacked structure includes: A first through opening is formed in the stacked structure, and the first through opening penetrates the insulating layer and the sacrificial layer along the first direction; The sacrificial layer is removed through the first through-hole to form a first lateral opening, the first lateral opening being located between adjacent insulating layers; The first initial word line portion and the gate oxide layer are sequentially formed on the sidewall of the first lateral opening; The sacrificial fill structure is filled into the first lateral opening and the first through opening.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The process of forming an isolation dielectric structure in the capacitor trench includes: An initial dielectric layer is formed, which covers the first word line portion and the gate oxide layer and is located on the sidewall of the second capacitor trench; A portion of the initial dielectric layer and a portion of the gate oxide layer are removed through the capacitor trench to expose the sidewalls of the second sacrificial portion, while the portion of the initial dielectric layer in contact with the first word line is retained to form an isolation dielectric structure.

13. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Before forming capacitor trenches in the stacked structure, the method further includes: A second opening is formed, the second opening being located between adjacent sacrificial fill structures and including a second through opening and a second lateral opening, the second through opening penetrating the stacked structure along the first direction, and the second lateral opening being located between adjacent insulating layers and exposing the first initial word line portion; A second character line portion is formed in the second lateral opening, and the second character line portion contacts the first initial character line portion.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: A character line isolation structure is formed in the second through opening, the character line isolation structure being located between adjacent second character line portions and in contact with adjacent second character line portions.

15. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 7; as well as A controller, connected to the semiconductor device, is used to control the semiconductor device to store data.

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