Semiconductor structure

Abstract

This application relates to a semiconductor structure, specifically within the field of semiconductor technology. The semiconductor structure includes a substrate and a word line structure. The substrate includes an isolation structure and a plurality of active regions spaced apart and defined by the isolation structure. The isolation structure includes a first trench isolation structure located between the ends of adjacent active regions and a second trench isolation structure located between the sidewalls of adjacent active regions. The word line structure is located within the substrate, extends along a first direction, and crosses the isolation structure and the active regions. The word line structure located on the first trench isolation structure includes a rough bottom surface. The first trench isolation structure includes a first insulating layer and a second insulating layer. The first insulating layer is in direct contact with the active regions. The second insulating layer is located within the first insulating layer. The highest point of the bottom surface of the word line structure is located at the boundary between the first insulating layer and the active regions, and the lowest point of the bottom surface of the word line structure is located at the boundary between the first insulating layer and the second insulating layer. This improves the performance and yield of semiconductor devices.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202520973631.5, filed on May 16, 2025, entitled "Semiconductor Structure", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0004] With the development of integrated circuit technology and the continuous shrinking of critical device dimensions, the types and number of devices contained in a single chip have increased, making it possible for even minor differences in the manufacturing process to affect device performance.

[0005] As semiconductor chip dimensions shrink, the demands on semiconductor manufacturing processes become increasingly stringent. Improving the performance and yield of semiconductor devices, at least without increasing their size, is a key research direction for researchers. Summary of the Invention

[0006] Based on this, this application provides a semiconductor structure that can improve the performance and yield of semiconductor devices without increasing the size of the semiconductor device or the complexity of the fabrication process.

[0007] To address the aforementioned technical problems and other issues, according to some embodiments, a first aspect of this application provides a semiconductor structure including a substrate and a word line structure. The substrate includes an isolation structure and a plurality of active regions spaced apart and defined by the isolation structure. The isolation structure includes a first trench isolation structure located between the ends of adjacent active regions and a second trench isolation structure located between the sidewalls of adjacent active regions. The word line structure is located within the substrate, extends along a first direction, and crosses the isolation structure and the active regions. The word line structure located on the first trench isolation structure includes a rough bottom surface. The first trench isolation structure includes a first insulating layer and a second insulating layer, the first insulating layer being in direct contact with the active regions; the second insulating layer being located within the first insulating layer; the highest point of the bottom surface of the word line structure is located at the boundary between the first insulating layer and the active regions, and the lowest point of the bottom surface of the word line structure is located at the boundary between the first insulating layer and the second insulating layer. By directly utilizing the difference in material etching selectivity between the first insulating layer and the second insulating layer, it is possible to make the word line structure located on the first trench isolation structure include a rough bottom surface without increasing the size of the semiconductor device or the complexity of the fabrication process. This relatively increases the proportion of the word line structure within the first trench isolation structure, thereby improving the performance and yield of the semiconductor device.

[0008] According to some embodiments, the rough bottom surface is wavy or W-shaped. Without increasing the complexity of the fabrication process, it relatively increases the proportion of the word line structure in the first trench isolation structure compared to a word line structure with a flat bottom surface, thereby improving the performance and yield of the semiconductor device.

[0009] According to some embodiments, the bottom surface of the word line structure located on the first trench isolation structure is W-shaped, and the convex surface of the W-shape along the direction away from the substrate is arc-shaped.

[0010] According to some embodiments, the isolation structure further includes a peripheral insulation structure located outside all active regions; wherein the lowest point of the bottom of the word line structure located on the peripheral insulation structure is lower than the lowest point of the bottom of the word line structure located on the first trench isolation structure.

[0011] According to some embodiments, the second trench isolation structure is made of the same material as the first insulating layer.

[0012] According to some embodiments, the word line structure includes a gate dielectric layer, a metal barrier layer, and a conductive layer stacked sequentially along a direction away from the substrate. The conductive layer extends along a first direction and includes a first embedded portion embedded in a first trench isolation structure and a second embedded portion embedded in a second trench isolation structure. The metal barrier layer is located between the conductive layer and the substrate. The metal barrier layer includes a first blocking portion located between the first embedded portion and the first trench isolation structure, and the bottom surface of the first blocking portion is wavy or W-shaped.

[0013] According to some embodiments, the word line structure includes a gate dielectric layer, a metal barrier layer, and a conductive layer stacked sequentially along a direction away from the substrate. The conductive layer extends along a first direction and includes a first embedded portion embedded in a first trench isolation structure and a second embedded portion embedded in a second trench isolation structure. The metal barrier layer is located between the conductive layer and the substrate. The metal barrier layer includes a first blocking portion located between the first embedded portion and the first trench isolation structure. The conductive layer and the first blocking portion together constitute the target bottom, and the bottom surface of the target bottom is wavy or W-shaped.

[0014] According to some embodiments, a second aspect of this application provides a semiconductor structure including a core region and a peripheral region. The core region includes an isolation structure and a plurality of active regions spaced apart and defined by the isolation structure. The peripheral region is disposed adjacent to the core region and includes a peripheral insulating structure. A word line structure extends from the core region to the peripheral region, and the word line structure is interleaved with the isolation structure, the active regions, and the peripheral insulating structure. The lowest point of the bottom of the word line structure located on the peripheral insulating structure is lower than the lowest point of the bottom of the word line structure located on the isolation structure.

[0015] According to some embodiments, the highest point of the bottom of the word line structure on the outer insulating structure is higher than the highest point of the bottom of the isolation structure.

[0016] According to some embodiments, the peripheral insulation structure includes a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer. The first peripheral insulation layer is in direct contact with the active region, and the second peripheral insulation layer is located between the first peripheral insulation layer and the third peripheral insulation layer. The bottom of the word line structure that is in direct contact with the second peripheral insulation layer is higher than the bottom of the word line structure that is in direct contact with the third peripheral insulation layer.

[0017] According to some embodiments, the isolation structure includes a first trench isolation structure located between the ends of adjacent active regions and a second trench isolation structure located between the sidewalls of adjacent active regions; the first trench isolation structure includes a first insulating layer and a second insulating layer, the first insulating layer being in direct contact with the active region; the second insulating layer being located within the first insulating layer; wherein, the highest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the active region, and the lowest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the second insulating layer.

[0018] According to some embodiments, a third aspect of this application provides a semiconductor structure including a core region and a peripheral region. The core region includes an isolation structure and a plurality of active regions arranged at intervals defined by the isolation structure. The peripheral region is disposed adjacent to the core region and includes a peripheral insulating structure. A word line structure extends from the core region to the peripheral region, and the word line structure is interleaved with the isolation structure, active regions, and peripheral insulating structure. The word line structure located on the peripheral insulating structure includes a stepped bottom surface.

[0019] According to some embodiments, a fourth aspect of this application provides a semiconductor structure, including: a core region and a peripheral region, the core region including an isolation structure and a plurality of active regions spaced apart by the isolation structure; the peripheral region is disposed adjacent to the core region, and the peripheral insulating structure includes at least a first peripheral insulating layer and a second peripheral insulating layer, the first peripheral insulating layer being in direct contact with the active regions; a word line structure extending from the core region to the peripheral region, the word line structure being located on the isolation structure, the active regions, and the peripheral insulating structure; wherein, the lowest point of the bottom of the word line structure in direct contact with the second peripheral insulating layer is higher than the lowest point of the bottom of the word line structure in direct contact with the first peripheral insulating layer.

[0020] According to some embodiments, the word line structure includes an extension located at the junction of the first peripheral insulating layer and the second peripheral insulating layer; the lowest point of the extension is lower than the lowest point of the bottom of the word line structure that is in direct contact with the second peripheral insulating layer.

[0021] According to some embodiments, a fifth aspect of this application provides a semiconductor structure including a core region, a peripheral region, and a word line structure. The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure. The peripheral region is disposed adjacent to the core region. The word line structure extends from the core region to the peripheral region and is located on the isolation structure, the active region, and the peripheral region. The bottom surface of the word line structure located in the peripheral region has a lowest point, which is adjacent to the end sidewall of the word line structure.

[0022] According to some embodiments, a sixth aspect of this application provides a semiconductor structure including a core region, a peripheral region, and a word line structure. The core region includes an isolation structure and a plurality of active regions arranged at intervals defined by the isolation structure. The peripheral region is disposed adjacent to the core region. The word line structure extends from the core region to the peripheral region and is located on the isolation structure, the active region, and the peripheral region. The bottom surface of the word line structure located in the peripheral region has a lowest point, which is located on the end sidewall of the word line structure.

[0023] According to some embodiments, the isolation structure includes a first trench isolation structure located between the ends of adjacent active regions and a second trench isolation structure located between the sidewalls of adjacent active regions; the first trench isolation structure includes a first insulating layer and a second insulating layer, the first insulating layer being in direct contact with the active region; the second insulating layer being located within the first insulating layer; wherein, the highest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the active region, and the lowest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the second insulating layer. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in one embodiment of the present application;

[0026] Figure 2a After forming the first trench, the second trench, and the third trench in one embodiment of this application, the resulting semiconductor structure follows... Figure 1 Schematic diagram of the longitudinal section structure obtained in the AA' direction;

[0027] Figure 2b After forming an oxide material layer in one embodiment of this application, the resulting semiconductor structure along... Figure 1 Schematic diagram of the longitudinal section structure obtained in the AA' direction;

[0028] Figure 3 A semiconductor structure is provided along one embodiment of this application. Figure 1 Schematic diagram of the longitudinal section structure obtained in the AA' direction;

[0029] Figure 4 In another embodiment of this application, a semiconductor structure is provided along... Figure 1 A schematic diagram of the longitudinal section structure obtained in the AA' direction.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100, Substrate; 1A, Core Region; 1P, Peripheral Region; 10, Active Region; 11, First Trench; 12, Second Trench; 13, Third Trench; 20, Isolation Structure; 21, First Trench Isolation Structure; 211, First Insulating Layer; 2110, Oxide Material Layer; 212, Second Insulating Layer; 22, Second Trench Isolation Structure; 30, Word Line Structure; 30s, Rough Bottom Surface; 31, Conductive Layer; 32, Metal Barrier Layer; 32a, First Barrier Section; 40, Peripheral Insulating Structure; 41, First Peripheral Insulating Layer; 42, Second Peripheral Insulating Layer; 43, Third Peripheral Insulating Layer; Y1, Extension Section; C1, End Sidewall. Detailed Implementation

[0032] To facilitate understanding of this application, a more complete description of the application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the application. However, the application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] Please refer to Figures 1-3 In some embodiments, a semiconductor structure is provided, including a substrate 100 and a word line structure 30. The substrate 100 includes an isolation structure 20 and a plurality of active regions 10 spaced apart and defined by the isolation structure 20. The isolation structure 20 includes a first trench isolation structure 21 located between the ends 20a of adjacent active regions 10 and a second trench isolation structure 22 located between the sidewalls of adjacent active regions 10. The word line structure 30 is located within the substrate 100, extends along a first direction (e.g., the ox direction), and crosses the isolation structure 20 and the active regions 10. The word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s. By providing a rough bottom surface 30s for the word line structure 30 located on the first trench isolation structure 21, the proportion of the word line structure 30 within the first trench isolation structure can be relatively increased without increasing the size of the semiconductor device or the complexity of the fabrication process, thereby improving the performance and yield of the semiconductor device.

[0039] Please refer to Figure 2a In some embodiments, the substrate 100 may be constructed from semiconductor materials, conductor materials, or any combination thereof. The substrate 100 may be a single-layer structure or a multi-layer structure. An etching process may be used to form spaced first trenches 11 and second trenches 12 within the substrate core region 1A; the first trenches 11 and second trenches 12 are alternately arranged in a first direction (e.g., the ox direction); the first trenches 11 define the shape, size, and position parameters of the first trench isolation structure; the second trenches 12 define the shape, size, and position parameters of the second trench isolation structure. For example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) processes, including but not limited to, may be used to form an array of first trenches 11 and second trenches 12 within the substrate core region 1A.

[0040] Please continue to refer to this. Figure 2a In some embodiments, during the formation of the first trench 11 and the second trench 12, a third trench 13 is formed simultaneously in the peripheral region 1P. The third trench 13 is used to define parameters such as the shape, size and position of the peripheral insulation structure.

[0041] Please refer to Figure 2bIn some embodiments, after forming the first trench 11, the second trench 12, and the third trench 13, an oxide material layer 2110 can be formed on the exposed surfaces of the first trench 11, the second trench 12, and the third trench 13 using a thermal oxidation process. Then, a first insulating material layer is deposited on the oxide material layer 2110. For example, an atomic layer deposition process can be used to form a first insulating material layer with a uniform film thickness reaching a target value. The first insulating material layer can be made of the same material as the oxide material layer 2110, for example, silicon oxide. Then, a second insulating material layer and a third insulating material layer are formed within the first trench 11, the second trench 12, and the third trench 13 using a deposition process.

[0042] Please refer to Figure 2a , Figures 2b-3 In some embodiments, the oxide layer 2110, the second insulating layer, the first insulating layer, and the third insulating layer can be etched back to expose parts of the sidewalls of the first trench 11, the second trench 12, and the third trench 13, as well as the surface of the substrate. Under the same etching conditions, the etching rate of the first insulating layer is greater than that of the second insulating layer. The remaining first insulating layer and oxide layer 2110 in the core region 1A are used together to form the first insulating layer 211, and the remaining second insulating layer is used to form the second insulating layer 212. The remaining first insulating layer and oxide layer 2110 in the peripheral region 1P are used together to form the first peripheral insulating layer 41, the remaining second insulating layer is used to form the second peripheral insulating layer 42, and the remaining third insulating layer is used to form the third peripheral insulating layer 43. The first insulating layer 211 and the second insulating layer 212 in the first trench 11 together form the first trench isolation structure 21. The first insulating layer 211 in the second trench 12 forms the second trench isolation structure 22. The first peripheral insulating layer 41, the second peripheral insulating layer 42, and the third peripheral insulating layer 43 in the third trench 13 together form the peripheral insulation structure 40. The top surfaces of the first insulating layer 211 and the second insulating layer 212 are both lower than the top surface of the inner substrate of the core region 1A. The top surface of the first trench isolation structure 21 is wavy or W-shaped. The top surface of the first trench isolation structure 21 has rounded corners and the sides are also arc-shaped. Compared with the existing right angles, the rounded corners can reduce the generation of gaps. The top surface of the second trench isolation structure 22 has rounded corners. The top surface of the peripheral insulation structure 40 has rounded corners.

[0043] In some embodiments, the material of the first insulating layer 211 may include silicon oxide, and the material of the second insulating layer 212 may include silicon nitride. The material of the third peripheral insulating layer 43 may include silicon oxide, silicon oxynitride, or a combination thereof.

[0044] Please continue to refer to this. Figure 3In some embodiments, a deposition process can be used to form the exposed top surface of the substrate, the exposed sidewalls of the first trench 11 and the second trench 12, and the gate dielectric layer (not shown) on the exposed top surface of the first trench isolation structure 21 and the exposed top surface of the second trench isolation structure 22. The deposition process can include, but is not limited to, at least one of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0045] Please continue to refer to this. Figure 3 In some embodiments, a deposition process can be used to form a metal barrier layer 32 and a conductive layer 31 covering the exposed surface of the gate dielectric layer. The metal barrier layer 32, the conductive layer 31, and the gate dielectric layer together constitute the word line structure 30. The material of the gate dielectric layer can be selected from silicon dioxide, silicon oxynitride, silicon nitride, and combinations thereof. The gate dielectric layer can also be a high-k dielectric material (dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the conductive layer 31 is selected from indium tin oxide, polycrystalline silicon, copper, tungsten, aluminum, copper alloys, titanium, titanium nitride, tantalum nitride, and combinations thereof, and the metal barrier layer 32 can be selected from titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof.

[0046] Please continue to refer to this. Figure 3 In some embodiments, the first trench isolation structure 21 includes a first insulating layer 211 and a second insulating layer 212. The first insulating layer 211 is in direct contact with the active region 10; the second insulating layer 212 is located within the first insulating layer 211. The highest point H of the bottom surface of the word line structure 30 within the core region 1A is located at the boundary between the first insulating layer 211 and the active region 10, and the lowest point B of the bottom surface of the word line structure 30 is located at the boundary between the first insulating layer 211 and the second insulating layer 212. By directly utilizing the difference in material etching selectivity between the first insulating layer 211 and the second insulating layer 212, without increasing the complexity of the fabrication process, the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s, thereby relatively increasing the proportion of the word line structure 30 within the first trench isolation structure 21.

[0047] Please continue to refer to this. Figure 3In some embodiments, the rough bottom surface 30s of the word line structure 30 is wavy or W-shaped, and the rough bottom surface 30s has rounded corners. When the bottom surface of the word line structure 30 is W-shaped, the convex surface 30a of the W-shape along the direction away from the substrate 100 is arc-shaped. In this embodiment, without increasing the complexity of the fabrication process, compared with a word line structure 30 with a flat bottom surface, the proportion of the word line structure 30 within the first trench isolation structure is relatively increased, and the impedance of the word line structure 30 is relatively reduced; the rounded corners of the bottom surface of the word line structure 30 improve the performance and yield of the semiconductor device.

[0048] Please continue to refer to this. Figure 3 In some embodiments, the peripheral insulation structure 40 is located outside all active regions. The lowest point dp of the word line structure 30 on the peripheral insulation structure 40 is lower than the lowest point B of the word line structure 30 on the first trench isolation structure 21, and the lowest point dp of the word line structure 30 on the peripheral insulation structure 40 is adjacent to the end sidewall of the word line structure 30. In some embodiments, the lowest point dp of the word line structure 30 on the peripheral insulation structure 40 is located on the end sidewall C1 of the word line structure 30. Please continue to refer to Figure 3 In some embodiments, the second trench isolation structure 22 is made of the same material as the first insulating layer 211, and the second trench isolation structure 22 and the first insulating layer 211 can be prepared simultaneously in the same process steps, which can at least reduce the complexity of the preparation process.

[0049] Please continue to refer to this. Figure 3 In some embodiments, the word line structure 30 includes a gate dielectric layer (not shown), a metal barrier layer 32, and a conductive layer 31, sequentially stacked along a direction away from the substrate 10. The conductive layer 31 extends along a first direction (e.g., the ox direction) and includes a first embedding portion embedded in a first trench isolation structure 21 and a second embedding portion embedded in a second trench isolation structure 22. The metal barrier layer 32 is located between the conductive layer 31 and the substrate 100. The metal barrier layer 32 includes a first blocking portion 32a located between the first embedding portion and the first trench isolation structure 21, and the bottom surface of the first blocking portion 32a is wavy or W-shaped. In other embodiments, the first blocking portion 32a and the conductive layer 31 together constitute a target bottom, and the bottom surface of the target bottom is wavy or W-shaped.

[0050] Please refer to Figure 3In some embodiments, a semiconductor structure is provided, including a core region 1A and a peripheral region 1P. The core region 1A includes an isolation structure and a plurality of active regions 10 spaced apart by the isolation structure. The peripheral region 1P is disposed adjacent to the core region 1A and includes a peripheral insulating structure 40. A word line structure 30 extends from the core region 1A to the peripheral region 1P, and the word line structure 30 is interleaved with the isolation structure, the active regions 10, and the peripheral insulating structure 40. The lowest point dp of the word line structure 30 located on the peripheral insulating structure 40 is lower than the lowest point B of the word line structure 30 on the first trench isolation structure 21.

[0051] Please continue to refer to this. Figure 3 In some embodiments, the isolation structure includes a first trench isolation structure 21 and a second trench isolation structure 22, and the highest point tp of the bottom of the word line structure 30 on the peripheral insulation structure 40 is higher than the highest point ta of the bottom of the isolation structure.

[0052] Please continue to refer to this. Figure 3 In some embodiments, the peripheral insulation structure 40 includes a first peripheral insulation layer 41, a second peripheral insulation layer 42, and a third peripheral insulation layer 43. The first peripheral insulation layer 41 is in direct contact with the active region 10, and the second peripheral insulation layer 42 is located between the first peripheral insulation layer 41 and the third peripheral insulation layer 43. The bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42 is higher than the bottom s3 of the word line structure 30 directly contacting the third peripheral insulation layer 43. The bottom s1 of the word line structure 30 directly contacting the first peripheral insulation layer 41 is lower than the bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42.

[0053] Please continue to refer to this. Figure 1 , Figure 3 In some embodiments, the isolation structure includes a first trench isolation structure 21 located between the ends of adjacent active regions 10 and a second trench isolation structure 22 located between the sidewalls of adjacent active regions 10; the word line structure 30 extends along a first direction (e.g., the ox direction) and crosses the isolation structure and the active region 10; wherein the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s.

[0054] Please continue to refer to this. Figure 3 In some embodiments, the rough bottom surface is wavy or W-shaped.

[0055] Please continue to refer to this. Figure 3In some embodiments, the first trench isolation structure 21 includes a first insulating layer 211 and a second insulating layer 212. The first insulating layer 211 is in direct contact with the active region 10. The second insulating layer 212 is located inside the first insulating layer 211. In the core region 1A, the highest point H of the bottom surface of the word line structure 30 on the first trench isolation structure 21 is located at the junction of the first insulating layer 211 and the active region 10, and the lowest point B of the bottom surface of the word line structure 30 on the first trench isolation structure 21 is located at the junction of the first insulating layer 211 and the second insulating layer 212.

[0056] Please continue to refer to this. Figure 3 In some embodiments, the two highest points of the top of the second peripheral insulation layer 42 located in the peripheral insulation structure 40 of the peripheral region 1P (e.g., Figure 3 The first highest point g1 and the second highest point g2 in the core area are both higher than the highest point g3 of the second insulating layer 212 in the core area 1A.

[0057] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, a semiconductor structure is provided, including a core region 1A and a peripheral region 1P. The core region 1A includes an isolation structure and a plurality of active regions 10 spaced apart by the isolation structure. The peripheral region 1P is disposed adjacent to the core region 1A and includes a peripheral insulating structure 40. A word line structure 30 extends from the core region 1A to the peripheral region 1P, and the word line structure 30 is interleaved with the isolation structure, the active regions 10, and the peripheral insulating structure 40. The word line structure 30 located on the peripheral insulating structure 40 includes a stepped bottom surface sd.

[0058] Please continue to refer to this. Figures 1-4 In some embodiments, the isolation structure 20 includes a first trench isolation structure 21 located between adjacent active region ends 20a and a second trench isolation structure 22 located between adjacent active region sidewalls; the word line structure 30 is located within the substrate 100, extends along a first direction (e.g., the ox direction), and crosses the isolation structure 20 and the active region 10; wherein the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s. By providing a rough bottom surface 30s for the word line structure 30 located on the first trench isolation structure 21, the proportion of the word line structure 30 within the first trench isolation structure can be relatively increased without increasing the size of the semiconductor device or the complexity of the fabrication process, thereby improving the performance and yield of the semiconductor device.

[0059] Please continue to refer to this. Figure 3 or Figure 4The top surfaces of the first insulating layer 211 and the second insulating layer 212 are both lower than the top surface of the inner substrate of the core region 1A. The top surface of the first trench isolation structure 21 is wavy or W-shaped. The top surface of the first trench isolation structure 21 has rounded corners, and the sides are also arc-shaped. Compared with existing right angles, the rounded corners can reduce the generation of voids. The top surface of the second trench isolation structure 22 has rounded corners. The top surface of the outer insulating structure 40 has rounded corners.

[0060] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the material of the first insulating layer 211 may include silicon oxide, and the material of the second insulating layer 212 may include silicon nitride.

[0061] Please continue to refer to this. Figure 3 In some embodiments, the peripheral insulation structure 40 includes a first peripheral insulation layer 41, a second peripheral insulation layer 42, and a third peripheral insulation layer 43. The first peripheral insulation layer 41 is in direct contact with the active region 10, and the second peripheral insulation layer 42 is located between the first peripheral insulation layer 41 and the third peripheral insulation layer 43. The bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42 is higher than the bottom s3 of the word line structure 30 directly contacting the third peripheral insulation layer 43. The bottom s1 of the word line structure 30 directly contacting the first peripheral insulation layer 41 is lower than the bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42.

[0062] Please continue to refer to this. Figure 3 In some embodiments, the word line structure 30 extends from the core region 1A to the peripheral region 1P. The word line structure 30 is located on the isolation structure, the active region 10, and the peripheral insulation structure 40. The lowest point d2 of the bottom of the word line structure 30 located on the second peripheral insulation layer 42 is higher than the lowest point d1 of the bottom of the word line structure 30 that is in direct contact with the first peripheral insulation layer 41. Specifically, the word line structure 30 has an extension Y1 located at the junction of the first peripheral insulation layer 41 and the second peripheral insulation layer 42. The extension Y1 has a lowest point d1.

[0063] Please continue to refer to this. Figure 3 In some embodiments, the lowest point d1 of the extension Y1 is lower than the lowest point d2 of the bottom of the word line structure 30, which is in direct contact with the second peripheral insulating layer 42.

[0064] Please continue to refer to this. Figure 3 or Figure 4In some embodiments, the word line structure 30 includes a gate dielectric layer (not shown), a metal barrier layer 32, and a conductive layer 31 sequentially stacked along a direction away from the substrate 10. The material of the gate dielectric layer can be selected from silicon dioxide, silicon oxynitride, silicon nitride, and combinations thereof. The gate dielectric layer can also be a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the conductive layer 31 is selected from indium tin oxide, polycrystalline silicon, copper, tungsten, aluminum, copper alloys, titanium, titanium nitride, tantalum nitride, and combinations thereof. The metal barrier layer 32 can be selected from titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof.

[0065] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the first trench isolation structure 21 includes a first insulating layer 211 and a second insulating layer 212. The first insulating layer 211 is in direct contact with the active region 10; the second insulating layer 212 is located within the first insulating layer 211. The highest point H of the bottom surface of the word line structure 30 within the core region 1A is located at the boundary between the first insulating layer 211 and the active region 10, and the lowest point B of the bottom surface of the word line structure 30 is located at the boundary between the first insulating layer 211 and the second insulating layer 212. By directly utilizing the difference in material etching selectivity between the first insulating layer 211 and the second insulating layer 212, without increasing the complexity of the fabrication process, the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s, thereby relatively increasing the proportion of the word line structure 30 within the first trench isolation structure 21.

[0066] Please continue to refer to this. Figure 3 In some embodiments, the rough bottom surface 30s of the word line structure 30 is wavy or W-shaped, and the rough bottom surface 30s has rounded corners. In this embodiment, without increasing the complexity of the fabrication process, compared with a word line structure 30 with a flat bottom surface, the proportion of the word line structure 30 within the first trench isolation structure is relatively increased, and the impedance of the word line structure 30 is relatively reduced; the rounded corners of the bottom surface of the word line structure 30 improve the performance and yield of the semiconductor device.

[0067] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the lowest point dp of the word line structure 30 located on the peripheral insulating structure 40 is lower than the lowest point B of the word line structure 30 on the first trench isolation structure 21.

[0068] Please continue to refer to this. Figure 3 or Figure 4In some embodiments, the second trench isolation structure 22 is made of the same material as the first insulating layer 211, and the second trench isolation structure 22 and the first insulating layer 211 can be prepared simultaneously in the same process steps, which can at least reduce the complexity of the preparation process.

[0069] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the conductive layer 31 in the word line structure 30 extends along a first direction (e.g., the ox direction). The conductive layer 31 includes a first embedded portion embedded in a first trench isolation structure 21 and a second embedded portion embedded in a second trench isolation structure 22. A metal barrier layer 32 is located between the conductive layer 31 and the substrate 100. The metal barrier layer 32 includes a first barrier portion 32a located between the first embedded portion and the first trench isolation structure 21. The bottom surface of the first barrier portion 32a is wavy or W-shaped. In other embodiments, the first barrier portion 32a and the conductive layer 31 together constitute a target bottom, and the bottom surface of the target bottom is wavy or W-shaped.

[0070] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the two highest points of the top of the second peripheral insulation layer 42 located in the peripheral insulation structure 40 of the peripheral region 1P (e.g., Figure 3 The first highest point g1 and the second highest point g2 in the core area are both higher than the highest point g3 of the second insulating layer 212 in the core area 1A.

[0071] Please continue to refer to this. Figure 3 In some embodiments, a semiconductor structure is provided, including: a core region 1A and a peripheral region 1P. The core region 1A includes an isolation structure and a plurality of active regions 10 spaced apart by the isolation structure. The peripheral region 1P is disposed adjacent to the core region 1A. The peripheral insulating structure 40 includes at least a first peripheral insulating layer 41 and a second peripheral insulating layer 42. The first peripheral insulating layer 41 is in direct contact with the active regions 10. A word line structure 30 extends from the core region 1A to the peripheral region 1P. The word line structure 30 is located on the isolation structure, the active regions 10, and the peripheral insulating structure 40. The lowest point d2 of the bottom of the word line structure 30 located on the second peripheral insulating layer 42 is higher than the lowest point d1 of the bottom of the word line structure 30 located on the first peripheral insulating layer 41.

[0072] Please continue to refer to this. Figure 3 In some embodiments, the two highest points of the top of the second peripheral insulation layer 42 located in the peripheral insulation structure 40 of the peripheral region 1P (e.g., Figure 3 The first highest point g1 and the second highest point g2 in the core area are both higher than the highest point g3 of the second insulating layer 212 in the core area 1A.

[0073] Please continue to refer to this. Figure 3 In some embodiments, the peripheral region 1P includes a peripheral insulation structure 40; the word line structure 30 extends from the core region 1A to the peripheral region 1P, and the word line structure 30 is interleaved with the isolation structure, the active region 10, and the peripheral insulation structure 40; wherein the word line structure 30 located on the peripheral insulation structure 40 includes a stepped bottom surface sd.

[0074] Please continue to refer to this. Figures 1-3 In some embodiments, the isolation structure 20 includes a first trench isolation structure 21 located between adjacent active region ends 20a and a second trench isolation structure 22 located between adjacent active region sidewalls; the word line structure 30 is located within the substrate 100, extends along a first direction (e.g., the ox direction), and crosses the isolation structure 20 and the active region 10; wherein the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s. By providing a rough bottom surface 30s for the word line structure 30 located on the first trench isolation structure 21, the proportion of the word line structure 30 within the first trench isolation structure can be relatively increased without increasing the size of the semiconductor device or the complexity of the fabrication process, thereby improving the performance and yield of the semiconductor device.

[0075] Please continue to refer to this. Figure 3 In some embodiments, the first trench isolation structure 21 includes a first insulating layer 211 and a second insulating layer 212. The first insulating layer 211 is in direct contact with the active region 10; the second insulating layer 212 is located within the first insulating layer 211. The highest point H of the bottom surface of the word line structure 30 within the core region 1A is located at the boundary between the first insulating layer 211 and the active region 10, and the lowest point B of the bottom surface of the word line structure 30 is located at the boundary between the first insulating layer 211 and the second insulating layer 212. By directly utilizing the difference in material etching selectivity between the first insulating layer 211 and the second insulating layer 212, without increasing the complexity of the fabrication process, the word line structure 30 located on the first trench isolation structure 21 includes a rough bottom surface 30s, thereby relatively increasing the proportion of the word line structure 30 within the first trench isolation structure 21.

[0076] Please continue to refer to this. Figure 3 The top surfaces of the first insulating layer 211 and the second insulating layer 212 are both lower than the top surface of the inner substrate of the core region 1A. The top surface of the first trench isolation structure 21 is wavy or W-shaped. The top surface of the first trench isolation structure 21 has rounded corners, and the sides are also arc-shaped. Compared with existing right angles, the rounded corners can reduce the generation of voids. The top surface of the second trench isolation structure 22 has rounded corners. The top surface of the outer insulating structure 40 has rounded corners.

[0077] Please continue to refer to this. Figure 3In some embodiments, the material of the first insulating layer 211 may include silicon oxide, and the material of the second insulating layer 212 may include silicon nitride.

[0078] Please continue to refer to this. Figure 3 In some embodiments, the peripheral insulation structure 40 includes at least a first peripheral insulation layer 41 and a second peripheral insulation layer 42, with the first peripheral insulation layer 41 in direct contact with the active region 10; the word line structure 30 extends from the core region 1A to the peripheral region 1P, and the word line structure 30 is located on the isolation structure, the active region 10, and the peripheral insulation structure 40; wherein, the lowest point d2 of the bottom of the word line structure 30 located on the second peripheral insulation layer 42 is higher than the lowest point d1 of the bottom of the word line structure 30 located on the first peripheral insulation layer 41.

[0079] Please continue to refer to this. Figure 3 In some embodiments, the side of the second peripheral insulating layer 42 facing away from the substrate 10 further includes a third peripheral insulating layer 43, and the material of the third peripheral insulating layer 43 may include silicon oxide, silicon oxynitride, or a combination thereof.

[0080] Please continue to refer to this. Figure 3 In some embodiments, the peripheral insulation structure 40 includes a first peripheral insulation layer 41, a second peripheral insulation layer 42, and a third peripheral insulation layer 43. The first peripheral insulation layer 41 is in direct contact with the active region 10, and the second peripheral insulation layer 42 is located between the first peripheral insulation layer 41 and the third peripheral insulation layer 43. The bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42 is higher than the bottom s3 of the word line structure 30 directly contacting the third peripheral insulation layer 43. The bottom s1 of the word line structure 30 directly contacting the first peripheral insulation layer 41 is lower than the bottom s2 of the word line structure 30 directly contacting the second peripheral insulation layer 42.

[0081] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the word line structure 30 includes a gate dielectric layer (not shown), a metal barrier layer 32, and a conductive layer 31 sequentially stacked along a direction away from the substrate 10. The material of the gate dielectric layer can be selected from silicon dioxide, silicon oxynitride, silicon nitride, and combinations thereof. The gate dielectric layer can also be a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. The material of the conductive layer 31 is selected from indium tin oxide, polycrystalline silicon, copper, tungsten, aluminum, copper alloys, titanium, titanium nitride, tantalum nitride, and combinations thereof. The metal barrier layer 32 can be selected from titanium nitride, tantalum nitride, tungsten nitride, and combinations thereof.

[0082] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the rough bottom surface 30s of the word line structure 30 is wavy or W-shaped, and the rough bottom surface 30s has rounded corners. In this embodiment, without increasing the complexity of the fabrication process, compared with a word line structure 30 with a flat bottom surface, the proportion of the word line structure 30 within the first trench isolation structure is relatively increased, and the impedance of the word line structure 30 is relatively reduced; the rounded corners of the bottom surface of the word line structure 30 improve the performance and yield of the semiconductor device.

[0083] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the lowest point dp of the word line structure 30 located on the peripheral insulating structure 40 is lower than the lowest point B of the word line structure 30 on the first trench isolation structure 21.

[0084] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the second trench isolation structure 22 is made of the same material as the first insulating layer 211, and the second trench isolation structure 22 and the first insulating layer 211 can be prepared simultaneously in the same process steps, which can at least reduce the complexity of the preparation process.

[0085] Please continue to refer to this. Figure 3 or Figure 4 In some embodiments, the conductive layer 31 in the word line structure 30 extends along a first direction (e.g., the ox direction). The conductive layer 31 includes a first embedding portion embedded in a first trench isolation structure 21 and a second embedding portion embedded in a second trench isolation structure 22. A metal barrier layer 32 is located between the conductive layer 31 and the substrate 100. The metal barrier layer 32 includes a first blocking portion 32a located between the first embedding portion and the first trench isolation structure 21. The bottom surface of the first blocking portion 32a is wavy or W-shaped. In other embodiments, the first blocking portion 32a and the conductive layer 31 together constitute a target bottom, and the bottom surface of the target bottom is wavy or W-shaped. Please continue to refer to... Figure 3 or Figure 4 In some embodiments, a semiconductor structure includes a core region 1A, a peripheral region 1P, and a word line structure 30. The core region 1A includes an isolation structure and a plurality of active regions 10 spaced apart by the isolation structure. The peripheral region 1P is disposed adjacent to the core region 1A. The word line structure 30 extends from the core region 1A to the peripheral region 1P and is located on the isolation structure, the active regions 10, and the peripheral region 1P. The bottom surface of the word line structure 30 located in the peripheral region 1P has a lowest point dp, which is adjacent to the end sidewall C1 of the word line structure 30.

[0086] Please continue to refer to this. Figure 3In some embodiments, a semiconductor structure includes a core region 1A, a peripheral region 1P, and a word line structure 30. The core region 1A includes an isolation structure and a plurality of active regions 10 spaced apart by the isolation structure. The peripheral region 1P is disposed adjacent to the core region 1A. The word line structure 30 extends from the core region 1A to the peripheral region 1P and is located on the isolation structure, the active regions 10, and the peripheral region 1P. The bottom surface of the word line structure 30 located in the peripheral region 1P has a lowest point dp, which is located on the end sidewall C1 of the word line structure 30.

[0087] Please continue to refer to this. Figure 4 In some embodiments, the isolation structure includes a first trench isolation structure 21 located between the ends of adjacent active regions 10 and a second trench isolation structure 22 located between the sidewalls of adjacent active regions 10; the first trench isolation structure 21 includes a first insulating layer 211 and a second insulating layer 212, the first insulating layer 211 being in direct contact with the active region 10; the second insulating layer 212 being located within the first insulating layer 211; wherein, the highest point of the bottom surface of the word line structure 30 located on the first trench isolation structure 21 is located at the junction of the first insulating layer 211 and the active region 10, and the lowest point of the bottom surface of the word line structure 30 located on the first trench isolation structure 21 is located at the junction of the first insulating layer 211 and the second insulating layer 212.

[0088] It should be understood that while the various steps in the semiconductor structure fabrication process described in this application are executed sequentially, these steps are not necessarily performed in the order exemplified herein. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, although at least some steps in the embodiments may include multiple steps or stages, these steps or stages are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of steps or stages in other steps.

[0089] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0090] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are quite specific and detailed, but they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A semiconductor structure, wherein, include: The substrate includes an isolation structure and a plurality of active regions spaced apart and defined by the isolation structure; The isolation structure includes a first trench isolation structure located between adjacent ends of the active region and a second trench isolation structure located between adjacent sidewalls of the active region; A word line structure is located within the substrate, extends along a first direction, and crosses the isolation structure and the active region; The first trench isolation structure includes: The first insulating layer is in direct contact with the active region; The second insulating layer is located within the first insulating layer; The highest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the active region, and the lowest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the second insulating layer.

2. The semiconductor structure according to claim 1, wherein, The rough bottom surface is wavy or W-shaped.

3. The semiconductor structure according to claim 2, wherein, The bottom surface of the word line structure located on the first trench isolation structure is W-shaped, and the convex surface of the W-shape along the direction away from the substrate is arc-shaped.

4. The semiconductor structure according to claim 1, wherein, The isolation structure also includes a peripheral insulation structure located outside all of the active regions; The lowest point of the word line structure located on the outer insulating structure is lower than the lowest point of the word line structure located on the first trench isolation structure.

5. The semiconductor structure according to any one of claims 1-4, wherein, The word line structure includes a gate dielectric layer, a metal barrier layer, and a conductive layer stacked sequentially along a direction away from the substrate: The conductive layer extends along the first direction and includes a first embedded portion embedded in the first trench isolation structure and a second embedded portion embedded in the second trench isolation structure. The metal barrier layer is located between the conductive layer and the substrate; The metal barrier layer includes a first barrier portion located between the first embedded portion and the first trench isolation structure, and the bottom surface of the first barrier portion is wavy or W-shaped.

6. The semiconductor structure according to any one of claims 1-4, wherein, The word line structure includes a gate dielectric layer, a metal barrier layer, and a conductive layer stacked sequentially along a direction away from the substrate: The conductive layer extends along the first direction and includes a first embedded portion embedded in the first trench isolation structure and a second embedded portion embedded in the second trench isolation structure. The metal barrier layer is located between the conductive layer and the substrate; The metal barrier layer includes a first barrier portion located between the first embedded portion and the first trench isolation structure; The conductive layer and the first blocking part together form the bottom of the target, and the bottom surface of the target bottom is wavy or W-shaped.

7. A semiconductor structure, wherein, include: The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure; An outer perimeter zone is disposed adjacent to the core zone, and the outer perimeter zone includes an outer insulation structure; The word line structure extends from the core area to the peripheral area, and the word line structure is interwoven with the isolation structure, the active area, and the peripheral insulation structure; Wherein, the lowest point of the bottom of the word line structure located on the outer insulating structure is lower than the lowest point of the bottom of the word line structure on the isolation structure.

8. The semiconductor structure according to claim 7, wherein, The highest point of the bottom of the word line structure on the outer insulating structure is higher than the highest point of the bottom of the isolation structure.

9. The semiconductor structure according to claim 7, wherein, The peripheral insulation structure includes a first peripheral insulation layer, a second peripheral insulation layer, and a third peripheral insulation layer. The first peripheral insulation layer is in direct contact with the active region, and the second peripheral insulation layer is located between the first peripheral insulation layer and the third peripheral insulation layer. The bottom of the word line structure that is in direct contact with the second peripheral insulation layer is higher than the bottom of the word line structure that is in direct contact with the third peripheral insulation layer.

10. The semiconductor structure according to claim 7, wherein, The isolation structure includes a first trench isolation structure located between the ends of the adjacent active regions and a second trench isolation structure located between the sidewalls of the adjacent active regions; The first trench isolation structure includes: The first insulating layer is in direct contact with the active region; The second insulating layer is located within the first insulating layer; The highest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the active region, and the lowest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the second insulating layer.

11. A semiconductor structure, wherein, include: The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure; An outer perimeter zone is disposed adjacent to the core zone, and the outer perimeter zone includes an outer insulation structure; The word line structure extends from the core area to the peripheral area, and the word line structure is interwoven with the isolation structure, the active area, and the peripheral insulation structure; The word line structure located on the outer insulating structure includes a stepped bottom surface.

12. A semiconductor structure, wherein, include: The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure; The peripheral region is adjacent to the core region, and the peripheral insulation structure includes at least a first peripheral insulation layer and a second peripheral insulation layer, wherein the first peripheral insulation layer is in direct contact with the active region. A word line structure extends from the core area to the peripheral area, and the word line structure is located on the isolation structure, the active area, and the peripheral insulation structure; The lowest point of the word line structure that is in direct contact with the second outer insulating layer is higher than the lowest point of the word line structure that is in direct contact with the first outer insulating layer.

13. The semiconductor structure according to claim 12, wherein, The word line structure includes an extension located at the junction of the first peripheral insulating layer and the second peripheral insulating layer; the lowest point of the extension is lower than the lowest point of the bottom of the word line structure that is in direct contact with the second peripheral insulating layer.

14. A semiconductor structure, wherein, include: The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure; The outer perimeter area is located adjacent to the core area; A word line structure extends from the core area to the peripheral area, and the word line structure is located on the isolation structure, the active area, and the peripheral area; The bottom surface of the character line structure located in the outer area has a lowest point, which is adjacent to the end sidewall of the character line structure.

15. A semiconductor structure, wherein, include: The core region includes an isolation structure and a plurality of active regions spaced apart by the isolation structure; The outer perimeter area is located adjacent to the core area; A word line structure extends from the core area to the peripheral area, and the word line structure is located on the isolation structure, the active area, and the peripheral area; The bottom surface of the character line structure located in the outer perimeter area has a lowest point, which is located on the end sidewall of the character line structure.

16. The semiconductor structure according to claim 15, wherein, The isolation structure includes a first trench isolation structure located between adjacent ends of the active region and a second trench isolation structure located between adjacent sidewalls of the active region; The first trench isolation structure includes: The first insulating layer is in direct contact with the active region; The second insulating layer is located within the first insulating layer; The highest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the active region, and the lowest point of the bottom surface of the word line structure located on the first trench isolation structure is located at the junction of the first insulating layer and the second insulating layer.

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