Semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device capable of shortening a step length. The semiconductor memory device of the embodiments includes: a laminate in which a plurality of conductive layers (WL) are layered apart from each other, having a step portion (SP) in which the plurality of conductive layers (WL) are processed into a step shape, including a plurality of step surface portions (T) that do not overlap the conductive layers (WL) of an upper layer; a pillar that extends in a layering direction of the laminate (LM) within the laminate (LM) that is separated from the step portion (SP), and in which a memory cell (MC) is formed at each of intersections with at least a portion of the plurality of conductive layers (WL); and a plurality of contacts (CC) that are arranged in the step portion (SP) and connected to the plurality of conductive layers (WL), and the plurality of contacts (CC) include a first contact (CC) group that is arranged in a first step surface portion (T) provided in a first conductive layer (WL) of the plurality of conductive layers (WL) and connected to each of the first conductive layer (WL) and one or more lower layer conductive layers (WL) that are continuous with the first conductive layer (WL) in the layering direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0002] Semiconductor memory devices, such as 3D non-volatile memories, have a configuration in which memory cells are arranged in 3D within a multilayer of stacked conductive layers. To electrically pull out these conductive layers, for example, these conductive layers are processed into a stepped shape to form contacts reaching each step. However, due to the multilayering of conductive layers, a problem arises where the step length increases. Summary of the Invention

[0003] The problem to be solved by the invention is to provide a semiconductor memory device that can shorten the step length.

[0004] The semiconductor memory device according to the embodiment includes: a stacked body, wherein a plurality of conductive layers are stacked separately from each other, and a stepped portion having the plurality of conductive layers processed into a stepped shape and including a plurality of stepped portions that do not overlap with the upper conductive layers; a pillar extending in the stacked body from the stepped portion in the stacked body in the stacked direction, and forming memory cells at intersections with at least a portion of the plurality of conductive layers; and a plurality of contacts disposed in the stepped portion and respectively connected to the plurality of conductive layers; and the plurality of contacts including a first contact group, the first contact group being disposed in a first stepped portion of a first conductive layer disposed in the plurality of conductive layers and respectively connected to the first conductive layer and one or more lower side conductive layers that are continuous with the first conductive layer in the stacked direction. Attached Figure Description

[0005] Figure 1 Figures (a) and (b) in the figure are schematic configuration examples of a semiconductor memory device according to an embodiment.

[0006] Figure 2 Figures (a) to (e) in the figure show an example of the configuration of the semiconductor memory device according to the embodiment.

[0007] Figure 3 (a) to (e) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0008] Figure 4 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0009] Figure 5 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0010] Figure 6 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0011] Figure 7 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0012] Figure 8 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0013] Figure 9 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0014] Figure 10 (a) to (d) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0015] Figure 11 (a) to (c) are cross-sectional views that sequentially illustrate a part of the manufacturing method of a semiconductor memory device according to an embodiment.

[0016] Figure 12 (a) to (i) in the diagram are schematic diagrams showing the arrangement order of the contact holes in the illustrated embodiment.

[0017] Figure 13 (a) to (c) are cross-sectional views showing a portion of the sequence of the contact formation methods of Variation Example 1 of the embodiments.

[0018] Figure 14 (a) to (c) are cross-sectional views showing a portion of the sequence of the contact formation methods of Variation Example 1 of the Embodiment.

[0019] Figure 15 (a) to (c) are cross-sectional views showing a portion of the sequence of the contact formation methods of Variation Example 1 of the Embodiment.

[0020] Figure 16 (a) to (c) are cross-sectional views showing a portion of the sequence of the contact formation methods of Variation Example 2 of the Implementation Method.

[0021] Figure 17 (a) to (c) are cross-sectional views showing a portion of the sequence of the connection formation methods of Variation Example 2 of the Embodiment.

[0022] Figure 18(a) to (c) are cross-sectional views showing a portion of the sequence of the connection formation methods of Variation Example 2 of the Embodiment. Detailed Implementation

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the constituent elements of the embodiments described below include those readily conceived or substantially the same by those skilled in the art.

[0024] (Example of a semiconductor memory device)

[0025] Figure 1 This is a diagram illustrating a schematic configuration example of the semiconductor memory device 1 according to an embodiment. More specifically, Figure 1 (a) is a cross-sectional view of semiconductor memory device 1 along the X direction. Figure 1 (b) is a schematic top view showing the layout of semiconductor memory device 1.

[0026] However, in Figure 1 In (a) of the figure, the shading lines are omitted for ease of viewing. Furthermore, in Figure 1 In (a), except for indicating that the components may not exist in the same cross section, some upper-layer wiring is omitted.

[0027] Furthermore, in this specification, the X and Y directions refer to the directions facing the surface of the word line WL, and the X and Y directions are orthogonal to each other. Additionally, the direction in which the electrical output of the word line WL is pulled out is sometimes referred to as the first direction, which is along the X direction. Furthermore, the direction intersecting the first direction is sometimes referred to as the second direction, which is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing errors, the first and second directions may not be orthogonal.

[0028] like Figure 1 As shown in (a), the semiconductor memory device 1, from the bottom side of the paper, sequentially includes an electrode film EL, a source line SL, one or more select gate lines SGS, multiple word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which peripheral circuitry CBA is disposed.

[0029] On the electrode film EL, a source line SL is disposed on an insulating layer 60. Multiple plugs PG are disposed in the insulating layer 60, through which the source line SL maintains electrical conductivity with the electrode film EL. Although not shown, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are disposed on the same layer as the electrode film EL. On the source line SL, a select gate line SGS, multiple word lines WL, and a select gate line SGD are sequentially stacked to form a stacked body LM.

[0030] like Figure 1 As shown in (a) and (b), a memory region MR is disposed at the center of the multiple word lines WL in the X direction, and stepped regions SR are disposed at both ends of the multiple word lines WL in the X direction. These memory regions MR and stepped regions SR are divided into multiple regions by multiple plate-like portions LI that extend in the X direction through the multiple word lines WL.

[0031] Furthermore, the region between adjacent plate-shaped portions LI in the Y direction, containing the memory region MR and the stepped region SR, is called the block region BLK. As described later, the memory region MR contains multiple storage cells that non-volatilely store data, and the block region BLK becomes the unit for erasing this data.

[0032] Furthermore, between adjacent plate-shaped portions LI in the Y direction, multiple separation layers SHE are arranged to pass through the select gate line SGD and extend in the X direction. The multiple separation layers SHE cover the entire memory region MR, extend in the X direction, and reach a portion of the stepped regions SR at both ends in the X direction.

[0033] In the memory region MR, multiple pillars PL are arranged, extending through word lines WL and select gate lines SGD and SGS in the stacking direction. The lower end of the pillar PL reaches the source line SL. Multiple memory cells are formed at the intersection of the pillar PL and the word line WL. Thus, the semiconductor memory device 1 is configured, for example, as a 3D non-volatile memory in which memory cells are arranged in 3D within the memory region MR.

[0034] In the stepped region SR, multiple word lines WL and select gate lines SGD and SGS are processed into a stepped shape and terminated. At this time, as the memory region MR moves away in the X direction, the multiple word lines WL and select gate lines SGD and SGS constituting the stepped section move from the upper layer side to the lower layer side, so the height position of the stepped section decreases towards the source line SL. In other words, as the memory region MR moves away in the X direction, the height position of the stepped section in the stacked volume LM changes.

[0035] In addition, in this specification, the orientation of the faces of the plurality of stepped surfaces disposed in the stepped region SR is defined as the upward direction in the semiconductor memory device 1.

[0036] Furthermore, the separation layer SHE extends from the memory region MR to the stepped region SR, where the select gate lines SGD are processed into stepped portions. Thus, within a single block region BLK, the select gate lines SGD are separated into multiple regions. In other words, the separation layer SHE penetrates a portion above multiple word lines WL, and this upper portion is divided into a pattern of multiple select gate lines SGD.

[0037] In each segment of the stepped surface consisting of multiple word lines WL and select gate lines SGD and SGS, contacts CC are respectively configured to connect the word lines WL and select gate lines SGD and SGS to each layer. At this time, multiple contacts CC are configured for each of the stepped surfaces of the word lines WL (and select gate lines SGD and SGS). In the select gate line SGD, stepped surfaces are configured for each block separated by the separation layer SHE, allowing multiple contacts to be configured separately.

[0038] Here, within a single block region BLK, multiple contact points CC are configured on one side of the stepped regions SR on both sides of the X direction. Furthermore, when viewed from one side in the X direction, for example, multiple contact points CC are configured for every two block regions BLK.

[0039] In other words, Figure 1 In example (b), in the topmost block region BLK of the paper, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, for example, the stepped region SR on the left side of the paper. Furthermore, in the lower one and two lower block regions BLK of the same block region BLK, multiple contacts CC are arranged in the stepped regions SR at both ends in the X direction, and the stepped region SR on the right side of the paper. Moreover, in the bottommost block region BLK of the paper, multiple contacts CC are arranged in the stepped region SR on the left side of the paper.

[0040] therefore, Figure 1 In (a) shown in the figure, the junctions CC of the stepped regions SR at both ends in the X direction are junctions belonging to different block regions BLK and are not actually located on the same cross section.

[0041] Through these contacts CC, the word lines WL of the multi-layered stack are pulled out individually. More specifically, write voltages and read voltages are applied from these contacts CC to the memory cells contained in the memory region MR at the center of the multiple word lines WL, via the word lines WL at the same height as the memory cells.

[0042] Multiple word lines WL, select gate lines SGD, SGS, pillar PL, and contact CC are covered by insulating layer 50. Insulating layer 50 also extends around the structure.

[0043] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. On the surface of the semiconductor substrate SB, peripheral circuitry CBA, including transistors TR and wiring, is disposed. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuitry CBA electrically connected to these contacts CC. Thus, the peripheral circuitry CBA controls the electrical operation of the memory cell.

[0044] The peripheral circuit CBA is covered by an insulating layer 40. By bonding the insulating layer 40 with an insulating layer 50 covering multiple word lines WL, a semiconductor memory device 1 is formed, which includes multiple word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC, and the peripheral circuit CBA.

[0045] Next, use Figure 2 A detailed configuration example of semiconductor memory device 1 will be described. Figure 2 This is a diagram illustrating an example of the configuration of the semiconductor memory device 1 according to an embodiment.

[0046] In more detail, Figure 2 (a) is a cross-sectional view along the Y direction of the memory region MR of the semiconductor memory device 1. Figure 2 In (a), the structure below the insulating layer 60 and above the insulating layer 53 described later is omitted.

[0047] Figure 2 (b) is an enlarged cross-sectional view of the pillar PL at the height position of the selected gate lines SGD and SGS. Figure 2 (c) is an enlarged sectional view of column PL at the height position of word line WL. Figure 2 (d) is an enlarged sectional view of the junctions CCa and CCb at the height position of the character line WL.

[0048] Figure 2 (e) in the diagram is a cross-sectional view along the X direction of the stepped region SR of the semiconductor memory device 1. Figure 2 In (e), the structure below the insulating layer 60 and above the insulating layer 53 described later is omitted.

[0049] like Figure 2 As shown in (a), the source line SL has a multilayer structure on the insulating layer 60, for example, by sequentially stacking a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb. Furthermore, the intermediate source line BSL is disposed below the memory region MR of the multilayer LM.

[0050] The lower source line DSLa, the middle source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Among them, at least the middle source line BSL can be a conductive polysilicon layer with diffused impurities.

[0051] Additionally, the source line SL connects the insulating layer 50 on the outside of the stacked body LM to the peripheral circuit CBA via the electrode film EL through a through-connection (not shown) extending from the electrode film EL to the peripheral circuit CBA.

[0052] A stacked layer LM is configured on the source line SL. The stacked layer LM has stacked layers LMa and LMb with multiple word lines WL and multiple insulating layers OL stacked alternately.

[0053] The stacked layer LMa is positioned above the source line SL. Below the bottom word line WL of the stacked layer LMa, an insulating layer OL separates the layers, and multiple select gate lines SGS0 and SGS1 are sequentially arranged from the top side of the stacked layer LMa. The stacked layer LMb is positioned on the stacked layer LMa. Above the top word line WL of the stacked layer LMb, an insulating layer OL separates the layers, and multiple select gate lines SGD0 and SGD1 are sequentially arranged from the top side of the stacked layer LMb.

[0054] The number of word lines (WL) and select gate lines (SGD, SGS) in the multilayer matrix (LM) is arbitrary. The word lines (WL) and select gate lines (SGD, SGS) are, for example, tungsten or molybdenum layers. The insulating layer (OL) is, for example, a silicon oxide layer.

[0055] like Figure 2 (b) in the middle Figure 2 As shown in (d), metal element layer 28 and metal element layer 58 are sequentially arranged on both sides of the stacking direction of multiple word lines WL and select gate lines SGD and SGS.

[0056] When the word line WL is a tungsten layer or the like, the metal element layer 28, such as a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer, functions as a barrier metal layer to inhibit the diffusion of tungsten atoms into the vicinity of the word line WL. When the word line WL is a molybdenum layer or the like, the metal element layer 28, such as a molybdenum nitride layer, functions as a precursor when forming the word line WL.

[0057] The metal element layer 58, such as an aluminum oxide (Al2O3) layer, functions as a barrier insulating layer in the memory cell MC.

[0058] like Figure 2 As shown in (a), the upper surface of the laminate LM is covered by insulating layer 52. Insulating layer 52 is covered by insulating layer 53. Insulating layers 52 and 53, together with insulating layer 51 described later, constitute... Figure 1 Part of the insulating layer 50.

[0059] As described above, the laminated body LM is divided into multiple plate-like portions LI in the Y direction. That is, the plate-like portions LI are arranged relative to each other in the Y direction and extend along the lamination direction and the X direction of the laminated body LM.

[0060] Thus, the plate-shaped portion LI extends continuously from one end of the stacked body LM in the X direction to the other end, within the stacked body LM. Furthermore, the plate-shaped portion LI penetrates the stacked body LM and the upper source line DSLb, reaching the intermediate source line BSL in the memory region MR.

[0061] Furthermore, the plate-like portion LI may have, for example, a tapered shape in which the width in the Y direction decreases from the upper end to the lower end. Alternatively, the plate-like portion LI may have, for example, an arched shape in which the width in the Y direction is greatest at a specified position between the upper end and the lower end.

[0062] The plate-shaped portion LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polycrystalline silicon layer. The insulating layer 54 covers the adjacent sidewalls of the plate-shaped portion LI in the Y direction. The conductive layer 24 fills the inner side of the insulating layer 54.

[0063] However, the laminated body LM can also be divided in the Y direction by replacing the plate-shaped portion LI with a plate-shaped member filled with an insulating layer that extends through the laminated body LM and extends in the X direction.

[0064] Between adjacent plate-shaped portions LI in the Y direction, there are upper portions of the through-layer LMb and multiple separation layers SHE extending in the X direction. These separation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the select gate line SGD1.

[0065] In other words, by extending in the X direction between the plate-shaped portion LI and a portion of the memory region MR and the stepped region SR through these separation layers SHE that penetrate the upper portion of the stacked matrix LMb, the upper portion of the stacked matrix LMb is divided into the selected gate lines SGD0 and SGD1.

[0066] In the memory region MR, there are distributed columns PL that connect the stacked layer LM, the upper source line DSLb, the middle source line BSL, and the lower source line DSLa.

[0067] Multiple columns (PLs) are arranged, for example, in a zigzag pattern when viewed from the lamination direction of the laminate LM. Each column (PL) has a shape such as circular, elliptical, or oval, which is the cross-sectional shape along the layer direction of the laminate LM, that is, along the XY plane.

[0068] Furthermore, in the portions of the through-laminated body LMa and LMb, the column PL has a conical shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, in the portions of the through-laminated body LMa and LMb, the column PL has, for example, an arch shape in which the diameter and cross-sectional area are maximized at a designated position between the upper and lower layers side.

[0069] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stacked body LM, a channel layer CN that runs through the stacked body LM and is connected to the intermediate source line BSL, a capping layer CP covering the upper surface of the channel layer CN, and a core layer CR that becomes the core material of the pillar PL.

[0070] like Figure 2 As shown in (b) and (c), the memory layer ME has a multilayer structure in which a barrier insulating layer BK, a charge accumulation layer CT, and a tunnel insulating layer TN are sequentially deposited from the outer periphery of the pillar PL. More specifically, the memory layer ME is disposed on the side of the pillar PL except at the depth of the intermediate source line BSL. In addition, the memory layer ME is also disposed on the bottom surface of the pillar PL reaching the depth of the lower source line DSLa.

[0071] The channel layer CN is located inside the memory layer ME, penetrating the stack volume LM, the upper source line DSLb, and the intermediate source line BSL, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is covered by the memory layer ME and is disposed on the side and bottom surfaces of the pillar PL. A portion of the channel layer CN contacts the intermediate source line BSL on its side, thereby electrically connecting to the source line SL containing the intermediate source line BSL. Further inside the channel layer CN, the core layer CR is filled.

[0072] Furthermore, each of the multiple pillars PL has a capping layer CP at its upper end. The capping layer CP is disposed at the upper end of the pillar PL such that it at least covers the upper end of the channel layer CN and is connected to the channel layer CN. In addition, the capping layer CP is connected to the bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction, intersecting the pull-out direction of the word line WL.

[0073] In addition, Figure 2 In (a) of the diagram, in the six pillars PL, three separate select gate lines SGD are connected and electrically connected to each other. Figure 2 In (a) shown, only three posts PL of the bit line BL are connected to the plug CH. The other posts PL are connected to... Figure 2 The cross-section shown in (a) at different locations, via Figure 2 (a) The plug CH (not shown) is connected to the Figure 2The other bit lines BL shown in (a) are parallel to the bit line BL and extend in the direction along the Y direction.

[0074] The memory layer ME consists of a barrier insulating layer BK, a tunnel insulating layer TN, and a core layer CR, which are, for example, silicon oxide layers. The charge accumulation layer CT of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN and the capping layer CP are, for example, semiconductor layers such as polycrystalline silicon or amorphous silicon layers.

[0075] like Figure 2 As shown in (c), with the above configuration, memory cells MC are formed on the side of the column PL opposite to each word line WL. Data is written to and read from the memory cells MC by applying a specified voltage from the word line WL.

[0076] In addition, such as Figure 2 As shown in (b), select gate STD is formed on the side of pillar PL opposite to the select gate lines SGD0 and SGD1 on the upper layer of the bit line WL. Furthermore, select gate STS is formed on the side of pillar PL opposite to the select gate lines SGS0 and SGS1 on the lower layer of the bit line WL.

[0077] By applying specified voltages from the select gate lines SGD and SGS respectively, the select gates STD and STS can be turned on or off, thus setting the memory cell MC of the column PL to which the select gates STD and STS belong to to a selected state or a non-selected state.

[0078] Furthermore, metal-containing layers 28 and 58, covering the upper and lower surfaces of word lines WL, are also disposed in the word lines WL, facing the side of the pillar PL. As described above, the metal-containing layer 58, interposed between the word lines WL and the pillar PL, functions as a metal-containing barrier insulating layer in the memory cell MC.

[0079] like Figure 2 As shown in (e), the stepped region SR has a stepped portion SP that processes multiple word lines WL and select gate lines SGD and SGS into a stepped shape. Figure 2 The stepped section SP shown in (e) is a part of the stepped region SR that is divided into multiple block regions BLK, which is used for the configuration of the contact CC and has the function of pulling out the word line WL.

[0080] The stepped portion SP is covered by insulating layer 51. Insulating layer 51 extends, for example, to the height of the uppermost layer of the laminate LM, and insulating layers 52 and 53 also cover the upper surface of insulating layer 51. As described above, insulating layer 51 also constitutes... Figure 1 Part of the insulating layer 50.

[0081] Furthermore, in the stepped region SR, the source line SL has an intermediate insulating layer SCO disposed between the upper source line DSLb and the lower source line DSLa, replacing the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0082] Therefore, the plate-shaped portion LI penetrates the insulating layer 51, the laminate LM and the upper source line DSLb in the stepped region SR, and reaches the intermediate insulating layer SCO.

[0083] like Figure 2 As shown in (d), multiple word lines WL, etc., are paired by combining one word line WL with one insulating layer OL, and are processed in such a way that each pair constitutes one step S. Figure 2 In example (d), the word lines WL and the insulating layer OL are arranged in pairs to form one step S. In addition, the step surface T of each step S is the part in which the multiple word lines WL and the insulating layer OL belonging to these steps S are processed into a stepped shape with the uppermost pair of word lines WL and the insulating layer OL.

[0084] like Figure 2 As shown in (e), each contact CC of the stepped portion SP penetrates the insulating layer 51 and is connected to multiple word lines WL or select gate lines SGD and SGS constituting the step S of the stepped portion SP. More specifically, in each step portion T of the stepped portion SP, the same number of contacts CC as the word lines WL contained in the step S are arranged, and are connected to the word lines WL corresponding to the step portion T of the step S, and the word lines WL of the lower layer that are continuous with the word lines WL in the stacking direction of the stacked body LM.

[0085] exist Figure 2 In example (e), as described above, a step S includes two pairs of word lines and an insulating layer, and two contacts CCa and CCb are arranged on the step surface S. Of the two contacts CCa and CCb, contact CCa is connected to the word line WL on the upper side of the step surface T, and contact CCb is connected to the word line WL on the next lower layer than the word line WL to which contact CCa is connected.

[0086] Furthermore, as mentioned above, the number of character lines WL, etc., contained in one step S is arbitrary and can be disregarded. Figure 2 In example (e), more than three contact points CC are configured on a step face T, depending on the number of word lines WL, etc., contained in a step S. These contact points CC are connected to each of the word lines WL, etc. contained in the step S.

[0087] Furthermore, the number of pairs of word lines WL and insulating layers OL in each step S can be the same in all steps S, or it can be different in some or all steps S. Therefore, the number of contacts CC arranged in each step face T can also be adjusted accordingly. In this case, the number of contacts CC arranged in each step face T may not be multiple, and may include one or more step faces T with only one contact CC.

[0088] Furthermore, the arrangement order of the contacts CC on a single-level face T is arbitrary. That is, these contacts CC can be arranged as follows: Figure 2 As in example (e), the arrangement can be in the X direction, the Y direction, or any other arrangement.

[0089] Furthermore, the configuration order of these contact CCs can also be as follows: Figure 2 As in example (e), the contacts CC that are connected to word lines WL, etc., on the upper layer side can be configured closer to the memory region MR in the X direction, or they can be configured further away from the memory region MR in the X direction. Alternatively, when the contacts CC are arranged in the Y direction, the contacts CC that are connected to word lines WL, etc., on the upper layer side can be configured closer to one side in the Y direction. Moreover, the contacts CC can be configured regardless of the height position of the connected word lines WL, etc., in the stack LM.

[0090] Each contact CC may have, for example, a conical shape in which the diameter and cross-sectional area decrease from the upper end to the lower end. Alternatively, the contact CC may have an arc shape in which the diameter and cross-sectional area are maximized at a designated position between the upper and lower ends.

[0091] Furthermore, each contact CC (CCa, CCb) has a conductive layer 25, such as a tungsten or copper layer, extending in the stacking direction of the stacked body LM within the insulating layer 51. These conductive layers 25 are connected to upper layer wiring MX disposed in the insulating layer 53 via plugs V0 disposed in the insulating layer 52. The upper layer wiring MX is connected to the peripheral circuit CBA (reference) Figure 1 Electrical connection.

[0092] like Figure 2 As shown in (d) and (e), among the multiple contacts CC configured in a single step surface T, except for the contact CCa which is connected to the word line WL on which the step surface T is set, the conductive layer 25 passes through the word line WL on the upper side of the step surface T and reaches the word line WL of the connected object in the other contacts CCb.

[0093] Thus, each contact CCb having a conductive layer 25 having word lines WL and the like extending through the upper layer has an insulating layer 55, such as a silicon oxide layer, covering the sidewalls of the conductive layer 25. The insulating layer 55 extends from the upper end of the conductive layer 25 of each contact CCb to the lower end of the conductive layer 25 connected to each word line WL and the like.

[0094] Therefore, in the contact CCb, the portion of the conductive layer 25 that extends through the upper word lines WL, etc., is covered by the insulating layer 55, which inhibits the conductive layer 25 from conducting with word lines WL, etc., that are not connected.

[0095] With this configuration, the word lines WL of each layer, and the select gate lines SGD and SGS of the upper and lower layers of the word lines WL, can be electrically pulled out from one end or the other end of the stacked layer LM in the X direction. In other words, with this configuration, a specified voltage can be applied to the memory cell MC from the peripheral circuit CBA via the upper layer wiring MX, the contact CC, and the word lines WL, so that the memory cell MC operates as a memory element.

[0096] In addition, the metal-containing layers 28 and 58 covering the upper and lower surfaces of the word line WL also cover the terminal part of the word line WL in the stepped part SP, that is, the end face that is in contact with the insulating layer 51.

[0097] Furthermore, metal element layers 28 and 58 are also disposed on the opposite side of the word lines WL, etc., and the side of the contact CCb. More specifically, as described above, the conductive layer 25 of the contact CCb extends through the upper word lines WL, etc., and connects to the lower word lines WL, etc. Metal element layers 28 and 58 are sequentially disposed on the opposite side of the contact CCb where the conductive layer 25 extends through the word lines WL, etc. That is, the insulating layer 55 covering the sidewall of the conductive layer 25 of the contact CCb separates the metal element layers 58 and 28 and is opposite to the word lines WL.

[0098] Furthermore, preferably, the conductive layer 25 of the contacts CCa and CCb connected to the word lines WL, etc., extends through and covers the metal element-containing layers 28 and 58 on the upper surface of the word lines WL, etc., to which the connection is made, and at least the metal element layer 58 is included. The conductive layer 25 of these contacts CCa and CCb may also extend through the metal element-containing layer 28 and be directly connected to the word lines WL, etc.

[0099] like Figure 2 As shown in (e), in the stepped region SR, multiple columnar portions HR are dispersedly arranged, extending through the stacked body LM, the upper source line DSLb, the intermediate insulating layer SCO, and reaching the lower source line DSLa. These columnar portions HR serve to support the aforementioned structure when the stacked body LM is formed from the stacked body with the sacrificial layer and the insulating layer in the manufacturing process of the semiconductor memory device 1 described later, but do not contribute to the function of the semiconductor memory device 1.

[0100] Therefore, the multiple columnar portions HR are individual units of insulating layers 59 such as silicon oxide layers extending in the stacking direction within the stacked body LM, and are not electrically connected to the source line SL.

[0101] Multiple columnar sections HR are arranged in a serrated or grid-like configuration, while avoiding interference with the plate-like sections LI and the junctions CC, when viewed from the lamination direction of the laminate LM. Each columnar section HR has a shape such as circular, elliptical, or oval, which serves as the cross-sectional shape along the layer direction of the laminate LM, that is, along the XY plane.

[0102] Furthermore, the columnar portion HR in the portions of the laminar body LMa and LMb respectively has a conical shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the columnar portion HR in the portions of the laminar body LMa and LMb respectively has, for example, an arch shape in which the diameter and cross-sectional area are maximized at a designated position between the upper and lower layers side.

[0103] At the same height position in the laminate LM, the cross-sectional area of ​​the columnar portion HR along the XY plane is, for example, greater than the cross-sectional area of ​​the column PL along the XY plane. Furthermore, the spacing between the multiple columnar portions HR is, for example, greater than the spacing between the multiple column PL, and the density of columnar portions HR per unit area of ​​word lines WL in the laminate LM is lower than the density of column PL per unit area of ​​word lines WL.

[0104] Thus, for example, by reducing the cross-sectional area of ​​the pillars PL compared to the columnar portion HR, and by setting them to a narrow pitch, multiple memory cells MC can be formed at high density within a stacked matrix LM of a specified size, thereby increasing the storage capacity of the semiconductor memory device 1. On the other hand, since the columnar portion HR is specifically designed to support the stacked matrix LM, for example, by not setting it to a precision configuration with a small cross-sectional area and narrow pitch like the pillars PL, the processing precision required to form the columnar portion HR can be relaxed.

[0105] (Manufacturing method of semiconductor memory device)

[0106] Next, use Figures 3 to 12 The manufacturing method of the semiconductor memory device 1 according to the embodiment will be described. Figures 3 to 11 This is a cross-sectional view that is part of the sequence of methods for manufacturing the semiconductor memory device 1 according to the embodiments.

[0107] first, Figure 3 The diagram shows the lower layer of the stacked matrix LM before the word line WL is formed, namely the stacked matrix LMsa, and the various configurations formed in the stacked matrix LMsa. Figure 3 This is a cross-sectional view along the X direction of the region that will later become the memory region MR and the step region SR.

[0108] like Figure 3 As shown in (a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are sequentially formed on a supporting substrate SS.

[0109] The supporting substrate SS can be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. The insulating layer 60 (see reference) can also be formed on the upper surface of the supporting substrate SS. Figure 2 wait).

[0110] An intermediate sacrificial layer SCN is formed on a region of the support substrate SS that will later become the memory region MR, and an intermediate insulating layer SCO is formed on a region of the support substrate SS that will later become the step region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which is later replaced by a polysilicon layer to become the intermediate source line BSL. The intermediate insulating layer SCO, as described above, is, for example, a silicon oxide layer.

[0111] Furthermore, on the upper source line DSLb, multiple insulating layers NL and multiple insulating layers OL are alternately deposited layer by layer to form a stacked body LMsa. The insulating layer NL, such as a silicon nitride layer, functions as a sacrificial layer that is later replaced with a conductive material to become the word line WL or the select gate line SGS.

[0112] like Figure 3 As shown in (b), in a portion of the stacked matrix LMsa, which later becomes the stepped region SR, the insulating layers NL and OL are processed into a stepped shape. This processing can be performed by thinning a mask pattern such as a photoresist layer and repeatedly etching the insulating layers NL and OL of the stacked matrix LMsa. In each etching of the insulating layers NL and OL, a subsequent step S (refer to...) is made. Figure 2 The amount of layers contained in (d) is used to process the insulating layer NL and the insulating layer OL.

[0113] In other words, as described Figure 2 As in examples (d) and (e), when a step S includes two pairs of insulating layers NL and OL, a mask pattern is formed on the upper surface of the laminate LMsa, and the exposed portions of the insulating layers NL and OL are etched away to remove the two pairs. Furthermore, by treatment with oxygen plasma or the like, the ends of the mask pattern are retracted, exposing the upper surface of the laminate LMsa again, and the insulating layers NL and OL are etched away again to remove the two pairs. By repeating this process multiple times, the stepped shape is formed. The stepped shape has multiple stepped surfaces Ts at different height positions in the laminate LMsa.

[0114] like Figure 3As shown in (c), an insulating layer 51 is formed covering the stepped portion and reaching the height of the upper surface of the laminate LMsa. The insulating layer 51 is also formed in the outer region of the laminate LMsa.

[0115] like Figure 3 As shown in (d), multiple memory holes MHa and multiple holes HLa are formed to extend the stacked body LMsa in the stacking direction.

[0116] The memory hole MHa is the lower part of the structure that will later become the pillar PL. Multiple memory holes MHa are arranged in the region that will later become the memory region MR, penetrating the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reaching the lower source line DSLa.

[0117] The via HLa is the lower structure of the columnar section HR. Multiple vias HLa are arranged in the region that will later become the stepped region SR, penetrating the insulating layer 51, the laminate LMsa, the upper source line DSLb, and the intermediate insulating layer SCO, and reaching the lower source line DSLa.

[0118] like Figure 3 As shown in (e), the memory holes MHa and HLa are filled with a sacrificial layer 26, such as an amorphous silicon layer. Thus, in the region that subsequently becomes the memory region MR, pillars PLc are formed in the plurality of memory holes MHa filled with the sacrificial layer 26. Furthermore, in the region that subsequently becomes the stepped region SR, pillar-shaped portions HRc are formed in the plurality of holes HRa filled with the sacrificial layer 26.

[0119] Next, the upper part of the stacked body LM before the word line WL is formed, namely the stacked body LMsb, and the various configurations formed in the stacked bodies LMsa and LMsb are shown. Figure 4 and Figure 5 . Figure 4 and Figure 5 With the Figure 3 Similarly, this is a cross-sectional view along the X direction of the region that will later become the memory region MR and the step region SR.

[0120] like Figure 4 As shown in (a), a multilayer LMsa is formed, which includes a portion processed into a stepped shape, and a multilayer LMsb is formed by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL of the multilayer LMsb functions as a sacrificial layer that is later replaced with a conductive material to become a word line WL or a select gate line SGD.

[0121] like Figure 4 As shown in (b), in a portion of the laminate LMsb, insulating layers NL and OL are processed into a stepped shape. This processing is consistent with the aforementioned... Figure 3The process shown in (b) can also be performed by repeatedly thinning the mask pattern such as the photoresist layer and etching multiple pairs of insulating layers NL and OL of the stacked body LMsa.

[0122] At this point, the uppermost segment of the stepped portion already formed in the laminate LMsa is brought close to the lowermost segment of the stepped portion formed in the laminate LMsb, and they are formed in a manner that continuously connects from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. Thus, a stepped shape is obtained in which a single step contains multiple pairs of insulating layers NL and OL, forming stepped facets Ts at different height positions in the laminate LMsb.

[0123] like Figure 4 As shown in (c), an insulating layer 51 is formed that covers the laminate LMsa and the stepped portion reformed on the laminate LMsb, reaching the height of the upper surface of the laminate LMsb. The insulating layer 51 is also formed in the outer region of the laminates LMsa and LMsb.

[0124] like Figure 5 As shown in (a), a plurality of memory holes MHb and a plurality of holes HLb are formed to extend the stacked body LMsb in the stacking direction.

[0125] The memory holes MHb are the upper structure of the pillar PL that will later become the memory region MR. Multiple memory holes MHb are arranged in the region that will later become the memory region MR, penetrating the stack LMsb and reaching the upper end of the pillar PLc formed in the stack LMsa.

[0126] The pores HLb are the upper structure of the columnar portion HR that will later become the columnar portion HR. Multiple pores HLb are arranged in the region that will later become the stepped region SR, penetrating the laminate LMsb and reaching the upper end of the columnar portion HRc formed in the laminate LMsa.

[0127] like Figure 5 As shown in (b), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, memory holes MHa open at the bottom of the multiple memory holes MHb, forming multiple memory holes MH that penetrate the stacked layers LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, reaching the lower source line DSLa.

[0128] In parallel, the sacrificial layer 26 is removed from the columnar portion HRc at the bottom of the via HLb. As a result, vias HLa open at the bottom of the multiple vias HLb, forming multiple vias HL that penetrate the insulating layer 51, the laminates LMsb and LMsa, the upper source line DSLb, and the intermediate insulating layer SCO, reaching the lower source line DSLa.

[0129] like Figure 5As shown in (c), a sacrificial layer 26 is refilled within multiple memory vias MH to form multiple pillars PLs extending through the stacked layers LMsa and LMsb. Furthermore, an insulating layer 59 is filled within multiple vias HL to form multiple pillar-shaped portions HR.

[0130] In addition, the laminates LMsa and LMsb are appropriately stepped. However, the step structure of the laminates LMsa and LMsb can also be formed in a concentrated manner during the aforementioned stage.

[0131] In this case, after forming the pillars PLs and columnar portions HR of the laminates LMsa and LMsb before forming the stepped structure, a stepped structure can be formed together in a portion of the laminates LMsa and LMsb. At this time, the columnar portions HR are processed in parallel with the insulating layers NL and OL being processed into a stepped shape, and the upper end of each columnar portion HR becomes approximately the same height as the upper surface of each of the insulating layers OL that are processed into a stepped shape.

[0132] Next, use Figure 6 and Figure 7 This shows the state in which the stepped-shaped portions of the laminates LMsa and LMsb are formed and then become the junction CC. Figure 6 and Figure 7 This is a cross-sectional view along the X direction of the area that will later become the stepped area SR.

[0133] like Figure 6 As shown in (a), multiple contact holes CL are formed, including a through insulating layer 51, an insulating layer OL with a stepped surface Ts, and an insulating layer NL reaching the stepped surface Ts. Figure 6 In example (a) of the above, with 1 step S (reference) Figure 2 The number of layers of word lines WL, etc., contained in (d) are used to set two contact holes CL in one step face Ts.

[0134] like Figure 6 As shown in (b), a resist pattern 90 is formed in one of the plurality of contact holes CL disposed on each step surface Ts, with the other contact hole CL having an opening. The remaining contact holes CL, except for the one contact hole CL, are covered by the resist pattern 90. The resist pattern 90 may also fill the contact holes CL.

[0135] like Figure 6 As shown in (c), additional etching is performed on the contact holes CL that open from the resist pattern 90, so that the lower ends of these contact holes CL reach the insulating layer NL below the insulating layer NL of the step surface Ts.

[0136] Additionally, when the face Ts is configured with more than 3 contact holes CL, repeat... Figure 6 The processes in (b) and (c) form multiple contacts with varying depths. This results in the formation of an insulating layer NL reaching the stepped surface Ts, and multiple contact holes CL extending from the insulating layer NL in the stacking direction for one or more consecutive insulating layers NL.

[0137] like Figure 7 As shown in (a), the contact hole CL of the insulating layer NL connected to the step surface Ts is kept covered with the resist pattern 90, and the insulating layer 55 is formed on the sidewall and bottom surface of the remaining contact hole CL.

[0138] like Figure 7 As shown in (b), the insulating layer 55 is removed from the bottom surface of the contact hole CL. Then, the resist pattern 90 is removed by ashing with oxygen plasma or the like.

[0139] like Figure 7 As shown in (c), a sacrificial layer 27, such as an amorphous silicon layer, is filled into multiple contact holes CL. This forms multiple contacts CCca and CCcb, each filled with the sacrificial layer 27. Contact CCca is configured without an insulating layer 55 covering the sacrificial layer 27, and subsequently becomes contact CCa. Contact CCcb is configured with an insulating layer 55 covering the sacrificial layer 27, and subsequently becomes contact CCb.

[0140] Next, use Figure 8 and Figure 9 This illustrates the formation of a pillar PL within a multi-layered structure within a memory hole MH. Figure 8 and Figure 9 This is a cross-sectional view along the Y direction of the region that will later become the memory region MR.

[0141] like Figure 8 As shown in (a), the sacrificial layer 26 is removed from the... Figure 5 The process in (c) removes the multiple pillars PLs formed, causing the multiple memory holes MH to reopen.

[0142] like Figure 8 As shown in (b), multiple insulating layers MEb, semiconductor layers CNb, and insulating layers CRb are sequentially formed inside the memory hole MH. Thus, multiple insulating layers MEb and semiconductor layers CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0143] The multilayer insulating layer MEb is the insulating layer that later becomes the memory layer ME in a multilayer structure. The semiconductor layer CNb is the layer that later becomes the channel layer CN. The insulating layer CRb is the silicon oxide layer that later becomes the core layer CR, etc.

[0144] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also sequentially formed on the upper surface of the laminate LMsb.

[0145] like Figure 8 As shown in (c), in the region that subsequently becomes the memory region MR, the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the upper surface of the stack LMsb. At the same time, a recess DN with the insulating layer CRb and the semiconductor layer CNb removed is formed at the upper end of the memory hole MH.

[0146] Thus, within the memory hole MH, the memory layer ME, the channel layer CN, and the core layer CR are formed sequentially from the outer periphery.

[0147] like Figure 9 As shown in (a), in the region that later becomes the memory region MR, a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is the layer that later becomes the capping layer CP. The semiconductor layer CPb is also formed on the upper surface of the stack LMsb.

[0148] like Figure 9 As shown in (b), in the region that will later become the memory region MR, the semiconductor layer CPb on the upper surface of the stack LMsb is removed by CMP (Chemical Mechanical Polishing) or the like, and a capping layer CP is formed at the upper end of the memory hole MH.

[0149] like Figure 9 As shown in (c), an insulating layer OL is added to the top layer of the laminate LMsb, which is thinned by CMP or other methods.

[0150] Thus, the capping layer CP is buried within the uppermost insulating layer OL of the pillar PL. However, at that point, the memory layer ME covers the entire sidewall of the pillar PL and is not exposed from the memory layer ME as part of the sidewall of the channel layer CN.

[0151] In addition, the columnar portion HR can also be obtained through the above. Figure 9 CMP processing in (b) and Figure 9 The addition of insulating layer OL in (c) results in a state where the upper end is buried in the uppermost insulating layer OL and covered by a stepped insulating layer 51.

[0152] Next, use Figure 10 and Figure 11 This shows the formation of the source line SL and the word line WL. Figure 10 and Figure 11 With the Figure 8 and Figure 9 Similarly, this is a cross-sectional view along the Y direction of the region that will later become the memory region MR.

[0153] like Figure 10 As shown in (a), a gap ST is formed that connects the stacked layers LMsb, LMsa, and the upper source line DSLb to the intermediate sacrificial layer SCN. In addition, an insulating layer 54s is formed on the adjacent sidewalls of the gap ST in the Y direction.

[0154] The slot ST has a conical or arc-shaped longitudinal section in the Y direction and extends in the X direction within the laminates LMsa and LMsb. Therefore, in the stepped region SR (not shown), the lower end of the slot ST reaches the intermediate insulating layer SCO.

[0155] like Figure 10 As shown in (b), the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb is removed by allowing a removal solution, such as hot phosphoric acid, to flow in through the gap ST of the sidewall protected by the insulating layer 54s.

[0156] Thus, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs.

[0157] like Figure 10 As shown in (c), the drug solution flows appropriately into the interstitial layer GPs through the gap ST, exposing the memory layer ME, the barrier insulating layer BK, the charge accumulation layer CT, and the tunnel insulating layer TN (see reference) within the interstitial layer GPs. Figure 2 (b) and (c) are removed sequentially. As a result, the memory layer ME is removed from a portion of the sidewall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0158] like Figure 10 As shown in (d), a raw material gas, such as amorphous silicon, is injected into the gap ST, whose sidewalls are protected by an insulating layer 54s, to fill the interstitial layers GPs with amorphous silicon. Furthermore, the supporting substrate SS is heat-treated to polycrystalline the amorphous silicon filled in the interstitial layers GPs, forming an intermediate source line BSL containing polycrystalline silicon.

[0159] Thus, a portion of the channel layer CN of the pillar PL is connected to the source line SL laterally via the intermediate source line BSL.

[0160] At this point, in the stepped region SR (not shown), no gap layer GPs are formed between the lower source line DSLa and the upper source line DSLb. Furthermore, the intermediate source line BSL is not formed.

[0161] like Figure 11 As shown in (a), the insulating layer 54s on the sidewall of the gap ST is temporarily removed.

[0162] like Figure 11 As shown in (b), a removal solution for insulating layer NL, such as hot phosphoric acid, flows into the interior of the laminates LMsa and LMsb from the gap ST, removing the insulating layer NL of the laminates LMsa and LMsb. This forms laminates LMga and LMgb with multiple gap layers GP, where the insulating layer NL between the insulating layers OL has been removed.

[0163] At this point, the stacked layers LMga and LMgb, which contain multiple interstitial layers GP, become a fragile structure. In the region that subsequently becomes the memory region MR, multiple pillars PL support this fragile stacked layer LMga and LMgb.

[0164] The support structure of this column PL suppresses the deflection of the remaining insulation layer OL, or the deformation and collapse of the laminate LMga and LMgb.

[0165] like Figure 11 As shown in (c), a raw material gas containing conductive materials such as tungsten or molybdenum is injected from the gap ST into the interior of the laminates LMga and LMgb, and the conductive material fills the interstitial layer GP of the laminates LMga and LMgb to form multiple word lines WL, etc.

[0166] In addition, although not shown in the figure, before forming multiple word lines WL, metal-containing layers 58 and 28 are sequentially formed on the upper and lower surfaces of the gap layer GP, the surface opposite to the side wall of the column PL, and the surface opposite to the contact CCcb.

[0167] Based on the above, a multilayer LM is formed, consisting of multiple word lines WL and multiple insulating layers OL stacked alternately.

[0168] As mentioned above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also referred to as replacement processes.

[0169] Subsequently, an insulating layer 54 is formed on the sidewall of the gap ST, and a conductive layer 24 is filled inside the insulating layer 54 to form a plate-shaped part LI. However, it is also possible to fill the gap ST with an insulating layer 54 instead of a conductive layer 24 to form a plate-shaped component.

[0170] Furthermore, by forming a trench through the topmost layer of the stacked body LMb and the second conductive layer from the topmost layer, and filling the trench with an insulating layer 56, a separation layer SHE is formed that divides the conductive layer into a pattern of selected gate lines SGD.

[0171] Furthermore, the sacrificial layer 27 is removed from the plurality of contacts CCc (CCca, CCcb) already formed on the stepped portion SP, and replaced by a conductive layer 25 to form a plurality of contacts CC. When removing the sacrificial layer 27 from the plurality of contacts CC, it is preferable to also remove the metal element layer 58 (see reference) covering the word line WL, etc., which is the connection object of the contacts CC. Figure 2 (d) etc.). At this time, the metal element layer 28 can also be removed.

[0172] Furthermore, an insulating layer 52 is formed on the upper surface of the stacked body LM and the upper surface of the insulating layer 51 covering the stepped region SR. A plug V0 connected to the contact CC is formed through the insulating layer 52. Additionally, a plug CH connected to the post PL is formed through the insulating layer 52. Moreover, an insulating layer 53 is formed on the insulating layer 52, forming upper wiring MX and bit lines BL connected to the plugs V0 and CH. Furthermore, an electrode pad for achieving electrical conductivity with the peripheral circuit CBA is formed on the upper surface of the insulating layer 53.

[0173] Alternatively, by using methods such as dual damascene, plugs V0, CH, upper-layer routing MX, and bit lines BL can be formed simultaneously.

[0174] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB, separate from the support substrate SS on which the stacked body LM is formed, and is covered by an insulating layer 40. In the insulating layer 40, contacts, vias, wiring, etc., are formed to pull the peripheral circuit CBA to the surface of the insulating layer 40, and are connected to electrode pads, etc., formed on the upper surface of the insulating layer 40.

[0175] Next, the support substrate SS and the semiconductor substrate SB are bonded together with insulating layers 50 and 40 respectively, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0176] Based on the above, a semiconductor memory device 1 is manufactured according to the embodiment.

[0177] However, as mentioned above, the number of contacts CC arranged in a step face T is equal to the number of layers of word lines WL, etc. contained in a step S. Furthermore, the arrangement order of these contacts CC in the step face T is arbitrary.

[0178] The following uses Figure 12 The following are examples of the arrangement order of multiple contact holes CL configured on a 1st face Ts, together with the method of forming the contact hole CL.

[0179] Figure 12 This is a schematic diagram showing the arrangement order of the contact holes CL in an exemplary embodiment. Additionally, Figure 12This example shows a step S containing two pairs of insulating layers NL and OL, thus forming two contact holes CL in a step surface Ts.

[0180] Figure 12 (a) in Figure 12 (d) is an example of multiple facets T in the lamination volume LM where the height position varies in the X and Y directions.

[0181] In other words, in this example, the stepped shape in the stepped portion SP ascends towards the memory region MR in the X direction, and also ascends unilaterally in the Y direction. Therefore, the stepped portion SP in this example contains multiple stepped surfaces T that are adjacent to each other in the X direction and also adjacent in the Y direction. In this example, two stepped surfaces T are arranged opposite each other in the Y direction.

[0182] Thus, a stepped structure in which the height position of the step facet T changes not only in the X direction but also in the Y direction within the laminated body LM is called a multi-row stepped structure, etc. Figure 12 (a) in Figure 12 In example (d), since the multiple stepped surfaces Ts arranged in the X direction are arranged in two columns in the Y direction, it is called a two-column stepped structure, etc.

[0183] Figure 12 Image (a) shows the state at the point in time when the contact hole CL of the insulating layer NL, which penetrates the insulating layer 51 and reaches each step surface Ts, is formed. That is, Figure 12 (a) in the text is equivalent to the above. Figure 6 The state of (a) in the text.

[0184] In more detail, Figure 12 The lower part of (a) is a layout diagram, showing the numbers in the circle representing the contact hole CL as the contact hole CL reaches the insulation layer NL from the bottommost insulation layer NL. Figure 12 The upper part of (a) is Figure 12 (a) A sectional view of the lower segment of line A-A' in the middle.

[0185] like Figure 12 As shown in (a), between two adjacent plate-shaped portions LI formed subsequently in the Y direction, a plurality of stepped surfaces Ts arranged in the X and Y directions are formed. Furthermore, in these stepped surfaces Ts, arranged in the X direction, two contact holes CL are formed in each.

[0186] Here, the stepped surface Ts in the lower right corner of the paper is the stepped surface Ts located on the second insulating layer NL2 from the bottom layer, and the two contacts CL of the stepped surface Ts both reach the insulating layer NL2.

[0187] Furthermore, the stepped section Ts in the lower left corner of the paper is the stepped section Ts located on the 6th insulating layer NL6 from the bottom layer, and the two contacts CL of the stepped section Ts both reach the insulating layer NL6.

[0188] Furthermore, the stepped surface Ts in the upper right corner of the paper is the stepped surface Ts located on the fourth insulating layer NL4 from the bottom layer, and the two contacts CL of the stepped surface Ts both reach the insulating layer NL4.

[0189] Furthermore, the stepped surface Ts in the upper left corner of the paper is the stepped surface Ts located on the 8th insulating layer NL8 from the bottom layer, and the two contacts CL of the stepped surface Ts both reach the insulating layer NL8.

[0190] like Figure 12 As shown in (b), a resist pattern 91 is formed covering the four contact holes CL arranged at the boundaries of the four stepped surfaces Ts in the X direction. That is, Figure 12 (b) in the above is equivalent to the above. Figure 6 The state of (b) in the middle.

[0191] like Figure 12 As shown in (c), four additional etched contact holes CL are exposed from the resist pattern 91, extending from the insulating layer NL of the step surface Ts to the next insulating layer NL. That is, Figure 12 (c) in the text is equivalent to the above. Figure 6 The state of (c) in the middle.

[0192] Thus, in the stepped surface Ts at the lower right of the paper, the contact hole CL located on the side away from the stepped surface Ts at the lower left of the paper reaches the next insulating layer NL of the insulating layer NL2, which is the bottommost insulating layer NL1.

[0193] Furthermore, in the stepped section Ts at the lower left of the paper, the contact hole CL located on the side away from the stepped section Ts at the lower right of the paper reaches the next insulating layer NL of the insulating layer NL6, which is the fifth insulating layer NL5 from the bottom.

[0194] Furthermore, in the stepped section Ts on the upper right of the paper, the contact hole CL located on the side away from the stepped section Ts on the upper left of the paper reaches the next insulating layer NL of the insulating layer NL4, that is, the third insulating layer NL3 from the bottom.

[0195] Furthermore, in the stepped section Ts on the upper left of the paper, the contact hole CL on the side away from the stepped section Ts on the upper right of the paper reaches the next insulating layer NL of the insulating layer NL8, that is, the 7th insulating layer NL7 from the bottom layer.

[0196] Although not illustrated, an insulating layer 55 is subsequently formed covering the sidewalls and bottom surface of the four additionally etched contact holes CL as described above, and the insulating layer 55 on the bottom surface is removed. Additionally, the resist pattern 91 is removed.

[0197] Figure 12 (d) shows the state where the resist pattern 91 has been removed. Figure 12 The upper part of (d) is the layout diagram. Figure 12 The section following (d) is Figure 12 A sectional view of line A-A' in the upper segment (d) of the diagram. Figure 12 In the section below (d), the insulating layer 55 is omitted.

[0198] like Figure 12 As shown in (d), according to the above, eight contact holes CL are formed on the four step surfaces Ts, each reaching one of the eight insulating layers NL.

[0199] In other words, in the column on the lower side of the paper in the two stepped sections, contact holes CL are arranged sequentially from the right side of the paper in the X direction, reaching insulating layers NL1, NL2, NL6, and NL5 respectively. Furthermore, in the column on the upper side of the paper in the two stepped sections, contact holes CL are arranged sequentially from the right side of the paper in the X direction, reaching insulating layers NL3, NL4, NL8, and NL7 respectively.

[0200] As described above, in a multi-step structure where the height of multiple stepped surfaces T in the laminate LM varies in the X and Y directions, the arrangement of the contact holes CL is determined by the position of the insulating layer NL in the laminate LM to which the final contact holes CL are reached. This process takes time, and for example, it can reduce the number of times the resist pattern is formed, making it easier to form the contact holes CL.

[0201] Figure 12 (e) in Figure 12 (h) is an example of multiple facets T in the stacked volume LM where the height position varies in the X direction.

[0202] In other words, in this example, the stepped shape in the stepped portion SP ascends towards the memory region MR in the X direction. Therefore, the stepped portion SP in this example has multiple stepped surfaces T that are adjacent to each other in the X direction.

[0203] Figure 12 (e) shows the state at the point in time when the contact hole CL of the insulating layer NL, which penetrates the insulating layer 51 and reaches each step surface Ts, is formed. That is, Figure 12 (e) in the text is equivalent to the above. Figure 6 The state of (a) in the text.

[0204] also, Figure 12 The section below (e) is a layout diagram. Figure 12 The upper part of (e) is Figure 12 A sectional view of the lower segment (e) of line B-B'.

[0205] like Figure 12 As shown in (e), between two adjacent plate-shaped portions LI formed in the Y direction, a plurality of stepped surfaces Ts arranged in the X direction are formed. Furthermore, in each of these stepped surfaces Ts, arranged in the Y direction, two contact holes CL are formed.

[0206] Here, the stepped surface Ts on the right side of the paper is the stepped surface Ts located on the second insulating layer NL2 from the bottom layer, and the two contacts CL of the stepped surface Ts both reach the insulating layer NL2.

[0207] Furthermore, the second step surface Ts from the right of the paper is the step surface Ts located on the fourth insulating layer NL4 from the bottom layer, and the two contacts CL of the step surface Ts both reach the insulating layer NL4.

[0208] Furthermore, the third step surface Ts from the right of the paper is a step surface Ts located on the sixth insulating layer NL6 from the bottom layer, and the two contacts CL of the step surface Ts both reach the insulating layer NL6.

[0209] Furthermore, the stepped section Ts at the left end of the paper is the stepped section Ts located on the 8th insulating layer NL8 from the bottom layer, and the two contacts CL of the stepped section Ts both reach the insulating layer NL8.

[0210] like Figure 12 As shown in (f), in each of the four facets Ts, a resist pattern 92 is formed covering the four contact holes CL arranged on one side of the Y direction. That is, Figure 12 (f) in the text is equivalent to the above. Figure 6 The state of (b) in the middle.

[0211] like Figure 12 As shown in (g), four additional etched contact holes CL are exposed from the resist pattern 92, extending from the insulating layer NL of the step surface Ts to the next insulating layer NL. That is, Figure 12 (g) in the text is equivalent to the above. Figure 6 The state of (c) in the middle.

[0212] Thus, in the stepped surface Ts at the right end of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL2, which is the bottommost insulating layer NL1.

[0213] Furthermore, in the second step surface Ts from the right of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL4, which is the third insulating layer NL3 from the bottom.

[0214] Furthermore, in the third step surface Ts from the right of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL6, which is the fifth insulating layer NL5 from the bottom.

[0215] Furthermore, in the stepped section Ts on the left side of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL8, which is the 7th insulating layer NL7 from the bottom.

[0216] Although not illustrated, an insulating layer 55 is subsequently formed covering the sidewalls and bottom surface of the four additionally etched contact holes CL as described above, and the insulating layer 55 on the bottom surface is removed. Additionally, the resist pattern 92 is removed.

[0217] Figure 12 (h) in the figure shows the state where the resist pattern 92 has been removed. Figure 12 The upper part of (h) is the layout diagram. Figure 12 The section following (h) is Figure 12 A sectional view of line B-B' in the upper segment (h) of the image. Figure 12 The insulation layer 55 is omitted in the lower part of (h) in the text.

[0218] like Figure 12 As shown in (h), according to the above, eight contact holes CL are formed on the four step surfaces Ts, each reaching one of the eight insulating layers NL.

[0219] In other words, in the right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL1 and NL2 respectively. Furthermore, in the second right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL3 and NL4 respectively. Furthermore, in the third right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL5 and NL6 respectively. Furthermore, in the left-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL7 and NL8 respectively.

[0220] As described above, in a stepped structure where the height of multiple stepped surfaces T in the laminate LM varies in the X direction, the arrangement of the contact holes CL takes time depending on the position of the insulating layer NL in the laminate LM to which the final contact holes CL are reached. This can reduce the number of times the resist pattern is formed and make it easier to form the contact holes CL.

[0221] Figure 12 (i) in Figure 12 (l) is another example of how the height position of multiple facets T in the stacked volume LM varies in the X direction.

[0222] Figure 12 (i) in the above is equivalent to the Figure 6 The state of (a) in the text, in addition, shows the state with Figure 12 The example shown in (e) is in the same state. Figure 12 The upper part of (i) is the layout diagram. Figure 12 The next part of (i) is Figure 12 (i) A cross-sectional view of the upper segment of line C-C'.

[0223] In other words, two contact holes CL are configured on each of the four stepped surfaces Ts, and from the contact holes CL of the stepped surface Ts located on the right end of the paper, they sequentially reach the insulating layers NL2, NL4, NL6, and NL8 of the stepped surface Ts, respectively.

[0224] like Figure 12 As shown in (j), in the four stepped surfaces Ts, a resist pattern 93 is formed covering any of the two contact holes CL arranged in the Y direction. Figure 12 (j) in the above is equivalent to the above. Figure 6 The state of (b) in the middle.

[0225] More specifically, the contact hole CL is selected to be covered by the resist pattern 93, regardless of where the insulating layer NL in the stacked body LM is located, so that the final obtained contact hole CL is located.

[0226] Thus, when arbitrarily selecting the contact hole CL covered by the resist pattern 93, it is possible to replace the position of the insulating layer NL reached by the final obtained contact hole CL in the stacked body LM, based on manufacturing reasons or other reasons such as the performance of the semiconductor memory device 1.

[0227] Other reasons include, for example, the arrangement of the semiconductor memory device 1, which makes subsequent processing of the contact holes CL easier, the arrangement of the contacts CC corresponding to each function, or the arrangement of the upper layer wiring MX of the contacts CC, which makes the layout simpler.

[0228] Alternatively, the contact hole CL covered with resist pattern 93 may be randomly selected without any reason.

[0229] exist Figure 12 In example (j), for the four facets Ts, a resist pattern 93 is formed covering the contact holes CL that are alternately arranged in the Y direction. More specifically, starting from the facet Ts on the right side of the paper, the contact holes CL on one side of the Y direction, the contact holes CL on the other side of the Y direction, the contact holes CL on one side of the Y direction, and the contact holes CL on the other side of the Y direction are covered sequentially by the resist pattern 93.

[0230] like Figure 12 As shown in (k), four additional etched contact holes CL are exposed from the resist pattern 93, extending from the insulating layer NL of the step surface Ts to the next insulating layer NL. That is, Figure 12 (k) in the above is equivalent to the Figure 6 The state of (c) in the middle.

[0231] Thus, in the stepped surface Ts at the right end of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL2, which is the bottommost insulating layer NL1.

[0232] Furthermore, in the second step surface Ts from the right of the paper, among the two contact holes CL, the contact hole CL located on the upper side of the paper reaches the next insulating layer NL of the insulating layer NL4, which is the third insulating layer NL3 from the bottom.

[0233] Furthermore, in the third step surface Ts from the right of the paper, among the two contact holes CL, the contact hole CL located on the lower side of the paper reaches the next insulating layer NL of the insulating layer NL6, which is the fifth insulating layer NL5 from the bottom.

[0234] Furthermore, in the stepped section Ts on the left side of the paper, among the two contact holes CL, the contact hole CL located on the upper side of the paper reaches the next insulating layer NL after the insulating layer NL8, which is the 7th insulating layer NL7 from the bottom.

[0235] Although not illustrated, an insulating layer 55 is subsequently formed covering the sidewalls and bottom surface of the four additionally etched contact holes CL as described above, and the insulating layer 55 on the bottom surface is removed. Additionally, the resist pattern 93 is removed.

[0236] Figure 12 (l) shows the state where the resist pattern 93 has been removed. Figure 12 The upper part of (l) is the layout diagram. Figure 12 The lower part of (l) is Figure 12 A sectional view of the upper segment (l) along line C-C'. Figure 12 In the lower part of (l) in the text, the insulating layer 55 is omitted.

[0237] like Figure 12 As shown in (l), according to the above, eight contact holes CL are formed on the four stepped surfaces Ts, each reaching one of the eight insulating layers NL.

[0238] In other words, in the right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL1 and NL2 respectively. Furthermore, in the second right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL4 and NL3 respectively. Furthermore, in the third right-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL5 and NL6 respectively. Furthermore, in the left-hand section Ts of the paper, contact holes CL are formed sequentially in the Y direction from the bottom of the paper, reaching insulating layers NL8 and NL7 respectively.

[0239] As mentioned above, in Figure 12 (i) in Figure 12 In example (l), the arrangement order of the contact holes CL can be determined regardless of the height position of the insulating layer NL reached by the final obtained contact hole CL in the laminate LM, so for example, the degree of freedom of the arrangement order of the contacts CC can be increased.

[0240] The above describes an example of the arrangement order of the contacts CC when two contacts CC are configured on a single-level face T. However, the number of contacts CC configured on a single-level face T can also be three or more. However, the number of contacts CC configured on a single-level face T is preferably five or less, and more preferably three or less.

[0241] In this way, by limiting the number of word lines WL and other layers contained in one step S to a certain extent, the number of contacts CC arranged on one step surface T is limited. As a result, when forming the contact hole CL, by adding etching or the like, when the contact hole CL temporarily reaches the step surface Ts and reaches the insulating layer NL of the step surface Ts, the over-etching or failure to reach the target of the contact hole CL can be suppressed, and the processing accuracy can be fully obtained.

[0242] (Summary)

[0243] In semiconductor memory devices such as 3D non-volatile memory, multiple word lines can be stacked, processed into a stepped shape, and connected to contacts, allowing multiple stacked word lines to be electrically pulled out. To reduce the number of processes, contact holes, which will become the contacts, are formed together, for example.

[0244] However, it is difficult to form multiple contact holes with different depths at the same time, as there are concerns that contact holes with depths exceeding the expected depth or those failing to reach the target depth may be formed, leading to electrical continuity between word lines in different layers, or problems such as word lines not being connected to the target object. In addition, a stepped surface must be set in each of the multi-layer word lines to connect the contacts, which may result in an increase in the step length and compression of the memory area.

[0245] According to an embodiment, a semiconductor memory device 1 includes a plurality of contacts CC, which are disposed on a stepped portion T of a designated word line WL and are respectively connected to the designated word line WL and one or more lower-layer word lines WL that are continuous with the designated word line WL in the stacking direction. This allows for a reduction in the step length of the stepped portion SP and an increase in the area of ​​the memory region MR in the semiconductor memory device 1.

[0246] According to the semiconductor memory device 1 of the embodiment, in a stepped structure where the height position of multiple stepped surfaces T in a stacked layer LM varies in the X direction, word lines WL adjacent to the designated stepped surface T in the X direction are provided on the upper layer of the designated word lines WL, with the same number as the contacts CC provided on the designated stepped surface T. This reduces the number of stepped surfaces T in the stepped portion SP, shortening the step length of the stepped portion SP.

[0247] According to the semiconductor memory device 1 of the embodiment, in a stepped structure where the height position of multiple stepped surfaces T in a multilayer LM varies in the X direction, the contacts CC disposed on each stepped surface T are arranged in the Y direction. Among the contacts CC, the contacts CC that are connected to the word lines WL on the upper side of the multilayer LM are disposed more on the Y-direction side within the stepped surface T. As a result, the number of times the resist pattern 92 used to form the contacts CC can be reduced, and the contacts CC can be formed more easily.

[0248] According to the semiconductor memory device 1 of the embodiment, the contacts CC disposed on each step surface T are arranged in the Y direction. Among the contacts CC disposed on a designated step surface T, the contact CC that is connected to the word line WL on the upper side of the stacked layer LM is disposed on one side of the Y direction within the step surface T. Furthermore, among the contacts CC disposed on the step surface T adjacent to the step surface T in the X direction, the contact CC that is connected to the word line WL on the upper side of the stacked layer LM is disposed on the other side of the Y direction within the step surface T. This improves the flexibility of contact CC placement.

[0249] According to the semiconductor memory device 1 of the embodiment, in a multi-row stepped structure in which the height positions of multiple stepped surfaces T in the stacked layer LM vary in the X and Y directions, word lines WL adjacent to the designated stepped surface T in the Y direction are provided on the upper layer of the designated word lines WL, with the same number as the contacts CC provided on the designated stepped surface T. This reduces the number of stepped surfaces T in the stepped section SP, shortening the step length of the stepped section SP.

[0250] According to the semiconductor memory device 1 of the embodiment, in a multi-row stepped structure in which the height positions of multiple stepped surfaces T in a multilayer LM vary in the X and Y directions, word lines WL are provided on top of the designated word lines WL, with the same number as the total number of contacts CC provided on the designated stepped surface T and the contacts CC provided on the stepped surfaces T arranged in the Y direction. This reduces the number of stepped surfaces T in the stepped section SP and shortens the step length of the stepped section SP.

[0251] According to the semiconductor memory device 1 of the embodiment, in a multi-row stepped structure in which the height positions of multiple stepped surfaces T in a multilayer LM vary in the X and Y directions, the contacts CC disposed on each stepped surface T are arranged in the X direction. Among the contacts CC, the contacts CC that are connected to the word lines WL on the upper side of the multilayer LM are disposed closer to the adjacent stepped surface T in the X direction within the stepped surface T. As a result, the number of times the resist pattern 91 used to form the contacts CC can be reduced, and the contacts CC can be formed more easily.

[0252] According to the embodiment of the semiconductor memory device 1, a plurality of contacts CCa and CCb are arranged on the stepped portion T of a designated word line WL. Contact CCa is connected to the designated word line WL, and contact CCb is connected to the next lower word line WL. This shortens the step length of the stepped portion SP and increases the area of ​​the memory region MR in the semiconductor memory device 1.

[0253] According to the embodiment of the semiconductor memory device 1, contacts CCa and CCb each have a conductive layer 25 extending toward the step portion SP in the stacking direction, and contact CCb has an insulating layer 55 covering the conductive layer 25. This suppresses electrical conduction between the conductive layer 25 of contact CCb and the word line WL of the upper layer to which contact CCa is connected.

[0254] (Variation Example 1)

[0255] Next, use Figures 13-15The semiconductor memory device of Variation Example 1 of the Embodiment will be described. In the semiconductor memory device of Variation Example 1, the method of forming the contacts CC (CCa, CCc) is different from that in the Embodiment described above.

[0256] In addition, in the following figures, the same symbols are sometimes used to refer to the same components as those in the described embodiments, and their descriptions are omitted.

[0257] Figures 13-15 This is a cross-sectional view showing a portion of the sequence of methods for forming contacts CC (CCa, CCc) in Variation Example 1 of the embodiments. More specifically, Figures 13-15 This is a cross-sectional view along the X direction of the region that will later become a stepped region.

[0258] In Variation Example 1, the same procedure as described in the embodiment is followed. Figures 3-5 The processing involves shaping a portion of the laminates LMsa and LMsb into a stepped shape to form the columnar portion HR.

[0259] like Figure 13 As shown in (a), a plurality of contact holes CL are formed, which are through insulating layer 51, insulating layer OL with stepped surface Ts, and insulating layer NL reaching the stepped surface Ts.

[0260] like Figure 13 As shown in (b), a resist pattern 90 is formed in a plurality of contact holes CL disposed on each step surface Ts, with one contact hole CL portion having an opening.

[0261] like Figure 13 As shown in (c), the contact hole CL, which opens through the resist pattern 90, is processed by wet etching to remove the insulating layer NL exposed on the bottom surface of the contact hole CL. Since the wet etching process proceeds isotropically, the insulating layer NL removed from the bottom surface of the contact hole CL also recedes a specified distance from the sidewall of the contact hole CL in the outward direction. At this point, the insulating layer NL recedes approximately equidistantly from the sidewall of the contact hole CL.

[0262] like Figure 14 As shown in (a), an insulating layer 55c is formed on the sidewalls and bottom surface of the contact hole CL after wet etching. The insulating layer 55c also fills the voids created by the wet etching process that causes the insulating layer NL to recede.

[0263] like Figure 14 As shown in (b), additional etching is performed to open the contact hole CL from the resist pattern 90, removing the insulating layer 55c on the bottom surface of the contact hole CL, while simultaneously bringing the lower end of the contact hole CL to the next insulating layer NL of the step surface Ts.

[0264] Then, the resist pattern 90 is removed by ashing with oxygen plasma, etc.

[0265] like Figure 14 As shown in (c), a sacrificial layer 27, such as an amorphous silicon layer, is filled into multiple contact holes CL. This forms multiple contacts CCca and CCcc, each filled with the sacrificial layer 27.

[0266] Next, the insulation layer NL is replaced.

[0267] like Figure 15 As shown in (a), multiple word lines WL are formed through replacement processing.

[0268] like Figure 15 As shown in (b), the sacrificial layer 27 is removed from contacts CCca and CCcc respectively, and the multiple contact holes CL are opened again. At this time, it is preferable to also remove the metal element layer 58 covering the upper surface of the word lines WL, etc. (see reference). Figure 2 (d) etc.

[0269] like Figure 15 As shown in (c), a plurality of contacts CCa and CCc are formed by filling a plurality of contact holes CL with a conductive layer 25. Contact CCa has the same configuration as contact CCa in the embodiment described above, and contact CCc has a conductive layer 25 and an insulating layer 55c.

[0270] Based on the above, the contacts CC (CCa, CCc) of Variation Example 1 are formed.

[0271] According to the semiconductor memory device of Variation 1, the insulating layer 55c of the contact CCc extends from the upper end of the contact CCc to the portion of the conductive layer 25 of the contact CCc that passes through the word line WL of the upper layer to which the contact CCc is connected. This suppresses electrical conduction between the conductive layer 25 of the contact CCc and the word line WL of the upper layer to which the contact CCc is connected.

[0272] According to the semiconductor memory device of Variation 1, the thickness of the insulating layer 55c is thicker in the portion through which the conductive layer 25 of the contact CCc penetrates the word line WL of the upper layer to which the contact CCc is connected. This further suppresses electrical conduction between the conductive layer 25 of the contact CCc and the word line WL of the upper layer to which the contact CCc is connected.

[0273] The semiconductor memory device according to Variation Example 1 achieves the same effect as the semiconductor memory device 1 of the described embodiment.

[0274] (Variation Example 2)

[0275] As mentioned above, if multiple contact holes with different depths are formed simultaneously, some contact holes may penetrate to the target sacrificial layer and reach the lower sacrificial layer. Therefore, sometimes the following method is adopted: a termination layer covering the stepped portion is formed, so that the contact holes temporarily reach the termination layer and then penetrate the termination layer to reach each step of the stepped portion.

[0276] The configuration of the described embodiment and variation 1 can also be applied to this semiconductor memory device having a termination layer covering the stepped portion.

[0277] In the following variation example 2 of the implementation method, the following is used Figures 16-18 A method for forming contacts CC (CCd, CCe) in a semiconductor memory device having a termination layer STP covering a stepped portion SP is described.

[0278] In addition, in the following figures, the same symbols are sometimes used to refer to the same components as those in the described embodiments, and their descriptions are omitted.

[0279] Figures 16-18 This is a cross-sectional view showing a portion of the sequence of methods for forming contacts CC (CCd, CCe) in Variation Example 2 of the implementation method. More specifically, Figures 16-18 This is a cross-sectional view along the X direction of the region that will later become a stepped region.

[0280] In addition, Figures 16-18 In this document, an example is described when the configuration of the above embodiment is applied to a semiconductor memory device having a stop layer STP.

[0281] In Variation Example 2, the same procedure is followed as described in the previous embodiment. Figures 3-5 The processing involves shaping a portion of the laminates LMsa and LMsb into a stepped shape to form the columnar portion HR.

[0282] like Figure 16 As shown in (a) of the figure, in Variation Example 2, insulating layer 51a and termination layer STP are sequentially covered by insulating layers NL and OL, which are processed into a stepped shape. Insulating layer 51a, like insulating layer 51, is a silicon oxide layer or the like, while termination layer STP is made of a material selective relative to insulating layer 51, such as silicon oxide layer. As an example, termination layer STP is an insulating layer such as silicon nitride layer.

[0283] More specifically, these insulating layers 51a and terminating layers STP are formed to cover each step surface Ts and along each step of the stepped shape. The columnar portion HR also penetrates these terminating layers STP and insulating layers 51a, extending from the upper surface of insulating layer 51 to the depth of source line SL.

[0284] Thus, since an insulating layer 51a is interposed between each step in the stepped shape and the termination layer STP, the termination layer STP does not contact the terminal portion of the insulating layer NL exposed on the end face of each step. Furthermore, at least the termination layer STP does not form a gap in the area where a replacement process would be performed later, between the insulating layer 51a and the termination layer STP.

[0285] like Figure 16 As shown in (b), multiple contact holes CL are formed that penetrate the insulating layer 51 and reach the termination layer STP above the surface layer Ts of each step.

[0286] like Figure 16 As shown in (c), the termination layer STP exposed on the bottom surface of the multiple contact holes CL is removed by, for example, wet etching. In the case of using wet etching, the termination layer STP is also removed a specified distance outward from the contact hole CL, receding from the sidewall of the contact hole CL.

[0287] In addition, additional etched contact holes CL are made to penetrate the termination layer STP, so that they penetrate the insulating layers 51a and OL and reach the insulating layer NL of the step surface Ts.

[0288] like Figure 17 As shown in (a), a resist pattern 90 is formed in a plurality of contact holes CL disposed on each step surface Ts, with one contact hole CL portion having an opening.

[0289] Furthermore, additional etching is performed to create contact holes CL that open from the resist pattern 90, such that the lower ends of these contact holes CL reach the next insulating layer NL of the step surface Ts.

[0290] like Figure 17 As shown in (b), an insulating layer 55e is formed on the sidewall and bottom surface of the contact hole CL of the insulating layer NL below the insulating layer NL reaching the step surface Ts, and the insulating layer 55e is removed from the bottom surface of the contact hole CL. The insulating layer 55e also fills the voids created by the retreat of the termination layer STP through a wet etching process.

[0291] Then, the resist pattern 90 is removed by ashing with oxygen plasma, etc.

[0292] like Figure 17 As shown in (c), a sacrificial layer 27, such as an amorphous silicon layer, is filled into multiple contact holes CL. This forms multiple contacts CCcd and CCce, each filled with the sacrificial layer 27.

[0293] Next, the insulation layer NL is replaced.

[0294] like Figure 18As shown in (a), multiple word lines WL are formed through a replacement process. As mentioned above, for example, the silicon nitride layer, also known as the termination layer STP, is not formed in the region where the gap is formed and is not in contact with the gap, so it is not replaced by a conductive layer such as a tungsten layer through the replacement process.

[0295] like Figure 18 As shown in (b), the sacrificial layer 27 is removed from contacts CCcd and CCce respectively, and the multiple contact holes CL are opened again. At this time, it is preferable to also remove the metal element layer 58 covering the upper surface of the word lines WL, etc. (see reference). Figure 2 (d) etc.

[0296] like Figure 18 As shown in (c), multiple contact holes CL are filled with conductive layers 25d and 25, such as tungsten layers, to form multiple contacts CCd and CCe. That is, in contact CCd, the conductive layer 25d is also filled into the gap created by the retreat of the termination layer STP through wet etching, forming a conductive layer 25d with a larger diameter at the height of the termination layer STP than other portions. In contact CCe, the same conductive layer 25 as that in contact CCb of the described embodiment is formed inside the insulating layer 55e.

[0297] Based on the above, the contacts CC (CCd, CCe) of variation example 2 are formed.

[0298] As mentioned above, in Figures 16-18 The text describes the application of the configuration of contacts CCa and CCb of the above embodiment to a semiconductor memory device with a termination layer STP.

[0299] However, the configuration of contacts CCa and CCc in Variation Example 1 can also be applied to a semiconductor memory device having a termination layer STP. In this case, in addition to the height position of the termination layer STP, the contact CCe also has an insulating layer 55e with a thickness equivalent to that of an insulating layer 55e that is thicker than other parts at the height position of the word line WL, etc., above the conductive layer 25 of the contact CCe.

[0300] The semiconductor memory device according to Variation 2 achieves the same effects as the semiconductor memory device of the described embodiment and Variation 1.

[0301] (Other variations)

[0302] In the embodiments and variations 1 and 2 described above, in the method of pulling out multiple word lines WL, etc., on one side, contacts CC are configured in every two block areas BLK in the stepped area SR on one side of the X direction. However, in the method of pulling out word lines WL, etc., on one side, it is sufficient to set the layout of configuring contacts on one side of the X direction within the same block area BLK, and the configuration order is not limited to the above.

[0303] Furthermore, in the embodiments and variations 1 and 2 described above, stepped regions SR are provided at both ends of the laminate LM in the X direction, but this is not a limitation. The stepped regions may also be provided, for example, in the central portion of the laminate LM. Such stepped regions are formed, for example, in the central portion of the laminates LMa and LMb before the replacement process, by repeatedly etching the insulating layers NL and OL and thinning the resist pattern.

[0304] Furthermore, in the embodiments and variations 1 and 2 described above, the laminate LM has a two-layer structure. However, the laminate may be a single-layer structure or a structure with three or more layers.

[0305] Furthermore, in the embodiments and variations 1 and 2 described above, the pillar PL is connected to the source line SL via the side of the channel layer CN, but this is not a limitation. For example, the memory layer at the bottom of the pillar can be removed, and the pillar can be formed by connecting the lower end of the channel layer to the source line.

[0306] Furthermore, in the embodiments and variations 1 and 2 described above, the peripheral circuit CBA is arranged above the stacked layer LM. However, the peripheral circuit may also be arranged below the stacked layer or on the same layer as the stacked layer.

[0307] When the peripheral circuit is positioned below the stacked body, for example, source lines and the stacked body can be formed on an insulating layer of a semiconductor substrate having peripheral circuits covered by an insulating layer. When the peripheral circuit is positioned on the same layer as the stacked body, the stacked body can be formed at a different location on the semiconductor substrate where the peripheral circuit is formed.

[0308] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and their equivalents.

[0309] [Symbol Explanation]

[0310] 1. Semiconductor memory device

[0311] 25,25d conductive layer

[0312] 55, 55c, 55e Insulation Layer

[0313] CC, CCa~CCe contacts

[0314] LI plate

[0315] LM,LMa,LMb,LMga,LMgb,LMsa,LMsb laminated body

[0316] MC storage unit

[0317] MR memory region

[0318] NL,OL insulation layer

[0319] PL column

[0320] SGD, SGS gate line selection

[0321] SHE Separation Layer

[0322] SP Staircase

[0323] SR stepped area

[0324] STP Termination Layer

[0325] WL lettering.

Claims

1. A semiconductor memory device comprising: A laminate, in which multiple conductive layers are stacked separately from each other, has a stepped portion in which the multiple conductive layers are processed into a stepped shape and include multiple stepped surfaces that do not overlap with the upper conductive layers. A column, extending in the stacking direction of the stack body from the stepped portion, forms a memory cell at its intersection with at least a portion of the plurality of conductive layers; and Multiple contacts are configured on the stepped portion and are respectively connected to the multiple conductive layers; and The multiple contacts It includes a first contact group, which is disposed on the first facet of the first conductive layer among the plurality of conductive layers, and is respectively connected to the first conductive layer and one or more lower side conductive layers that are continuous with the first conductive layer in the stacking direction.

2. The semiconductor memory device according to claim 1, wherein In the stepped portion, the height position of the plurality of stepped portions changes in the laminated body along the first direction, which is either a first direction intersecting the lamination direction or a second direction intersecting both the lamination direction and the first direction. A second-order surface adjacent to the first-order surface in the first direction is disposed in a second conductive layer among the plurality of conductive layers. The second conductive layer It is located on top of the first conductive layer with the same number of layers as the number of contacts contained in the first contact group.

3. The semiconductor memory device according to claim 2, wherein The multiple contacts It includes a second contact group, which is disposed on the second-level facet and is respectively connected to the second conductive layer and to each of one or more lower-level conductive layers that are continuous with the second conductive layer in the stacking direction. The contacts contained in the first contact group and the contacts contained in the second contact group are respectively arranged in the second direction. Among the contacts included in the first contact group and the contacts included in the second contact group, the contacts that are connected to the conductive layer on the upper side of the laminate are arranged more on one side of the second direction within the first and second facets.

4. The semiconductor memory device according to claim 2, wherein The multiple contacts It includes a second contact group, which is disposed on the second-level facet and is respectively connected to the second conductive layer and to each of one or more lower-level conductive layers that are continuous with the second conductive layer in the stacking direction. The contacts contained in the first contact group and the contacts contained in the second contact group are respectively arranged in the second direction. Among the contacts included in the first contact group, the contacts that are connected to the conductive layer on the upper side of the laminate are more likely to be disposed on one side of the second direction within the first facet. Among the contacts included in the second contact group, the more the contacts are connected to the conductive layer on the upper side of the laminate, the more they are disposed on the other side of the second direction within the second facet.

5. The semiconductor memory device according to claim 1, wherein... In the stepped portion, the height position of the plurality of stepped surfaces changes in the laminated body in a first direction intersecting the lamination direction and in a second direction intersecting both the lamination direction and the first direction. A second stepped surface adjacent to the first stepped surface in the second direction is disposed in a second conductive layer among the plurality of conductive layers. The second conductive layer It is located on top of the first conductive layer with the same number of layers as the number of contacts contained in the first contact group.

6. The semiconductor memory device according to claim 5, wherein A third-order surface adjacent to the first-order surface in the first direction is disposed in the third conductive layer among the plurality of conductive layers. The third conductive layer The layer above the first conductive layer has the same number of layers as the contacts contained in the first contact group and the contacts arranged in the plurality of stepped surfaces that are arranged in the second direction and include one or more stepped surfaces of the second stepped surface.

7. The semiconductor memory device according to claim 6, wherein The contacts contained in the first contact group are arranged in the first direction. Among the contacts included in the first contact group, the contacts that are connected to the conductive layer on the upper side of the laminate are located closer to the third-order face.

8. The semiconductor memory device according to claim 7, wherein The multiple contacts It includes a second contact group, which is disposed on the third-level facet and is respectively connected to the third conductive layer and to each of one or more lower-level conductive layers that are continuous with the third conductive layer in the stacking direction. The contacts in the second contact group are arranged in the first direction. Among the contacts in the second contact group, the contacts that are connected to the conductive layer on the upper side of the laminate are located closer to the first-order face.

9. The semiconductor memory device according to claim 1, wherein The first group of contacts each has a conductive portion that extends toward the stepped portion in the stacking direction. The contacts included in the first contact group, each contact connected to one or more lower side conductive layers, has a first insulating layer covering the conductive portion.

10. The semiconductor memory device according to claim 9, It also has a second insulating layer covering the stepped portion. The conductive portion connected to the contact in the first conductive layer is directly in contact with the second insulating layer, and extends in the lamination direction within the second insulating layer. Each conductive portion connected to a contact of one or more lower-layer conductive layers is separated from the first insulating layer and extends in the stacking direction within the second insulating layer.

11. A semiconductor memory device comprising: A laminate, in which multiple conductive layers are stacked separately from each other, has a stepped portion in which the multiple conductive layers are processed into a stepped shape and include multiple stepped surfaces that do not overlap with the upper conductive layers. A column, extending in the stacking direction of the stack body from the stepped portion, forms a memory cell at its intersection with at least a portion of the plurality of conductive layers; and Multiple contacts are configured on the stepped portion and are respectively connected to the multiple conductive layers; and Among the plurality of contacts The first and second contacts are configured on the first surface of the first conductive layer, which is disposed among the plurality of conductive layers, and the first contact is connected to the first conductive layer. The second contact is connected to the second conductive layer below the first conductive layer.

12. The semiconductor memory device according to claim 11, wherein In the stepped portion, the height position of the plurality of stepped portions changes in the laminated body along the first direction, which is either a first direction intersecting the lamination direction or a second direction intersecting both the lamination direction and the first direction. Among the plurality of contacts The third and fourth contacts are disposed on the second-order facet, which is adjacent to the first-order facet in the first direction, and a third conductive layer is disposed among the plurality of conductive layers. The third contact is connected to the third conductive layer. The fourth contact is connected to the fourth conductive layer, which is the layer below the third conductive layer. The first and second contacts, along with the third and fourth contacts, are arranged in the second direction, respectively. The first contact point is located within the first-order face and is positioned on one side in the second direction relative to the second contact point. The third contact is located within the second-order face and is positioned on one side in the second direction relative to the fourth contact.

13. The semiconductor memory device according to claim 11, wherein In the stepped portion, the height position of the plurality of stepped portions changes in the laminated body along the first direction, which is either a first direction intersecting the lamination direction or a second direction intersecting both the lamination direction and the first direction. Among the plurality of contacts The third and fourth contacts are disposed on the second-order facet, which is adjacent to the first-order facet in the first direction, and a third conductive layer is disposed among the plurality of conductive layers. The third contact is connected to the third conductive layer. The fourth contact is connected to the fourth conductive layer, which is the layer below the third conductive layer. The first and second contacts, along with the third and fourth contacts, are arranged in the second direction, respectively. The first contact point is located within the first-order face and is positioned on one side in the second direction relative to the second contact point. The third contact is located within the second-order face and is positioned on the opposite side of the second direction relative to the fourth contact.

14. The semiconductor memory device of claim 11, wherein In the stepped portion, the height position of the plurality of stepped portions changes in the laminated body in a first direction intersecting the lamination direction and in a second direction intersecting both the lamination direction and the first direction. Among the plurality of joints... The third and fourth contacts are disposed on the second-order facet, which is adjacent to the first-order facet in the second direction, and a third conductive layer is disposed among the plurality of conductive layers. The third contact is connected to the third conductive layer. The fourth contact is connected to the fourth conductive layer, which is the layer below the third conductive layer. The first and second contacts, along with the third and fourth contacts, are arranged in the first direction. The first contact point is located within the first-order face and is positioned on one side of the first direction relative to the second contact point. The third contact is located within the second-order face and is positioned on one side of the first direction relative to the fourth contact.

15. The semiconductor memory device according to claim 11, wherein In the stepped portion, the height position of the plurality of stepped surfaces changes in the laminated body in a first direction intersecting the lamination direction and a second direction intersecting both the lamination direction and the first direction. The first and second junctions are arranged in the first direction. The first contact point is located within the first-order facet and, relative to the second contact point, is positioned against a third-order facet adjacent to the first-order facet in the first direction.

16. The semiconductor memory device of claim 15, wherein The third-order face is disposed in the fifth conductive layer among the plurality of conductive layers. Among the plurality of contacts The 5th and 6th contacts are located on the 3rd face. The fifth contact is connected to the fifth conductive layer. The sixth contact is connected to the sixth conductive layer, which is the layer below the fifth conductive layer. The fifth contact is located within the third-order face and is positioned relative to the sixth contact against the first-order face.

17. The semiconductor memory device of claim 11, wherein... The first and second contacts each have conductive portions extending toward the stepped portion in the stacking direction, and the second contact has a first insulating layer covering the conductive portions.

18. The semiconductor memory device according to claim 17, wherein The conductive portion of the second contact penetrates the first conductive layer and is connected to the second conductive layer. The first insulating layer extends from the upper end of the second contact to at least the through portion of the first conductive layer.

19. The semiconductor memory device of claim 18, wherein The thickness of the first insulating layer is thicker in the portion through which the first conductive layer passes than in other portions.

20. The semiconductor memory device according to claim 17, It also includes a termination layer, which is disposed above the plurality of step surfaces and covers the plurality of step surfaces; The conductive portions of the first and second contacts extend through the termination layer and toward the first-order face.

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