Semiconductor devices and manufacturing methods thereof

Abstract

This invention relates to a semiconductor device and a method for manufacturing the same. According to one embodiment, the semiconductor device includes a first insulating film, a first bonding pad disposed within the first insulating film, a second insulating film disposed on the first insulating film, and a second bonding pad disposed on the first bonding pad within the second insulating film. Furthermore, the first insulating film comprises a first film and a second film, the first film being in contact with the first bonding pad and the second insulating film, the second film being spaced apart from the first bonding pad and the second insulating film, and having a portion disposed at the same height as at least a portion of the first bonding pad; and / or, the second insulating film comprises a third film and a fourth film, the third film being in contact with the second bonding pad and the first insulating film, the fourth film being spaced apart from the second bonding pad and the first insulating film, and having a portion disposed at the same height as at least a portion of the second bonding pad.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on December 1, 2021, with application number 202111452099.5 and title "Semiconductor Device and Method of Manufacturing Thereof".

[0003] [Citation of relevant applications]

[0004] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-100408 filed on June 16, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0006] In the case of manufacturing a semiconductor device by bonding one substrate to another, it is desirable to reduce poor bonding between the metal pads of these substrates. Summary of the Invention

[0007] The present invention provides a semiconductor device capable of properly bonding pads together and a method thereof.

[0008] According to one embodiment, a semiconductor device includes a first insulating film, a first bonding pad disposed within the first insulating film, a second insulating film disposed on the first insulating film, and a second bonding pad disposed on the first bonding pad within the second insulating film. Furthermore, the first insulating film includes a first film and a second film, the first film being in contact with the first bonding pad and the second insulating film, the second film being spaced apart from the first bonding pad and the second insulating film, and having a portion disposed at the same height as at least a portion of the first bonding pad; and / or, the second insulating film includes a third film and a fourth film, the third film being in contact with the second bonding pad and the first insulating film, the fourth film being spaced apart from the second bonding pad and the first insulating film, and having a portion disposed at the same height as at least a portion of the second bonding pad.

[0009] According to the aforementioned configuration, a semiconductor device capable of properly bonding pads together and a method thereof can be provided. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 2This is a cross-sectional view showing the structure of the columnar portion in the first embodiment.

[0012] Figure 3 This is a cross-sectional view (1 / 2) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 4 This is a cross-sectional view (2 / 2) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0014] Figures 5(a) to (c) are cross-sectional views showing the structure of the semiconductor device according to the first embodiment.

[0015] Figures 6(a) and (b) are cross-sectional views showing two examples of the structure of the semiconductor device according to the first embodiment.

[0016] Figures 7(a) to (c) are cross-sectional views showing the structure of the semiconductor device of the first variation of the first embodiment.

[0017] Figures 8(a) to (c) are cross-sectional views showing the structure of the semiconductor device of the second variation of the first embodiment.

[0018] Figures 9(a) to (c) are cross-sectional views showing the structure of the semiconductor device of the third variation of the first embodiment.

[0019] Figures 10(a) to (c) are cross-sectional views showing an overview of the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figures 11(a) and (b) are cross-sectional views (1 / 5) showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0021] Figures 12(a) and (b) are cross-sectional views (2 / 5) showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0022] Figures 13(a) and (b) are cross-sectional views (3 / 5) showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0023] Figures 14(a) and (b) are cross-sectional views (4 / 5) showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0024] Figures 15(a) and (b) are cross-sectional views (5 / 5) showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0025] Figure 16 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0026] Figure 17This is a cross-sectional view showing the structure of the semiconductor device in the first variation of the second embodiment.

[0027] Figure 18 This is a cross-sectional view showing the structure of a semiconductor device according to a second variation of the second embodiment.

[0028] Figure 19 This is a cross-sectional view showing the structure of a semiconductor device in the third variation of the second embodiment.

[0029] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device in the fourth variation of the second embodiment.

[0030] Figures 21(a) to (c) are cross-sectional views showing an overview of the manufacturing method of the semiconductor device according to the second embodiment.

[0031] Figures 22(a) and (b) are cross-sectional views (1 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0032] Figures 23(a) and (b) are cross-sectional views (2 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0033] Figures 24(a) and (b) are cross-sectional views (3 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0034] Figures 25(a) and (b) are cross-sectional views (4 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0035] Figures 26(a) and (b) are cross-sectional views (5 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0036] Figures 27(a) and (b) are cross-sectional views (6 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0037] Figures 28(a) and (b) are cross-sectional views (7 / 7) showing details of the manufacturing method of the semiconductor device according to the second embodiment.

[0038] Figures 29(a) and (b) are cross-sectional views (1 / 4) showing details of another manufacturing method of the semiconductor device according to the second embodiment.

[0039] Figures 30(a) and (b) are cross-sectional views (2 / 4) showing details of another manufacturing method of the semiconductor device according to the second embodiment.

[0040] Figures 31(a) and (b) are cross-sectional views (3 / 4) showing details of another manufacturing method of the semiconductor device according to the second embodiment.

[0041] Figures 32(a) and (b) are cross-sectional views (4 / 4) showing details of another manufacturing method of the semiconductor device according to the second embodiment.

[0042] Figure 33 This is a graph used to explain the materials of the semiconductor device in the second embodiment. Detailed Implementation

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 33 In this context, identical components are marked with the same symbol, and repeated explanations are omitted.

[0044] (First Embodiment) Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 Semiconductor devices, such as three-dimensional memory, are fabricated by bonding an array wafer containing array region 1 with a circuit wafer containing circuit region 2, as described below.

[0045] Array region 1 includes a memory cell array 11 containing multiple memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film (SiO2 film) or a silicon nitride film (SiN film). The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film containing a silicon oxide film and other insulating films. The interlayer insulating film 13 is an example of a second insulating film.

[0046] Circuit region 2 is disposed below array region 1. The symbol S represents the interface (adhesion surface) between array region 1 and circuit region 2. Circuit region 2 includes an interlayer insulating film 14 and a substrate 15 beneath the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a laminated film comprising a silicon oxide film and other insulating films. The interlayer insulating film 14 is an example of a first insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon (Si) substrate.

[0047] Figure 1 The diagram shows the X and Y directions, which are parallel to and perpendicular to the surface of substrate 15, and the Z direction, which is perpendicular to the surface of substrate 15. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0048] Array region 1 has multiple word lines WL and source lines SL as multiple electrode layers within the memory cell array 11. Figure 1The stepped structure 21 of the memory cell array 11 is shown. Each word line WL is electrically connected to the word wiring layer 23 via contact plugs 22. Each columnar portion CL passing through the plurality of word lines WL is electrically connected to the bit line BL via dielectric plugs 24, and is also electrically connected to the source line SL. The source line SL includes a lower layer SL1 as a semiconductor layer and an upper layer SL2 as a metal layer.

[0049] Circuit region 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 disposed on a substrate 15 separated by a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. In addition, circuit region 2 includes a plurality of contact plugs 33 disposed on the gate electrode 32, the source diffusion layer or the drain diffusion layer of the transistors 31, a wiring layer 34 disposed on the contact plugs 33 and including a plurality of wirings, and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings.

[0050] Circuit region 2 also includes a wiring layer 36 disposed on wiring layer 35 and containing multiple wirings, multiple interlayer plugs 37 disposed on wiring layer 36, and multiple metal pads 38 disposed on the interlayer plugs 37. The metal pads 38 are, for example, metal layers containing a Cu (copper) layer. The metal pads 38 are an example of the first pad. Circuit region 2 functions as a control circuit (logic circuit) for controlling the operation of array region 1. This control circuit includes transistors 31, etc., and is electrically connected to the metal pads 38.

[0051] Array region 1 includes a plurality of metal pads 41 disposed on metal pads 38, and a plurality of interlayer plugs 42 disposed on the metal pads 41. Additionally, array region 1 includes a wiring layer 43 disposed on the interlayer plugs 42 and containing a plurality of wirings, and a wiring layer 44 disposed on the wiring layer 43 and containing a plurality of wirings. The metal pads 41 are, for example, metal layers containing Cu layers. The metal pads 41 are examples of second pads. The bit line BL is contained in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 38, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 38, etc.

[0052] The array region 1 also includes a plurality of dielectric plugs 45 disposed on the wiring layer 44, metal pads 46 disposed on the dielectric plugs 45 and the insulating film 12, and a passivation film 47 disposed on the metal pads 46 and the insulating film 12. The metal pads 46 are, for example, metal layers containing a Cu layer, as... Figure 1The external bonding pads (bonding pads) of the semiconductor device function as bonding pads. The passivation film 47 is an insulating film, such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal bonding pad 46. The metal bonding pad 46 can be connected to the mounting substrate or other device through the opening P and via bonding wires, solder balls, metal bumps, etc.

[0053] Figure 2 This is a cross-sectional view showing the structure of the columnar portion CL in the first embodiment. Figure 2 It shows Figure 1 One of the multiple columnar portions CL shown.

[0054] like Figure 2 As shown, the memory cell array 11 includes an interlayer insulating film 13 ( Figure 1 Multiple word lines WL and multiple insulating layers 51 are alternately stacked on the surface. The word lines WL are, for example, W (tungsten) layers. The insulating layers 51 are, for example, silicon oxide films.

[0055] The columnar portion CL sequentially comprises a barrier insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56. The charge storage layer 53, for example, is an insulating film such as silicon nitride, formed on the side of the word line WL and the insulating layer 51, separated by the barrier insulating film 52. The charge storage layer 53 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 55, for example, is a polysilicon layer, formed on the side of the charge storage layer 53, separated by the tunnel insulating film 54. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0056] Figure 3 and Figure 4 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0057] Figure 3 The diagram shows an array wafer W1 containing multiple array regions 1 and a circuit wafer W2 containing multiple circuit regions 2. The array wafer W1 is also referred to as a "memory wafer", and the circuit wafer W2 is also referred to as a "CMOS (Complementary Metal Oxide Semiconductor) wafer".

[0058] Figure 3 The orientation of the array wafer W1 and Figure 1 The array region 1 is oriented in the opposite direction. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 to the circuit wafer W2. Figure 3 The image shows the array wafer W1 before its orientation is reversed for bonding. Figure 1 The diagram shows the array region 1 after orientation reversal, bonding, and cutting for bonding.

[0059] Figure 3 In the diagram, symbol S1 represents the upper surface of array wafer W1, and symbol S2 represents the upper surface of circuit wafer W2. Array wafer W1 includes a substrate 16 disposed under insulating film 12. Substrate 16 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 15 is an example of a first substrate, and substrate 16 is an example of a second substrate.

[0060] In this embodiment, firstly, as Figure 3 As shown, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a stepped structure 21, and a metal pad 41 are formed on the substrate 16 of the array wafer W1, and an interlayer insulating film 14, a transistor 31, and a metal pad 38 are formed on the substrate 15 of the circuit wafer W2. For example, a dielectric plug 45, a wiring layer 44, a wiring layer 43, a dielectric plug 42, and a metal pad 41 are sequentially formed on the substrate 16. Similarly, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a dielectric plug 37, and a metal pad 38 are sequentially formed on the substrate 15. Next, as... Figure 4 As shown, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed. This allows the metal pads 41 and 38 to bond together.

[0061] Then, the substrate 15 is thinned using CMP (Chemical Mechanical Polishing), and after the substrate 16 is removed using CMP, the array wafer W1 and the circuit wafer W2 are diced into multiple chips. This is how the process is performed. Figure 1 The semiconductor device. In addition, the metal pad 46 and the passivation film 47 are formed on the insulating film 12, for example, after the substrate 15 is thinned and the substrate 16 is removed.

[0062] Furthermore, in this embodiment, the array wafer W1 is bonded to the circuit wafer W2, but alternatively, the array wafers W1 can be bonded to each other. (Referring to the above...) Figures 1-4 The content described, and will be referenced in Figure 5 below. Figure 33 The same applies to the case where array wafers W1 are bonded together.

[0063] in addition, Figure 1 The interface between interlayer insulating film 13 and interlayer insulating film 14, and the interface between metal pad 41 and metal pad 38 are shown, but these interfaces are usually no longer observable after the annealing. However, the location of the interfaces can be estimated by detecting, for example, the slope of the side of metal pad 41 or the side of metal pad 38, or the positional offset between the side of metal pad 41 and metal pad 38.

[0064] Hereinafter, the semiconductor device of this embodiment will be described in more detail with reference to Figures 5 to 15.

[0065] Figure 5 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0066] Figure 5(a) shows Figure 1 Figure 5(a) shows a longitudinal sectional view of one pair of the multiple pairs of metal pads 38 and 41. In Figure 5(a), metal pad 38 is disposed on the interlayer plug 37 within the interlayer insulating film 14, and metal pad 41 is disposed below the interlayer plug 42 within the interlayer insulating film 13. Figure 5(b) is a cross-sectional view along line A-A' shown in Figure 5(a), showing the XY section of metal pad 41. Figure 5(c) is a cross-sectional view along line B-B' shown in Figure 5(a), showing the XY section of metal pad 38.

[0067] The following is a more detailed description of the metal solder pads 38 and 41 and the interlayer insulating films 14 and 13 shown in FIG. 5(a). FIG. 5(b) and FIG. 5(c) will also be referred to as appropriate in this description.

[0068] As shown in Figure 5(a), the metal pad 38 comprises a barrier metal layer 38a and a pad material layer 38b. The barrier metal layer 38a is formed on the side and upper surface of the interlayer insulating film 14, and the pad material layer 38b is formed within the interlayer insulating film 14 through the barrier metal layer 38a. Similarly, the metal pad 41 comprises a barrier metal layer 41a and a pad material layer 41b. The barrier metal layer 41a is formed on the side and lower surface of the interlayer insulating film 13, and the pad material layer 41b is formed within the interlayer insulating film 14 through the barrier metal layer 41a. The barrier metal layers 38a and 41a are, for example, metal layers containing Ti (titanium) or Ta (tantalum). The pad material layers 38b and 41b are, for example, metal layers containing a Cu layer. Thus, the metal pads 38 and 41 are also referred to as "Cu pads".

[0069] The interlayer insulating film 14 in this embodiment includes an insulating film 14a and an insulating film 14b. The insulating film 14a is in contact with the metal pad 38 and the interlayer insulating film 13, and is disposed in the lateral and downward directions of the metal pad 38. On the other hand, the insulating film 14b is not in contact with either the metal pad 38 or the interlayer insulating film 13, and is disposed in the lateral direction of the metal pad 38. That is, the insulating film 14b is disposed with a gap between it and the metal pad 38 and the interlayer insulating film 13. In this embodiment, the thickness of the insulating film 14b is thinner than the thickness of the metal pad 38, so the entire insulating film 14b is at the same height as a portion of the metal pad 38. Therefore, the B-B' line, parallel to the XY plane, passes through both the metal pad 38 and the insulating film 14b. The insulating film 14a is an example of a first film, and the insulating film 14b is an example of a second film.

[0070] Furthermore, the reference for the "height" may be, for example, the interface S. Alternatively, the reference for the "height" may also be the upper surface of the substrate 15. This reference will also be used in the context of the term "height" below.

[0071] In this embodiment, both insulating films 14a and 14b are SiO2 films. However, insulating film 14a in this embodiment is formed, for example, using dTEOS (densified tetraethyl orthosilicate). On the other hand, insulating film 14b in this embodiment is formed, for example, using PSZ (polysilazane). Therefore, insulating film 14b contains N (nitrogen) atoms as impurity atoms, and the N atom concentration in insulating film 14b becomes higher than the N atom concentration in insulating film 14a. Furthermore, insulating film 14b shrinks during the thermal steps of manufacturing a semiconductor device. When manufacturing the semiconductor device of this embodiment, as described below, by utilizing this property of insulating film 14b, metal pads 38 and 41 can be properly bonded.

[0072] Furthermore, the insulating film 14b in this embodiment can also be other SiO2 films (e.g., NSG (None-doped Silicate Glass) films) that shrink during the thermal steps of manufacturing a semiconductor device. Additionally, the insulating films 14a and 14b in this embodiment can also be films other than SiO2 films.

[0073] The interlayer insulating film 13 in this embodiment includes an insulating film 13a and an insulating film 13b. The insulating film 13a is in contact with the metal pad 41 and the interlayer insulating film 14, and is disposed in the lateral and upward directions of the metal pad 41. On the other hand, the insulating film 13b is not in contact with either the metal pad 41 or the interlayer insulating film 14, and is disposed in the lateral direction of the metal pad 41. That is, the insulating film 13b is disposed with a gap between it and the metal pad 41 and the interlayer insulating film 14. In this embodiment, the thickness of the insulating film 13b is thinner than the thickness of the metal pad 41, so the entire insulating film 13b is at the same height as a portion of the metal pad 41. Therefore, the line A-A', parallel to the XY plane, passes through both the metal pad 41 and the insulating film 13b. The insulating film 13a is an example of a third film, and the insulating film 13b is an example of a fourth film.

[0074] In this embodiment, both insulating films 13a and 13b are SiO2 films. However, insulating film 13a in this embodiment is formed, for example, using dTEOS. On the other hand, insulating film 13b in this embodiment is formed, for example, using PSZ. Therefore, insulating film 13b contains N atoms as impurity atoms, and the N atom concentration in insulating film 13b becomes higher than the N atom concentration in insulating film 13a. Furthermore, insulating film 13b shrinks during the thermal steps of manufacturing a semiconductor device. When manufacturing the semiconductor device of this embodiment, as described below, by utilizing this property of insulating film 13b, metal pads 38 and 41 can be properly bonded.

[0075] Furthermore, the insulating film 13b in this embodiment can also be other SiO2 films (such as NSG films) that shrink during the thermal steps of manufacturing a semiconductor device. In addition, the insulating films 13a and 13b in this embodiment can also be films other than SiO2 films.

[0076] As shown in FIG5(a), the insulating film 13a of this embodiment includes a portion P1 disposed between the side surface of the metal pad 41 and the side surface of the insulating film 13b. Therefore, the insulating film 13b is not in contact with the metal pad 41. Portion P1 is an example of the second part. Similarly, the insulating film 14a of this embodiment includes a portion P2 disposed between the side surface of the metal pad 38 and the side surface of the insulating film 14b. Therefore, the insulating film 14b is not in contact with the metal pad 38. Portion P2 is an example of the first part.

[0077] Figure 5(b) shows the XY cross-section of portion P1 of the insulating film 13a. As shown in Figure 5(b), portion P1 in this embodiment has an annular planar shape surrounding the metal pad 41. Portion P1 is further surrounded in an annular shape by the insulating film 13b.

[0078] Figure 5(c) shows the XY cross-section of portion P2 of the insulating film 14a. As shown in Figure 5(c), portion P2 in this embodiment has an annular planar shape surrounding the metal pad 38. Portion P2 is further surrounded in an annular shape by the insulating film 14b.

[0079] Figure 6 is a cross-sectional view showing two structural examples of the semiconductor device according to the first embodiment.

[0080] Figure 6(a) shows a first example of the structure of the semiconductor device according to this embodiment. Figure 6(a) is a cross-sectional view showing a wider range than Figure 5(b). In this example, each metal pad 41 has a solid quadrilateral planar shape, and the portion P1 surrounding each metal pad 41 has a hollow quadrilateral planar shape. In this example, an insulating film 13b individually surrounds multiple metal pads 41 across multiple portions P1.

[0081] Figure 6(b) shows a second example of the structure of the semiconductor device according to this embodiment. Like Figure 6(a), Figure 6(b) is a cross-sectional view showing a wider range than Figure 5(b), but it shows a structure different from that shown in Figure 6(a). In this example, each metal pad 41 has a solid hexagonal planar shape, and the portion P1 surrounding each metal pad 41 has an approximately hollow hexagonal planar shape. Specifically, each portion P1 has an annular planar shape composed of multiple (here, six) hexagons, each hexagon having the same size as one metal pad 41. Similarly, the insulating film 13b also has a planar shape composed of multiple hexagons, each hexagon having the same size as one metal pad 41. Thus, the planar shapes of the metal pads 41, portions P1, and insulating film 13b in this example have a honeycomb structure. In this example, similarly, one insulating film 13b individually surrounds multiple metal pads 41 across multiple portions P1.

[0082] Furthermore, in the first example, the planar shapes of the metal pad 38, part of P2, and insulating film 14b are the same as those of the metal pad 41, part of P1, and insulating film 13b, respectively. In the second example, the planar shapes of the metal pad 38, part of P2, and insulating film 14b are the same as those of the metal pad 41, part of P1, and insulating film 13b, respectively.

[0083] Figure 7 is a cross-sectional view showing the structure of a semiconductor device according to a first variation of the first embodiment. Figures 7(a) to 7(c) Corresponding to Figures 5(a) to 5(c) .

[0084] In this variation, the insulating film 14b is the same as that in the first embodiment, not in contact with the metal pad 38 and the interlayer insulating film 13, and is disposed in the transverse direction of the metal pad 38. Similarly, in this variation, the insulating film 13b is not in contact with the metal pad 41 and the interlayer insulating film 14, and is disposed in the transverse direction of the metal pad 41.

[0085] However, in this variation, the insulating film 14b is thicker than the metal pad 38, and only a portion of the insulating film 14b is located at the same height as a portion of the metal pad 38. Therefore, the insulating film 14b in this variation includes not only a portion located higher than the lower surface of the metal pad 38, but also a portion located lower than the lower surface of the metal pad 38. Similarly, in this variation, the insulating film 13b is thicker than the metal pad 41, and only a portion of the insulating film 13b is located at the same height as a portion of the metal pad 41. Therefore, the insulating film 13b in this variation includes not only a portion located lower than the upper surface of the metal pad 41, but also a portion located higher than the upper surface of the metal pad 41. According to this variation, the metal pads 38 and 41 can be properly bonded using insulating films 14b and 13b with these shapes.

[0086] Furthermore, the thickness of the insulating film 14b in this variation can also be thinner than the thickness of the metal pad 38, and the thickness of the insulating film 13b in this variation can also be thinner than the thickness of the metal pad 41.

[0087] Figure 8 is a cross-sectional view showing the structure of a semiconductor device according to a second variation of the first embodiment. Figures 8(a) to 8(c) Corresponding to Figures 5(a) to 5(c) .

[0088] In this variation, the interlayer insulating film 14 includes insulating films 14a and 14b having the same shape as those in the first variation. On the other hand, the interlayer insulating film 13 in this variation includes insulating film 13a but does not include insulating film 13b. According to this variation, the insulating film 14b having this shape can be used to properly bond the metal pad 38 to the metal pad 41.

[0089] Figure 9 is a cross-sectional view showing the structure of a semiconductor device according to a third variation of the first embodiment. Figures 9(a) to 9(c) Corresponding to Figures 5(a) to 5(c) .

[0090] In this variation, the interlayer insulating film 13 includes insulating films 13a and 13b having the same shape as those in the first variation. On the other hand, the interlayer insulating film 14 in this variation includes an insulating film 14a but does not include an insulating film 14b. According to this variation, the insulating film 13b having this shape can be used to properly bond the metal pad 38 to the metal pad 41.

[0091] Figure 10 is a cross-sectional view showing an overview of the manufacturing method of the semiconductor device according to the first embodiment. Figures 10(a) to 10(c) express Figure 3 and Figure 4 Details of the method shown.

[0092] Figure 10(a) shows array region 1 (array wafer W1) before it is bonded to circuit region 2 (circuit wafer W2). In Figure 10(a), the upper surface of the metal pad 38 is recessed downward relative to the upper surface of the interlayer insulating film 14, and the lower surface of the metal pad 41 is recessed upward relative to the lower surface of the interlayer insulating film 13. These recesses are referred to as dishing, for example, that occur when the surfaces of the interlayer insulating films 14 and 13 are planarized by CMP. Even when array region 1 is bonded to circuit region 2, there is a concern that these recesses may prevent proper bonding of the metal pads 41 and 38.

[0093] Figure 10(b) shows the array region 1 after it has been attached to circuit region 2 and before annealing for bonding the metal pads 38, 41. In Figure 10(b), a gap is created between the metal pads 41 and 38 due to the depression. If this gap is not eliminated, there is a concern about poor bonding between the metal pads 41 and 38.

[0094] Figure 10(c) shows the array region 1 after it has been bonded to circuit region 2 and annealed to bond the metal pads 38 and 41. In Figure 10(c), the gap between metal pads 41 and 38 has been eliminated, and the metal pads 41 and 38 are properly bonded. This phenomenon is due to the thermal expansion of the metal pads 41 and 38 caused by annealing, and the effect of the insulating films 14b and 13b manifested by annealing.

[0095] Here, the function of the insulating films 14b and 13b in this embodiment will be explained.

[0096] In this embodiment, the insulating films 14b and 13b are formed, for example, using PSZ (polysilazane). Therefore, during annealing of the metal pads 41 and 38, the insulating films 14b and 13b are heated and shrink. This applies compressive stress to the metal pads 41 and 38 from the insulating films 14b and 13b, making it easier for the metal pads 41 and 38 to come into contact. Thus, according to this embodiment, through the thermal expansion of the metal pads 41 and 38 and the action of the insulating films 14b and 13b, the metal pads 41 and 38 can be properly bonded.

[0097] The thickness of the insulating film 14b in this embodiment decreases by, for example, more than 9% and less than 25% due to shrinkage during annealing. When T1 represents the thickness of the insulating film 14b before shrinkage and T2 represents the thickness of the insulating film 14b after shrinkage, the relationship T1×0.75 ≤ T2 < T1×0.91 holds true. Similarly, the thickness of the insulating film 13b in this embodiment decreases by, for example, more than 9% and less than 25% due to shrinkage during annealing. This allows for sufficient compressive stress to be generated, thereby enabling adequate and proper bonding of the metal pad 41 and the metal pad 38.

[0098] In this embodiment, the metal pads 41 and 38 comprise, for example, a Cu layer. Therefore, to suppress the adverse effects of annealing on the Cu layer, it is preferable to anneal the metal pads 41 and 38 at a temperature below 400°C. Consequently, it is preferable that the thickness of the insulating film 14b in this embodiment is reduced by more than 9% and less than 25% through annealing at a temperature below 400°C. This insulating film 14b can be achieved, for example, by forming the insulating film 14b using PSZ. The same applies to the insulating film 13b.

[0099] Ideally, the interlayer insulating film 14 in this embodiment includes not only an insulating film 14b formed using PSZ or the like, but also an insulating film 14a formed using dTEOS or the like. The reason is that immediately after the PSZ film is formed on the substrate 15, the PSZ film immediately has properties close to liquid, making it difficult to process the PSZ film (e.g., CMP).

[0100] Figures 11 to 15 are cross-sectional views showing details of the manufacturing method of the semiconductor device according to the first embodiment. Figures 11(a) to 15(b) express Figures 10(a) to 10(c) Details of the method shown.

[0101] Figure 11(a) shows a portion of circuit region 2 (circuit wafer W2). When forming circuit region 2, an insulating film 14a1 is formed above substrate 15, an interlayer plug 37 is formed within the insulating film 14a1, and an insulating film 14a2 is formed on the insulating film 14a1 and the interlayer plug 37 (Figure 11(a)). Insulating films 14a1 and 14a2 are part of insulating film 14a, and are formed, for example, using dTEOS as the feed gas and by CVD (Chemical Vapor Deposition).

[0102] Next, a recess H1 is formed in the insulating film 14a2 using photolithography and RIE (Reactive Ion Etching) (Fig. 11(b)). Next, an insulating film 14b is formed in the recess H1 (Fig. 12(a)). The insulating film 14b is formed, for example, using a PSZ coating method. The insulating film 14b of this embodiment can be formed, for example, with the planar shape shown in Fig. 5(c) and Fig. 6(a), or with the planar shape shown in Fig. 6(b).

[0103] Next, an insulating film 14a3 is formed on the insulating films 14a2 and 14b (Fig. 12(b)). The insulating film 14a3 is a part of the insulating film 14a, and is formed, for example, by CVD using dTEOS. Next, a recess H2 is formed in the insulating films 14a2 and 14a3 by photolithography and RIE (Fig. 13(a)). As a result, the upper surface of the interlayer plug 37 is exposed in the recess H2. The recess H2 is used as a pad groove for embedding the metal solder pad 38.

[0104] Next, a barrier metal layer 38a (Fig. 13(b)) is formed on the interlayer plug 37 and the insulating films 14a1, 14a2, and 14a3. The barrier metal layer 38a is, for example, a metal layer containing Ti or Ta elements, and is formed by CVD.

[0105] Next, a pad material layer 38b is formed on the interlayer plug 37 and the insulating films 14a1, 14a2, and 14a3, through a barrier metal layer 38a (Fig. 14(a)). The pad material layer 38b is, for example, a Cu layer, formed by plating.

[0106] Next, the surface of the pad material layer 38b is planarized using CMP (Fig. 14(b)). As a result, the barrier metal layer 38a and the pad material layer 38b outside the recess H2 are removed, and a metal pad 38 is formed inside the recess H2. In this embodiment, the metal pad 38 is formed at a position that is in contact with the insulating films 14a1, 14a2, and 14a3 but not with the insulating film 14b. In Fig. 14(b), the thickness of the insulating film 14b is thinner than the thickness of the metal pad 38, and the entire insulating film 13b is located at the same height as a portion of the metal pad 38.

[0107] Figure 15(a) shows a portion of array region 1 (array wafer W1). Array region 1 shown in Figure 15(a), like circuit region 2, is constructed using... Figures 11(a) to 14(b)The substrate 16, insulating films 13a1, 13a2, 13a3, insulating film 13b, interlayer plug 42, barrier metal layer 41a, and solder pad material layer 41b within the insulating film 13a are processed in the same manner as the substrate 15 and insulating films 14a1, 14a2, 14a3, insulating film 14b, interlayer plug 37, barrier metal layer 38a, and solder pad material layer 38b within the insulating film 14a.

[0108] Next, substrate 15 and substrate 16 are bonded together (Fig. 15(b)) with metal pad 41 disposed on metal pad 38 and insulating film 13a1 (interlayer insulating film 13) disposed on insulating film 14a1 (interlayer insulating film 14). Specifically, interlayer insulating film 14 and interlayer insulating film 13 are bonded together by applying mechanical pressure. Furthermore, metal pads 38 and 41 and interlayer insulating films 14 and 13 are annealed to bond metal pads 41 and 38. During annealing, insulating films 14b and 13b shrink, thereby promoting the bonding of metal pads 38 and 41.

[0109] Then, substrate 15 is thinned by CMP, and substrate 16 is removed by CMP. The array wafer W1 and circuit wafer W2 (see reference) are then... Figure 4 The semiconductor device of this embodiment, as shown in Figure 5, is manufactured in this manner by cutting it into multiple chips.

[0110] In addition, utilizing Figures 11(a) to 15(b) The insulating films 14b and 13b formed by the method shown can also have any of the shapes in the first to third variations of this embodiment. The shape of the insulating film 14b can be controlled by adjusting the shape of the recess H1. Similarly, the shape of the insulating film 13b can also be controlled by adjusting the shape of the recess corresponding to the recess H1.

[0111] As described above, the semiconductor device of this embodiment includes an interlayer insulating film 14 that includes both insulating film 14a and insulating film 14b, and an interlayer insulating film 14 that includes both insulating film 13a and insulating film 13b. Insulating films 14a and 13a are formed, for example, using dTEOS. Insulating films 14b and 13b are formed, for example, using PSZ. Therefore, according to this embodiment, the insulating films 14b and 13b can be used to properly bond the metal pad 38 to the metal pad 41.

[0112] (Second Implementation) Figure 16 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0113] Figure 16 Similar to Figure 5(a), it represents Figure 1The longitudinal sectional view of one of the multiple pairs of metal pads 38 and 41 shown. Figure 16 In this configuration, metal solder pads 38 are disposed on the interlayer plug 37 within the interlayer insulating film 14, and metal solder pads 41 are disposed below the interlayer plug 42 within the interlayer insulating film 13. Furthermore, the interlayer plug 37 is disposed on the wiring layer 36 within the interlayer insulating film 14, and the interlayer plug 42 is disposed below the wiring layer 43 within the interlayer insulating film 13.

[0114] The following is about Figure 16 The metal solder pads 38 and 41 and the interlayer insulating films 14 and 13 shown will be described in more detail. In this description, details that are common to the metal solder pads 38 and 41 and the interlayer insulating films 14 and 13 shown in FIG. 5(a) will be omitted as appropriate.

[0115] like Figure 16 As shown, the interlayer insulating film 14 of this embodiment includes multiple insulating films 14a, 14c, and 14d. Each insulating film 14a is, for example, a SiO2 film formed using dTEOS. The insulating film 14c is disposed laterally in the interlayer plug 37 and sandwiched between two insulating films 14a. The insulating film 14c is, for example, a SiCN film (silicon carbonitride film). The insulating film 14d is disposed on the upper surface of the wiring layer 36 and sandwiched between two insulating films 14a. The insulating film 14d is, for example, a SiN film.

[0116] Similarly, the interlayer insulating film 13 in this embodiment includes a plurality of insulating films 13a, 13c, and 13d. Each insulating film 13a is, for example, a SiO2 film formed using dTEOS. The insulating film 13c is disposed laterally in the interlayer plug 42 and sandwiched between two insulating films 13a. The insulating film 13c is, for example, a SiCN film. The insulating film 13d is disposed on the lower surface of the wiring layer 43 and sandwiched between two insulating films 13a. The insulating film 13d is, for example, a SiN film.

[0117] The semiconductor device of this embodiment further includes a metal layer 39 disposed within the uppermost insulating film 14a. The metal layer 39 is located laterally to the dielectric plug 37 and is in contact with the dielectric plug 37. Furthermore, the metal layer 39 is located below the metal pad 38 and above the wiring layer 36, and is not in contact with either the metal pad 38 or the wiring layer 36. In other words, the metal layer 39 is disposed spaced apart from the metal pad 38 and the wiring layer 36. The metal layer 39 of this embodiment has an annular planar shape surrounding the dielectric plug 37. The metal layer 39 is an example of a first layer and a first metal layer.

[0118] In this embodiment, the thickness of the metal layer 39 is thinner than the thickness of the interlayer plug 37, so the entire metal layer 39 is at the same height as a portion of the interlayer plug 37. Therefore, the upper surface of the metal layer 39 is at a lower height than the upper surface of the interlayer plug 37, and the lower surface of the metal layer 39 is at a higher height than the lower surface of the interlayer plug 37. Furthermore, the thickness of the metal layer 39 in this embodiment is thinner than the thickness of the metal pad 38, for example, by 5% to 30% of the thickness of the metal pad 38. When T3 represents the thickness of the metal pad 38 and T4 represents the thickness of the metal layer 39, the relationship T3×0.05 ≤ T4 ≤ T3×0.30 holds true.

[0119] In this embodiment, the metal layer 39 has a coefficient of linear expansion that is larger than that of the pad material layer 38b of the metal pad 38. Therefore, during the thermal steps of manufacturing the semiconductor device, the thermal expansion coefficient of the metal layer 39 becomes larger than that of the pad material layer 38b. When manufacturing the semiconductor device of this embodiment, this property of the metal layer 39 can be used to properly bond the metal pad 38 to the metal pad 41, as described below. For example, the pad material layer 38b is a Cu (copper) layer, and the metal layer 39 is an Al (aluminum) layer or a Zn (zinc) layer. At the same temperature, aluminum or zinc has a larger coefficient of linear expansion than copper. For example, the coefficients of linear expansion of copper, aluminum, and zinc at 20°C are 16.5 × 10⁻⁶. -6 / ℃, 23.1×10 -6 / ℃ and 30.2×10 -6 / ℃. Furthermore, a more detailed explanation of the coefficient of linear expansion will be provided below.

[0120] The semiconductor device of this embodiment further includes a metal layer 48 disposed within the lowest insulating film 13a. The metal layer 48 is located laterally to the dielectric plug 42 and is in contact with the dielectric plug 42. Furthermore, the metal layer 48 is located above the metal pad 41 and below the wiring layer 43, and is not in contact with either the metal pad 41 or the wiring layer 43. In other words, the metal layer 48 is disposed spaced apart from the metal pad 41 and the wiring layer 43. The metal layer 48 of this embodiment has an annular planar shape surrounding the dielectric plug 42. The metal layer 48 is an example of a second layer and a second metal layer.

[0121] In this embodiment, the thickness of the metal layer 48 is thinner than the thickness of the interlayer plug 42, so the entire metal layer 48 is at the same height as a portion of the interlayer plug 42. Therefore, the lower surface of the metal layer 48 is at a higher height than the lower surface of the interlayer plug 42, and the upper surface of the metal layer 48 is at a lower height than the upper surface of the interlayer plug 42. Furthermore, the thickness of the metal layer 48 in this embodiment is thinner than the thickness of the metal pad 41, for example, by 5% to 30% of the thickness of the metal pad 41.

[0122] In this embodiment, the metal layer 48 has a coefficient of linear expansion that is larger than that of the pad material layer 41b of the metal pad 41. Therefore, during the thermal steps of manufacturing the semiconductor device, the thermal expansion rate of the metal layer 48 becomes greater than that of the pad material layer 41b. When manufacturing the semiconductor device of this embodiment, this property of the metal layer 48 can be used to properly bond the metal pad 38 to the metal pad 41, as described below. For example, the pad material layer 41b is a Cu layer, and the metal layer 48 is an Al layer or a Zn layer.

[0123] Furthermore, the semiconductor device of this embodiment can replace the metal layer 39 with a non-metallic layer having a larger coefficient of linear expansion than the pad material layer 38b, or it can replace the metal layer 48 with a non-metallic layer having a larger coefficient of linear expansion than the pad material layer 41b. In this case, this property of the non-metallic layer can be used to properly bond the metal pads 38 and 41. The non-metallic layer can be formed from inorganic or organic materials.

[0124] Figure 17 This is a cross-sectional view showing the structure of the semiconductor device in the first variation of the second embodiment.

[0125] In this variation, the metal layer 39 is in contact not only with the interlayer plug 37 but also with the metal pad 39. Similarly, in this variation, the metal layer 48 is in contact not only with the interlayer plug 42 but also with the metal pad 41. According to this variation, the metal pad 38 and the metal pad 41 can be properly bonded by utilizing the property of the significant expansion of the metal layers 39 and 48, just as in the second embodiment.

[0126] Figure 18 This is a cross-sectional view showing the structure of a semiconductor device according to a second variation of the second embodiment.

[0127] In this variation, the metal layer 39 is arranged in a ring around the interlayer plug 37 in a state separate from it, and is not in contact with the interlayer plug 37. Similarly, in this variation, the metal layer 48 is arranged in a ring around the interlayer plug 42 in a state separate from it, and is not in contact with the interlayer plug 42. According to this variation, the metal pad 38 and the metal pad 41 can be properly bonded by utilizing the property of the significant expansion of the metal layers 39 and 48, just as in the second embodiment.

[0128] Figure 19 This is a cross-sectional view showing the structure of a semiconductor device in the third variation of the second embodiment.

[0129] The semiconductor device of this variation includes a metal layer 39 having the same shape as the metal layer 39 in the first embodiment, but does not include a metal layer 48. According to this variation, the property of the metal layer 39 to expand significantly can be used to properly bond the metal pads 38 and 41.

[0130] Figure 20 This is a cross-sectional view showing the structure of the semiconductor device in the fourth variation of the second embodiment.

[0131] The semiconductor device of this variation includes a metal layer 48 having the same shape as the metal layer 48 in the first embodiment, but does not include a metal layer 39. According to this variation, the property of the metal layer 48 to expand significantly can be used to properly bond the metal pads 38 and 41.

[0132] Figure 21 is a cross-sectional view showing an overview of the manufacturing method of the semiconductor device according to the second embodiment. Figures 21(a) to 21(c) express Figure 3 and Figure 4 Details of the method shown.

[0133] Similar to Figure 10(a), Figure 21(a) shows the array region 1 (array wafer W1) before it is bonded to the circuit region 2 (circuit wafer W2). In Figure 21(a), similarly, the upper surface of the metal pad 38 is recessed downwards relative to the upper surface of the interlayer insulating film 14, and the lower surface of the metal pad 41 is recessed upwards relative to the lower surface of the interlayer insulating film 13. Even when the array region 1 is bonded to the circuit region 2, there is a concern that the aforementioned recesses may prevent the metal pads 41 and 38 from properly bonding.

[0134] Similar to Figure 10(b), Figure 21(b) shows the array region 1 after it has been attached to circuit region 2 and before annealing for bonding the metal pads 38 and 41. In Figure 21(b), similarly, a gap is created between the metal pads 41 and 38 due to the aforementioned recess. If this gap is not eliminated, there is a concern about poor bonding between the metal pads 41 and 38.

[0135] Similar to Figure 10(c), Figure 21(c) shows the array region 1 after it has been bonded to circuit region 2 and annealed to bond the metal pads 38 and 41. In Figure 21(c), the gap between metal pads 41 and 38 has been eliminated, and the metal pads 41 and 38 are properly bonded. This is due to the thermal expansion of the metal pads 41 and 38 caused by annealing, and the effect of the metal layers 39 and 48 that are manifested by annealing.

[0136] Here, the function of the metal layers 39 and 48 in this embodiment will be explained.

[0137] In this embodiment, the pad material layers 38b and 41b within the metal pads 38 and 41 are, for example, Cu layers. On the other hand, the metal layers 39 and 48 in this embodiment are, for example, Al or Zn layers. Therefore, the coefficient of linear expansion of the metal layers 39 and 48 becomes greater than that of the pad material layers 38b and 41b. As a result, when the metal pads 38 and 41 and the metal layers 39 and 41 are annealed, the coefficient of thermal expansion of the metal layers 39 and 48 becomes greater than that of the pad material layers 38b and 41b, causing the metal layers 39 and 48 to expand significantly. Consequently, compressive stress is applied to the metal pads 41 and 38 from the metal layers 39 and 48, making it easier for the metal pads 41 and 38 to approach each other. Therefore, according to this embodiment, through the thermal expansion of the metal pads 41 and 38, and the further thermal expansion of the metal layers 39 and 48, the metal pads 41 and 38 can be properly bonded. To suppress the adverse effects of annealing on the Cu layer, it is ideal to anneal the metal pads 41 and 38 of this embodiment at a temperature below 400°C.

[0138] Figures 22 to 27 are cross-sectional views showing details of the manufacturing method of the semiconductor device according to the second embodiment. Figures 22(a) to 27(b) express Figures 21(a) to 21(c) Details of the method shown.

[0139] Figure 22(a) shows a portion of circuit region 2 (circuit wafer W2). When circuit region 2 is formed, an insulating film 14a4 is formed over substrate 15 (Figure 21(a)). Insulating film 14a4 is a portion of insulating film 14a, and is formed, for example, using dTEOS as the feed gas and by CVD. Furthermore, in the following description, insulating films 14c and 14d within the interlayer insulating film 14 are omitted. Figure 16 (Explanation of ).

[0140] Next, a recess H3 is formed within the insulating film 14a4 using photolithography and RIE (Fig. 22(b)). Next, a metal layer 39 is formed within the recess H3 (Fig. 23(a)). The metal layer 39 is, for example, an Al layer or a Zn layer. In this embodiment, the metal layer 39 is formed by depositing the metal layer 39 inside and outside the recess H3 using CVD, and removing the metal layer 39 outside the recess H3 using CMP.

[0141] Next, an insulating film 14a5 is formed on the insulating film 14a4 and the metal layer 39 (Fig. 23(b)). The insulating film 14a5 is a part of the insulating film 14a, and is formed, for example, by CVD using dTEOS.

[0142] Next, recesses H4 are formed within insulating films 14a4 and 14a5 and metal layer 39 using photolithography and RIE (Fig. 24(a)). As a result, the upper surface of wiring layer 36 (not shown) is exposed within recesses H4. Recesses H4 are formed through metal layer 39 and are used as vias for embedding interlayer plugs 37.

[0143] Next, a material for the interlayer plug 37 is formed on the wiring layer 36 (not shown) and the insulating film 14a5 (Fig. 24(b)). This material may be the same as or different from the material of the metal plug 38. In the former case, the interlayer plug 37 is formed, for example, by including a Cu layer. In the latter case, the interlayer plug 37 is formed, for example, by including a W (tungsten) layer. Next, the surface of this material is planarized by CMP (Fig. 25(a)). As a result, the material outside the recess H4 is removed, and the interlayer plug 37 is formed inside the recess H4 by a single-layer metal inlay. In Fig. 25(a), the interlayer plug 37 is in contact with the metal layer 39 and is surrounded by the metal layer 39 in a ring shape. Furthermore, in Fig. 25(a), the thickness of the metal layer 39 is thinner than the thickness of the interlayer plug 37, and the entire metal layer 39 is at the same height as a portion of the interlayer plug 37.

[0144] Next, an insulating film 14a6 is formed on the insulating film 14a5 and the interlayer plug 37 (Fig. 25(b)). The insulating film 14a6 is a part of the insulating film 14a, and is formed, for example, by CVD using dTEOS. Next, a recess H5 is formed in the insulating film 14a6 by photolithography and RIE (Fig. 26(a)). As a result, the upper surface of the interlayer plug 37 is exposed in the recess H5. The recess H5 is used as a pad groove for embedding the metal solder pad 38.

[0145] Next, a barrier metal layer 38a (Fig. 26(b)) is formed on the interlayer plug 37 and the insulating films 14a5 and 14a6. The barrier metal layer 38a is, for example, a metal layer containing Ti or Ta elements, and is formed by CVD.

[0146] Next, a pad material layer 38b is formed on the interlayer plug 37 and the insulating films 14a5 and 14a6 through a barrier metal layer 38a (Fig. 27(a)). The pad material layer 38b is, for example, a Cu layer, formed by plating.

[0147] Next, the surface of the pad material layer 38b is planarized by CMP (Fig. 27(b)). As a result, the barrier metal layer 38a and the pad material layer 38b outside the recess H5 are removed, and a metal pad 38 is formed inside the recess H5 by a single-layer metal inlay. In this embodiment, the metal pad 38 is formed at a position that is in contact with the interlayer plug 37 but not with the metal layer 39.

[0148] Figure 28(a) shows a portion of array region 1 (array wafer W1). Array region 1 shown in Figure 28(a), like circuit region 2, is constructed using... Figures 22(a) to 27(b) The substrate 16, insulating films 13a4, 13a5, 13a6 within insulating film 13a, interlayer plug 42, barrier metal layer 41a, pad material layer 41b, and metal layer 48 within insulating film 13a are processed in the same manner as insulating films 14a1, 14a2, 14a3 within insulating film 14a, insulating film 14b, interlayer plug 37, barrier metal layer 38a, pad material layer 38b, and metal layer 39 within insulating film 15. Furthermore, in Figure 28(a), insulating films 13c and 13d within interlayer insulating film 13 are omitted. Figure 16 The illustration is shown.

[0149] Next, substrate 15 and substrate 16 are bonded together with metal pad 41 disposed on metal pad 38 and insulating film 13a1 (interlayer insulating film 13) disposed on insulating film 14a1 (interlayer insulating film 14) (Fig. 28(b)). Specifically, interlayer insulating film 14 and interlayer insulating film 13 are bonded together by applying mechanical pressure. Furthermore, metal pads 38 and 41 and interlayer insulating films 14 and 13 are annealed to bond metal pads 41 and 38 together. During the annealing process, metal layers 39 and 48 expand, thereby promoting the bonding of metal pads 38 and 41.

[0150] Then, substrate 15 is thinned by CMP, and substrate 16 is removed by CMP. The array wafer W1 and circuit wafer W2 (see reference) are then... Figure 4 The semiconductor device of this embodiment, as shown in FIG21, is manufactured in this manner by cutting it into multiple chips.

[0151] In addition, utilizing Figures 22(a) to 28(b) The metal layers 39 and 48 formed by the method shown can also have any of the shapes in the first to fourth variations of this embodiment. The shape of the metal layer 39 can be controlled by adjusting the shape of the recess H3. Similarly, the shape of the metal layer 38 can also be controlled by adjusting the shape of the recess corresponding to the recess H3.

[0152] Figures 29 to 32 are cross-sectional views showing details of another manufacturing method of the semiconductor device according to the second embodiment.

[0153] First, implementation Figures 22(a) to 25(b) The steps shown are omitted. However, the steps related to the mesothelial plug 37 are omitted. Figures 23(a) to 25(a) Figure 29(a) shows circuit region 2 (circuit wafer W2) after implementing the steps shown in Figure 25(b).

[0154] Next, a recess H5 is formed in the insulating film 14a6 using photolithography and RIE (Fig. 29(b)). Then, a recess H4 is formed in the insulating films 14a5 and 14a4 and the metal layer 39 located below the recess H5 using photolithography and RIE (Fig. 30(a)). As a result, the upper surface of the wiring layer 36 (not shown) is exposed within the recess H4.

[0155] Next, a barrier metal layer 38a (Fig. 30(b)) is formed on the wiring layer 36 (not shown) and the insulating films 14a5 and 14a6. The barrier metal layer 38a is, for example, a metal layer containing Ti or Ta elements, and is formed by CVD.

[0156] Next, a pad material layer 38b (Fig. 31(a)) is formed on the wiring layer 36 (not shown) and the insulating films 14a5 and 14a6, separated by a barrier metal layer 38a. The pad material layer 38b is, for example, a Cu layer, formed by plating.

[0157] Next, the surface of the pad material layer 38b is planarized using CMP (Fig. 31(b)). As a result, the barrier metal layer 38a and the pad material layer 38b outside the recesses H5 and H4 are removed, and a metal pad 38 and a dielectric plug 37 are formed in the recesses H5 and H4 respectively by double-pass metal inlay. In this case, the dielectric plug 37, like the metal pad 38, is formed by the barrier metal layer 38a and the pad material layer 38b.

[0158] Figure 32(a) shows a portion of array region 1 (array wafer W1). Array region 1 shown in Figure 32(a), like circuit region 2, is constructed using... Figures 29(a) to 31(b) The substrate 16, insulating films 13a4, 13a5, 13a6, interlayer plug 42, barrier metal layer 41a, pad material layer 41b, and metal layer 48 within the insulating film 13a are processed in the same manner as the substrate 15, insulating films 14a1, 14a2, 14a3, insulating film 14b, interlayer plug 37, barrier metal layer 38a, pad material layer 38b, and metal layer 39 within the insulating film 14a.

[0159] Next, substrate 15 and substrate 16 are bonded together with metal pad 41 disposed on metal pad 38 and insulating film 13a1 (interlayer insulating film 13) disposed on insulating film 14a1 (interlayer insulating film 14) (Fig. 32(b)). Specifically, interlayer insulating film 14 and interlayer insulating film 13 are bonded together by applying mechanical pressure. Furthermore, metal pads 38 and 41 and interlayer insulating films 14 and 13 are annealed to bond metal pads 41 and 38 together. During the annealing process, metal layers 39 and 48 expand, thereby promoting the bonding of metal pads 38 and 41.

[0160] Then, substrate 15 is thinned by CMP, and substrate 16 is removed by CMP. The array wafer W1 and circuit wafer W2 (see reference) are then... Figure 4 The semiconductor device of this embodiment, as shown in FIG21, is manufactured in this manner by cutting it into multiple chips.

[0161] In addition, utilizing Figures 29(a) to 32(b) The metal layers 39 and 48 formed by the method shown can also have any of the shapes in the first to fourth variations of this embodiment. The shape of the metal layer 39 can be controlled by adjusting the shape of the recess H3. Similarly, the shape of the metal layer 38 can also be controlled by adjusting the shape of the recess corresponding to the recess H3.

[0162] Figure 33 This is a graph used to explain the materials of the semiconductor device in the second embodiment.

[0163] Figure 33 This represents the temperature dependence of the linear expansion coefficients of silicon (Si), copper (Cu), aluminum (Al), and zinc (Zn). For example... Figure 33 As shown, the coefficient of linear expansion of the substance at the same temperature is... Figure 33 The coefficients of linear expansion increase in the order Zn > Al > Cu > Si across approximately all temperature regions shown. Therefore, in this embodiment, by setting the pad material layers 38b and 41b within the metal pads 38 and 41 as Cu layers and setting the metal layers 39 and 48 as Al or Zn layers, the coefficients of linear expansion of the metal layers 39 and 48 can be made greater than the coefficients of linear expansion of the pad material layers 38b and 41b within the metal pads 38 and 41.

[0164] As described above, the semiconductor device of this embodiment has a metal layer 39 in the circuit region 2 and a metal layer 48 in the array region 1. For example, the metal pads 38 and 41 contain Cu layers, while the metal layers 39 and 48 are Al layers or Zn layers. Thus, according to this embodiment, the metal pads 38 and 41 can be properly bonded by the action of the metal layers 39 and 48.

[0165] Several embodiments have been described above, but these embodiments are merely examples and are not intended to limit the scope of the invention. The novel apparatus and method described in this specification can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the form of the apparatus and method described in this specification without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass such forms or variations contained in the scope or spirit of the invention.

Claims

1. A semiconductor device comprising a first insulating film, a first plug disposed within the first insulating film, a first bonding pad disposed on the first plug within the first insulating film, a second insulating film disposed on the first insulating film, a second bonding pad disposed on the first bonding pad within the second insulating film, and a second plug disposed on the second bonding pad within the second insulating film, further comprising a first layer and / or a second layer, the first layer having a larger coefficient of linear expansion than the first bonding pad and having a portion disposed within the first insulating film at the same height as at least a portion of the first plug, the second layer having a larger coefficient of linear expansion than the second bonding pad and having a portion disposed within the second insulating film at the same height as at least a portion of the second plug.

2. The semiconductor device of claim 1, wherein the first layer comprises a first metal layer, and / or the second layer comprises a second metal layer.

3. The semiconductor device according to claim 1 or 2, wherein the first pad comprises copper, the first layer comprises aluminum or zinc, and / or, the second pad comprises copper, and the second layer comprises aluminum or zinc.

4. The semiconductor device according to claim 1, wherein the thickness of the first layer is 5% or more and 30% or less of the thickness of the first pad, and / or the thickness of the second layer is 5% or more and 30% or less of the thickness of the second pad.

5. The semiconductor device of claim 1, wherein the first layer is connected to the first plug, and / or the second layer is connected to the second plug.

6. The semiconductor device of claim 1, wherein the first layer is spaced apart from the first plug, and / or the second layer is spaced apart from the second plug.

7. The semiconductor device of claim 1, wherein the first layer is connected to the first bonding pad, and / or the second layer is connected to the second bonding pad.

8. The semiconductor device of claim 1, wherein the first layer is spaced apart from the first pad, and / or the second layer is spaced apart from the second pad.

9. A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on a first substrate; forming a first plug within the first insulating film; forming a first bonding pad on the first plug within the first insulating film; forming a second insulating film on a second substrate; forming a second plug within the second insulating film; forming a second bonding pad on the second plug within the second insulating film; disposing the second insulating film on the first insulating film; and disposing the second bonding pad on the first bonding pad, thereby bonding the first substrate and the second substrate together; further comprising the steps of: forming a first layer within the first insulating film, the first layer having a coefficient of linear expansion larger than the first bonding pad, and having a portion disposed at the same height as at least a portion of the first plug; and / or forming a second layer within the second insulating film, the second layer having a coefficient of linear expansion larger than the second bonding pad, and having a portion disposed at the same height as at least a portion of the second plug.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the first layer is formed prior to the formation of the first plug, and / or the second layer is formed prior to the formation of the second plug.

Images