Method for manufacturing a mim capacitor electrode plate

Abstract

This invention discloses a method for manufacturing a MIM capacitor electrode plate, comprising: Step 1, providing an underlying structure with a lower dielectric layer and sequentially forming a current electrode metal layer and a current dielectric layer. Step 2, defining the formation area of ​​the current electrode plate. Step 3, performing a first etching, in which the first etching sequentially removes the current dielectric layer and the current electrode metal layer outside the formation area of ​​the current electrode plate and stops at the top surface of the lower dielectric layer, forming the current electrode plate from the etched current electrode metal layer. Step 4, performing pretreatment to form a protective layer on the side of the current electrode plate. Step 5, performing wet cleaning to remove etching residue from the first etching, wherein the protective layer prevents the current electrode plate from being etched from the side during wet cleaning. This invention can effectively etch the electrode metal layer and remove etching residue while ensuring the thickness of the lower dielectric layer, while preventing the side of the electrode plate from being etched away and thus preventing voids on the right side.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit manufacturing method, and more particularly to a method for manufacturing a MIM capacitor plate. Background Technology

[0002] In analog IC circuits, capacitors are important passive components, widely inserted into downstream metal interconnects, primarily serving functions such as bypassing, decoupling, filtering, and energy storage. With the rapid development of integrated circuits today, the construction of capacitors is becoming increasingly diverse due to the evolving functional requirements. Deep trench capacitors (DTCs) use TiN as the electrode plates and Al2O3 as the dielectric layer, with multiple cross-depositions (dep) to form parallel capacitors, significantly increasing capacitance density.

[0003] like Figure 1 The diagram shows a schematic of a conventional MIM capacitor, in which a deep trench 102 is formed in the bottom layer structure 101. The bottom layer structure 101 has a semiconductor substrate, and the deep trench 102 is formed in the semiconductor substrate; or, an interlayer film is also formed on the surface of the semiconductor substrate of the bottom layer structure 101, and the deep trench 102 is formed in the interlayer film.

[0004] The MIM capacitor comprises Al2O3 dielectric layers 103a, 103b, 103c, 103d, and 103e; and TiN plates 104a, 104b, 104c, and 104d. The dielectric layers and plates are arranged alternately. Each plate extends to the outside of the deep trench 102 and is led out through a contact hole formed at the top of the portion extending to the outside of the deep trench 102. The plates of the odd-numbered layers are connected to a first electrode, and the plates of the even-numbered layers are connected to a second electrode. Thus, adjacent plates and the dielectric layers between them form a capacitor, and these capacitors are connected in parallel to form the MIM capacitor.

[0005] Figure 1 Each electrode in the device is formed using the DTC MIM process. In the DTC MIM process, the Al2O3 thickness is designed to be extremely thin, such as about 80 Å, and the final Al2O3 thickness after etching and wet cleaning is required to reach a safe range, such as a remaining thickness > 60 Å. To ensure the final remaining amount, the WET process uses EKC cleaning conditions. The EKC cleaning solution does not consume much Al2O3, but it will consume the TiN electrode laterally. This will form voids after subsequent film deposition, which will ultimately have an adverse effect on the device profile and performance.

[0006] like Figures 2 to 5 The diagram shown is a schematic representation of the device structure in each step of the existing MIM capacitor plate manufacturing method. The existing MIM capacitor plate manufacturing method includes the following steps: Step 1, such as Figure 2 As shown, a bottom layer structure 101 is provided with a lower dielectric layer 103f and a current electrode metal layer 104 and a current dielectric layer 103g are formed sequentially.

[0007] The materials of both the lower dielectric layer 103f and the current dielectric layer 103g are Al2O3.

[0008] The material of the current electrode metal layer 104 includes TiN.

[0009] The current electrode metal layer 104 is Figure 1 The metal layer of any one of the plates 104a to 104d in the process.

[0010] Step Two, as follows Figure 2 As shown, a photoresist pattern 105 is formed using photolithography to define the formation area of ​​the current electrode.

[0011] Step 3, as follows Figure 3 As shown, the first etching is performed, which sequentially removes the current dielectric layer 103g and the current electrode metal layer 104 outside the formation area of ​​the current electrode plate and stops at the top surface of the lower dielectric layer 103f, and the current electrode plate is formed by the etched current electrode metal layer 104.

[0012] The first etching was performed using a dry etching method.

[0013] Step 4, as follows Figure 4 As shown, wet cleaning is performed to remove the etching residue from the first etching.

[0014] To prevent the wet cleaning process from causing loss of the thickness of the lower dielectric layer 103f, the cleaning solution used in the wet cleaning process is EKC, which does not cause significant loss of Al2O3.

[0015] However, as Figure 4 As shown, EKC will cause lateral loss to the current electrode metal layer 104 and form a depression 106.

[0016] After that, as Figure 5 As shown, a film layer 107 is deposited. After the film layer 107 is deposited, the depression 106 is sealed to form a cavity. Summary of the Invention

[0017] The technical problem to be solved by the present invention is to provide a method for manufacturing MIM capacitor plates, which can effectively etch and remove etching residues from the metal layer of the plate and ensure the thickness of the underlying dielectric layer, while preventing the side of the plate from being etched away and thus preventing voids from forming on the right side.

[0018] To solve the above-mentioned technical problems, the manufacturing method of MIM capacitor plates provided by the present invention includes: Step 1: Provide an underlying structure with a lower dielectric layer and sequentially form the current electrode metal layer and the current dielectric layer.

[0019] Step 2: Define the formation region of the current layer plate.

[0020] Step 3: Perform the first etching. The first etching sequentially removes the dielectric layer and the metal layer of the current electrode plate outside the formation area of ​​the current electrode plate and stops at the top surface of the lower dielectric layer. The current electrode plate is formed by the etched metal layer of the current electrode plate.

[0021] Step 4: Perform pretreatment to form a protective layer on the side of the current layer electrode.

[0022] Step 5: Perform wet cleaning to remove the etching residue from the first etching, and in the wet cleaning, the protective layer prevents the current layer plate from being etched from the side.

[0023] A further improvement is that both the lower dielectric layer and the current dielectric layer are made of high dielectric constant materials.

[0024] A further improvement is that the materials of both the lower dielectric layer and the current dielectric layer include Al2O3.

[0025] A further improvement is that the material of the current electrode metal layer includes TiN.

[0026] A further improvement is that the first etching is performed using a dry etching method, and the etching gases include Cl2 and BCl3.

[0027] A further improvement is that the pretreatment adopts a dry method, the treated gas includes CF4 and AR, the bias voltage is 50V to 80V, and the flow rate of AR is 100sccm to 150sccm.

[0028] A further improvement is that the first etching and the pretreatment are performed in the same etching cavity or different etching cavities.

[0029] A further improvement is that, in step one, the minimum thickness of the dielectric layer is less than or equal to 80 Å.

[0030] In step four, the wet etching solution ensures that the thickness of the dielectric layer after wet etching is greater than the minimum safe range required by the MIM capacitor.

[0031] A further improvement is that the minimum required safety range for the MIM capacitor includes 60 Å.

[0032] A further improvement is that the wet cleaning solution includes EKC.

[0033] A further improvement is that deep trenches are formed in the underlying structure.

[0034] The lower dielectric layer is formed in the deep trench and extends to the outside of the deep trench.

[0035] In step one, the current electrode metal layer and the current dielectric layer also extend to the outer side of the lower dielectric layer.

[0036] In step three, the side of the lower dielectric layer is located outside the side of the current electrode plate.

[0037] A further improvement is that the MIM capacitor includes multiple layers of plates; each layer of plates is formed by repeating steps one through five.

[0038] A further improvement is that the thickness of the lower dielectric layer is greater than the minimum safe range required by the MIM capacitor.

[0039] A further improvement is that, after all the electrode layers of the MIM capacitor are formed, it further includes: Contact holes are formed to connect the odd-numbered layers of electrodes to the first electrode and the even-numbered layers of electrodes to the second electrode.

[0040] A further improvement is that the number of layers of the plates of the MIM capacitor is four or more.

[0041] This invention utilizes the lower dielectric layer at the bottom of the current electrode plate as a stop layer to etch the current electrode plate metal layer. After the first etching, wet cleaning is used to remove etching residue. Therefore, it can effectively etch the current electrode plate metal layer. The wet cleaning of this invention uses a solution that ensures the thickness of the lower dielectric layer. At the same time, this invention adds a pretreatment before wet cleaning to form a protective layer on the side of the current electrode plate. The protective layer can prevent the side of the current electrode plate from being etched and consumed during wet cleaning. Therefore, this invention can effectively etch and remove etching residue from the electrode plate metal layer and ensure the thickness of the lower dielectric layer, while preventing the side of the electrode plate from being etched and consumed, thereby preventing voids on the right side. Attached Figure Description

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the structure of an existing MIM capacitor; Figures 2-5 This is a schematic diagram of the device structure in each step of the existing MIM capacitor plate manufacturing method; Figure 6 This is a flowchart of a method for manufacturing MIM capacitor plates according to an embodiment of the present invention; Figures 7-10 This is a schematic diagram of the device structure in each step of the manufacturing method of the MIM capacitor plate according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a MIM capacitor formed using the manufacturing method of the MIM capacitor plate according to an embodiment of the present invention. Detailed Implementation

[0043] like Figure 6 The diagram shown is a flowchart of a method for manufacturing the MIM capacitor plate according to an embodiment of the present invention; as shown Figures 7 to 10 The diagram shown is a schematic diagram of the device structure in each step of the manufacturing method of the MIM capacitor plate according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of a MIM capacitor formed using the manufacturing method of the MIM capacitor plate according to an embodiment of the present invention; the manufacturing method of the MIM capacitor plate according to an embodiment of the present invention includes: Step 1, such as Figure 7 As shown, a bottom layer structure 301 is provided with a lower dielectric layer 201a and a current electrode metal layer 202 and a current dielectric layer 201b are formed sequentially.

[0044] In this embodiment of the invention, the materials of the lower dielectric layer 201a and the current dielectric layer 201b are both high dielectric constant materials.

[0045] The materials of both the lower dielectric layer 201a and the current dielectric layer 201b include Al2O3.

[0046] The material of the current electrode metal layer 202 includes TiN.

[0047] Step Two, as follows Figure 7 As shown, the photoresist 203 pattern is formed using photolithography to define the formation area of ​​the current electrode.

[0048] Step 3, as follows Figure 8 As shown, the first etching is performed, which sequentially removes the current dielectric layer 201b and the current electrode metal layer 202 outside the formation area of ​​the current electrode plate and stops at the top surface of the lower dielectric layer 201a, and the current electrode plate is formed by the etched current electrode metal layer 202.

[0049] In this embodiment of the invention, the first etching is performed using dry etching, and the etching gas includes Cl2 and BCl3. A slow etching rate (ER) is used for the etching of the current electrode metal layer 202. This slow etching rate can be achieved by setting the flow rate of the etching gas, for example, setting the flow rate ratio of Cl2 to BCl3 to 1:6.

[0050] Step 4, as follows Figure 9 As shown, pretreatment is performed to form a protective layer 204 on the side of the current layer electrode.

[0051] In this embodiment of the invention, the pretreatment adopts a dry process, the treatment gas includes CF4 and AR, the bias voltage is 50V to 80V, and the flow rate of AR is 100sccm to 150sccm. In the pretreatment, the low bias voltage combined with AR can provide weak bombardment, which partially deconstructs the material of the lower dielectric layer 201a, such as Al2O3. Due to the step difference in morphology on the TiN side of the current layer electrode, a protective layer 204 of C-based and AlO-based will be deposited.

[0052] The first etching and the pretreatment are performed in the same etching chamber. After the first etching is completed, a process switch, such as changing the etching gas, can be performed. In other embodiments, the first etching and the pretreatment can also be performed in different etching chambers.

[0053] Step 5, as follows Figure 9 As shown, wet cleaning is performed to remove the etching residue from the first etching, and the protective layer 204 is used to prevent the current layer plate from being etched from the side during the wet cleaning.

[0054] In this embodiment of the invention, in step one, the minimum thickness of the dielectric layer 201b is less than or equal to 80 Å. In step four, the wet etching solution ensures that the thickness of the dielectric layer 201b after wet etching is greater than the minimum safe range required by the MIM capacitor. For example, the minimum safe range required by the MIM capacitor includes 60 Å. The wet cleaning solution includes EKC. EKC causes minimal Al2O3 loss.

[0055] The thickness of the lower dielectric layer 201a is greater than the minimum safe range required by the MIM capacitor.

[0056] After that, as Figure 10 As shown, a film layer 205 is deposited.

[0057] like Figure 11As shown, a deep trench 302 is formed in the underlying structure 301. In some embodiments, the underlying structure 301 has a semiconductor substrate, and the deep trench 302 is formed in the semiconductor substrate. In some embodiments, the underlying structure 301 may also have a semiconductor substrate and an interlayer film formed on the surface of the semiconductor substrate, and the deep trench 302 is formed in the interlayer film.

[0058] The lower dielectric layer 201a is formed in the deep trench 302 and extends to the outside of the deep trench 302.

[0059] In step one, the current electrode metal layer 202 and the current dielectric layer 201b also extend to the outer side of the lower dielectric layer 201a.

[0060] In step three, the side of the lower dielectric layer 201a is located outside the side of the current electrode plate.

[0061] In this embodiment of the invention, the MIM capacitor includes multiple layers of plates; each layer of the plates is formed by repeating steps one to five. The MIM capacitor has four or more layers of plates. Figure 11 The image shows four electrode layers, namely electrode layers 202a, 202b, 202c, and 202d. The dielectric layer comprises five layers, namely dielectric layers 201c, 201d, 201e, 201f, and 201g. When forming each electrode layer, the upper and lower dielectric layers of each electrode layer serve as the lower dielectric layer 201a and the current dielectric layer 201b, respectively. For example, when forming electrode layer 202a, the upper and lower dielectric layers 201c and 201d of electrode layer 202a serve as the lower dielectric layer 201a and the current dielectric layer 201b, respectively.

[0062] In this embodiment of the invention, after all the plates of the MIM capacitor are formed, it further includes: Contact holes are formed to connect the odd-numbered electrode layers to the first electrode and the even-numbered electrode layers to the second electrode. In this way, each adjacent electrode layer and the dielectric layer between them form a capacitor, and these capacitors are connected in parallel to form the MIM capacitor.

[0063] This invention embodiment utilizes the lower dielectric layer 201a at the bottom of the current electrode plate as a stop layer to etch the current electrode plate metal layer 202. After the first etching, wet cleaning is used to remove etching residues, thus effectively etching the current electrode plate metal layer 202. The wet cleaning in this embodiment uses a solution such as EKC that ensures the thickness of the lower dielectric layer. Furthermore, this embodiment adds a pretreatment before wet cleaning to form a protective layer 204 on the side of the current electrode plate. The protective layer 204 prevents the side of the current electrode plate from being etched away during wet cleaning. Therefore, this invention embodiment effectively etches the electrode plate metal layer, removes etching residues, and ensures the thickness of the lower dielectric layer 201a, while preventing the side of the electrode plate from being etched away and thus preventing voids on the right side.

[0064] In existing methods, during the DTC MIM process, WET (Washing with EKC) is used for cleaning, which results in minimal Al2O3 loss. However, EKC laterally consumes the TiN electrode, forming voids after etching, which negatively impacts profile and performance. In this invention, an additional pretreatment step is added after the first etching step (ETCH) to create C-based and ALO-based protective layers on the TiN sidewalls, i.e., the sides of the current electrode layer. This effectively prevents EKC solution from penetrating and corroding the TiN during WET.

[0065] In this embodiment of the invention, during the first etching, a gas (CL2 / BCL3) with a flow rate ratio of approximately 1 / 6 is used to etch the body, and the TiN electrode is etched slowly by ER etching, stopping on the Al2O3 medium.

[0066] In the pretreatment, the CF4 / AR gas treatment is switched to a low bias voltage of 50-80 V, with an AR of 100-150 sccm to provide weak bombardment, which partially deconstructs the Al2O3 film, i.e. the lower dielectric layer 201a. Due to the step difference in morphology of the TiN sidewall, a C-based and ALO-based protective layer 204 is deposited.

[0067] WET cleaning is performed, at which point the sidewall protective layer prevents the EKC solution from corroding TiN.

[0068] This invention adds a treatment step after DTC TiN Etch, using CF4 / AR gas and low bias energy to create slight physical bombardment conditions, to create C-based and ALO-based protective layers on the TiN sidewalls, effectively preventing EKC solution from penetrating into and corroding the TiN during WET.

[0069] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method of manufacturing a MIM capacitor plate, characterized by, include: Step 1: Provide an underlying structure with a lower dielectric layer and sequentially form the current electrode metal layer and the current dielectric layer; Step 2: Define the formation region of the current layer electrode; Step 3: Perform the first etching. The first etching sequentially removes the dielectric layer and the metal layer of the current electrode plate outside the formation area of ​​the current electrode plate and stops at the top surface of the lower dielectric layer. The current electrode plate is formed by the etched metal layer of the current electrode plate. Step 4: Perform pretreatment to form a protective layer on the side of the current layer electrode; Step 5: Perform wet cleaning to remove the etching residue from the first etching, and in the wet cleaning, the protective layer prevents the current layer plate from being etched from the side.

2. The method of claim 1, wherein: Both the lower dielectric layer and the current dielectric layer are made of high dielectric constant materials.

3. The method of claim 2, wherein: The materials of both the lower dielectric layer and the current dielectric layer include Al2O3.

4. The method of claim 3, wherein: The material of the current electrode metal layer includes TiN.

5. The method of claim 4, wherein: The first etching is performed using a dry etching method, and the etching gases include Cl2 and BCl3.

6. The method of claim 4, wherein: The pretreatment is a dry process, and the treated gases include CF4 and AR. The bias voltage is 50V to 80V, and the flow rate of AR is 100sccm to 150sccm.

7. The method of claim 5, wherein: The first etching and the pretreatment are performed in the same etching cavity or in different etching cavities.

8. The method of claim 4, wherein: In step one, the minimum thickness of the dielectric layer is less than or equal to 80 Å; In step four, the wet etching solution ensures that the thickness of the dielectric layer after wet etching is greater than the minimum safe range required by the MIM capacitor.

9. The method for manufacturing MIM capacitor plates as described in claim 8, characterized in that: The minimum required safety range for the MIM capacitor includes 60 Å.

10. The method of claim 9, wherein: The wet cleaning solution includes EKC.

11. The method of claim 4, wherein: Deep trenches are formed in the underlying structure; The lower dielectric layer is formed in the deep trench and extends to the outside of the deep trench; In step one, the current electrode metal layer and the current dielectric layer also extend to the outer side of the lower dielectric layer; In step three, the side of the lower dielectric layer is located outside the side of the current electrode plate.

12. The method of claim 11, wherein: MIM capacitors comprise multiple layers of plates; each layer of plates is formed by repeating steps one through five.

13. The method of claim 4, wherein: The thickness of the lower dielectric layer is greater than the minimum safe range required by the MIM capacitor.

14. The method of claim 12, wherein: After all the plates of the MIM capacitor are formed, it also includes: Contact holes are formed to connect the odd-numbered layers of electrodes to the first electrode and the even-numbered layers of electrodes to the second electrode.

15. The method of claim 14, wherein: The MIM capacitor has four or more layers of plates.

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