A parallel integrated variable resistance and nmos ligbt device

Abstract

This invention relates to a LIGBT device integrating a variable resistor and an NMOS in parallel, belonging to the field of semiconductor power device technology. The device includes a cathode P+ region, a cathode N+ region, a P-body region, an N-drift region, an anode P+ region, an anode N-buffer region, an anode-side P-polysilicon gate, a P-buffered1 region, a P-buffered2 region, an anode-side N-type polysilicon gate, an anode N- region, and an anode N+ region. The anode N- and anode N+ regions are located above the P-buffered1 region and are depleted by the anode-side P-polysilicon gate, gate oxide layer, and P-buffered1 region, forming a variable resistor region; the anode-side N-type polysilicon gate, gate oxide layer, P-buffered2 region, and anode N+ region constitute an NMOS structure. In the initial stage of forward conduction, the anode N-region is depleted and forms a high-resistivity electron channel, which can suppress the snapback effect. During turn-off, the depletion effect weakens, and the anode N-region forms a low-resistivity electron channel, which is beneficial for electron extraction and reduces turn-off loss. During reverse conduction, the P-Buried2 region inverts to form an electron channel, realizing reverse conduction.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a LIGBT device that integrates a variable resistor and an NMOS in parallel. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) combines the high input impedance and low drive power of MOSFET with the strong current capability of bipolar transistor, and has been widely used in power electronics fields such as industrial control, automotive electronics, power conversion and consumer electronics.

[0003] Lateral insulated gate bipolar transistors (LIGBTs) are compatible with integrated circuit processes, facilitating the implementation of high-voltage power switching functions in power integrated circuits. When a LIGBT is turned on, conductance modulation reduces the on-state voltage drop; however, when turned off, excess carriers in the drift region need to be extracted. Therefore, there is usually a trade-off between the on-state voltage drop and the turn-off loss.

[0004] To achieve reverse conduction capability, existing technologies typically connect a freewheeling diode in parallel outside the LIGBT, or introduce a short-circuited anode region on the anode side to form a reverse-conducting LIGBT. External parallel connection increases chip area and parasitic parameters, resulting in lower integration density. While the reverse-conducting structure can achieve reverse conduction and accelerate electron extraction, it is prone to voltage foldback during the initial forward conduction phase, a phenomenon known as the snapback effect, which affects device conduction stability and practical application reliability.

[0005] Existing short-circuit anode LIGBT structures still have room for improvement in suppressing the snapback effect, reducing turn-off losses, and maintaining good reverse conduction capability. Therefore, a new LIGBT device structure is needed to simultaneously improve forward conduction, reverse conduction, and turn-off performance within a smaller structure size. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a LIGBT device that integrates a variable resistor and an NMOS in parallel, which suppresses the snapback effect during forward conduction, reduces turn-off losses, and achieves reverse conduction function by setting a variable resistor region and an NMOS structure in parallel on the anode side.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A LIGBT device integrating a variable resistor and an NMOS in parallel includes a cathode P+ region 1, a cathode N+ region 2, a P-Body region 3 located below the cathode N+ region, an N-drift region 4, an oxide layer 5 below the drift region, a P-type substrate 6, a cathode N-type polysilicon gate 7, an oxide layer 8 below the cathode N-type polysilicon gate, an anode P+ region 9, an anode N-Buffer region 10, an anode-side P-polysilicon gate 11, an anode-side lightly doped P-Buried2 region 12, an anode-side N-type polysilicon gate 13, a gate oxide layer 14 below the anode-side polysilicon gate, an anode N- region 15, an anode N+ region 16, and a P-Buried1 region 17 located below the anode N+ region.

[0009] The anode N-region 15 and anode N+region 16 are located above the P-Buried1 region 17. Above the anode N-region 15 is an anode-side P-polysilicon gate 11 and a gate oxide layer 14 below the anode-side polysilicon gate. Below the anode N-region 15 is the P-Buried1 region 17. The anode-side P-polysilicon gate 11 is connected to the anode electrode and, together with the P-Buried1 region 17, provides depletion control for the anode N-region 15, making the anode N-region 15 a variable resistance region.

[0010] The anode-side N-type polysilicon gate 13, the gate oxide layer 14 below the anode-side polysilicon gate, the lightly doped P-Buried 2 region 12 on the anode side, and the anode N+ region 16 together constitute the anode-side NMOS structure. The anode-side N-type polysilicon gate 13 is shorted to the anode N-Buffer region 10, and the potential change of the anode N-Buffer region 10 can control the formation of the inversion channel in the P-Buried 2 region 12.

[0011] Furthermore, when the anode voltage is low during the initial forward conduction of the device, due to the difference in work function between the P-polysilicon gate 11 on the anode side and the anode N-region 15, as well as the depletion effect of the P-Buried1 region 17 on the anode N-region 15, the anode N-region 15 exhibits a high-resistance electron channel, thereby limiting the premature extraction of electrons through the anode N+ region 16 and suppressing the snapback effect.

[0012] Furthermore, when the device is turned off, the anode voltage increases, and the depletion effect of the anode-side polysilicon gate 11 and P-Buried1 region 17 on the anode N-region 15 is weakened. The anode N-region 15 then acts as a low-resistance electron channel, enabling the anode N+ region 16 to extract electrons more quickly and reducing turn-off losses.

[0013] Furthermore, when the device is reverse-biased, as the cathode voltage increases, the potential of the anode N-Buffer region 10 rises, and the potential of the anode-side N-type polysilicon gate 13, which is shorted to it, rises synchronously. The P-Buffer 2 region 12 inverts to form an electron channel, and the anode-side NMOS structure is turned on. Electrons can be extracted through the anode N+ region 16, thereby achieving reverse conduction.

[0014] Furthermore, the variable resistance region and the NMOS structure are connected in a horizontal parallel configuration, allowing adjustment of the device's forward and reverse conduction performance by changing their width ratio. The variable resistance region and the NMOS structure are located above the anode N-Buffer region 10 and are separated from the anode P+ region 9.

[0015] The beneficial effects of this invention are as follows: This invention integrates a variable resistance region and an NMOS structure in parallel on the anode side of the LIGBT. During the initial forward conduction phase, the variable resistance region is in a high-resistance state, which can suppress voltage foldback and eliminate the snapback effect; during turn-off, the variable resistance region switches to a low-resistance state, which is beneficial for rapid electron extraction and reduces turn-off losses; during reverse conduction, the NMOS structure on the anode side can form an electron channel, realizing reverse conduction of the device. This structure can improve the trade-off relationship between the LIGBT's on-state voltage drop and turn-off losses, while simultaneously increasing the device's integration density.

[0016] Other advantages, objectives, and features of the present invention will be further apparent in the following description. Those skilled in the art, based on the content of this specification, can make appropriate adjustments or equivalent substitutions to the present invention without departing from its inventive concept. Attached Figure Description

[0017] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described below with reference to the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic diagram and cross-sectional view of the device structure in Embodiment 1 of the present invention;

[0019] Figure 2 for Figure 1 The equivalent circuit diagram of the device shown;

[0020] Figure 3 This is a comparison diagram of the forward conduction voltage-current output characteristics of Embodiment 1 of the present invention and the SSA-LIGBT;

[0021] Figure 4 This is a comparison diagram of the forward blocking characteristics of Embodiment 1 of the present invention and SSA-LIGBT;

[0022] Figure 5 This is a comparison diagram of the reverse conduction voltage-current output characteristics of Embodiment 1 of the present invention and the SSA-LIGBT;

[0023] Figure 6 This is a comparison chart of the turn-off characteristics of Embodiment 1 of the present invention and SSA-LIGBT;

[0024] Figure reference numerals: 1. Cathode P+ region; 2. Cathode N+ region; 3. P-Body region below the cathode N+ region; 4. N-drift region; 5. Oxide layer below the drift region; 6. P-type substrate; 7. Cathode N-type polysilicon gate; 8. Oxide layer below the cathode N-type polysilicon gate; 9. Anode P+ region; 10. Anode N-Buffer region; 11. Anode-side P-polysilicon gate; 12. Anode-side low-doped P-Buried2 region; 13. Anode-side N-type polysilicon gate; 14. Gate oxide layer below the anode-side polysilicon gate; 15. Anode N+ region; 16. P-Buried1 region below the anode N+ region; 17. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Equivalent substitutions or conventional improvements made by those skilled in the art based on the technical solutions of the present invention should all fall within the scope of protection of the present invention.

[0026] The accompanying drawings are for illustrative purposes only, representing a comparison of device structure or performance, and do not represent actual product dimensions. For ease of explanation, some structures in the drawings may be omitted, enlarged, or simplified. The directional terms such as "upper," "lower," "left," and "right" used in this specification are based on the positional relationships shown in the accompanying drawings and are for descriptive purposes only; they should not be construed as limitations on the actual fabrication direction or usage of the device.

[0027] The same or similar reference numerals in the embodiments of the present invention represent the same or similar structures. Where there is no conflict, the structural features in this embodiment can be combined with each other.

[0028] Example 1:

[0029] like Figure 1 As shown, this embodiment provides a LIGBT device that integrates a variable resistor and an NMOS in parallel. The device includes a cathode P+ region 1, a cathode N+ region 2, a P-Body region 3 located below the cathode N+ region, an N-drift region 4, an oxide layer 5 below the drift region, a P-type substrate 6, a cathode N-type polysilicon gate 7, an oxide layer 8 below the cathode N-type polysilicon gate, an anode P+ region 9, an anode N-Buffer region 10, an anode-side P-polysilicon gate 11, an anode-side lightly doped P-Buried2 region 12, an anode-side N-type polysilicon gate 13, a gate oxide layer 14 below the anode-side polysilicon gate, an anode N- region 15, an anode N+ region 16, and a P-Buried1 region 17 located below the anode N+ region.

[0030] The cathode P+ region 1 and cathode N+ region 2 are disposed within the P-Body region 3. The cathode N-type polysilicon gate 7 is isolated from the P-Body region 3 by the oxide layer 8 below the cathode N-type polysilicon gate. The N-drift region 4 is located between the P-Body region 3 and the anode side structure. An oxide layer 5 is disposed below the drift region, and a P-type substrate 6 is disposed below the oxide layer 5.

[0031] The anode P+ region 9 is located above the anode N-Buffer region 10. The anode N- region 15 and the anode N+ region 16 are located above the P-Buffer region 17. Above the anode N- region 15, the anode-side P-polysilicon gate 11 and the gate oxide layer 14 below the anode-side polysilicon gate are disposed. The anode-side P-polysilicon gate 11 is connected to the anode electrode. The anode-side P-polysilicon gate 11, the gate oxide layer 14, and the P-Buffer region 17 together perform depletion regulation on the anode N- region 15, making the anode N- region 15 a variable resistance region.

[0032] When the device is forward-biased and the anode voltage is low, the anode N-region 15 is depleted by the anode-side P-polysilicon gate 11 and P-Buried1 region 17, exhibiting a high-resistance electron channel. This reduces the degree to which electrons are directly extracted through the anode N+ region 16, making the bipolar conduction process on the anode side smoother, thereby suppressing the snapback effect.

[0033] When the device is turned off, the anode voltage increases, and the depletion effect of the anode-side polysilicon gate 11 and P-Buried1 region 17 on the anode N-region 15 weakens, causing the anode N-region 15 to change from a high-resistance state to a low-resistance state. At this time, the anode N+ region 16 can act as an electron extraction channel, accelerating the removal of excess carriers in the drift region and reducing turn-off losses.

[0034] The anode-side N-type polysilicon gate 13, the gate oxide layer 14 below the anode-side polysilicon gate, the lightly doped P-Buried 2 region 12 on the anode side, and the anode N+ region 16 constitute the anode-side NMOS structure. When the device is reverse-biased, the cathode voltage increases, causing the potential of the anode N-Buffer region 10 to rise. The potential of the anode-side N-type polysilicon gate 13, which is shorted to the anode N-Buffer region 10, also rises. The P-Buried 2 region 12 inverts to form an electron channel, and the anode-side NMOS structure is turned on, achieving reverse conduction.

[0035] like Figure 2 As shown, the device in this embodiment can be equivalent to a LIGBT body, a drift region resistor, an anode-side variable resistor branch, and an anode-side NMOS branch. The anode-side variable resistor branch and the NMOS branch are connected in parallel, wherein the variable resistor branch is used for resistance adjustment during forward conduction and turn-off, and the NMOS branch is used for electron channel formation during reverse conduction.

[0036] like Figure 3 As shown, under the same device parameters, the forward conduction characteristics of this embodiment and the SSA-LIGBT are compared. When the current density is 100 A / cm², the forward conduction voltage of this embodiment is 1.82 V, while the forward conduction voltage of the SSA-LIGBT is 1.88 V. This embodiment does not show obvious voltage foldback, indicating that it can effectively suppress the snapback effect.

[0037] like Figure 4 As shown, this embodiment has similar forward blocking characteristics to the SSA-LIGBT, and the breakdown voltage can reach about 250V, indicating that this embodiment can maintain good blocking capability while improving the conduction and turn-off performance.

[0038] like Figure 5 As shown, in the reverse conduction state, when the current density is -100 A / cm², the reverse conduction voltage of this embodiment is approximately -0.98 V, and the reverse conduction voltage of the SSA-LIGBT is approximately -1.05 V, indicating that this embodiment has good reverse conduction capability.

[0039] like Figure 6 As shown, under the same test conditions, the turn-off loss of this embodiment is 0.65 mJ, while that of the SSA-LIGBT is 0.7 mJ. This embodiment reduces turn-off loss by forming a low-resistance electron channel during turn-off through a variable resistance region on the anode side, which accelerates the extraction of excess electrons.

[0040] The lateral width of the variable resistance region and the NMOS structure can be adjusted according to the requirements of forward and reverse conduction performance. The variable resistance region and the NMOS structure are located above the anode N-Buffer region 10 and separated from the anode P+ region 9, with the spacing between them set to 1 μm.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described with reference to the above embodiments, those skilled in the art can still make modifications or equivalent substitutions to the technical solutions of the present invention; all modifications or substitutions that do not depart from the spirit and substance of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A LIGBT device that integrates a variable resistor and an NMOS in parallel, comprising a cathode P+ region (1), a cathode N+ region (2), a P-Body region (3) located below the cathode N+ region, an N-drift region (4), an oxide layer (5) below the drift region, a P-type substrate (6), a cathode N-type polysilicon gate (7), an oxide layer (8) below the cathode N-type polysilicon gate, an anode P+ region (9), an anode N-Buffer region (10), an anode-side P-polysilicon gate (11), an anode-side low-doped P-Buried2 region (12), an anode-side N-type polysilicon gate (13), a gate oxide layer (14) below the anode-side polysilicon gate, an anode N- region (15), an anode N+ region (16), and a P-Buried1 region (17) located below the anode N+ region. The anode N- region (15) and the anode N+ region are above the P-Buried1 region (17). The anode N- region is surrounded above and below by the anode-side P-polysilicon gate (11), the gate oxide layer (14) below the polysilicon gate, and the P-Buried1 region (17). The anode-side P-polysilicon gate (11) is connected to the anode electrode. When the anode voltage is low, the P-polysilicon gate (11) and the P-Buried1 region (17) will deplete the cathode N- region (15), forming a high-resistance electron channel to eliminate the snpaback effect. In addition, the anode-side N-type polysilicon gate (13), the gate oxide layer (14) below the anode-side polysilicon gate, the P-Buried2 region (12), and the anode N+ region (16) together constitute the NMOS structure to realize the reverse conduction function.

2. The LIGBT device integrating a variable resistor and an NMOS in parallel according to claim 1, characterized in that, The P-type polysilicon gate (11) uses a P-type polysilicon gate as the gate material and is connected to the anode electrode. The cathode-side N-type polysilicon gate (13) uses an N-type polysilicon gate as the gate material and is shorted in the anode N-Buffer region (10).

3. The LIGBT device integrating a variable resistor and NMOS in parallel according to claim 1, the anode N- region (15) and the anode N+ region are above the P-Buried1 region (17). The anode N- region is surrounded by the anode-side P polysilicon gate (11), the gate oxide layer (14) below the polysilicon gate, and the P-Buried1 region (17). As the anode voltage increases, the P polysilicon gate (11) and the P-Buried1 region (17) will deplete the anode N- region (15), and the anode N- region (15) is a variable resistor region. The P-Buried2 region (12) is located above the P-Buried1 region (17). As the cathode voltage increases, the potential of the anode N-Buffer region (10) rises, and the P-Buried2 region (12) inverts to generate an electron channel. The gate oxide layer (14) below the anode-side polysilicon gate, the P-Buried2 region (12), and the anode N+ region (16) together constitute an NMOS structure to achieve reverse conduction.

4. According to claim 1, when the LIGBT device with parallel integrated variable resistor and NMOS is forward-biased and the anode voltage is low, due to the difference in work function, the P polysilicon gate (11) and P-Buried1 region (17) have a strong depletion effect on the anode N-region (15), and the anode N-region (15) exhibits a high-resistance electron channel, thereby eliminating the snapback effect.

5. The LIGBT device of claim 1 integrated in parallel with a variable resistance and NMOS, wherein, When the device is turned off, when the anode voltage rises to a higher level, the P polysilicon gate (11) and P-Buried1 region (17) have a weak depletion effect on the anode N-region (15). The anode N-region (15) acts as a low-resistance electron channel, which can accelerate electron extraction and reduce turn-off loss.

6. The LIGBT device integrating a variable resistor and an NMOS in parallel according to claim 1, characterized in that, As the cathode voltage increases, the potential of the anode N-Buffer region (10) rises, and the potential of the N-type polysilicon gate (13) connected to it rises. The P-Buried2 region (12) generates an electron channel through inversion, and the reverse NMOS structure is turned on. The anode N+ region (16) can extract electrons to realize the reverse conduction function.

7. The LIGBT device of claim 1 integrated in parallel with a variable resistance and NMOS, wherein, The variable resistance region and the NMOS structure are connected in a horizontal parallel structure. The forward and reverse conduction performance of the device can be adjusted by changing the width of the variable resistance region and the NMOS structure.

8. The LIGBT device of claim 1 integrated in parallel with a variable resistance and NMOS, wherein, The variable resistance region and the NMOS structure are located above the anode N-Buffer region (10) and separated from the anode P+ region (9) by a distance of 1 μm.

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