A power device, manufacturing method and chip

Abstract

The application discloses a power device, a manufacturing method and a chip, and is applied to the technical field of semiconductors, and can realize voltage sampling without any additional power supply circuit, so that the design cost and application difficulty are reduced; meanwhile, the P-type protection ring shared below all the trenches can effectively shield the electric field concentration at the bottom of the trenches, and local breakdown is avoided; the dummy gate trench and the first P-type well region on the two sides of the dummy gate trench separate the real gate trench from the floating gate trench, so that the electric field and the current between different regions do not interfere with each other, so that the voltage sampling function with adjustable linearity is realized under the premise of ensuring high voltage resistance, and the integration and reliability of the power device are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a power device, manufacturing method, and chip. Background Technology

[0002] With the rapid development of semiconductor technology, the demand for integrated voltage sampling functions in power semiconductor devices is increasing. However, the voltage sampling structure in related technologies requires an additional power supply circuit inside the device to power the sampling structure, which leads to increased design costs and application complexity. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a power device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] In a first aspect, embodiments of the present invention provide a power device connected to a sampling resistor, the power device comprising: N-type drift zone; Multiple grooves are provided within the N-type drift zone; the multiple grooves are arranged laterally at intervals and parallel to each other; the multiple grooves include at least one true grid groove, at least one false grid groove and at least one floating grid groove, the false grid groove being located between the true grid groove and the floating grid groove; A P-type protective ring is disposed below the plurality of grooves; Multiple first P-type well regions are located on both sides of the true gate trench and between adjacent dummy gate trenches, respectively; Multiple second P-type well regions are located on both sides of the floating gate trench; Multiple P+ regions are respectively disposed on the surfaces of the first P-type well region and the second P-type well region; Multiple N+ regions are disposed on the surface of a portion of the first P-type well region and the surface of the second P-type well region, wherein the N+ regions are close to both sides of the true gate trench and both sides of the floating gate trench, and are in contact with the P+ regions; A dielectric layer is disposed on the outer surface of the plurality of trenches, a portion of the surface of the first P-type well region, a portion of the surface of the second P-type well region, a portion of the surface of the plurality of P+ regions, and a portion of the surface of the plurality of N+ regions. Emitter metal is disposed on the surfaces of multiple P+ regions on both sides of the true gate trench, the surfaces of multiple N+ regions on both sides of the true gate trench, the surface of the dummy gate trench, the surface of the P+ region between adjacent dummy gate trenches, and the surface of the dielectric layer above the true gate trench and the dummy gate trench. The sampling electrode metal is disposed on the surface of the dielectric layer above the floating gate trench, and on the surfaces of multiple N+ and P+ regions on both sides of the floating gate trench; the sampling resistor is connected to the sampling electrode metal.

[0005] Optionally, the power device further includes: An N-type cutoff layer is disposed below the N-type drift region and connected to the N-type drift region; A P-type collector region is located below the N-type cutoff layer and connected to the N-type cutoff layer; The collector metal is located below the P-type collector region and connected to the P-type collector region.

[0006] Optionally, the doping concentration of the second P-type well region is lower than that of the first P-type well region.

[0007] Optionally, the polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

[0008] Optionally, the doping concentration of the first P-type well region is 1e13cm. -3 ~5e13cm -3 The doping concentration of the second P-type well region is 1e11cm. -3 ~1e13cm -3 .

[0009] Secondly, the present invention also discloses a method for manufacturing a power device, for manufacturing the power device as described above, the method comprising: Provide N-type drift region substrate; Multiple trenches are formed on the N-type drift region substrate, the multiple trenches including at least one true gate trench, at least one dummy gate trench and at least one floating gate trench, the dummy gate trench being located between the true gate trench and the floating gate trench; A P-type protective ring is formed below the plurality of trenches; and a second P-type well region is formed on both sides of the plurality of trenches; Multiple first P-type well regions are formed on both sides of some trenches; P-type ions are injected into the upper sides of each trench to form multiple P+ regions, wherein the multiple P+ regions are respectively disposed on the surface of the first P-type well region and the second P-type well region. N-type ions are implanted on the surface of the second P-type well region and part of the surface of the first P-type well region to form multiple N+ regions; wherein the N+ regions are close to both sides of the true gate trench and both sides of the floating gate trench, and are in contact with the P+ regions; A dielectric layer is formed on the outer surface of the plurality of trenches, a portion of the surface of the first P-type well region, a portion of the surface of the second P-type well region, a portion of the surface of the plurality of P+ regions, and a portion of the surface of the plurality of N+ regions. Emitter metal is formed on the surfaces of multiple P+ regions on both sides of the true gate trench, the surfaces of multiple N+ regions on both sides of the true gate trench, the surface of the dummy gate trench, the surface of the P+ region between adjacent dummy gate trenches, and the surface of the dielectric layer above the true gate trench and the dummy gate trench. Sampling electrode metal is formed on the surface of the dielectric layer above the floating gate trench and on the surfaces of multiple N+ and P+ regions on both sides of the floating gate trench.

[0010] Optionally, it also includes: N-type ions are implanted beneath the N-type drift region substrate to form an N-type cutoff layer; the N-type cutoff layer is connected to the N-type drift region substrate. P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form a collector metal; the collector metal is connected to the P-type collector region.

[0011] Optionally, the doping concentration of the second P-type well region is lower than that of the first P-type well region.

[0012] Optionally, the polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

[0013] Thirdly, embodiments of the present invention provide a chip including the power device as described in the first aspect.

[0014] Embodiments of the present invention provide a power device, manufacturing method, and chip. When the collector voltage increases, the potential of the floating gate trench automatically rises with the collector voltage, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This enables the voltage sampling region to conduct, and the current flows from the back collector to the front voltage sampling electrode. Voltage sampling can be achieved without any additional power supply circuit, thereby reducing design costs and application difficulty. At the same time, the P-type protection ring shared under all trenches can effectively shield the electric field concentration at the bottom of the trench, avoiding local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, a self-powered, linearly adjustable voltage sampling function is achieved, improving the integration and reliability of the device.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a power device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another power device according to an embodiment of the present invention; Figure 3 This is a graph of the sampling voltage for different resistors according to an embodiment of the present invention; Figure 4 This is a voltage sampling characteristic curve of a second P-type well region with different doping concentrations according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a power semiconductor device with integrated voltage sampling function according to an embodiment of the present invention; Figure 6 This is a flowchart illustrating the steps of a method for manufacturing a power device according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 1 ; Figure 8 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 2 ; Figure 9 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 3 ; Figure 10 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 4 ; Figure 11 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 5 ; Figure 12 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 6 ; Figure 13 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 7 ; Figure 14 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 8 ; Figure 15 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 9 ; Figure 16 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 10 ; Figure 17 This is a schematic diagram of a method for manufacturing a power device according to an embodiment of the present invention. Figure 10 one. Detailed Implementation

[0017] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0018] This invention achieves voltage sampling by automatically raising the potential of the floating gate trench when the collector voltage increases, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This allows the voltage sampling region to conduct, and the current flows directly from the back collector through this channel to the front voltage sampling electrode. The current then passes through the sampling resistor to form a sampling voltage, achieving voltage sampling without any additional power supply circuit, thus reducing design costs and application difficulty. At the same time, the P-type protection ring shared by all trenches effectively shields the electric field concentration at the bottom of the trench, preventing local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, it achieves self-powered, linearly adjustable voltage sampling function, improving the integration and reliability of the device.

[0019] Reference Figure 1 The diagram illustrates a structural block diagram of a power device according to an embodiment of the present invention. The power device is connected to a sampling resistor and includes: N-type drift zone 10; Multiple trenches 11 are provided within the N-type drift zone 10; the multiple trenches 11 are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one true grid trench 111, at least one false grid trench 112 and at least one floating grid trench 113, with the false grid trench 112 located between the true grid trench 111 and the floating grid trench 113. P-type protective rings 12 are located below multiple grooves 11.

[0020] Multiple first P-type well regions 13 are located on both sides of the true gate trench 111 and between the adjacent dummy gate trench 112, respectively; Multiple second P-type trap regions 14 are located on both sides of the floating gate trench 113; Multiple P+ regions 15 are respectively disposed on the surfaces of the first P-type well region 13 and the second P-type well region 14; Multiple N+ regions 16 are disposed on the surface of a portion of the first P-type well region 13 and the surface of the second P-type well region 14, wherein the N+ regions 16 are close to both sides of the true gate trench 111 and both sides of the floating gate trench 113, and are in contact with the P+ regions 15. The dielectric layer 17 is disposed on the outer surface of the plurality of trenches 11, a portion of the surface of the first P-type well region 13, a portion of the surface of the second P-type well region 14, a portion of the surface of the plurality of P+ regions 15, and a portion of the surface of the plurality of N+ regions 16. Emitter metal 18 is provided on the surfaces of multiple P+ regions 15 on both sides of the true gate trench 111, multiple N+ regions 16 on both sides of the true gate trench 111, the surface of the dummy gate trench 112, the surface of the P+ region 15 between adjacent dummy gate trenches 112, and the surface of the dielectric layer 17 above the true gate trench 111 and the dummy gate trench 112. The sampling electrode metal 19 is disposed on the surface of the dielectric layer 17 above the floating gate trench 113 and on the surface of the multiple N+ regions 16 and P+ regions 15 on both sides of the floating gate trench 113. The sampling resistor is connected to the sampling electrode metal 19.

[0021] The P-type guard ring 12 is located below multiple trenches. On the one hand, it can shield and divide the electric field, avoiding excessive concentration of the electric field at the bottom of the trench and improving the withstand voltage stability of the device. On the other hand, during the normal turn-off process of the IGBT, when the collector voltage Vce begins to increase, the potential of the P-type guard ring will increase synchronously with Vce. Through capacitive coupling, the potential change is transmitted to the floating gate trench above, causing its potential to rise synchronously. This induces the formation of electron channels on both sides of the floating gate trench, allowing the voltage sampling area to conduct and forming a current flowing from the back collector to the front voltage sampling electrode.

[0022] It should be noted that the floating gate trench is not connected to any electrode, and its potential is floating, changing with the collector voltage of the IGBT.

[0023] In power devices, such as Figure 1 Based on different functions, it can be divided into three regions: IGBT cell region 100, isolation region 200 and IGBT voltage sampling region 300.

[0024] The IGBT cell region 100 is the area where the device implements the main power switching function. It contains multiple repeating cell structures. Within this region, the true gate trench 111 (G) is filled with polysilicon and connected to the gate potential, serving as the control electrode of the device. First P-type well regions are provided on both sides of the true gate trench, with a high doping concentration (e.g., 1e13cm).- (on the order of ³).

[0025] The isolation region 200 is located between the IGBT cell region 100 and the voltage sampling region 300, and serves as an electrical isolation and potential transition area. Multiple dummy gate trenches 112 (E) are provided in this region, and the polysilicon inside is connected to the emitter potential, so it does not participate in the switching control.

[0026] The IGBT voltage sampling region 300 is a key area for realizing the voltage sampling function without additional power supply. It is located at the edge of the device and occupies a small area. A floating gate trench 113 (F) is provided in this region. The polysilicon inside is not connected to any electrodes and is in a completely floating state. A second P-type well region (Pwell2) is provided on both sides of the floating gate trench. Its doping concentration is lower than that of the first P-type well region (Pwell) of the IGBT cell region 100. An N+ region is provided on the surface of Pwell2 near the floating gate trench and a P+ region is provided away from the trench. The two are in contact with each other and are metal-connected to the sampling electrode. A P-type guard ring is provided under all trenches (including the floating gate trench). The potential of the guard ring increases as the collector voltage Vce increases when it is subjected to voltage. Its working principle is as follows: During the normal turn-off process of the IGBT (or any operating condition that causes Vce to rise), the collector voltage Vce begins to increase. Since the potential of the P-type guard ring (Ring) below the floating gate trench (F) increases synchronously with Vce, the potential of the floating gate trench (F) also increases through capacitive coupling. When the floating gate potential exceeds the threshold voltage of Pwell2, electron channels are formed on the Pwell2 surfaces on both sides of the floating gate trench (F) through inversion, thereby turning on the voltage sampling region 300 and generating a current flowing from the back collector (P+Collector) to the front sampling electrode metal (Sensor metal). In one example, a sampling resistor can be connected in series outside the sampling electrode to achieve voltage sampling, such as... Figure 2 This diagram illustrates a structural block diagram of another power device provided by an embodiment of the present invention. A sampling resistor R can be connected in series outside the sampling electrode metal to achieve voltage sampling. The principle is as follows: During the normal turn-off process of the IGBT, the collector voltage Vce begins to increase. In the voltage sampling region, the potential of the P-type guard ring Ring increases with Vce, thereby increasing the potential of the floating gate trench (F). As a result, an electron channel is formed in the Pwell2 on both sides of the floating gate trench (F). The voltage sampling region is turned on, and a current flows from the back collector to the front voltage sampling electrode (Sensor metal). A sampling resistor is connected in series at the voltage sampling electrode port. After the current flows through the resistor, a small voltage Vsensor that varies with Vce can be obtained, which is the sampling voltage.

[0027] As can be seen, this invention does not require any external driving voltage or power supply circuit for the floating gate, completely avoiding the design costs and application difficulties of related technologies that require additional power supply. Furthermore, by selecting an appropriate sampling resistor value, a Vsensor~Vce sampling curve with high linearity can be obtained, such as... Figure 3 The figure shows a sampling voltage curve with different resistors provided in an embodiment of the present invention. It can be seen that the curve is obtained by sampling Vce with sampling resistors of 0.1Ω, 1Ω and 10Ω respectively. The results show that the linearity of the voltage sampling curve is the highest when Rs=1Ω. Therefore, the collector voltage Vce from 0V to 600V can be mapped to a sampling voltage Vsensor that varies within 5V.

[0028] This invention discloses a power device in which the potential of the floating gate trench automatically rises with the collector voltage as the collector voltage increases, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This enables the voltage sampling region to conduct, and the current flows from the back collector to the front voltage sampling electrode, forming a sampling voltage through the sampling resistor. Voltage sampling can be achieved without any additional power supply circuit, thereby reducing design costs and application difficulty. At the same time, the P-type protection ring shared by all trenches can effectively shield the electric field concentration at the bottom of the trench, avoiding local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, a self-powered, linearly adjustable voltage sampling function is achieved, improving the integration and reliability of the power device.

[0029] In one embodiment of the present invention, the power device further includes: The N-type cutoff layer is located below the N-type drift region and is connected to the N-type drift region; The P-type collector area is located below the N-type cutoff layer and connected to the N-type cutoff layer; The collector metal is located below the P-type collector region and connected to the P-type collector region.

[0030] In embodiments of the present invention, such as Figure 1 The power device also includes: an N-type cutoff layer 20, a P-type collector region 21, and a collector metal 22.

[0031] In one embodiment of the present invention, the doping concentration of the second P-type well region is lower than that of the first P-type well region.

[0032] In one embodiment of the present invention, the polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

[0033] In one embodiment of the present invention, the doping concentration of the first P-type well region is 1e13cm. -3 ~5e13cm -3 The doping concentration of the second P-type well region is 1e11cm. -3 ~1e13cm -3 .

[0034] In this embodiment of the invention, since the doping concentration of the second P-type well region Pwell2 directly affects the turn-on threshold and channel resistance of the electron channel, the slope of the sampling curve can be flexibly controlled by adjusting the implantation dose of the second P-type well region Pwell2, thereby meeting the requirements of different application scenarios for sampling sensitivity and range, such as... Figure 4 The figure shows voltage sampling characteristic curves of a second P-type well region with different doping concentrations provided by an embodiment of the present invention. It can be seen that as the Pwell2 implantation dose of the second P-type well region increases, the slope of the voltage sampling curve decreases. This is because the potential of the floating gate trench (F) is the same under the same Vce condition. As the Pwell2 concentration increases, the channel inversion degree of the voltage sampling region is smaller, the current decreases, and the Vsensor decreases.

[0035] like Figure 5 This diagram illustrates a power semiconductor device with integrated voltage sampling function according to an embodiment of the present invention. It includes an IGBT cell region 100, an isolation region 200, an IGBT voltage sampling region 300, and a gate pad region 400. The IGBT cell region 100 occupies most of the total device area, effectively ensuring the device's power requirements. The IGBT voltage sampling region 300 is located at the edge of the IGBT cell region 100, occupying only a small portion of the device area, ensuring that it does not affect the normal operation of the power IGBT device and has a high degree of integration. The isolation region 200 separates it from the IGBT cell region 100. Figure 5 The section shown along A-A1 is... Figure 1 The structure shown.

[0036] This invention discloses a power device in which the potential of the floating gate trench automatically rises with the collector voltage as the collector voltage increases, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This enables the voltage sampling region to conduct, and the current flows from the back collector to the front voltage sampling electrode, forming a sampling voltage through the sampling resistor. Voltage sampling can be achieved without any additional power supply circuit, thereby reducing design costs and application difficulty. At the same time, the P-type protection ring shared by all trenches can effectively shield the electric field concentration at the bottom of the trench, avoiding local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, a self-powered, linearly adjustable voltage sampling function is achieved, improving the integration and reliability of the power device.

[0037] Reference Figure 6 The diagram illustrates a step-by-step flowchart of a method for manufacturing a power device according to an embodiment of the present invention. The method for manufacturing the power device includes the following steps: Step 201: Provide an N-type drift region substrate.

[0038] Step 202: A plurality of trenches are formed on the N-type drift region substrate. The plurality of trenches include at least one true gate trench, at least one dummy gate trench and at least one floating gate trench, with the dummy gate trench located between the true gate trench and the floating gate trench.

[0039] like Figure 7 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 1 Using the N-type drift region 10 as a substrate, a trench array arranged laterally and parallel to each other is formed by silicon etching process. These trenches correspond to the subsequent true gate trench (G), dummy gate trench (E) and floating gate trench (F), respectively, wherein the dummy gate trench is set between the true gate trench and the floating gate trench.

[0040] Step 203: A P-type protective ring is formed below the multiple trenches, and a second P-type trap region is formed on both sides of the multiple trenches.

[0041] In this embodiment of the invention, after the trench etching is completed, the entire chip surface can be implanted. After high-temperature annealing at 1100°C, a second P-type well region Pwell2 is formed on the trench sidewall, and a P-type protective ring Ring is formed at the bottom of the trench.

[0042] like Figure 8 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 2 A P-type floating protection ring (Ring) can be formed at the bottom of the trench using ion implantation and high-temperature annealing processes, and a second P-type trap region (14) can be formed on the sidewall of the trench.

[0043] Step 204: Multiple first P-type well regions are formed on both sides of a portion of the trench.

[0044] In embodiments of the present invention, such as Figure 8 Boron ion implantation can be performed on the entire chip surface first, with an ion implantation dose of approximately 1e12cm. -3 After annealing at 1100℃, Pwell2 is formed on the sidewalls of the grooves. Further, as... Figure 9 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 3 A gate oxide layer of approximately 0.1µm to 0.12µm can be grown on the sidewall of each trench using a thermo-oxidative process.

[0045] Furthermore, such as Figure 10 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 4 A polysilicon deposition process can be performed, and then the polysilicon on the chip surface can be etched away, leaving only the polysilicon filling the trenches.

[0046] Furthermore, such as Figure 11 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 5 Boron ion implantation can be performed on the IGBT cell region and isolation region using a Pwell mask, specifically by implanting boron ions at a dose of approximately 1e13cm² on both sides of the true gate trench 111 and part of the dummy gate trench 112. -3 After annealing at 1100℃, a Pwell region with a deeper junction depth than Pwell2 is formed.

[0047] Step 205: P-type ions are injected into the upper sides of each trench to form multiple P+ regions, wherein the multiple P+ regions are respectively disposed on the surface of the first P-type well region and the second P-type well region.

[0048] Step 206: N-type ions are implanted on the surface of the second P-type well region and part of the surface of the first P-type well region to form multiple N+ regions; wherein, the N+ regions are close to both sides of the true gate trench and both sides of the floating gate trench, and are in contact with the P+ regions.

[0049] like Figure 12 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 6 Arsenic ions can be implanted using an N+ Mask and boron ions can be implanted using a P+ Mask, respectively, followed by high-temperature annealing to form N+ and P+ regions.

[0050] Step 207: A dielectric layer is formed on the outer surface of the multiple trenches, a portion of the surface of the first P-type well region, a portion of the surface of the second P-type well region, a portion of the surface of the multiple P+ regions, and a portion of the surface of the multiple N+ regions.

[0051] like Figure 13 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 7 First, a 1.1µm thick dielectric layer can be deposited to obtain the power device shown in the figure. Further, as... Figure 14 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 8 The dielectric layer 17 required by this invention can be obtained by using CT hole etching process.

[0052] Step 208: An emitter metal is formed on the surfaces of multiple P+ regions on both sides of the true gate trench, the surfaces of multiple N+ regions on both sides of the true gate trench, the surface of the dummy gate trench, the surface of the P+ regions between adjacent dummy gate trenches, and the surface of the dielectric layer above the true gate trench and the dummy gate trench.

[0053] Step 209: Form sampling electrode metal on the surface of the dielectric layer above the floating gate trench and on the surfaces of multiple N+ and P+ regions on both sides of the floating gate trench.

[0054] In embodiments of the present invention, such as Figure 15 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 9 First, a metal layer can be deposited on the surface of the dielectric layer 17; then, etching can be performed to obtain the emitter metal 18 and the sampling electrode metal 19, such as... Figure 16 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 10 The deposited metal layer can be etched to obtain the emitter metal 18 and the sampling electrode metal 19.

[0055] This invention discloses a method for manufacturing a power device. When the collector voltage increases, the potential of the floating gate trench automatically rises with the collector voltage, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This enables the voltage sampling region to conduct, and the current flows from the back collector to the front voltage sampling electrode. Voltage sampling can be achieved without any additional power supply circuit, thereby reducing design costs and application difficulty. At the same time, the P-type protection ring shared by all trenches can effectively shield the electric field concentration at the bottom of the trench, avoiding local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, a self-powered, linearly adjustable voltage sampling function is achieved, improving the integration and reliability of the power device.

[0056] In one embodiment of the present invention, it further includes: N-type ions are implanted beneath the N-type drift region substrate to form an N-type cutoff layer; the N-type cutoff layer is connected to the N-type drift region substrate. P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form the collector metal; the collector metal is connected to the P-type collector region.

[0057] In one embodiment of the present invention, the doping concentration of the second P-type well region is lower than that of the first P-type well region.

[0058] In embodiments of the present invention, such as Figure 17 This illustration shows a method for manufacturing a power device according to an embodiment of the present invention. Figure 10 First, N+_FS ions can be implanted onto the surface of the N-type drift region substrate to obtain an N-type cutoff layer. Then, P-type ions are implanted below the N-type cutoff layer to obtain a P-type collector region. Finally, metal is deposited below the P-type collector region to form a collector metal.

[0059] In one embodiment of the present invention, the polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

[0060] This invention discloses a method for manufacturing a power device. When the collector voltage increases, the potential of the floating gate trench automatically rises with the collector voltage, forming an electron channel on the surface of the second P-type well region on both sides of the floating gate trench. This enables the voltage sampling region to conduct, and the current flows from the back collector to the front voltage sampling electrode. Voltage sampling can be achieved without any additional power supply circuit, thereby reducing design costs and application difficulty. At the same time, the P-type protection ring shared by all trenches can effectively shield the electric field concentration at the bottom of the trench, avoiding local breakdown. The dummy gate trench and the first P-type well region on both sides separate the real gate trench from the floating gate trench, preventing mutual interference of electric fields and currents between different regions. Thus, while ensuring high withstand voltage capability, a self-powered, linearly adjustable voltage sampling function is achieved, improving the integration and reliability of the power device.

[0061] This invention also provides a chip, including the power device described above.

[0062] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0063] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0064] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A power device, characterized by, The power device is connected to the sampling resistor, including: N-type drift zone; Multiple grooves are provided within the N-type drift zone; the multiple grooves are arranged laterally at intervals and parallel to each other; the multiple grooves include at least one true grid groove, at least one false grid groove and at least one floating grid groove, the false grid groove being located between the true grid groove and the floating grid groove; A P-type protective ring is disposed below the plurality of grooves; Multiple first P-type well regions are located on both sides of the true gate trench and between adjacent dummy gate trenches, respectively; Multiple second P-type well regions are located on both sides of the floating gate trench; Multiple P+ regions are respectively disposed on the surfaces of the first P-type well region and the second P-type well region; Multiple N+ regions are disposed on the surface of a portion of the first P-type well region and the surface of the second P-type well region, wherein the N+ regions are close to both sides of the true gate trench and both sides of the floating gate trench, and are in contact with the P+ regions; A dielectric layer is disposed on the outer surface of the plurality of trenches, a portion of the surface of the first P-type well region, a portion of the surface of the second P-type well region, a portion of the surface of the plurality of P+ regions, and a portion of the surface of the plurality of N+ regions. Emitter metal is disposed on the surfaces of multiple P+ regions on both sides of the true gate trench, the surfaces of multiple N+ regions on both sides of the true gate trench, the surface of the dummy gate trench, the surface of the P+ region between adjacent dummy gate trenches, and the surface of the dielectric layer above the true gate trench and the dummy gate trench. The sampling electrode metal is disposed on the surface of the dielectric layer above the floating gate trench, and on the surfaces of multiple N+ and P+ regions on both sides of the floating gate trench; the sampling resistor is connected to the sampling electrode metal.

2. The power device of claim 1, wherein, The power device further includes: An N-type cutoff layer is disposed below the N-type drift region and connected to the N-type drift region; A P-type collector region is located below the N-type cutoff layer and connected to the N-type cutoff layer; The collector metal is located below the P-type collector region and connected to the P-type collector region.

3. The power device of claim 1, wherein, The doping concentration of the second P-type well region is lower than that of the first P-type well region.

4. The power device according to claim 1, characterized in that, The polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

5. The power device according to claim 1, characterized in that, the first P-type well region has a doping concentration of 1e13cm -3 ~5e13cm -3 ; the second P-type well region has a doping concentration of 1e11cm -3 ~1e13cm -3 .

6. A method for manufacturing a power device, characterized in that, The manufacturing method for manufacturing the power device as described in any one of claims 1 to 5 includes: Provide N-type drift region substrate; Multiple trenches are formed on the N-type drift region substrate, the multiple trenches including at least one true gate trench, at least one dummy gate trench and at least one floating gate trench, the dummy gate trench being located between the true gate trench and the floating gate trench; A P-shaped protective ring is formed below the plurality of trenches, and a second P-shaped well region is formed on both sides of the plurality of trenches; Multiple first P-type well regions are formed on both sides of some trenches; P-type ions are injected into the upper sides of each trench to form multiple P+ regions, wherein the multiple P+ regions are respectively disposed on the surface of the first P-type well region and the second P-type well region. N-type ions are implanted on the surface of the second P-type well region and part of the surface of the first P-type well region to form multiple N+ regions; wherein the N+ regions are close to both sides of the true gate trench and both sides of the floating gate trench, and are in contact with the P+ regions; A dielectric layer is formed on the outer surface of the plurality of trenches, a portion of the surface of the first P-type well region, a portion of the surface of the second P-type well region, a portion of the surface of the plurality of P+ regions, and a portion of the surface of the plurality of N+ regions. Emitter metal is formed on the surfaces of multiple P+ regions on both sides of the true gate trench, the surfaces of multiple N+ regions on both sides of the true gate trench, the surface of the dummy gate trench, the surface of the P+ region between adjacent dummy gate trenches, and the surface of the dielectric layer above the true gate trench and the dummy gate trench. Sampling electrode metal is formed on the surface of the dielectric layer above the floating gate trench and on the surfaces of multiple N+ and P+ regions on both sides of the floating gate trench.

7. The method for manufacturing a power device according to claim 6, characterized in that, Also includes: N-type ions are implanted beneath the substrate in the N-type drift region to form an N-type cutoff layer; The N-type cutoff layer is connected to the N-type drift region; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form a collector metal; the collector metal is connected to the P-type collector region.

8. The method for manufacturing a power device according to claim 6, characterized in that, The doping concentration of the second P-type well region is lower than that of the first P-type well region.

9. The method for manufacturing a power device according to claim 6, characterized in that, The polysilicon in the true gate trench is connected to the gate potential, and the polysilicon in the dummy gate trench is connected to the emitter potential.

10. A chip, characterized in that, Includes the power device as described in any one of claims 1 to 5.

Images