A two-dimensional semiconductor transistor containing a contact layer and a method of manufacturing the same

Abstract

The application discloses a two-dimensional semiconductor transistor containing a contact layer and a preparation method thereof. The preparation method comprises the following steps: providing a substrate with a two-dimensional semiconductor material on the surface of the substrate; preparing a mask layer; defining a channel region; preparing a gate dielectric layer; defining a gate dielectric region to expose two opposite sidewalls of the channel region; etching and removing two sidewalls of the exposed mask layer to expose the surface of the two-dimensional semiconductor material; preparing a contact layer; defining and preparing a gate, a source and a drain; and finally etching and removing the contact layer which is not covered by the source, the drain and the gate to obtain the two-dimensional semiconductor transistor. The electrode contact is realized through the contact layer, and the contact layer is a conductive compound. Therefore, the defect of migration of metal atoms to the two-dimensional channel and the gate dielectric caused by metal contact is avoided, the structural alignment error is small, the device yield is higher, the mature process system based on silicon is adapted, and industrial production is facilitated.

Description

Technical Field

[0001] This invention relates to the field of two-dimensional semiconductor device technology, and in particular to a two-dimensional semiconductor transistor with a contact layer and its fabrication method. Background Technology

[0002] Two-dimensional semiconductor materials possess atomically thin thickness and excellent electrical transport properties, making them promising candidates for integrated circuit devices in the post-Moore's Law era and preferred channel materials for next-generation microelectronic devices. Currently, in conventional two-dimensional semiconductor transistor fabrication processes, source / drain contacts and gate contacts are generally made of elemental metals. However, metal atoms are prone to diffusion and migration under electric fields and thermal stress, infiltrating the two-dimensional semiconductor channel and the interior of the gate dielectric. This results in increased leakage current, electrical parameter drift, and severely degrades the transistor's electrical performance and long-term reliability.

[0003] Meanwhile, the source / drain and gate contacts of existing transistors are fabricated using separate, step-by-step processes, requiring multiple high-temperature thin-film depositions and multiple rounds of photolithography patterning. These multiple high-temperature processes result in high thermal budgets. During repeated photolithography, chemicals such as photoresist and developer can easily come into contact with and corrode the two-dimensional semiconductor channel, causing irreversible physical damage and chemical contamination to the atomically thin two-dimensional material. This disrupts the intrinsic electrical characteristics of the channel, ultimately leading to degradation of key performance aspects such as device mobility and switching characteristics. Furthermore, the multiple discrete fabrication steps increase process complexity and production costs, hindering the large-scale mass production and application of two-dimensional semiconductor transistors.

[0004] Therefore, there is an urgent need to develop a two-dimensional semiconductor transistor structure and its fabrication method that can suppress metal migration, simplify the fabrication process, and reduce process damage. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a two-dimensional semiconductor transistor with a contact layer and a method for fabricating the same. The electrode contact of the two-dimensional semiconductor transistor is achieved through a contact layer, which is a conductive compound. This avoids the defects caused by the migration of metal atoms to the two-dimensional channel and gate dielectric caused by metal contact. At the same time, the structure alignment error is small, the device yield is higher, it is compatible with mature silicon-based process systems, and it is convenient for industrial production.

[0006] To address the aforementioned technical problems, a first aspect of the present invention provides a method for fabricating a two-dimensional semiconductor transistor containing a contact layer, comprising: S1. A substrate is provided, the surface of which has a two-dimensional semiconductor material; S2. Prepare a mask layer on the surface of a two-dimensional semiconductor material; S3. Define the channel region of the transistor, and etch away the two-dimensional semiconductor material and mask layer outside the channel region; S4. Prepare a gate dielectric layer that covers the entire channel region, and the periphery of the gate dielectric layer extends at least beyond the edge of the channel region. S5. Define the gate dielectric layer region, etch away the gate dielectric layer outside the gate dielectric layer region, and expose the two opposing sidewalls of the channel region to expose the sidewalls of the two-dimensional semiconductor material and the mask layer. S6. Etch the two opposite sidewalls of the exposed mask layer to remove part of the mask layer, so as to expose part of the upper surface of the two-dimensional semiconductor material. S7. Prepare a contact layer that covers the entire channel region and whose periphery extends at least beyond the edge of the channel region. At the same time, the upper surface of the exposed two-dimensional semiconductor material in S6 also has a contact layer. The material of the contact layer is a conductive compound. S8. Define the gate, source, and drain regions on the surface of the contact layer, and simultaneously fabricate the source, drain, and gate. S9. Etch away the contact layer not covered by the source, drain and gate to obtain a two-dimensional semiconductor transistor.

[0007] Preferably, the substrate in S1 includes silicon oxide, sapphire, single-crystal silicon, single-crystal germanium, silicon carbide, and gallium arsenide; Two-dimensional semiconductor materials include single-layer or multi-layer molybdenum disulfide, tungsten selenide, and tungsten sulfide.

[0008] Preferably, in S2, the material of the mask layer includes aluminum oxide; The thickness of the mask layer is 30-50 angstroms; The fabrication processes for mask layers include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S4, the gate dielectric layer is made of one or more of silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide, and when multiple materials are used, the gate dielectric layer is formed into a stacked structure. The thickness of the gate dielectric layer is 10-30 nm; The fabrication processes for the gate dielectric layer include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S7, the contact layer is made of materials including titanium nitride, tantalum nitride, titanium carbide, and zirconium nitride. The thickness of the contact layer is 10-20 nm; The fabrication process of the contact layer includes atomic layer deposition.

[0009] Preferably, the processes for defining the channel region of the transistor in S3 and the gate dielectric layer region in S5 are both photolithography processes. The etching processes in S3 to remove the two-dimensional semiconductor material and mask layer outside the channel region, and in S5 to remove the gate dielectric layer outside the gate dielectric layer region, are both dry etching processes.

[0010] Preferably, the etching in S6 is wet etching; After etching, the exposed surface width of the two-dimensional semiconductor material is 50-100 angstroms.

[0011] Preferably, the process for defining the gate, source, and drain regions in S8 is a photolithography process; The gate, source, and drain electrodes are made of materials including titanium and gold; The fabrication processes for the gate, source, and drain electrodes include electron beam evaporation, magnetron sputtering, and resistance evaporation. The thickness of the gate, source, and drain is 20-50 nm.

[0012] Preferably, the etching process in S9 includes dry etching.

[0013] Preferably, the material of the mask layer has a different dry etching selectivity and / or wet etching selectivity than the two-dimensional semiconductor material; The materials of the contact layer and the gate dielectric layer have different dry etching selectivity and / or wet etching selectivity. The material of the contact layer has different dry etching selectivity and / or wet etching selectivity than the materials of the gate, source, and drain.

[0014] The present invention provides a method for fabricating a two-dimensional semiconductor transistor with a contact layer, which enables the fabrication of the contact layer and the source, drain, and gate in a single process. This not only avoids the defects caused by the migration of metal atoms into the two-dimensional channel and gate dielectric due to metal contacts, but also significantly reduces the potential performance impact of high-temperature thermal shock and photoresist and developer contact erosion caused by multiple processes on the two-dimensional semiconductor material. The fabrication method provided by the present invention not only helps to improve device stability and long-term reliability, but also effectively increases overlay redundancy, reduces process alignment difficulty, simplifies the process, and reduces production costs. The fabrication process in the present invention has good compatibility with existing silicon-based processes, which is conducive to the industrial-scale mass production of devices.

[0015] To solve the above-mentioned technical problems, a second aspect of the present invention is to provide a two-dimensional semiconductor transistor with a contact layer prepared by the aforementioned method for preparing a two-dimensional semiconductor transistor with a contact layer.

[0016] The two-dimensional semiconductor transistor with a contact layer provided by this invention has electrode contacts (including source contacts, drain contacts, and gate contacts) implemented through the contact layer. The contact layer is a conductive compound rather than a metal, thus avoiding the defects of metal atoms migrating to the two-dimensional channel and gate dielectric caused by metal contacts, which helps to improve device stability and long-term reliability. At the same time, the source, drain, and gate are fabricated in a single process, resulting in small structural alignment errors, higher device yield, and the overall structure is compatible with mature silicon-based process systems, facilitating industrial production. Attached Figure Description

[0017] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figures 1A-9C The present invention illustrates a method for fabricating a two-dimensional semiconductor transistor containing a contact layer, wherein: Figure 1A It is a top view of a substrate containing two-dimensional semiconductor material; Figure 1B yes Figure 1A A cross-sectional view at position AA; Figure 1C yes Figure 1A A cross-sectional view at the BB position; Figure 2A This is a top view after a mask layer has been deposited on a two-dimensional semiconductor material; Figure 2B yes Figure 2A A cross-sectional view at position AA; Figure 2C yes Figure 2A A cross-sectional view at the BB position; Figure 3A This is a top view after the trench area has been defined; Figure 3B yes Figure 3A A cross-sectional view at position AA; Figure 3C yes Figure 3A A cross-sectional view at the BB position; Figure 4A This is a top view of the entire deposition grid medium layer; Figure 4B yes Figure 4A A cross-sectional view at position AA; Figure 4C yes Figure 4A A cross-sectional view at the BB position; Figure 5A This is a top view after defining the gate dielectric region; Figure 5B yes Figure 5A A sectional view at position AA in the middle; Figure 5C yes Figure 5A A cross-sectional view at the BB position; Figure 6A This is a top view of the etched mask layer, where the dashed line indicates the etch termination position. Figure 6Byes Figure 6A A sectional view at position AA in the middle; Figure 6C yes Figure 6A A cross-sectional view at the BB position; Figure 7A This is a top view after the deposition of the contact layer; Figure 7B yes Figure 7A A sectional view at position AA in the middle; Figure 7C yes Figure 7A A sectional view at position BB in the middle; Figure 8A This is a top view after the source, drain, and gate electrodes have been deposited; Figure 8B yes Figure 8A A sectional view at position AA in the middle; Figure 8C yes Figure 8A A sectional view at position BB in the middle; Figure 9A It is a top view after removing the contact layer that is not covered by the source, drain and gate, that is, a top view of a two-dimensional semiconductor transistor with the contact layer. Figure 9B yes Figure 9A A sectional view at position AA in the middle; Figure 9C yes Figure 9A A sectional view at position BB in the middle; Wherein, 1-substrate; 2-two-dimensional semiconductor material; 21-channel region; 3-mask layer; 4-gate dielectric layer; 41-gate dielectric region; 5-contact layer; 6-source; 7-drain; 8-gate. Detailed Implementation

[0019] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] refer to Figures 1A to 9C This invention illustrates a method for fabricating a two-dimensional semiconductor transistor containing a contact layer, comprising: S1. A substrate is provided, the surface of which has a two-dimensional semiconductor material (reference). Figure 1A , Figure 1B and Figure 1C ); S2. Fabrication of a mask layer on the surface of a two-dimensional semiconductor material (refer to...) Figure 2A , Figure 2B and Figure 2C ); S3. Define the channel region of the transistor, and etch away the two-dimensional semiconductor material and mask layer outside the channel region (see reference). Figure 3A , Figure 3B and Figure 3C ); S4. Prepare a gate dielectric layer that covers the entire channel region, and the periphery of the gate dielectric layer extends at least beyond the edge of the channel region (refer to...). Figure 4A , Figure 4B and Figure 4C ); S5. Define the gate dielectric layer region, etch away the gate dielectric layer outside the gate dielectric layer region, and expose the two opposing sidewalls of the channel region to expose the sidewalls of the two-dimensional semiconductor material and the mask layer (see reference). Figure 5A , Figure 5B and Figure 5C ); S6. Etch the two opposite sidewalls of the exposed mask layer to remove part of the mask layer, thereby exposing part of the upper surface of the two-dimensional semiconductor material (refer to...). Figure 6A , Figure 6B and Figure 6C ); S7. Prepare a contact layer that covers the entire channel region, with the periphery of the contact layer extending at least beyond the edge of the channel region. Simultaneously, the upper surface of the exposed two-dimensional semiconductor material from S6 also has a contact layer. The contact layer is made of a conductive compound (see reference). Figure 7A , Figure 7B and Figure 7C ); S8. Define the gate, source, and drain regions on the contact layer surface, and simultaneously fabricate the source, drain, and gate (refer to...). Figure 8A , Figure 8B and Figure 8C ); S9. Etch away the contact layer not covered by the source, drain, and gate to obtain a two-dimensional semiconductor transistor (reference). Figure 9A , Figure 9B and Figure 9C ).

[0021] In this invention, electrode contacts (including source, drain, and gate contacts) are achieved through a contact layer. This contact layer is a conductive compound, not a metal, thus avoiding the defects caused by metal atoms migrating into the two-dimensional channel and gate dielectric, which helps improve device stability and long-term reliability. Simultaneously, the source, drain, and gate are fabricated in a single process, significantly reducing the impact of high-temperature thermal shock and photoresist / developer contact erosion caused by multiple processes on the performance of the two-dimensional semiconductor material. Furthermore, the gate region, source region, and drain region are defined simultaneously. Compared to two or more definitions, this effectively increases overlay redundancy, reduces process alignment difficulty, simplifies the fabrication process, and reduces production costs. The fabrication process in this invention has good compatibility with existing silicon-based processes, facilitating the industrial-scale mass production of devices.

[0022] In one specific embodiment, the substrate in S1 includes silicon oxide, sapphire, single-crystal silicon, single-crystal germanium, silicon carbide, and gallium arsenide; the two-dimensional semiconductor material includes single-layer or multi-layer molybdenum disulfide, tungsten selenide, and tungsten sulfide. Understandably, the two-dimensional semiconductor material can be formed through physical vapor deposition, chemical vapor deposition, metal-organic chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition. It can also be formed by peeling a pre-grown two-dimensional material wafer from its metal or insulating substrate and transferring it to the target substrate using a dry or wet method; or by mechanically peeling off a two-dimensional material bulk to obtain a two-dimensional atomic crystal thin film material, which is then transferred to the target substrate using a dry method. The substrate and two-dimensional semiconductor material structure are as follows: Figure 1A-1C As shown in the figure, the two-dimensional semiconductor material covers the entire substrate, where Figure 1A It is a top view. Figure 1B and 1C They are Figure 1A Cross-sectional views at positions AA and BB; since the growth of two-dimensional semiconductor materials on the substrate can be achieved by existing technology, it will not be described in detail here.

[0023] In one specific embodiment, in S2, the material of the mask layer includes aluminum oxide; The thickness of the mask layer is 30-50 angstroms; The fabrication processes for mask layers include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S4, the gate dielectric layer is made of one or more of silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide, and when multiple materials are used, the gate dielectric layer is formed into a stacked structure. The thickness of the gate dielectric layer is 10-30 nm; The fabrication processes for the gate dielectric layer include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S7, the contact layer is made of materials including titanium nitride, tantalum nitride, titanium carbide, and zirconium nitride. The thickness of the contact layer is 10-20 nm; The fabrication process of the contact layer includes atomic layer deposition.

[0024] In this specific scheme, the mask layer is preferably aluminum oxide, which has excellent etching selectivity with the two-dimensional semiconductor material. During the sidewall etching step, it can be selectively etched, preserving the two-dimensional semiconductor material, and the entire sidewall forms a concave shape, exposing the upper surface of the two-dimensional semiconductor material. In this application, there are no special requirements for the thickness and fabrication process of the mask layer. It should be noted that, for process convenience, when depositing the mask layer, it is preferable to cover the entire surface of the two-dimensional semiconductor material (see reference). Figures 2A to 2C This shows a view behind the global deposition mask layer, where Figure 2A It is a top view. Figure 2B and Figure 2C They are Figure 2A (Cross-sectional views at positions AA and BB), but we do not wish to be constrained by this; the coverage area should not be smaller than the trench area.

[0025] In this specific scheme, there are no particular limitations on the material, thickness, and process of the gate dielectric layer; it is only necessary to ensure that the gate dielectric layer and the contact layer have excellent etching selectivity. When depositing the gate dielectric layer, full coverage is preferred, such as... Figures 4A to 4C As shown, where Figure 4A It is a top view. Figure 4B and Figure 4C They are Figure 4A Cross-sectional views at positions AA and BB.

[0026] In this specific scheme, the contact layer material is a conductive compound such as titanium nitride, tantalum nitride, titanium carbide, or zirconium nitride, which has good conductivity. The preferred thickness is 10-20 nm. Too thin a layer can easily lead to power outages and voids, and its ability to prevent metal migration is limited. Too thick a layer may result in high contact layer stress and easy cracking, which can also affect the performance of the electrode. During the deposition of the contact layer, it also achieves limited full coverage. Furthermore, during the deposition process, the contact layer material fills the portion of the mask layer removed by etching, that is, it fills the concave areas of the sidewalls. Figures 7A to 7C As shown, where Figure 7A It is a top view. Figure 7B and Figure 7C They are Figure 7A Cross-sectional views at positions AA and BB.

[0027] In one specific scheme, the processes for defining the channel region of the transistor in S3 and the gate dielectric layer region in S5 are both photolithography processes. The etching processes in S3 to remove the two-dimensional semiconductor material and mask layer outside the channel region, and in S5 to remove the gate dielectric layer outside the gate dielectric layer region, are both dry etching processes.

[0028] In this specific scheme, the channel region of the transistor and the gate dielectric layer region are defined. Photolithography is preferably used, including spin-coating photoresist, exposure, and development to form a photomask (or directly using a mask) to block non-target etching areas. Then, an etching process is used to remove the layer to be etched in the target area, and finally, the photomask is removed. Specifically, for the transistor channel region, photolithographic grinding blocks the transistor channel region. Then, dry etching removes the mask layer and the two-dimensional semiconductor material, exposing the deposited surface, and then the photomask is removed. After etching, the result is as follows: Figures 3A to 3C As shown, where Figure 3A It is a top view. Figure 3B and Figure 3C They are Figure 3A Cross-sectional views at positions AA and BB; for the gate dielectric layer, a photomask is used to block the gate dielectric layer area, then the gate dielectric in the non-gate dielectric layer area is removed by dry etching, and finally the photomask is removed; the gate dielectric area is as follows: Figures 5A to 5C As shown (where Figure 5A It is a top view. Figure 5B and Figure 5C They are Figure 5A (Cross-sectional views at positions AA and BB) The X-axis direction is defined as the width, and the Y-axis direction is defined as the length (the subsequent definitions of width and length in this invention are the same). The width of the gate dielectric region is the same as the width of the channel region, and the edge of the gate dielectric region along the Y-axis direction is flush with the edge of the channel region along the Y-axis direction. The sidewalls of the channel region along the Y-axis direction are exposed to facilitate subsequent etching to remove the mask layer and to contact the contact layer. The length of the gate dielectric region is greater than the length of the channel region, and the edge of the gate dielectric region along the X-axis direction extends beyond and covers the edge of the channel region along the X-axis direction.

[0029] In one specific scheme, the etching in S6 is wet etching; after etching, the exposed surface width of the two-dimensional semiconductor material is 50-100 angstroms.

[0030] In this specific scheme, a wet etching process is used to etch the mask layer along the sidewalls to a depth of 50-100 angstroms. This means that after etching, the upper surface edge of the two-dimensional semiconductor material is exposed with a width of 50-100 angstroms, and the edge of the etched mask layer is recessed 50-100 angstroms along the Y-axis. Figures 6A to 6C As shown, where Figure 6A It is a top view. Figure 6B and Figure 6C They are Figure 6A Cross-sectional views at positions AA and BB; the etching solution for wet etching is, for example, a mixture of phosphoric acid and water, and the etching temperature is, for example, 50°C. Wet etching is a conventional technique and will not be described in detail here.

[0031] In one specific scheme, the process for defining the gate, source, and drain regions in S8 is a photolithography process. The gate, source, and drain electrodes are made of materials including titanium and gold; The fabrication processes for the gate, source, and drain electrodes include electron beam evaporation, magnetron sputtering, and resistance evaporation. The thickness of the gate, source, and drain is 20-50 nm.

[0032] In this specific scheme, the process of defining the electrode regions (gate, source, and drain regions) on the contact layer surface preferably employs photolithography, including spin-coating photoresist, exposure, and development to form a photomask (or directly using a photomask) to block the contact layer of non-target electrode regions. The contact layer of the electrode regions is exposed. Electrodes are then deposited, bringing the electrodes into contact with the contact layer. After electrode deposition, the electrode layer of the non-electrode regions is peeled off, and the photomask is removed. The process is as follows: Figures 8A to 8C As shown, where Figure 8A It is a top view. Figure 8B and Figure 8C They are Figure 8A Cross-sectional views at positions AA and BB. This specific scheme achieves the fabrication of the gate, source, and drain in a single step.

[0033] In one specific embodiment, the etching process in S9 includes dry etching. Understandably, due to the excellent etch selectivity between the electrode material and the contact layer, the electrode can act as a mask for the contact layer. The portion of the contact layer not masked by the electrode is etched away, while the portion masked by the electrode is retained, forming the electrode contact, such as... Figures 9A to 9C As shown, where Figure 9A It is a top view. Figure 9B and Figure 9C They are Figure 9A Sectional views at positions AA and BB, and 9A to... Figure 9C The schematic diagram of the two-position semiconductor transistor structure with contact layer provided by the present invention is also shown; at the same time, the source, drain and gate are isolated to prevent conduction through the contact layer.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a two-dimensional semiconductor transistor containing a contact layer, characterized in that, include: S1. A substrate is provided, the surface of which has a two-dimensional semiconductor material; S2. Prepare a mask layer on the surface of a two-dimensional semiconductor material; S3. Define the channel region of the transistor, and etch away the two-dimensional semiconductor material and mask layer outside the channel region; S4. Prepare a gate dielectric layer that covers the entire channel region, and the periphery of the gate dielectric layer extends at least beyond the edge of the channel region. S5. Define the gate dielectric layer region, etch away the gate dielectric layer outside the gate dielectric layer region, and expose the two opposing sidewalls of the channel region to expose the sidewalls of the two-dimensional semiconductor material and the mask layer. S6. Etch the two opposite sidewalls of the exposed mask layer to remove part of the mask layer, so as to expose part of the upper surface of the two-dimensional semiconductor material. S7. Prepare a contact layer that covers the entire channel region and whose periphery extends at least beyond the edge of the channel region. At the same time, the upper surface of the exposed two-dimensional semiconductor material in S6 also has a contact layer. The material of the contact layer is a conductive compound. S8. Define the gate, source, and drain regions on the surface of the contact layer, and simultaneously fabricate the source, drain, and gate. S9. Etch away the contact layer not covered by the source, drain and gate to obtain a two-dimensional semiconductor transistor.

2. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, The substrate in S1 includes silicon oxide, sapphire, single-crystal silicon, single-crystal germanium, silicon carbide, and gallium arsenide; Two-dimensional semiconductor materials include single-layer or multi-layer molybdenum disulfide, tungsten selenide, and tungsten sulfide.

3. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, In S2, the mask layer is made of aluminum oxide; The thickness of the mask layer is 30-50 angstroms; The fabrication processes for mask layers include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S4, the gate dielectric layer is made of one or more of silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide, and when multiple materials are used, the gate dielectric layer is formed into a stacked structure. The thickness of the gate dielectric layer is 10-30 nm; The fabrication processes for the gate dielectric layer include atomic layer deposition, chemical vapor deposition, and electron beam evaporation. In S7, the contact layer is made of materials including titanium nitride, tantalum nitride, titanium carbide, and zirconium nitride. The thickness of the contact layer is 10-20 nm; The fabrication process of the contact layer includes atomic layer deposition.

4. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, The processes used to define the channel region of the transistor in S3 and the gate dielectric layer region in S5 are both photolithography processes. The etching processes in S3 to remove the two-dimensional semiconductor material and mask layer outside the channel region, and in S5 to remove the gate dielectric layer outside the gate dielectric layer region, are both dry etching processes.

5. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, The etching in S6 is wet etching; After etching, the exposed surface width of the two-dimensional semiconductor material is 50-100 angstroms.

6. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, In S8, the process for defining the gate, source, and drain regions is a photolithography process. The gate, source, and drain electrodes are made of materials including titanium and gold; The fabrication processes for the gate, source, and drain electrodes include electron beam evaporation, magnetron sputtering, and resistance evaporation. The thickness of the gate, source, and drain is 20-50 nm.

7. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, The etching process in S9 includes dry etching.

8. The method for fabricating a two-dimensional semiconductor transistor containing a contact layer as described in claim 1, characterized in that, The material of the mask layer has different dry etching selectivity and / or wet etching selectivity compared to the two-dimensional semiconductor material; The materials of the contact layer and the gate dielectric layer have different dry etching selectivity and / or wet etching selectivity. The material of the contact layer has different dry etching selectivity and / or wet etching selectivity than the materials of the gate, source, and drain.

9. A two-dimensional semiconductor transistor with a contact layer prepared by the method for preparing a two-dimensional semiconductor transistor with a contact layer as described in any one of claims 1-8.

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