A silicon carbide-based gallium oxide mosfet device

Abstract

This application belongs to the field of semiconductor technology and provides a silicon carbide-based gallium oxide MOSFET device. The device includes a silicon carbide substrate layer, a functional intermediate layer, and a gallium oxide channel layer stacked sequentially from bottom to top; the thermal conductivity of the functional intermediate layer is >1 W·cm⁻¹. ‑1 ·K ‑1 The bandgap is >4.0 eV. The functional intermediate layer of this application can, on the one hand, block the diffusion of high voltage electric field to silicon carbide substrate, significantly improving the three-terminal breakdown voltage of the device; on the other hand, it can quickly dissipate channel heat by relying on the excellent thermal conductivity of the intermediate layer, effectively alleviating the self-heating effect of gallium oxide devices and reducing channel temperature rise under high power; at the same time, it can also buffer the lattice mismatch of heterogeneous interfaces and reduce interface defects, thereby improving the withstand voltage and heat dissipation capabilities while ensuring the excellent electrical transport performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a silicon carbide-based gallium oxide MOSFET device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core devices in power electronic systems, widely used in aerospace, communications, industrial control, new energy power generation, electric vehicles, rail transportation, and many other fields. Currently, applications are increasingly moving towards higher frequencies, higher power, and higher temperatures, placing more stringent demands on the power density, switching speed, and thermal stability of MOSFETs. Traditional semiconductor devices are gradually becoming insufficient to meet the demands of extreme operating conditions.

[0003] β-Ga₂O₃, as a new generation of ultra-wide bandgap semiconductor material, possesses outstanding electrical properties: its bandgap can reach 4.8~4.9 eV, its critical breakdown field strength is as high as 8 MV / cm, and its Baliga figure of merit is theoretically 4 times that of gallium nitride (GaN) and 10 times that of silicon carbide (SiC). It is an ideal material for fabricating low-voltage-loss, high-voltage, high-power MOSFET devices and has enormous development potential in the next generation of power electronics. However, β-Ga₂O₃ has a significant drawback: its intrinsic thermal conductivity is only 0.1~0.3 W·cm⁻¹. -1 ·K -1 β-Ga2O3 devices exhibit extremely poor thermal conductivity. When operating under high power density conditions, they experience severe self-heating, causing a rapid increase in channel temperature. This leads to a series of problems, including decreased carrier mobility, increased on-resistance, and reduced device reliability, significantly limiting the practical application of β-Ga2O3 devices.

[0004] To address the heat dissipation challenge of gallium oxide, the industry commonly employs a heterogeneous integration approach using SiC substrates and β-Ga₂O₃ thin films. SiC boasts a room-temperature thermal conductivity of up to 3.7 W·cm⁻¹. -1 ·K -1 With excellent thermal conductivity, it can effectively dissipate the heat generated during device operation, which is the mainstream approach to improve the self-heating problem of β-Ga2O3 lateral MOSFETs.

[0005] Currently, the mainstream technology in the industry uses alumina as a buffer layer to bond SiC substrates with β-Ga2O3 to fabricate MOSFET devices. This approach still faces three major technical bottlenecks: First, lattice mismatch and interface defects. There is a certain lattice mismatch between β-Ga2O3 and SiC (e.g., the mismatch between (-201)β-Ga2O3 and (0001)SiC is about 6.9%). Direct epitaxy or bonding will form a large number of dislocations and interface states at the interface, severely interfering with the normal transport of charge carriers in the channel and degrading the device's electrical performance. Second, premature substrate breakdown. The critical breakdown field strength of SiC is only 2.5 MV / cm, far lower than that of β-Ga2O3. When the device is subjected to high voltage, the electric field extends from the β-Ga2O3 channel layer to the SiC substrate, causing premature breakdown of the device in the SiC layer, significantly limiting the device's withstand voltage limit. Third, high thermal boundary resistance. The current alumina buffer layer has low thermal conductivity, which will form a large thermal boundary resistance at the heterogeneous interface, hindering the transfer of channel heat to the SiC substrate. This will prevent the full utilization of the high thermal conductivity of SiC and greatly reduce the heat dissipation effect of the device. Summary of the Invention

[0006] This application provides a silicon carbide-based gallium oxide MOSFET device to at least solve the above-mentioned technical problems existing in the prior art.

[0007] According to a first aspect of this application, a silicon carbide-based gallium oxide MOSFET device is provided, comprising a silicon carbide substrate layer, a functional intermediate layer, and a gallium oxide channel layer stacked sequentially from bottom to top; the thermal conductivity of the functional intermediate layer is >1 W·cm⁻¹. -1 ·K -1 The band gap width is greater than 4.0 eV.

[0008] Specifically, this application sets up a dedicated functional intermediate layer between the silicon carbide substrate layer and the gallium oxide channel layer: (1) Compared with the extremely low thermal conductivity of the traditional alumina buffer layer, the functional intermediate layer of this application has excellent thermal conductivity, which can significantly reduce the thermal boundary resistance of the heterostructure interface, quickly conduct the heat generated by the gallium oxide channel to the silicon carbide substrate, significantly improve the self-heating problem caused by the intrinsic thermal conductivity difference of gallium oxide, suppress the channel temperature rise, avoid the problems of decreased carrier mobility and increased on-resistance caused by excessive temperature, and improve the long-term reliability of the device. (2) The functional intermediate layer has an ultra-wide bandgap characteristic of greater than 4.0 eV, and its breakdown field strength is much better than that of the silicon carbide substrate. It can effectively block the electric field from the gallium oxide channel layer to the silicon carbide substrate under high voltage, eliminate the phenomenon of premature breakdown of the silicon carbide substrate, break through the voltage withstand bottleneck of existing devices, and adapt to high voltage and high power application scenarios. This application features a simple structure and is easy to fabricate. Relying on a functional intermediate layer with high thermal conductivity and an ultra-wide bandgap, it solves the problems of poor heat dissipation and low withstand voltage of traditional silicon carbide-based gallium oxide MOSFETs in one step. The device also has high thermal stability, high breakdown voltage and excellent carrier transport capability, and can be widely used in high-frequency and high-power power electronics fields such as aerospace, electric vehicles, new energy, and rail transportation.

[0009] In one embodiment, the material of the functional intermediate layer is selected from aluminum nitride (AlN) and aluminum gallium nitride (Al). 1-x Ga x At least one of N (x≥0.2), boron nitride (BN), diamond, and BeO.

[0010] Specifically, the above-mentioned material was selected as the functional intermediate layer, strictly matching two core indicators: thermal conductivity > 1 W·cm -1 ·K -1 The bandgap is >4.0eV, while taking into account lattice compatibility and semiconductor process compatibility, and specifically solves the three major problems of existing technologies: (1) Ultra-wide bandgap: blocks the diffusion of high voltage electric field, avoids premature breakdown of silicon carbide substrate, and improves device withstand voltage; (2) High thermal conductivity: reduces interface thermal resistance, quickly dissipates channel heat, and alleviates gallium oxide self-heating effect; (3) Interface compatibility: buffers lattice mismatch between silicon carbide and gallium oxide, reduces interface defects, and ensures normal carrier transport.

[0011] In one embodiment, the thickness of the functional intermediate layer is 100 nm to 50 μm.

[0012] In one embodiment, the method for preparing the functional intermediate layer includes the following steps: epitaxially growing the functional intermediate layer on the surface of a silicon carbide substrate using any one of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), magnetron sputtering, or pulsed laser deposition (PLD).

[0013] In one embodiment, the gallium oxide channel layer is a doped gallium oxide channel layer with a thickness of 10 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 .

[0014] In a preferred embodiment, the gallium oxide channel layer is a doped β-phase gallium oxide channel layer.

[0015] In one embodiment, the doping element of the doped gallium oxide channel layer is selected from at least one of silicon, tin, and hafnium.

[0016] Specifically, the reasons for choosing a doped gallium oxide channel layer are as follows: (1) Pure intrinsic gallium oxide has an extremely low carrier concentration and extremely poor conductivity, making it impossible to form an effective conductive channel. The device in this application is positioned as a high-current power MOSFET. By doping gallium oxide, free carriers are introduced to improve the channel conduction capability and meet the requirements of high-power and high-current operation. (2) By precisely doping and controlling the carrier concentration at 1×10 17 cm -3 ~5×10 18 cm -3 The range can balance the two core indicators of the device: on-resistance and breakdown voltage. It avoids the voltage drop caused by excessive doping concentration and prevents the on-resistance from being too large and the device loss from being too low, making it suitable for high voltage and high frequency power electronics scenarios. (3) This device adopts a silicon carbide heterostructure and selects silicon, tin, hafnium and other donor elements for doping. The relevant doping process is compatible with existing preparation processes such as epitaxial growth and heterobonding. The process is mature and easy to achieve mass production. At the same time, the doping system has a high degree of matching with the characteristics of gallium oxide material, which can retain the inherent advantage of high breakdown field strength of gallium oxide material to the greatest extent.

[0017] In one embodiment, the gallium oxide channel layer is prepared by epitaxial growth or heterobonding.

[0018] Specifically, the epitaxial growth process is selected from any one of MOCVD, MBE, magnetron sputtering, and PLD.

[0019] Specifically, the heterobonding process includes any of the following methods: a. Use ion knife peeling technology to peel off gallium oxide bulk or thin film, and then transfer it to a silicon carbide template with a functional intermediate layer for bonding; b. First, the gallium oxide bulk is bonded to a silicon carbide template with a functional intermediate layer, and then the gallium oxide bulk is thinned to the thickness required for the channel layer through a thinning process.

[0020] In one embodiment, the thickness of the silicon carbide substrate layer is 300 μm to 600 μm.

[0021] In a preferred embodiment, the thickness of the silicon carbide substrate layer is 500 μm.

[0022] In one embodiment, the surface of the gallium oxide channel layer is further provided with a gate oxide layer, the material of which is selected from at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), and silicon nitride (Si3N4), and the thickness of the gate oxide layer is 5nm~80nm.

[0023] In one embodiment, the silicon carbide-based gallium oxide MOSFET device further includes a source, a drain, and a gate; the source and the drain are disposed on the surface of the gallium oxide channel layer, and the gate is disposed on the surface of the gate oxide layer.

[0024] Specifically, the materials of the source and the drain are both selected from Ti / Au and Ti / Al / Ni / Au.

[0025] Specifically, the material of the gate is selected from Ni / Au.

[0026] The thicknesses of the source, drain, and gate mentioned above are the commonly used thicknesses for transistor devices, and will not be elaborated on here.

[0027] According to one possible implementation of this application, at least the following beneficial effects are achieved: 1. The bandgap of the functional intermediate layer of this application is greater than 4.0eV, which has a strong electric field blocking capability. Under high voltage operation, it can effectively block the high voltage electric field on the channel side from spreading to the silicon carbide substrate, avoid premature breakdown of the silicon carbide substrate, effectively improve the three-terminal breakdown voltage of the device, and adapt to high voltage and high power electronic application scenarios.

[0028] 2. The functional intermediate layer uses high thermal conductivity materials such as AlN and BN, with AlN having a thermal conductivity of up to 2.85 W·cm. -1 ·K -1 The thermal conductivity of BN can reach 2.5 W·cm. -1 ·K -1 Its thermal conductivity is far superior to that of gallium oxide; at the same time, the thickness of the intermediate layer is limited to the range of 100nm~50μm, which takes into account both interface adhesion and vertical thermal conduction channels. It can quickly conduct the heat generated by the operation of the gallium oxide channel to the silicon carbide substrate. Under high power conditions, the channel temperature rise is much lower than that of the comparative devices without an intermediate layer or with an excessively thin intermediate layer, which reduces the mobility decay and on-resistance increase caused by high temperature, and improves the high-temperature operation stability and lifespan of the device.

[0029] 3. The fabrication of the functional intermediate layer in this application can rely on mature processes such as MOCVD, MBE, and magnetron sputtering epitaxy, or it can be fabricated using wafer-level heterobonding. The entire process is compatible with existing wide-bandgap semiconductor mass production processes, without the need for additional special equipment or complex procedures. At the same time, the intermediate layer structure can be matched with gallium oxide channel layers of different thicknesses and doping concentrations, and is compatible with silicon carbide substrates of various specifications, making device design flexible and applicable to a wide range of scenarios.

[0030] 4. The functional intermediate layer can buffer the lattice mismatch between the silicon carbide substrate and the gallium oxide film, reduce dislocation defects and interface state density at the heterojunction, reduce interface charge scattering, ensure stable carrier transport in the channel, and enable the device to maintain excellent conduction characteristics while improving its voltage withstand and heat dissipation performance.

[0031] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0032] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0033] Figure 1 The schematic diagrams of the silicon carbide-based gallium oxide MOSFET devices of Embodiments 1-4 and Comparative Example 1 of this application are shown. Figure 2 A schematic diagram of the structure of the silicon carbide-based gallium oxide MOSFET device of Comparative Example 2 of this application is shown.

[0034] Figure label: 1-Silicon carbide substrate; 2-Functional intermediate layer; 3-Gallium oxide channel layer; 4-Gate oxide layer; 5-Source; 6-Drain; 7-Gate. Detailed Implementation

[0035] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following embodiments, a functional intermediate layer is epitaxially grown on the surface of a silicon carbide substrate using any one of the following methods: MOCVD, MBE, magnetron sputtering, or PLD.

[0037] The gallium oxide channel layer is prepared by epitaxial growth or heterogeneous bonding. The epitaxial growth process is selected from MOCVD, MBE, magnetron sputtering, and PLD. The heterogeneous bonding process can be any of the following: a. using ion knife lift-off technology to lift the gallium oxide bulk or thin film and then transfer it to a silicon carbide template with a functional intermediate layer for bonding; b. first bonding the gallium oxide bulk to the silicon carbide template with a functional intermediate layer, and then thinning the gallium oxide bulk to the thickness required for the channel layer through a thinning process.

[0038] Appropriate preparation methods can be selected as needed, and these preparation methods will not be described again in the following examples.

[0039] Example 1 This embodiment provides a silicon carbide-based gallium oxide MOSFET device, which incorporates a 1μm thick AlN interlayer, as detailed below: Its structural diagram is as follows Figure 1 As shown, it includes a silicon carbide substrate layer 1, a functional intermediate layer 2, a gallium oxide channel layer 3, and a gate oxide layer 4, which are stacked sequentially from bottom to top.

[0040] The thickness of silicon carbide substrate 1 is 500 μm.

[0041] Functional interlayer 2 is an AlN interlayer with a thickness of 1 μm and a bandgap of approximately 6.2 eV. As an interlayer, it effectively prevents breakdown of MOSFET devices at the silicon carbide interface. Simultaneously, its room temperature thermal conductivity is approximately 2.85 W·cm⁻¹. -1 ·K -1 This helps to enhance the heat dissipation capacity of the device and increases its thermal stability.

[0042] Gallium oxide channel layer 3 is a lightly doped β-Ga₂O₃ channel layer with Si as the dopant element. The carrier concentration of this layer is 5 × 10⁻⁶. 17 cm -3 The thickness is 150nm.

[0043] The gate oxide layer 4 is 30nm thick aluminum oxide.

[0044] After the growth of the functional intermediate layer 2 and the gallium oxide channel layer 3 is completed, mesa etching is performed on the gallium oxide channel layer 3 and the functional intermediate layer 2 to achieve device isolation. This mesa etching process can divide the active area of ​​the independent device, isolate the conductive channel between adjacent MOSFETs, avoid the generation of lateral leakage current when the device is working, and ensure the independent and stable operation of each device unit under high voltage conditions.

[0045] MOSFET devices also include source 5, drain 6 and gate 7.

[0046] Source 5 and drain 6 are disposed on the surface of gallium oxide channel layer 3 and located on both sides of gate oxide layer 4. The materials of source 5 and drain 6 are both Ti (50nm) / Au (500nm) bilayer structure.

[0047] Gate 7 is disposed on the surface of gate oxide layer 4, and its material is a Ni (50nm) / Au (100nm) bilayer structure.

[0048] Example 2 This embodiment provides a silicon carbide-based gallium oxide MOSFET device, which incorporates a 10μm thick AlN interlayer.

[0049] Its structure is the same as that of Example 1, see [link / reference]. Figure 1 The difference lies in the fact that the thickness of the functional intermediate layer (AlN intermediate layer) in this embodiment is 10μm. Thicker AlN can more effectively block the spread of electric field.

[0050] Example 3 This embodiment provides a silicon carbide-based gallium oxide MOSFET device, which incorporates a 1μm thick BN interlayer.

[0051] Its structure is the same as that of Example 1, see [link / reference]. Figure 1 The difference lies in that the functional intermediate layer in this embodiment is a BN intermediate layer with a thickness of 1 μm. The bandgap of BN is approximately 5.9 eV, effectively preventing breakdown of the MOSFET device at the silicon carbide interface as an intermediate layer; simultaneously, its room temperature thermal conductivity is approximately 2.5 W·cm⁻¹. -1 ·K -1 This helps to enhance the heat dissipation capacity of the device and increases its thermal stability.

[0052] Example 4 This embodiment provides a silicon carbide-based gallium oxide MOSFET device, which incorporates a 1μm thick diamond interlayer.

[0053] Its structure is the same as that of Example 1, see [link / reference]. Figure 1 The difference lies in that the functional interlayer in this embodiment is a diamond interlayer with a thickness of 1 μm. Diamond has a bandgap of approximately 5.5 eV, effectively preventing breakdown of the MOSFET device at the silicon carbide interface as an interlayer; simultaneously, its room temperature thermal conductivity is greater than 20 W·cm. -1 ·K -1 This helps to enhance the heat dissipation capacity of the device and increases its thermal stability.

[0054] Comparative Example 1 This comparative example provides a silicon carbide-based gallium oxide MOSFET device with a 10nm thick aluminum oxide interlayer.

[0055] Its structure is the same as that of Example 1, see [link / reference]. Figure 1 The difference lies in the fact that the functional interlayer in this comparative example is an alumina interlayer with a thickness of 10 nm. Alumina has a room temperature thermal conductivity of only 0.36 W·cm⁻¹. -1 ·K -1 The left and right sides limit the heat dissipation of the device.

[0056] Comparative Example 2 This comparative example provides a silicon carbide-based gallium oxide MOSFET device, which differs from Example 1 in that no functional intermediate layer is introduced between the silicon carbide substrate layer and the gallium oxide channel layer. Specifically: Its structural diagram is as follows Figure 2 As shown, it includes a silicon carbide substrate layer 1, a gallium oxide channel layer 3, and a gate oxide layer 4, which are stacked sequentially from bottom to top.

[0057] The thickness of silicon carbide substrate 1 is 500 μm.

[0058] Gallium oxide channel layer 3 is a lightly doped β-Ga₂O₃ channel layer with Si as the dopant element. The carrier concentration of this layer is 5 × 10⁻⁶. 17 cm -3 The thickness is 150nm.

[0059] The gate oxide layer 4 is 30nm thick aluminum oxide.

[0060] After the growth of gallium oxide channel layer 3 is completed, mesa etching is performed on gallium oxide channel layer 3 to achieve device isolation. This mesa etching process can divide the active area of ​​independent devices, isolate the conductive channels between adjacent MOSFETs, avoid lateral leakage current during device operation, and ensure independent and stable operation of each device unit under high voltage conditions.

[0061] MOSFET devices also include source 5, drain 6 and gate 7.

[0062] Source 5 and drain 6 are disposed on the surface of gallium oxide channel layer 3 and located on both sides of gate oxide layer 4. The materials of source 5 and drain 6 are both Ti (50nm) / Au (500nm) bilayer structure.

[0063] Gate 7 is disposed on the surface of gate oxide layer 4, and its material is a Ni (50nm) / Au (100nm) bilayer structure.

[0064] Since no functional intermediate layer is introduced, the electric field under high voltage will extend from the gallium oxide channel layer 3 to the silicon carbide substrate layer 1, and the breakdown site of the device may be in the silicon carbide, which limits the breakdown voltage of the device.

[0065] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon carbide-based gallium oxide MOSFET device, characterized in that, The silicon carbide-based gallium oxide MOSFET device includes a silicon carbide substrate layer, a functional intermediate layer, and a gallium oxide channel layer stacked adjacent to each other from bottom to top; the thermal conductivity of the functional intermediate layer is >1 W·cm -1 ·K -1 Bandwidth gap > 4.0 eV; The thickness of the functional intermediate layer is 100nm~50μm.

2. The silicon carbide-based gallium oxide MOSFET device according to claim 1, characterized in that, The material of the functional intermediate layer is selected from AlN and Al. 1-x Ga x At least one of N, BN, diamond, and BeO; wherein x ≥ 0.

2.

3. The silicon carbide-based gallium oxide MOSFET device according to claim 1, characterized in that, The gallium oxide channel layer is a doped gallium oxide channel layer with a thickness of 10 nm to 500 nm and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 .

4. The silicon carbide-based gallium oxide MOSFET device according to claim 3, characterized in that, The gallium oxide channel layer is a doped β-phase gallium oxide channel layer.

5. The silicon carbide-based gallium oxide MOSFET device according to claim 3, characterized in that, The doping element of the doped gallium oxide channel layer is selected from at least one of silicon, tin, and hafnium.

6. The silicon carbide-based gallium oxide MOSFET device according to claim 1, characterized in that, The thickness of the silicon carbide substrate is 300μm~600μm.

7. The silicon carbide-based gallium oxide MOSFET device according to claim 1, characterized in that, The surface of the gallium oxide channel layer is further provided with a gate oxide layer, the material of which is selected from at least one of aluminum oxide, hafnium oxide, and silicon nitride, and the thickness of the gate oxide layer is 5nm~80nm.

8. The silicon carbide-based gallium oxide MOSFET device according to claim 7, characterized in that, The silicon carbide-based gallium oxide MOSFET device further includes a source, a drain, and a gate; the source and the drain are disposed on the surface of the gallium oxide channel layer, and the gate is disposed on the surface of the gate oxide layer.

9. The silicon carbide-based gallium oxide MOSFET device according to claim 8, characterized in that, The materials of the source and the drain are both selected from Ti / Au and Ti / Al / Ni / Au. The material of the gate is selected from Ni / Au.

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