Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a carrier substrate, a semiconductor fin structure, a gate insulating layer, and a gate structure. The semiconductor fin structure is disposed on the carrier substrate and extends along a first direction. A width of the semiconductor fin structure varies along a second direction perpendicular to a top surface of the carrier substrate, and a widest portion of the semiconductor fin structure is located in a middle of the semiconductor fin structure. The gate insulating layer is disposed on the semiconductor fin structure. The gate structure is disposed on the gate insulating layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its manufacturing method. Background Technology

[0002] A fin field-effect transistor (FinFET) is a three-dimensional transistor in which the channel is shaped like a fin, allowing the gate to control the channel from three sides. Compared to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), this structure improves performance by reducing leakage current and increasing switching efficiency, especially in smaller nodes.

[0003] FinFETs are widely used in advanced semiconductor technologies for applications requiring low power consumption and high performance. These applications include smartphones, high-performance computing, artificial intelligence (AI) devices, and Internet of Things (IoT) devices, where finFETs offer better efficiency, faster processing speeds, and longer battery life. Summary of the Invention

[0004] This invention provides a semiconductor structure and its manufacturing method. By adjusting the shape of the semiconductor fin structure, a larger effective channel width can be achieved.

[0005] According to some embodiments disclosed herein, a semiconductor structure includes a carrier substrate, a semiconductor fin structure, a gate insulating layer, and a gate structure. The semiconductor fin structure is disposed above the carrier substrate and extends along a first direction. The width of the semiconductor fin structure varies along a second direction perpendicular to the top surface of the carrier substrate, with the widest portion of the semiconductor fin structure located at its center. The gate insulating layer is disposed on the semiconductor fin structure. The gate structure is disposed on the gate insulating layer.

[0006] In some embodiments, a portion of the gate insulating layer is located along a second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

[0007] In some embodiments, a portion of the gate structure is located along a second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

[0008] In some embodiments, the semiconductor fin structure has a curved surface, and a gate insulating layer is disposed on the curved surface of the semiconductor fin structure.

[0009] In some embodiments, a dielectric layer is disposed between a carrier substrate and a semiconductor fin structure. The semiconductor fin structure is in contact with the dielectric layer, and the width of the semiconductor fin structure increases and then decreases along a second direction as the semiconductor fin structure moves away from the dielectric layer.

[0010] In some embodiments, a dielectric layer is disposed between a carrier substrate and a semiconductor fin structure. A portion of a gate insulating layer is located along a second direction between the widest portion of the semiconductor fin structure and the dielectric layer.

[0011] According to some embodiments of this disclosure, a method for manufacturing a semiconductor structure includes the following steps: forming a semiconductor layer over a carrier substrate; etching the semiconductor layer to form a semiconductor strip extending over the carrier substrate along a first direction, wherein the semiconductor strip has sidewalls perpendicular to the top surface of the carrier substrate; heating the semiconductor strip in a hydrogen environment to transform the shape of the semiconductor strip into a semiconductor fin structure, wherein the width of the semiconductor fin structure varies along a second direction perpendicular to the top surface of the carrier substrate, and the widest portion is located in the middle of the semiconductor fin structure; forming a gate insulating layer on the semiconductor fin structure; and forming a gate structure on the gate insulating layer.

[0012] In some embodiments, a portion of the gate insulating layer is located along a second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

[0013] In some embodiments, the manufacturing method further includes the following steps: forming a dielectric layer on a carrier substrate; forming a semiconductor layer on the dielectric layer; forming a first mask layer on the semiconductor layer; forming a first photoresist layer on the first mask layer; etching the first mask layer using the first photoresist layer as a mask to form a patterned first mask layer extending along a first direction; etching the semiconductor layer using the patterned first mask layer as a mask to form a semiconductor strip; forming a conductive material layer above a gate insulating layer; forming a second mask layer above the conductive material layer; forming a second photoresist layer on the second mask layer; etching the second mask layer using the second photoresist layer as a mask to form a patterned second mask layer extending along a third direction; and etching the conductive material layer using the patterned second mask layer as a mask to form a gate structure.

[0014] In some embodiments, spacers are formed on the sidewalls of the gate structure. Attached Figure Description

[0015] Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A A top view schematic diagram of various stages in a semiconductor structure manufacturing method according to some embodiments of this disclosure is shown;

[0016] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B They are along Figure 1A , 2A A cross-sectional view of line A-A' in 3A, 4A, 5A, 6A, 7A and 8A;

[0017] Figure 9 yes Figure 8A and Figure 8B A three-dimensional schematic diagram of the semiconductor structure is shown;

[0018] Figure 10 This invention discloses a schematic cross-sectional view of a semiconductor structure according to another embodiment. Detailed Implementation

[0019] The embodiments are described in detail below with reference to the accompanying drawings, but these embodiments are not intended to limit the scope of the invention. Furthermore, the illustrations are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be designated by the same reference numerals in the following description.

[0020] In the text, terms such as “contains,” “including,” “containing,” and “having” are all open-ended terms, meaning “including but not limited to.”

[0021] When terms such as "first" and "second" are used to describe elements, they are used only to distinguish elements and do not limit the order or importance of the devices. Therefore, in some cases, a first element may also be referred to as a second element, and a second element may also be referred to as a first element, which does not exceed the scope of this invention.

[0022] Furthermore, directional terms used in this document, such as “on,” “above,” “below,” and “under,” are used only to refer to the directions shown in the illustrations and are not intended to limit the invention.

[0023] Furthermore, the use of "from one value to another" to indicate a range is a general way of representing a range to avoid listing all values ​​within that range in the specification. Therefore, a statement of a particular numerical range includes any value within that range, as well as the smaller range of values ​​defined by any value within that range.

[0024] Reference Figure 1A and Figure 1BA semiconductor layer 120 is formed on a carrier substrate 100. In some embodiments, the carrier substrate 100 may include a wafer, glass, or the like. For example, the wafer may be composed of elemental semiconductors such as silicon or germanium, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, or alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0025] In some embodiments, the semiconductor layer 120 includes silicon, and the method of forming the semiconductor layer 120 includes an epitaxial growth process or other processes.

[0026] In this embodiment, a dielectric layer 110 is first formed on the carrier substrate 100 before forming the semiconductor layer 120, and then the semiconductor layer 120 is formed on the dielectric layer 110. In this embodiment, the semiconductor layer 120, the dielectric layer 110, and the carrier substrate 100 can be collectively referred to as a silicon-on-insulator (SOI) substrate. In some embodiments, the dielectric layer 110 includes an oxide (such as silicon dioxide) or other suitable insulating material. In some embodiments, the dielectric layer 110 may also be referred to as a buried oxide (BOX) layer.

[0027] A first mask layer 200 is formed on the semiconductor layer 120. The first mask layer 200 may have a single-layer structure or a multi-layer structure. In some cases, the first mask layer 200 may be referred to as a hard mask layer. In some embodiments, the first mask layer 200 includes an anti-reflection coating (ARC).

[0028] A first photoresist layer 310 is formed on the first mask layer 200. In this embodiment, the first photoresist layer 310 undergoes an exposure process and a development process to form a strip-shaped structure extending along a first direction D1. The first direction D1 is parallel to the top surface 100t of the carrier substrate 100.

[0029] Reference Figure 2A and Figure 2B The first photoresist layer 310 is used as a mask to etch the first mask layer 200, forming a patterned first mask layer 201 extending along the first direction D1. Then, the patterned first mask layer 201 is used as a mask to etch the semiconductor layer 120, forming a semiconductor strip 121 extending along the first direction D1 above the carrier substrate 100. The semiconductor strip 121 has sidewalls 121s that are substantially perpendicular to the top surface 100t of the carrier substrate 100. In this embodiment, the sidewalls 121s of the semiconductor strip 121 are substantially parallel to the second direction D2, which is perpendicular to the top surface 100t.

[0030] Reference Figure 3A and Figure 3B The semiconductor strip 121 is heated in a hydrogen environment, causing its shape to transform into a semiconductor fin structure 122. The sidewalls 121s are reshaped into curved surfaces 122s, transforming the originally rectangular semiconductor strip 121 into an approximately cylindrical semiconductor fin structure 122. In this embodiment, the width of the semiconductor fin structure 122 varies along the second direction D2, with the widest portion WP located in the middle of the semiconductor fin structure 122. In this embodiment, the semiconductor fin structure 122 is in contact with the dielectric layer 110, and the width of the semiconductor fin structure 122 along the second direction D2 first increases and then decreases as the semiconductor fin structure 122 moves away from the dielectric layer 110.

[0031] In some embodiments, the semiconductor strip 121 is annealed in a hydrogen (H2) environment at a temperature of 750 to 900 degrees Celsius and a pressure of 550 to 750 Torr for 4.5 to 8 minutes.

[0032] Reference Figure 4A and Figure 4B A gate insulating layer 130 is formed on the curved surface 122s of the semiconductor fin structure 122. For example, methods for forming the gate insulating layer 130 include in-situ steam generated (ISSG) oxide, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable techniques. In this embodiment, silicon dioxide is formed on the curved surface 122s of the semiconductor fin structure 122 using ISSG; however, this disclosure is not limited thereto. In other embodiments, a high-k dielectric material is deposited on the curved surface 122s of the semiconductor fin structure 122. Examples of high-k dielectric materials include materials with a dielectric constant higher than silicon dioxide (SiO2) or greater than about 3.9. In some embodiments, the gate insulating layer 130 may include metal oxides, such as hafnium oxide (HfO2), hafnium silicate (HSO), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), or combinations thereof.

[0033] In this embodiment, the gate insulating layer 130 on one semiconductor fin structure 122 is separate from the gate insulating layer 130 on another semiconductor fin structure 122. However, this disclosure is not limited thereto. In other embodiments, the gate insulating layers 130 on adjacent semiconductor fin structures 122 may be connected.

[0034] In this embodiment, since the widest portion WP of the semiconductor fin structure 122 is located in the middle of the semiconductor fin structure 122, a portion of the gate insulating layer 130 is located along the second direction D2 between the widest portion WP of the semiconductor fin structure 122 and the carrier substrate 100 (or dielectric layer 110).

[0035] Reference Figure 5A and Figure 5B A first conductive material layer 140 and a second conductive material layer 150 are formed over the gate insulating layer 130 and the dielectric layer 110. In some embodiments, the first conductive material layer 140 comprises polysilicon and the second conductive material layer 150 comprises metal. However, the first conductive material layer 140 and the second conductive material layer 150 may also be made of other conductive materials.

[0036] Reference Figure 6A and Figure 6B A second mask layer 160 is formed over the first conductive material layer 140 and the second conductive material layer 150. In some embodiments, the second mask layer 160 comprises a nitride material (e.g., silicon nitride), but this disclosure is not limited thereto. The second mask layer 160 may be made of other suitable insulating materials.

[0037] A second photoresist layer 320 is formed on the second mask layer 160. In this embodiment, the second photoresist layer 320 undergoes an exposure process and a development process to form a strip-shaped structure extending along a third direction D3. The third direction D3 is parallel to the top surface 100t of the carrier substrate 100. In some embodiments, the third direction D3 is perpendicular to the first direction D1.

[0038] Reference Figure 7A and Figure 7B The second photoresist layer 320 is used as a mask to etch the second mask layer 160, forming a patterned second mask layer 162 extending along the third direction D3. Then, the patterned second mask layer 162 is used as a mask to etch the first conductive material layer 140 and the second conductive material layer 150, forming a gate structure G including the first layer 142 and the second layer 152. The first layer 142 and the second layer 152 are formed by etching the first conductive material layer 140 and the second conductive material layer 150, respectively.

[0039] In some embodiments, a portion of the gate structure G is located along the second direction D2 between the widest portion WP of the semiconductor fin structure 122 and the carrier substrate 100 (or dielectric layer 110). In some embodiments, the portion of the gate structure G is located along the second direction D2 between the gate insulating layer 130 and the carrier substrate 100 (or dielectric layer 110). By adjusting the shape of the semiconductor fin structure 122, the effective channel width of the semiconductor fin structure 122 can be increased, thereby reducing the risk of leakage current in the semiconductor device and enabling the gate structure G to better control the current in the semiconductor fin structure 122.

[0040] In this embodiment, the gate structure G defines the source region, drain region, and channel region of the semiconductor fin structure 122. The channel region overlaps with the gate structure G, while the source and drain regions are located on either side of the channel region and do not overlap with the gate structure G. After the gate structure G is formed, a doping process, such as a light doping process, is performed on the source and drain regions.

[0041] Next, refer to Figure 8A , Figure 8B and Figure 9 Spacers 170 are formed on the sidewalls of the gate structure G. After the spacers 170 are formed, a heavy doping process is performed on the source and drain regions.

[0042] In some embodiments, after performing a heavy doping process on the source and drain regions, an interlayer dielectric layer (not shown in the figure) is formed over the semiconductor structure 10 (i.e., the transistor). Then, source, drain, and gate contact structures (not shown in the figure) are formed in the interlayer dielectric layer, and the source contact, drain contact, and gate contact are respectively connected to the source region, drain region, and gate structure G of the semiconductor structure 10.

[0043] Figure 10 A schematic cross-sectional view of a semiconductor structure 10a according to another embodiment of this disclosure is shown. It should be noted that... Figure 10 In the provided embodiments, the following are used Figures 1A to 9 The component reference numerals and partial contents provided in the embodiments use the same or similar reference numerals to represent the same or similar components, and descriptions of identical technical content are omitted. For the omitted descriptions, please refer to the foregoing embodiments, and they will not be repeated here.

[0044] Reference Figure 10 In this embodiment, the gate structure Ga is made entirely of metal, and the gate insulating layer 130a includes a high-k dielectric material that covers the semiconductor fin structure 122 and the dielectric layer 110.

[0045] Based on the above, through a heating process in a hydrogen environment, the semiconductor fin structure 122 exhibits a shape that is wider in the middle and narrower at the top and bottom. This structure effectively increases the effective channel width of the semiconductor fin structure 122, thereby helping to mitigate leakage current problems.

[0046] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

Claims

1. A semiconductor structure, comprising: Carrier substrate; A semiconductor fin structure is disposed above the carrier substrate and extends along a first direction, wherein the width of the semiconductor fin structure varies along a second direction perpendicular to the top surface of the carrier substrate, and the widest portion of the semiconductor fin structure is located in the middle of the semiconductor fin structure. A gate insulating layer is disposed on the semiconductor fin structure; as well as A gate structure is disposed on the gate insulating layer.

2. The semiconductor structure of claim 1, wherein a portion of the gate insulating layer is located along the second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

3. The semiconductor structure of claim 1, wherein a portion of the gate structure is located along the second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

4. The semiconductor structure according to claim 1, wherein the semiconductor fin structure has a curved surface, and the gate insulating layer is disposed on the curved surface of the semiconductor fin structure.

5. The semiconductor structure according to claim 1, further comprising: A dielectric layer is disposed between the carrier substrate and the semiconductor fin structure, wherein the semiconductor fin structure is in contact with the dielectric layer, and the width of the semiconductor fin structure along the second direction first increases and then decreases as the semiconductor fin structure moves away from the dielectric layer.

6. The semiconductor structure according to claim 1, further comprising: A dielectric layer is disposed between the carrier substrate and the semiconductor fin structure, wherein a portion of the gate insulating layer is located along the second direction between the widest portion of the semiconductor fin structure and the dielectric layer.

7. A method for manufacturing a semiconductor structure, comprising: A semiconductor layer is formed above the carrier substrate; The semiconductor layer is etched to form a semiconductor strip extending in a first direction over the carrier substrate, wherein the semiconductor strip has a sidewall perpendicular to the top surface of the carrier substrate; Heating the semiconductor strip in a hydrogen atmosphere causes the shape of the semiconductor strip to transform into a semiconductor fin structure, wherein the width of the semiconductor fin structure varies along a second direction perpendicular to the top surface of the carrier substrate, and the widest part of the semiconductor fin structure is located in the middle of the semiconductor fin structure. A gate insulating layer is formed on the semiconductor fin structure; as well as A gate structure is formed on the gate insulating layer.

8. The manufacturing method of claim 7, wherein a portion of the gate insulating layer is located along the second direction between the widest portion of the semiconductor fin structure and the carrier substrate.

9. The manufacturing method according to claim 7, further comprising: A dielectric layer is formed on the carrier substrate; The semiconductor layer is formed on the dielectric layer; A first mask layer is formed on the semiconductor layer; A first photoresist layer is formed on the first mask layer; The first photoresist layer is used as a mask to etch the first mask layer to form a patterned first mask layer extending along the first direction; The semiconductor layer is etched using the patterned first mask layer as a mask to form the semiconductor strip; A conductive material layer is formed above the gate insulating layer; A second mask layer is formed above the conductive material layer; A second photoresist layer is formed on the second mask layer; The second photoresist layer is used as a mask to etch the second mask layer to form a patterned second mask layer extending in a third direction; as well as The patterned second mask layer is used as a mask to etch the conductive material layer to form the gate structure.

10. The manufacturing method according to claim 9, further comprising: Spacers are formed on the sidewalls of the gate structure.

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