Trench super junction power device, manufacturing method and chip

Abstract

This application discloses a trench-gate superjunction power device, its manufacturing method, and a chip, belonging to the field of power semiconductor technology. The trench-gate superjunction power device includes: a substrate, an N-type drift region, a P-type drift region, a P-type body region, an N+ source, a P+ source, a dielectric layer, N-type polysilicon, a source metal, and a drain metal. The P-type and N-type drift regions form a superjunction structure, significantly reducing on-resistance at the same breakdown voltage. The P+ source provides a low-resistance contact to the P-type body region, while enhancing the hole extraction capability of the P-type body region and improving the device's avalanche tolerance. By partially separating the P-type drift region from the P-type body region, the P-pillars are made non-contact, and a source-controlled MOS channel is constructed by combining a second trench with the source metal. During reverse conduction, this channel preferentially conducts to suppress hole injection, inhibiting hole injection from the P-type body region into the N-type drift region, thereby significantly reducing reverse recovery charge and preventing a decrease in avalanche tolerance.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology, specifically relating to a trench gate superjunction power device, its manufacturing method, and a chip. Background Technology

[0002] Superjunction MOSFETs are widely used in medium- and high-voltage power conversion. However, the PN junction contact area of ​​a superjunction structure is much larger than that of a conventional VDMOS. When the body diode is reverse-biased, the P-type body region injects a large number of holes into the N-type drift region, and the drift region stores excessive excess carriers. During the reverse recovery phase, these stored charges need to be extracted, which significantly increases the reverse recovery charge and reverse recovery loss, thereby deteriorating the reverse recovery characteristics of the device.

[0003] To improve the reverse recovery characteristics of superjunction MOSFETs, related technologies attempt to suppress hole injection. However, this approach increases the parasitic resistance of the P-type body region. When avalanche breakdown occurs, the voltage drop generated by the avalanche current flowing through this parasitic resistance can easily trigger the turn-on of parasitic bipolar transistors, leading to amplification of the avalanche current, a sharp increase in leakage current, and ultimately a significant reduction in the device's avalanche robustness. Therefore, how to effectively improve the reverse recovery characteristics of superjunction MOSFETs without sacrificing their avalanche robustness has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] The purpose of this application is to provide a trench gate superjunction power device, manufacturing method, and chip that can improve the reverse recovery characteristics of the trench gate superjunction power device while avoiding the decrease in avalanche tolerance caused by the introduction of additional structures.

[0005] In a first aspect, embodiments of this application provide a trench-gate superjunction power device, comprising: Substrate; An N-type drift region is located on a portion of the upper surface of the substrate; the upper surface of the N-type drift region has a first groove, and the side has a first cutout area and a second cutout area. The first cutout area is adjacent to a portion of the upper surface of the substrate and not adjacent to the first groove; the second cutout area is located above the first cutout area, not adjacent to the first cutout area, and in contact with the first groove. The P-type drift region is located in the first and second hollowed-out regions of the N-type drift region; The P-shaped body region is located within the N-shaped drift regions on both sides of the first groove, is flush with the upper surface of the N-shaped drift region, contacts the P-shaped drift region of the second hollow region, and does not contact the P-shaped drift region of the first hollow region. The N+ source is located within the P-type body region on both sides of the first groove, flush with the upper surface of the P-type body region, and adjacent to the first groove. The P+ source is located within the P-type body region on both sides of the first groove, flush with the upper surface of the P-type body region, and in contact with the N+ source. The dielectric layer is located in a portion of the first groove excluding the second groove and on the upper surface of the portion of the first groove, as well as on the upper surface of the N+ source near the first groove; the second groove is the region within the first groove near the P-type drift region; N-type polycrystalline silicon is located within the first groove and is enclosed by the dielectric layer; The source metal is located within the second groove, on the upper surface of the dielectric layer, on a portion of the upper surface of the N+ source, and on the upper surface of the P+ source. The drain metal is located below the substrate.

[0006] Optionally, the thickness of the first groove is greater than the thickness of the P-shaped body region.

[0007] Optionally, the doping concentration of the substrate is greater than the doping concentration of the N-type drift region.

[0008] Optionally, the doping concentration and width of the N-type drift region satisfy the charge balance with the doping concentration and width of the P-type drift region.

[0009] Secondly, embodiments of this application provide a method for manufacturing a trench-gate superjunction power device, used to manufacture the aforementioned trench-gate superjunction power device, the method comprising: Provide substrate; An N-type drift region is formed on a portion of the upper surface of the substrate; the sides of the N-type drift region are etched to form a first hollow region and a second hollow region; the first hollow region is adjacent to a portion of the upper surface of the substrate; the second hollow region is located above the first hollow region, is not adjacent to the first hollow region, and is in contact with the first groove; A P-type drift region is formed in the first and second hollowed-out regions of the N-type drift region; P-type ions are injected into a region within the N-type drift region that is flush with the upper surface of the N-type drift region and does not contact the P-type drift region of the first hollow region to form a P-type body region; a portion of the lower surface of the P-type body region contacts the P-type drift region of the second hollow region. N-type ions are implanted in the region of the P-type body region that is flush with the upper surface of the P-type body region to form an N+ source. P-type ions are implanted in the region of the P-type body region that is flush with the upper surface of the P-type body region to form a P+ source; the P+ source is in contact with the N+ source. The N+ source, the P-type body region, and the N-type drift region are etched to form a first groove; the first groove is not adjacent to the first hollow area; a dielectric layer is formed on a portion of the first groove excluding the second groove, on the upper surface of the portion of the first groove, and on the upper surface of the N+ source near the first groove; the second groove is the region within the first groove near the P-type drift region. An N-type polycrystalline silicon is formed within the first groove; the N-type polycrystalline silicon is encapsulated by the dielectric layer; Metal is deposited in the second groove, on the upper surface of the dielectric layer, on a portion of the upper surface of the N+ source, and on the upper surface of the P+ source to form source metal; Metal is deposited beneath the substrate to form a drain metal.

[0010] Optionally, forming a dielectric layer on a portion of the first groove excluding the second groove, on the upper surface of the portion of the first groove, and on the upper surface of the N+ source near the first groove, includes: The dielectric layer is formed on the sidewalls and bottom of the first groove; The N-type polycrystalline silicon is formed on the dielectric layer at the bottom of the first groove; The region of the N-type polysilicon near the P-type drift region is etched. The dielectric layer is formed in the area excluding the N-type polysilicon within the first groove, on the upper surface of the N-type polysilicon, on the upper surface of the N+ source, and on the upper surface of the P+ source. The dielectric layer of the first groove is etched to form the second groove; the side of the second groove does not contact the side of the N-type polysilicon; the side of the second groove does not coincide with the side of the first groove, and the bottom does not coincide with the bottom of the first groove. The dielectric layer on the upper surface of the N+ source near the P+ source and the dielectric layer on the upper surface of the P+ source are etched.

[0011] Optionally, the doping concentration of the substrate is greater than the doping concentration of the N-type drift region.

[0012] Optionally, the doping concentration and width of the N-type drift region satisfy the charge balance with the doping concentration and width of the P-type drift region.

[0013] Thirdly, embodiments of this application provide a chip including the aforementioned trench gate superjunction power device.

[0014] The embodiments of this application have the following advantages: The trench gate superjunction power device of this application includes: a substrate, an N-type drift region, a P-type drift region, a P-type body region, an N+ source, a P+ source, a dielectric layer, N-type polysilicon, a source metal, and a drain metal.

[0015] The N-type and P-type drift regions are located on the upper surface of the substrate. The P-type drift region (P-pillar) and N-type drift region (N-pillar) forming the superjunction constitute a superjunction structure, significantly reducing on-resistance at the same breakdown voltage. The P-type drift region is vertically divided into upper and lower segments: the lower segment is located in the first cutout region, maintaining a floating state; the upper segment is located in the second cutout region, contacting the P-type body region. The upper P-type drift region reduces gate-drain capacitance and improves device switching speed; the lower P-type drift region continues to cut off the hole injection path, improving reverse recovery characteristics.

[0016] The P-type body region is located on the upper surface of the N-type drift region and serves as a channel region. When the gate is forward biased, it forms a conductive channel in reverse. The P-type body region does not contact the P-type drift region, thus achieving P-pillar floating and cutting off the path for direct hole injection from the P-type body region to the P-pillar. This significantly reduces the injection of holes from the P-pillar to the N-pillar during reverse conduction, thereby reducing reverse recovery charge.

[0017] The N+ source and P+ source are located on the upper surface of the P-type body region. The N+ source is adjacent to the first groove, providing a low-ohmic contact for the source metal and ensuring that electrons can flow smoothly from the N+ source into the inversion channel when the channel is turned on. The P+ source provides a low-resistance contact for the P-type body region and enhances the hole extraction capability of the P-type body region, improving the avalanche tolerance of the device.

[0018] The N-type polysilicon is located in the first groove; the N-type polysilicon, as the gate material of the trench gate, can control the inversion of the P-type body region when a voltage is applied; the N-type polysilicon is wrapped by a dielectric layer, which ensures that the gate is electrically insulated from the surrounding semiconductor.

[0019] The source metal is located in the second groove and is in ohmic contact with both the N+ source and the P+ source. The second groove is the region in the first groove that is close to the P-type drift region. The source metal contacts the N-type drift region and the P-type body region through the second groove. During reverse conduction, the MOS channel controlled by the source metal (composed of the N+ source, P-type body region, N-type drift region, dielectric layer, and metal source) conducts before the body diode, suppressing the injection of holes from the P-type body region into the N-type drift region and further reducing the reverse recovery charge.

[0020] The drain metal is located below the substrate, forming a drain ohmic contact to provide a path for current to flow out.

[0021] In this embodiment, the P-pillar is made floating by non-contact between the P-type drift region and the P-type body region, and a source-controlled MOS channel is constructed by combining the second groove with the source metal. During reverse conduction, it is preferentially turned on to suppress hole injection, thereby significantly reducing reverse recovery charge and avoiding a decrease in avalanche tolerance. Attached Figure Description

[0022] Figure 1 This is a structural block diagram of a trench gate superjunction power device according to an embodiment of this application; Figure 2 This is a structural block diagram of another trench gate superjunction power device according to an embodiment of this application; Figure 3 This is a comparison diagram of the reverse recovery characteristics of an embodiment of this application; Figure 4 This is a flowchart illustrating the steps of a method for manufacturing a trench gate superjunction power device according to an embodiment of this application. Figure 5 This is a process structure diagram of the manufacturing method of the substrate, N-type drift region and P-type drift region according to an embodiment of this application; Figure 6 This is a process structure diagram of the manufacturing method of the P-type body region according to an embodiment of this application; Figure 7 This is a process structure diagram of the manufacturing method of the N+ source and P+ source according to an embodiment of this application; Figure 8 This is a process structure diagram of the method for manufacturing the dielectric layer according to an embodiment of this application; Figure 9 This is a process structure diagram of a method for manufacturing N-type polysilicon according to an embodiment of this application; Figure 10 This is a process structure diagram of another method for manufacturing a dielectric layer and N-type polysilicon according to an embodiment of this application.

[0023] Explanation of reference numerals in the attached figures: Substrate 1, N-type drift region 2, P-type drift region 3, P-type body region 4, N+ source 5, P+ source 6, dielectric layer 7, N-type polysilicon 8, source metal 9, drain metal 10. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0026] The trench gate superjunction power device provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0027] Reference Figure 1 This diagram illustrates a structural block diagram of a trench-gate superjunction power device according to an embodiment of this application. The trench-gate superjunction power device includes: Substrate 1; The N-type drift region 2 is located on a portion of the upper surface of the substrate 1. The upper surface of the N-type drift region 2 has a first groove, and the side has a first hollow area and a second hollow area. The first hollow area is adjacent to a portion of the upper surface of the substrate 1 and is not adjacent to the first groove. The second hollow area is located above the first hollow area, is not adjacent to the first hollow area, and is in contact with the first groove. The P-type drift region 3 is located in the first and second hollowed-out regions of the N-type drift region 2; The P-type body region 4 is located in the N-type drift region 2 on both sides of the first groove, flush with the upper surface of the N-type drift region 2, in contact with the P-type drift region 3 of the second hollow region, and not in contact with the P-type drift region 3 of the first hollow region. The N+ source 5 is located in the P-type body region 4 on both sides of the first groove, flush with the upper surface of the P-type body region 4, and adjacent to the first groove. The P+ source 6 is located within the P-type body region 4 on both sides of the first groove, flush with the upper surface of the P-type body region 4, and in contact with the N+ source 5. The dielectric layer 7 is located in a portion of the first groove excluding the second groove and on the upper surface of the portion of the first groove, as well as on the upper surface of the N+ source 5 near the first groove; the second groove is the region within the first groove near the P-type drift region 3; N-type polycrystalline silicon 8 is located in the first groove and is wrapped by the dielectric layer 7; Source metal 9 is located in the second groove, on the upper surface of the dielectric layer 7, on a portion of the upper surface of the N+ source 5, and on the upper surface of the P+ source 6; Drain metal 10 is located below the substrate 1.

[0028] In this embodiment, the substrate 1 can be made of heavily doped N-type (N+) single-crystal silicon material, with a doping concentration much higher than that of the subsequently formed N-type drift region 2, in order to reduce the drain series resistance of the device. The lower surface of the substrate 1 forms an ohmic contact with the drain metal 10, serving as the main channel for current to flow out from the drain; its upper surface is used for epitaxial growth of the N-type drift region 2.

[0029] The N-type drift region 2 is located on a portion of the upper surface of the substrate 1 and serves as the longitudinal current path when the device is turned on. The doping concentration and thickness of the N-type drift region 2 are designed according to the superjunction charge balance principle, and together with the subsequently formed P-type drift region 3, they constitute a superjunction structure. The upper surface of the N-type drift region 2 has a downwardly extending first groove, which is used to accommodate the trench gate structure. The side of the N-type drift region 2 has a first cutout region and a second cutout region, which extend from the side of the N-type drift region 2 into its interior to fill the P-type drift region 3. The first cutout region is adjacent to a portion of the upper surface of the substrate 1 to ensure that the bottom of the P-type drift region 3 can contact the area near the upper surface of the substrate 1. At the same time, the first cutout region is not adjacent to the first groove, that is, they are horizontally offset from each other, thereby avoiding direct coupling between the gate structure and the P-type drift region 3 and providing space for isolation between the subsequent P-type body region 4 and the P-type drift region 3. The second cutout area is located above the first cutout area. The two are longitudinally separated and not adjacent, i.e., they are separated by the body portion of the N-type drift region 2. The second cutout area is in direct contact with the first groove. The purpose of this second cutout area is to provide an additional space for filling the P-type drift region on the upper part of the device, and to allow the upper P-type drift region to make contact with the P-type body region 4 on the sidewall of the first groove, thereby creating conditions for the local grounding of the P-type drift region.

[0030] P-type drift region 3 fills the first and second hollowed-out regions of N-type drift region 2. P-type drift region 3 and N-type drift region 2 form the P-pillar and N-pillar of a superjunction. By adjusting the width and doping concentration of P-type drift region 3 and N-type drift region 2 to achieve charge balance, when the device is turned off, P-type drift region 3 and N-type drift region 2 deplete each other, generating a transverse electric field. This transforms the longitudinal electric field distribution from a one-dimensional distribution in a conventional MOSFET to a two-dimensional distribution, significantly improving the device's breakdown voltage. Simultaneously, due to the charge compensation effect of the superjunction, the doping concentration of N-type drift region 2 can be increased without reducing the breakdown voltage, thereby reducing the on-resistance. P-type drift region 3 can be vertically divided into upper and lower segments: the lower segment is located in the first hollowed-out region and remains floating; the upper segment is located in the second hollowed-out region and is used to contact the P-type body region 4. The upper and lower segments of the P-type drift region are separated by the body of N-type drift region 2 and are electrically independent. This segmented structure can be achieved through multiple epitaxial or deep trench etching filling processes.

[0031] The P-type body region 4 is located inside the N-type drift regions 2 on both sides of the first groove, and its top is flush with the upper surface of the N-type drift region 2. The doping concentration of the P-type body region 4 can be 1×10¹. 7 ~4×10¹ 7 cm - The thickness can be 1–1.5 μm. The P-type body region 4 serves as the channel region of the device. When a positive voltage is applied to the gate, its sidewall near the first groove inverts to form a conductive channel, allowing electrons to flow from the N+ source 5 through the channel to the N-type drift region 2. Part of the lower surface of the P-type body region 4 directly contacts the P-type drift region 3 in the second hollowed-out area. This contact achieves an electrical connection between the upper P-type drift region 3 and the P-type body region 4, thereby grounding the upper P-type drift region 3 through the P+ source 6 and the source metal 9. The P-type body region 4 does not contact the P-type drift region 3 in the first hollowed-out area; the two are separated longitudinally by a portion of the N-type drift region 2, thus achieving electrical levitation of the P-type drift region 3. The floating structure cuts off the path for direct hole injection from the P-type body region 4 to the P-type drift region 3. When the body diode is reverse-biased, the P-type drift region 3 cannot obtain a large number of holes from the P-type body region 4, reducing the number of holes injected from the P-type drift region 3 to the N-type drift region 2. This significantly reduces the number of minority carriers that need to be extracted during the reverse recovery process and improves the reverse recovery characteristics of the device.

[0032] With the above structure, this application can divide the P-type drift region 3 of the superjunction into two parts: an upper section (grounded P-pillar) in contact with the P-type body region 4 and a completely floating lower section (floating P-pillar). The grounded P-pillar helps reduce gate-drain capacitance and improve the switching speed of the device; the floating P-pillar continues to cut off the hole injection path and improves reverse recovery characteristics. By adjusting the longitudinal length ratio of the first and second cutout regions through the process, the length ratio of the grounded P-pillar to the floating P-pillar can be dynamically adjusted, thereby achieving a flexible trade-off optimization between reverse recovery charge, switching speed, and switching losses.

[0033] The N+ source 5 is located within the P-type body regions 4 on both sides of the first groove. Its top is flush with the upper surface of the P-type body regions 4 and adjacent to the sidewall of the first groove. The N+ source 5 can be a highly concentrated N-type doped region with a doping concentration of 1×10¹. 9 ~5×10¹ 9 cm - ³, the injection depth can be 0.2–0.5 μm. The N+ source 5 serves as the source region of the MOSFET, providing electrons to the channel when the device is turned on; at the same time, it forms a low-resistance ohmic contact with the source metal 9, reducing the source series resistance.

[0034] The P+ source 6 is also located within the P-type body region 4 on both sides of the first groove. Its top is flush with the upper surface of the P-type body region 4 and is in contact with the N+ source 5. The doping concentration of the P+ source 6 can be 1×10¹. 9 ~5×10¹ 9 cm - ³. The P+ source 6 provides a low-resistance body contact for the P-type body region 4. When the source metal 9 covers the P+ source 6, it effectively stabilizes the potential of the P-type body region 4, preventing parasitic NPN transistors from causing false turn-on and increasing the avalanche tolerance of the device. In addition, during reverse recovery, the P+ source 6 helps to quickly extract holes stored in the P-type body region 4.

[0035] The dielectric layer 7 is located in a portion of the first groove, excluding the second groove, and on the upper surface of that portion. It also covers a portion of the upper surface of the N+ source 5 near the first groove. The second groove refers to a specific area within the first groove near the P-type drift region 3, where a dielectric layer is also deposited. However, the dielectric layer in the second groove is thinner than that in the first groove, providing an opening for the source metal 9 to directly contact the N-type drift region 2 or the P-type body region 4. The dielectric layer 7 can be silicon dioxide produced through high-temperature thermal oxidation, with a thickness of 80–120 nm. The dielectric layer 7 located on the sidewalls and bottom of the first groove serves as a gate oxide layer, isolating the N-type polysilicon 8 from the semiconductor region. The dielectric layer 7 on the upper surface of the N+ source 5 is used to isolate the source metal 9 from the gate structure, preventing short circuits.

[0036] The N-type polysilicon 8 fills the first groove and is completely encapsulated by the dielectric layer 7, without directly contacting any semiconductor region. The N-type polysilicon 8 serves as the gate of the device, and when a gate voltage is applied, it can couple to the underlying P-type body region 4 through the dielectric layer 7 to form a conductive channel. Using N-type polysilicon can reduce gate resistance and improve switching speed.

[0037] The source metal 9 is located within the second groove, on the upper surface of the dielectric layer 7, on part of the upper surface of the N+ source 5, and on the upper surface of the P+ source 6. Specifically, the source-controlled MOS structure formed by "source metal 9, dielectric layer 7, N-type drift region 2, P-type body region 4, and N+ source 5" can be made to conduct before the body diode in reverse conduction by adjusting the thickness of the dielectric layer. When the device is in reverse conduction, the threshold voltage of the source-controlled MOS channel is designed to be lower than the turn-on voltage of the body diode between the P-type body region 4 and the N-type drift region 2, so the source-controlled MOS channel conducts before the body diode. After the source-controlled MOS channel conducts, it suppresses the injection of holes from the P-type body region 4 into the N-type drift region 2, thereby further reducing minority carrier storage in the drift region and reducing reverse recovery charge.

[0038] Drain metal 10 is located below substrate 1 and forms an ohmic contact with the lower surface of substrate 1. Drain metal 10 serves as the drain lead of the device. The material of drain metal 10 can be a titanium / nickel / silver (Ti / Ni / Ag) stack with a thickness of 1–5 μm.

[0039] Through the above structure, this application, based on a conventional trench-gate superjunction MOSFET, achieves two key improvements. First, by preventing the P-type body region 4 from contacting a portion of the P-type drift region 3, the P-pillar is made to float, cutting off the main path for hole injection from the P-pillar to the N-pillar. Second, by setting a second groove and forming a source-controlled MOSFET channel with the source metal 9, the N-type drift region 2, and the P-type body region 4, this channel conducts before the body diode during reverse conduction, suppressing hole injection. The synergistic effect of these two factors significantly reduces the stored charge during reverse recovery, improves reverse recovery characteristics, and avoids the avalanche tolerance reduction problem caused by introducing structures such as Schottky contacts.

[0040] Reference Figure 2 This illustrates a structural block diagram of another trench-gate superjunction power device according to an embodiment of this application, such as... Figure 2 As shown, the side of the N-type drift region 2 has only a first hollow area, which is adjacent to a portion of the upper surface of the substrate and not adjacent to the first groove. The P-type drift region 3 is located in the first hollowed-out region of the N-type drift region 2; The P-shaped body region 4 is located within the N-shaped drift region 2 on both sides of the first groove, flush with the upper surface of the N-shaped drift region 2, and does not contact the P-shaped drift region 3 of the first hollowed-out area.

[0041] In this embodiment, the N-type drift region 2 is located on a portion of the upper surface of the substrate 1 and serves as the longitudinal current path when the device is turned on. The doping concentration and thickness of the N-type drift region 2 are designed according to the superjunction charge balance principle, and together with the subsequently formed P-type drift region 3, they constitute a superjunction structure. The upper surface of the N-type drift region 2 has a downwardly extending first groove, which is used to accommodate the trench gate structure; the side of the N-type drift region 2 has a first hollow area, which extends from the side of the N-type drift region 2 into its interior, and is used to fill the P-type drift region 3. The first hollow area is adjacent to a portion of the upper surface of the substrate 1 to ensure that the bottom of the P-type drift region 3 can contact the area near the upper surface of the substrate 1; at the same time, the first hollow area is not adjacent to the first groove, that is, the two are staggered in horizontal position, thereby avoiding direct coupling between the gate structure and the P-type drift region 3, and providing space for the subsequent isolation between the P-type body region 4 and the P-type drift region 3.

[0042] P-type drift region 3 fills the first hollowed-out region of N-type drift region 2. P-type drift region 3 and N-type drift region 2 form the P-pillar and N-pillar of the superjunction. By adjusting the width and doping concentration of P-type drift region 3 and N-type drift region 2 to achieve charge balance, when the device is turned off, P-type drift region 3 and N-type drift region 2 deplete each other, generating a transverse electric field. This changes the longitudinal electric field distribution from a one-dimensional distribution in a conventional MOSFET to a two-dimensional distribution, thereby significantly improving the breakdown voltage of the device. At the same time, due to the charge compensation effect of the superjunction, the doping concentration of N-type drift region 2 can be increased without reducing the breakdown voltage, thereby reducing the on-resistance.

[0043] The P-type body region 4 is located inside the N-type drift regions 2 on both sides of the first groove, and its top is flush with the upper surface of the N-type drift region 2. The doping concentration of the P-type body region 4 can be 1×10¹. 7 ~4×10¹ 7 cm -The thickness can be 1–1.5 μm. The P-type body region 4 serves as the channel region of the device. When a forward voltage is applied to the gate, its sidewall near the first groove inverts to form a conductive channel, allowing electrons to flow from the N+ source 5 through the channel to the N-type drift region 2. The P-type body region 4 does not contact the P-type drift region 3 in the first hollowed-out region; they are separated longitudinally by a portion of the N-type drift region 2, thus achieving electrical levitation of the P-type drift region 3. This levitation structure cuts off the path for direct hole injection from the P-type body region 4 to the P-type drift region 3. When the body diode is reverse-biased, the P-type drift region 3 cannot obtain a large number of holes from the P-type body region 4, reducing the injection of holes from the P-type drift region 3 to the N-type drift region 2. This significantly reduces the number of minority carriers that need to be extracted during reverse recovery, improving the reverse recovery characteristics of the device.

[0044] In one embodiment, the thickness of the first groove is greater than the thickness of the P-shaped body region 4.

[0045] In this embodiment, "thickness" refers to the longitudinal dimension in the vertical direction of the device. The first groove is a trench formed by etching downwards from the upper surface of the N-type drift region 2, and its thickness is the depth of the groove; the thickness of the P-type body region 4 refers to its longitudinal junction depth extending downwards from the upper surface of the N-type drift region 2. The depth of the first groove is greater than the junction depth of the P-type body region 4, ensuring that when the N-type polysilicon 8 and the dielectric layer 7 are filled into the first groove, the bottom of the trench gate can penetrate deep into the P-type body region 4 and enter the interior of the N-type drift region 2.

[0046] When a positive voltage is applied to the gate, the sidewalls of the trench gate can form a continuous inverse channel over its entire depth (including the entire thickness of the P-type body region 4), avoiding incomplete opening of the channel region due to insufficient trench depth.

[0047] Furthermore, when the P-type body region 4 does not contact the P-type drift region 3, the deeper slot grid can better control the depletion behavior of the channel and the upper part of the drift region, thereby improving the reverse recovery characteristics while maintaining good conduction characteristics.

[0048] In one embodiment, the doping concentration of the substrate 1 is greater than the doping concentration of the N-type drift region 2.

[0049] In this embodiment, substrate 1 can be made of heavily doped N-type (N+) semiconductor material, with a doping concentration of 1×10¹. 9 ~5×10¹ 9 cm - ³; N-type drift region 2 is a lightly doped N-type region, and its doping concentration is designed according to the superjunction charge balance requirements, and can be 1×10¹ 5 ~1×10¹ 7 cm -³. The doping concentration of substrate 1 is higher than that of N-type drift region 2. The highly doped substrate 1 can form a good ohmic contact with drain metal 10, reduce drain series resistance, and reduce device conduction loss.

[0050] In one embodiment, the doping concentration and width of the N-type drift region 2 are in charge balance with the doping concentration and width of the P-type drift region 3.

[0051] In the embodiments of this application, when the N-type drift region 2 (N-pillar) and the P-type drift region 3 (P-pillar) are arranged alternately in the lateral direction, the product of their doping concentrations and their respective widths is equal or approximately equal, thereby satisfying charge balance. This can be expressed by the formula: WN × ND = WP × NA, where WN is the width of the N-type drift region 2, ND is its doping concentration, WP is the width of the P-type drift region 3, and NA is its doping concentration. When this relationship is satisfied, under device turn-off and a reverse voltage is applied between the drain and source, the N-pillars and P-pillars will deplete each other, and the total net charge within them will be essentially zero, thus achieving the desired superjunction effect.

[0052] Based on this, the P-pillar is further floated by disconnecting the P-type drift region 3 from the P-type body region 4, and a source-controlled MOS channel is constructed through the source metal 9 and the dielectric layer 7, thereby significantly improving the reverse recovery characteristics without sacrificing the breakdown voltage and on-resistance.

[0053] Reference Figure 3 This diagram illustrates a comparison of reverse recovery characteristics of an embodiment of this application, showing a comparison between the reverse recovery characteristics of a conventional structure and the trench-gate superjunction power device of this application. Figure 3 As shown, the reverse recovery charge of the structure in this application is much lower than that of the traditional structure, which significantly improves the reverse recovery characteristics of the device.

[0054] Reference Figure 4 This document illustrates a flowchart of the manufacturing steps of a trench-gate superjunction power device according to an embodiment of this application, used for manufacturing such a device. Figure 1 The method for the trench-gate superjunction power device shown may specifically include the following steps: Step 201, Provide substrate 1; Step 202: An N-type drift region 2 is formed on a portion of the upper surface of the substrate 1; the side of the N-type drift region 2 is etched to form a first hollow region and a second hollow region; the first hollow region is adjacent to a portion of the upper surface of the substrate 1; the second hollow region is located above the first hollow region, is not adjacent to the first hollow region, and is in contact with the first groove. Step 203: In the first and second hollowed-out areas of the N-type drift area 2, a P-type drift area 3 is formed; Reference Figure 5This diagram illustrates the process structure of the manufacturing method for the substrate, N-type drift region, and P-type drift region provided in the embodiments of this application. Figure 5 As shown, substrate 1 is provided as the bottom substrate for device fabrication. Substrate 1 can be a heavily doped N-type (N+) single-crystal silicon wafer with a doping concentration of 1×10¹. 9 ~5×10¹ 9 cm - ³. The substrate 1 not only serves as a support structure for subsequent epitaxial growth, but also constitutes the drain region of the device, and its lower surface subsequently forms an ohmic contact with the drain metal 10.

[0055] An N-type drift region 2 is formed on the upper surface of substrate 1 using an epitaxial growth process. The doping concentration and thickness of the N-type drift region 2 are designed according to the target breakdown voltage and superjunction charge balance requirements. Subsequently, the sides of the N-type drift region 2 are etched using photolithography and deep trench etching processes to form a first and a second hollow region extending from the side into the interior. The first hollow region extends downwards to be adjacent to a portion of the upper surface of substrate 1, ensuring that the bottom of the subsequently filled P-type drift region 3 can approach substrate 1, thereby forming a complete superjunction P-pillar. The second hollow region is located above the first hollow region, and the two are separated vertically and not adjacent, i.e., separated by the body portion of the N-type drift region 2. The second hollow region is in direct contact with the first trench. The purpose of the second hollow region is to provide an additional space for filling the P-type drift region at the top of the device, and to allow the upper P-type drift region to contact the P-type body region 4 of the sidewall of the first trench, thereby creating conditions for local grounding of the P-type drift region.

[0056] P-type drift regions 3 are formed in the first and second hollowed-out regions through epitaxial filling or chemical vapor deposition (CVD) combined with etch-back processes. The doping concentration and width of the P-type drift regions 3 satisfy the charge balance condition (WN·ND ≈ WP·NA) with the doping concentration and width of the N-type drift regions 2. After this step, the N-type drift regions 2 (N-pillars) and P-type drift regions 3 (P-pillars) are arranged alternately to form a superjunction structure. The P-type drift regions 3 are divided into upper and lower segments in the vertical direction: the lower segment is located in the first hollowed-out region and remains floating; the upper segment is located in the second hollowed-out region and is used to contact the P-type body region 4. The upper and lower segments of the P-type drift regions are separated by the body of the N-type drift regions 2 and are electrically independent of each other. This segmented structure can be achieved through multiple epitaxial or deep trench etching filling processes.

[0057] Step 204: P-type ions are injected into the region of the N-type drift region 2 that is flush with the upper surface of the N-type drift region 2 and does not contact the P-type drift region 3 of the first hollowed-out region to form a P-type body region 4; a portion of the lower surface of the P-type body region contacts the P-type drift region of the second hollowed-out region. Reference Figure 6The diagram illustrates the process structure of the manufacturing method for the P-type body region provided in an embodiment of this application. Figure 6 As shown, a P-type body region 4 is formed on top of the N-type drift region 2 through ion implantation and annealing. The doping concentration of the P-type body region 4 can be 1×10¹. 7 ~4×10¹ 7 cm - ³, with a thickness of 1–1.5 μm. A portion of the lower surface of the P-type body region 4 directly contacts the P-type drift region 3 within the second hollowed-out region. This contact establishes an electrical connection between the upper P-type drift region 3 and the P-type body region 4, thereby grounding the upper P-type drift region 3 through the P+ source electrode 6 and the source metal 9. The bottom and sides of the P-type body region 4 do not contact the P-type drift region 3 within the first hollowed-out region; they are separated by the body of the N-type drift region 2, thus achieving electrical levitation of the P-type drift region 3.

[0058] Step 205: N-type ions are implanted in the region of the P-type body region 4 that is flush with the upper surface of the P-type body region 4 to form an N+ source 5; Step 206: P-type ions are injected into the region of the P-type body region 4 that is flush with the upper surface of the P-type body region 4 to form a P+ source 6; the P+ source 6 is in contact with the N+ source 5. Reference Figure 7 This diagram illustrates the process structure of the manufacturing methods for the N+ and P+ sources provided in embodiments of this application. Figure 7 As shown, an N+ source 5 is formed on top of the P-type body region 4 by high-dose N-type ion implantation (such as arsenic or phosphorus). The doping concentration of the N+ source 5 can be 1 × 10¹ 9 ~5×10¹ 9 cm - ³, the implantation depth can be 0.2–0.5 μm. The N+ source 5 serves as the source region of the device and subsequently forms an ohmic contact with the source metal 9.

[0059] At the top of the P-type body region 4, adjacent to the N+ source 5, a P+ source 6 is formed through high-dose P-type ion implantation. The doping concentration of the P+ source 6 can be 1×10¹. 9 ~5×10¹ 9 cm - ³. The P+ source 6 and N+ source 5 are in contact with each other, providing a low-resistance body contact for the P-type body region 4, avoiding mis-conduction by parasitic NPN transistors, and improving avalanche resistance.

[0060] Step 207: Etch the N+ source 5, the P-type body region 4, and the N-type drift region 2 to form a first groove; the first groove is not adjacent to the first hollow area; a dielectric layer 7 is formed on a portion of the first groove excluding the second groove, on the upper surface of the portion of the first groove, and on the upper surface of the N+ source 5 near the first groove; the second groove is the region within the first groove near the P-type drift region 3; Reference Figure 8 This diagram illustrates the process structure of a method for manufacturing a dielectric layer according to an embodiment of this application. Figure 8 As shown, a downwardly extending first groove is formed in the N+ source 5, P-type body region 4, and N-type drift region 2 through photolithography and anisotropic dry etching. The etching depth of the first groove exceeds the bottom of the P-type body region 4 (i.e., the thickness of the first groove is greater than the thickness of the P-type body region 4). The first groove is not adjacent to the first cutout region (i.e., P-type drift region 3) in a horizontal position, and the two maintain a certain distance to avoid direct coupling between the gate and the P-pillar.

[0061] The dielectric layer 7 does not continuously cover the entire first groove, but rather etches out a second groove region. The second groove is located within the first groove on the side near the P-type drift region 3, and its function is to provide a window for the subsequent source metal 9 to directly contact the N-type drift region 2 and the P-type body region 4. The dielectric layer 7 also covers a portion of the upper surface of the N+ source 5 near the first groove, serving as an isolation between the gate and the source metal.

[0062] Step 208: An N-type polysilicon 8 is formed in the first groove; the N-type polysilicon 8 is encapsulated by the dielectric layer 7; N-type polysilicon is deposited in the first groove using a CVD process and then etched back to ensure that the polysilicon fills only the groove and is completely encapsulated by the dielectric layer 7. The N-type polysilicon 8 serves as the gate of the device and is coupled to the P-type body region 4 through the dielectric layer 7 when a voltage is applied, forming a conductive channel.

[0063] In one embodiment, the step of forming the dielectric layer 7 in a portion of the first groove excluding the second groove, on the upper surface of the portion of the first groove, and on the upper surface of the N+ source 5 near the first groove may further include the following sub-steps: Sub-step S11: The dielectric layer 7 is formed on the sidewall and bottom of the first groove; like Figure 8 As shown, a dielectric layer 7 (such as silicon dioxide) with a thickness of 80–120 nm is grown on the sidewalls and bottom of the first groove formed by etching through a high-temperature thermal oxidation or CVD process. This dielectric layer serves as a gate oxide layer, providing electrical insulation between the subsequent N-type polysilicon and the semiconductor region.

[0064] Sub-step S12: On the dielectric layer 7 at the bottom of the first groove, the N-type polysilicon 8 is formed; Reference Figure 9 This diagram illustrates the process structure of a method for manufacturing N-type polycrystalline silicon according to an embodiment of this application. Figure 9 As shown, N-type polysilicon is deposited in the first groove to fill the groove and cover the bottom dielectric layer 7. Then, through an etch-back process, the height of the polysilicon is controlled at the desired position within the groove to form N-type polysilicon 8. The upper surface of this polysilicon can be lower than or flush with the upper surface of the N+ source 5.

[0065] Sub-step S13 involves etching the region of the N-type polysilicon 8 near the P-type drift region 3; Sub-step S14: The dielectric layer 7 is formed in the area of ​​the first groove other than the N-type polysilicon 8, the upper surface of the N-type polysilicon 8, the upper surface of the N+ source 5 and the upper surface of the P+ source 6. In sub-step S15, the dielectric layer 7 of the first groove is etched to form the second groove; the side of the second groove does not contact the side of the N-type polysilicon 8; the side of the second groove does not coincide with the side of the first groove, and the bottom does not coincide with the bottom of the first groove. Sub-step S16 involves etching the dielectric layer 7 on the upper surface of the N+ source 5 near the P+ source 6 and the dielectric layer 7 on the upper surface of the P+ source 6.

[0066] Reference Figure 10 This diagram illustrates the process structure of another method for manufacturing a dielectric layer and N-type polysilicon according to an embodiment of this application. Figure 10 As shown, firstly, through photolithography and anisotropic etching, a portion of the material in the N-type polysilicon 8 near the P-type drift region 3 is selectively removed, reserving space for the subsequent formation of a second groove on this side of the groove, thus preventing the polysilicon from occupying the position where the source metal needs to directly contact the N-type drift region 2.

[0067] Next, a dielectric layer 7 is deposited again, covering the area within the first groove that is not filled with polysilicon, the upper surface of the N-type polysilicon 8, the upper surface of the N+ source 5, and the upper surface of the P+ source 6. This dielectric layer can isolate the subsequent source metal from the N-type polysilicon, protect the surfaces of the N+ source 5 and the P+ source 6, and provide a sacrificial layer for the subsequent etching to form the second groove.

[0068] Then, through photolithography and dielectric etching processes, a portion of the dielectric layer 7 is removed from the side of the first groove near the P-type drift region 3 to form a second groove. The side of the second groove does not contact the side of the N-type polysilicon 8, meaning a dielectric layer 7 is left between them to prevent short circuits between the source metal and the gate. The side of the second groove does not coincide with the side of the first groove, meaning the opening width of the second groove is smaller than the width of the first groove, thus retaining a portion of the dielectric layer 7 on the sidewall of the groove. The bottom of the second groove also does not coincide with the bottom of the first groove, meaning the second groove is not completely etched to the bottom, but forms a shallow pit or window in the dielectric layer. This allows the source metal 9 subsequently deposited in the second groove to form a source-controlled MOS through the dielectric layer 7 with the N-type drift region 2 and the P-type body region 4, while preventing direct contact between the metal and the semiconductor at the bottom of the first groove. The second groove is the core structure for constructing the source-controlled MOS channel: the source metal contacts the N-type drift region 2 and the P-type body region 4 through the second groove, and together with the dielectric layer 7, the N-type drift region 2, the P-type body region 4, and the N+ source 5, forms a source-controlled MOS channel.

[0069] Finally, through photolithography and etching processes, the dielectric layer 7 on the upper surface of the N+ source 5 near the P+ source 6 and on the entire upper surface of the P+ source 6 is removed, exposing the underlying N+ source 5 and P+ source 6. This allows the subsequently deposited source metal 9 to form ohmic contacts with these regions. After this step, the source metal 9 can simultaneously contact the N+ source 5, the P+ source 6, and, through the second groove, the N-type drift region 2 and the P-type body region 4, achieving potential unification for all source-related regions.

[0070] Through the multi-step process of forming the dielectric layer described above, this application forms both a gate structure encapsulating the N-type polysilicon 8 and a second groove window for direct contact between the source metal and the semiconductor within the first groove, thereby integrating the source-controlled MOS channel function without adding additional photolithography layers.

[0071] Step 209: Deposit metal in the second groove, on the upper surface of the dielectric layer 7, on a portion of the upper surface of the N+ source 5, and on the upper surface of the P+ source 6 to form source metal 9; Step 210: Deposit metal under the substrate 1 to form drain metal 10.

[0072] like Figure 1As shown, a metal layer (such as Al or Cu) is deposited by sputtering or evaporation, and the source metal 9 is formed by photolithography etching. The source metal 9 fills the second groove and can form a MOS structure with the N-type drift region 2 and the P-type body region 4 through the dielectric layer 7, thereby forming the source terminal of the source-controlled MOS channel; at the same time, the source metal 9 covers part of the upper surface of the N+ source 5 and the entire upper surface of the P+ source 6, realizing the equipotential connection between the source region and the body region. A metal stack (such as Ti / Ni / Ag) is deposited on the back side of the substrate 1 by sputtering or evaporation, and annealing is performed to form an ohmic contact, resulting in the drain metal 10.

[0073] In one embodiment, the doping concentration of the substrate 1 is greater than the doping concentration of the N-type drift region 2.

[0074] In one embodiment, the doping concentration and width of the N-type drift region 2 are in charge balance with the doping concentration and width of the P-type drift region 3.

[0075] This application introduces a source-metal controlled MOS conduction channel, constructing a structure composed of an N+ source, a P-type body region, an N-type pillar region, a dielectric layer, and a metal source. Utilizing the control capability of the MOS channel, it preemptively conducts during reverse conduction, reducing the number of holes injected from the P-region (anode) to the N-region (drift region), directly reducing the amount of stored charge. By adjusting the dielectric layer thickness, the source-controlled MOS channel conducts before the body diode, thereby suppressing the injection of holes from the P-type body region to the drift region, suppressing minority carrier injection, and reducing reverse recovery charge.

[0076] By adjusting the process, some P pillars are disconnected from the P-type body region and placed in an electrically floating state. After the P pillars are "suspended", the main source of holes, which is directly connected to the P-type body region, is cut off. This significantly reduces the number of carriers that need to be extracted during reverse recovery. During reverse conduction, the P pillars cannot inject holes into the N pillars, further reducing the number of minority carriers in the N pillars, cutting off the hole injection path, and significantly improving the reverse recovery characteristics.

[0077] The width, thickness, and doping concentration of N-type and P-type pillars are adjusted to meet charge balance. By utilizing the superjunction principle, the drift region is depleted through the transverse electric field in the off state, so that the longitudinal electric field distribution changes from a one-dimensional distribution to a two-dimensional distribution. This allows for the reduction of on-resistance while increasing doping concentration, while maintaining excellent breakdown voltage performance. The reverse recovery charge is reduced without sacrificing the breakdown voltage of the device.

[0078] In this embodiment, the P-pillar is segmented, with one part connected to the P-type body region (grounded) and the other part floating. By adjusting the ratio of grounded to floating, the gate-source capacitance and gate-drain capacitance can be dynamically adjusted, avoiding the increase in gate-drain capacitance due to full floating, which affects the switching speed, thus optimizing the overall switching performance and achieving a trade-off between reverse recovery characteristics and switching losses.

[0079] This application also provides a chip including the above-described trench gate superjunction power device.

[0080] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A trench gate super junction power device, characterized in that, include: Substrate; The N-type drift region is located on a portion of the upper surface of the substrate; The upper surface of the N-type drift region has a first groove, and the side has a first hollow area and a second hollow area. The first hollow area is adjacent to a portion of the upper surface of the substrate and is not adjacent to the first groove. The second hollow area is located above the first hollow area, is not adjacent to the first hollow area, and is in contact with the first groove. The P-type drift region is located in the first and second hollowed-out regions of the N-type drift region; The P-shaped body region is located within the N-shaped drift regions on both sides of the first groove, is flush with the upper surface of the N-shaped drift region, contacts the P-shaped drift region of the second hollow region, and does not contact the P-shaped drift region of the first hollow region. The N+ source is located within the P-type body region on both sides of the first groove, flush with the upper surface of the P-type body region, and adjacent to the first groove. The P+ source is located within the P-type body region on both sides of the first groove, flush with the upper surface of the P-type body region, and in contact with the N+ source. A dielectric layer is located in a portion of the first groove excluding the second groove and on the upper surface of the portion of the first groove, as well as on the upper surface of the N+ source near the first groove. The second groove is the area within the first groove that is close to the P-type drift region; N-type polycrystalline silicon is located within the first groove and is enclosed by the dielectric layer; The source metal is located within the second groove, on the upper surface of the dielectric layer, on a portion of the upper surface of the N+ source, and on the upper surface of the P+ source. The drain metal is located below the substrate.

2. The trench gate super junction power device of claim 1, wherein, The thickness of the first groove is greater than the thickness of the P-shaped body region.

3. The trench gate super junction power device of claim 1, wherein, The doping concentration of the substrate is greater than the doping concentration of the N-type drift region.

4. The trench gate super junction power device of claim 1, wherein, The doping concentration and width of the N-type drift region satisfy the charge balance with the doping concentration and width of the P-type drift region.

5. A method for manufacturing a trench gate super junction power device, characterized by, The method for manufacturing a trench-gate superjunction power device as described in any one of claims 1-4 comprises: Provide substrate; An N-type drift region is formed on a portion of the upper surface of the substrate; the sides of the N-type drift region are etched to form a first hollow region and a second hollow region; the first hollow region is adjacent to a portion of the upper surface of the substrate; the second hollow region is located above the first hollow region, is not adjacent to the first hollow region, and is in contact with the first groove; A P-type drift region is formed in the first and second hollowed-out regions of the N-type drift region; P-type ions are injected into a region within the N-type drift region that is flush with the upper surface of the N-type drift region and does not contact the P-type drift region of the first hollow region to form a P-type body region; a portion of the lower surface of the P-type body region contacts the P-type drift region of the second hollow region. N-type ions are implanted in the region of the P-type body region that is flush with the upper surface of the P-type body region to form an N+ source. P-type ions are implanted in the region of the P-type body region that is flush with the upper surface of the P-type body region to form a P+ source; the P+ source is in contact with the N+ source. The N+ source, the P-type body region, and the N-type drift region are etched to form a first groove; the first groove is not adjacent to the first hollow area; a dielectric layer is formed on a portion of the first groove excluding the second groove, on the upper surface of the portion of the first groove, and on the upper surface of the N+ source near the first groove; the second groove is the region within the first groove near the P-type drift region. An N-type polycrystalline silicon is formed within the first groove; the N-type polycrystalline silicon is encapsulated by the dielectric layer; Metal is deposited in the second groove, on the upper surface of the dielectric layer, on a portion of the upper surface of the N+ source, and on the upper surface of the P+ source to form source metal; Metal is deposited beneath the substrate to form a drain metal.

6. The method of manufacturing a trench gate super junction power device according to claim 5, wherein, The formation of a dielectric layer in a portion of the first groove excluding the second groove, on the upper surface of that portion, and on the upper surface of the N+ source near the first groove, includes: The dielectric layer is formed on the sidewalls and bottom of the first groove; The N-type polycrystalline silicon is formed on the dielectric layer at the bottom of the first groove; The region of the N-type polysilicon near the P-type drift region is etched. The dielectric layer is formed in the area excluding the N-type polysilicon within the first groove, on the upper surface of the N-type polysilicon, on the upper surface of the N+ source, and on the upper surface of the P+ source. The dielectric layer of the first groove is etched to form the second groove; the side of the second groove does not contact the side of the N-type polysilicon; the side of the second groove does not coincide with the side of the first groove, and the bottom does not coincide with the bottom of the first groove. The dielectric layer on the upper surface of the N+ source near the P+ source and the dielectric layer on the upper surface of the P+ source are etched.

7. The method for manufacturing a trench-gate superjunction power device according to claim 5, characterized in that, The doping concentration of the substrate is greater than the doping concentration of the N-type drift region.

8. The method of manufacturing a trench gate super junction power device according to claim 5, wherein, The doping concentration and width of the N-type drift region satisfy the charge balance with the doping concentration and width of the P-type drift region.

9. A chip, characterized by Including the trench gate superjunction power device as described in any one of claims 1-4.

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