Semiconductor device structure and method of fabricating the same

Abstract

The application relates to a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a substrate, an epitaxial layer of a first conductive type, a well region of a second conductive type, a source region of the first conductive type, a second conductive type column structure, a first trench gate structure and a second trench gate structure. The second conductive type column structure comprises a filling dielectric layer and a doped region of the second conductive type. The filling dielectric layer is located in the epitaxial layer. The doped region has a spacing from the substrate and the well region on a side close to the substrate and a side surrounding the side wall of the filling dielectric layer. The first trench gate structure is located on a side of the second conductive type column structure away from the substrate. The first trench gate structure comprises a first trench gate and a first gate dielectric layer. The second trench gate structure is located on a side of the first trench gate structure and has a spacing from the first trench gate structure. The second trench gate structure comprises a second trench gate and a second gate dielectric layer. The semiconductor device structure provided by the application has better performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor device structures are widely used in industries, new energy, transportation and other fields due to their advantages such as not generating tail current and being able to achieve lower on-resistance.

[0003] In conventional techniques, forming a superjunction structure within the epitaxial layer reduces the on-resistance of semiconductor devices and prevents a decrease in breakdown voltage (BV). However, conventional superjunction processes involve implanting ions of a second conductivity type into an epitaxial layer of a first conductivity type to form pillars of the second conductivity type. Consequently, semiconductor devices with this superjunction structure exhibit poor performance. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device structure and its fabrication method to address the aforementioned technical problems.

[0005] In a first aspect, one embodiment of this application provides a semiconductor device structure, including:

[0006] Substrate;

[0007] An epitaxial layer of the first conductivity type is located on one side of the substrate;

[0008] The second conductivity type well region is located within the epitaxial layer; the second conductivity type is the opposite of the first conductivity type.

[0009] The source region of the first conductivity type is located within the well region;

[0010] The second conductivity type pillar structure includes a filled dielectric layer and a doped region of the second conductivity type; the filled dielectric layer is located within the epitaxial layer; the doped region surrounds the sidewall of the filled dielectric layer and the side close to the substrate, and has a gap with both the substrate and the well region;

[0011] The first trench gate structure is located on the side of the second conductivity type pillar structure away from the substrate; the first trench gate structure includes a first trench gate and a first gate dielectric layer; the first trench gate extends from the source region through the well region into the epitaxial layer; the first gate dielectric layer surrounds the sidewall of the first trench gate and the side close to the second conductivity type pillar structure.

[0012] The second trench gate structure is located on one side of the first trench gate structure and has a gap with the first trench gate structure; the second trench gate structure includes a second trench gate and a second gate dielectric layer; the second trench gate extends from the source region through the well region into the epitaxial layer; the second gate dielectric layer surrounds the sidewall of the second trench gate and the side close to the substrate.

[0013] In one embodiment, there are multiple second conductivity type pillar structures and multiple first trench gate structures; the multiple second conductivity type pillar structures are arranged at intervals along a first direction, and the multiple first trench gate structures are arranged at intervals along a first direction.

[0014] In one embodiment, there are multiple second trench gate structures, which are located between adjacent first trench gate structures and are spaced apart along a first direction.

[0015] In one embodiment, along the second direction, both the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate are lower than the side of the source region away from the substrate; the semiconductor device structure further includes:

[0016] An interlayer dielectric layer is located on the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate; the side of the interlayer dielectric layer away from the substrate is flush with the side of the source region away from the substrate; the first direction and the second direction intersect.

[0017] In one embodiment, the semiconductor device structure further includes:

[0018] The source electrode is located on the side of the source region away from the substrate and is electrically connected to the source region at least;

[0019] The drain is located on the side of the substrate away from the epitaxial layer and is electrically connected to the substrate.

[0020] The first gate lead-out electrode is electrically connected to the first trench gate.

[0021] Secondly, one embodiment of this application provides a method for fabricating a semiconductor device structure, the method comprising:

[0022] A substrate is provided, and a first sub-epieptaxial layer of a first conductivity type is formed on one side of the substrate;

[0023] A second conductivity type pillar structure is formed within the first sub-epitaxial layer; the second conductivity type pillar structure includes a filling dielectric layer and a doped region of the second conductivity type; the doped region surrounds the sidewall of the filling dielectric layer and the side close to the substrate, and has a gap with the substrate;

[0024] A second sub-epitaxial layer of a first conductivity type is formed on the side of the first sub-epitaxial layer away from the substrate; the second sub-epitaxial layer and the first sub-epitaxial layer together constitute an epitaxial layer;

[0025] A well region of a second conductivity type is formed within the second sub-epitaxial layer; the well region and the pillar structure of the second conductivity type are spaced apart.

[0026] A source region of the first conductivity type is formed within a well region of the second conductivity type;

[0027] A first trench gate structure is formed on the side of the second conductivity type pillar structure away from the substrate; the first trench gate structure includes a first trench gate and a first gate dielectric layer; the first trench gate extends from the source region through the well region into the epitaxial layer; the first gate dielectric layer surrounds the sidewall of the first trench gate and the side close to the second conductivity type pillar structure.

[0028] A second trench gate structure is formed on one side adjacent to the first trench gate structure; the second trench gate structure has a spacing with the first trench gate structure; the second trench gate structure includes a second trench gate and a second gate dielectric layer; the second trench gate extends from the source region through the well region into the epitaxial layer; the second gate dielectric layer surrounds the sidewalls of the second trench gate and the side near the substrate.

[0029] In one embodiment, the number of second conductive type pillar structures and the number of first trench gate structures are both multiple; the multiple second conductive type pillar structures are arranged at intervals along a first direction, and the multiple first trench gate structures are arranged at intervals along a first direction.

[0030] In one embodiment, the number of formed second trench gate structures is multiple, the multiple second trench gate structures are located between adjacent first trench gate structures, and the multiple second trench gate structures are arranged at intervals along a first direction.

[0031] In one embodiment, along the second direction, both the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate are lower than the side of the source region away from the substrate; the first direction and the second direction intersect; the fabrication method further includes:

[0032] An interlayer dielectric layer is formed on the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate, and the side of the interlayer dielectric layer away from the substrate is flush with the side of the source region away from the substrate.

[0033] In one embodiment, the preparation method further includes:

[0034] A first gate contact hole is formed on the side of the source region away from the substrate; the first gate contact hole exposes the first trench gate;

[0035] A source electrode and a first gate electrode are formed on the side of the source region away from the substrate; the source electrode is electrically connected to the source region; the first gate electrode is electrically connected to the first trench gate.

[0036] A drain is formed on the side of the substrate away from the epitaxial layer; the drain is electrically connected to the substrate.

[0037] This application provides a semiconductor device structure and its fabrication method. The semiconductor device structure includes a substrate, an epitaxial layer of a first conductivity type, a well region of a second conductivity type, a source region of the first conductivity type, a pillar structure of the second conductivity type, a first trench gate structure, and a second trench gate structure. The second conductivity type pillar structure includes a doped region, which acts as an "electric field shield" to protect the filling dielectric layer in the second conductivity type pillar structure. The filling dielectric layer in the second conductivity type pillar structure can optimize the electric field strength of the first gate dielectric layer in the first trench gate structure and the second gate dielectric layer in the second trench gate structure, thus isolating cells and maintaining the breakdown voltage of the cells, effectively improving the reliability of the first and second gate dielectric layers. The presence of the filling dielectric layer in the second conductivity type pillar structure can change the peak electric field distribution near the first trench gate in the first trench gate structure and the second trench gate in the second trench gate structure under high voltage, helping to alleviate the hot carrier injection effect, thereby extending the lifetime of the semiconductor device structure and improving its performance. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device structure provided in one embodiment of this application;

[0040] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device structure provided in another embodiment of this application;

[0041] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device structure provided in another embodiment of this application;

[0042] Figure 4 This is a schematic flowchart illustrating the steps of a method for fabricating a semiconductor device structure according to an embodiment of this application;

[0043] Figure 5 This is a schematic diagram illustrating the fabrication process of a semiconductor device structure provided in one embodiment of this application;

[0044] Figure 6 This is a schematic diagram illustrating the fabrication process of a semiconductor device structure provided in another embodiment of this application;

[0045] Figure 7 This is a schematic flowchart illustrating the steps of a method for fabricating a semiconductor device structure according to another embodiment of this application.

[0046] Explanation of reference numerals in the attached figures:

[0047] 1. Initial doped region; 2. First trench; 3. Second trench; 100. Substrate; 200. Epitaxial layer; 210. First sub-epitaxy layer; 220. Second sub-epitaxy layer; 300. Well region; 400. Source region; 500. Second conductivity type pillar structure; 510. Filled dielectric layer; 520. Doped region; 600. First trench gate structure; 610. First trench gate; 620. First gate dielectric layer; 700. Second trench gate structure; 710. Second trench gate; 720. Second gate dielectric layer; 800. Interlayer dielectric layer; 900. Source; 910. Drain. Detailed Implementation

[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0049] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] Furthermore, in the instruction manual, the phrase "cross-sectional schematic diagram" or "cross-sectional structural schematic diagram" refers to the accompanying drawing when viewing a cross-section taken by vertically cutting the target portion from the side.

[0052] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0053] Before detailing the technical solutions of the embodiments of this application, the technical background or evolution of the embodiments of this application will be introduced first. In the field of semiconductor technology, the silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) is a unipolar device that does not generate tail current. Due to its advantages such as achieving lower on-resistance, it is widely used in industry, new energy, transportation and other fields. In the silicon carbide vertical double-diffused metal oxide semiconductor field effect transistor (SiC VDMOSFET), the current spreading layer (CSL) is usually an N-type epitaxial layer (N-Epi) single-component structure with intrinsic resistance, accounting for more than 60% of the on-resistance. If the CSL layer is replaced with a superjunction P-pillar and N-pillar structure, the on-resistance can be reduced to the greatest extent and the breakdown voltage drop can be avoided. However, SiC VDMOSFETs employing superjunction P-pillar and N-pillar structures exhibit poor performance. Therefore, this application provides a semiconductor device structure with superior performance.

[0054] The technical solution of this application and how the technical solution of this application solves the technical problem are described in detail below with specific embodiments.

[0055] Please see Figure 1 One embodiment of this application provides a semiconductor device structure, including a substrate 100, an epitaxial layer 200 of a first conductivity type, a well region 300 of a second conductivity type, a source region 400 of a first conductivity type, a pillar structure 500 of a second conductivity type, a first trench gate structure 600, and a second trench gate structure 700.

[0056] The epitaxial layer 200 of the first conductivity type is located on one side of the substrate 100; the well region 300 of the second conductivity type is located within the epitaxial layer 200; the source region 400 of the first conductivity type is located within the well region 300; the second conductivity type is the opposite of the first conductivity type.

[0057] The first conductivity type is N-type, with electrons as the majority carriers; the second conductivity type is P-type, with holes as the majority carriers. Of course, in other examples, the first conductivity type can be P-type, and the second conductivity type can be N-type. The substrate 100 serves as the base for the semiconductor device structure, supporting epitaxial growth, implantation, etching, and other processes. The material of the substrate 100 can be single-crystal silicon, silicon carbide, silicon nitride, etc. The epitaxial layer 200 of the first conductivity type is made of the same material as the substrate 100. The substrate 100 can be a substrate of the first conductivity type. Based on the substrate 100, an epitaxial layer 200 of the first conductivity type can be formed on one side of the substrate 100 through an epitaxial growth process. The size and doping concentration of the epitaxial layer 200 can be set according to actual conditions and are not limited here, as long as the performance of the semiconductor device structure is guaranteed.

[0058] The well region 300 of the second conductivity type can be formed by implanting dopant ions of the second conductivity type into the epitaxial layer, thereby transforming the corresponding region of the epitaxial layer. The dopant ions of the second conductivity type can be p-type dopant ions, such as boron or aluminum. Implanting dopant ions of the second conductivity type into the epitaxial layer 200 can form the well region 300. There is direct contact between the epitaxial layer 200 and the well region 300. The size and doping concentration of the well region 300 can be set according to actual conditions and are not limited here, as long as the performance of the semiconductor device structure is guaranteed.

[0059] The source region 400 of the first conductivity type can be formed by injecting dopant ions of the first conductivity type into the well region, thereby transforming the corresponding well region. The dopant ions of the first conductivity type can be N-type dopant ions, such as phosphorus, arsenic, and nitrogen. Injecting dopant ions of the first conductivity type into the well region 300 can form the source region 400. The well region 300 and the source region are in direct contact. The size and doping concentration of the source region 400 can be set according to actual conditions and are not limited here, as long as the performance of the semiconductor device structure can be guaranteed.

[0060] It is understandable that the substrate 100, epitaxial layer 200, well region 300 and source region 400 are made of the same material system, such as all silicon or all silicon carbide.

[0061] The second conductivity type pillar structure 500 includes a filled dielectric layer 510 and a doped region 520 of the second conductivity type; the filled dielectric layer 510 is located within the epitaxial layer 200; the doped region 520 surrounds the sidewall of the filled dielectric layer 510 and the side close to the substrate 100, and has a distance from both the substrate 100 and the well region 300.

[0062] The relative permittivity of the filling dielectric layer 510 can be much smaller than that of the epitaxial layer 200. When the epitaxial layer is made of silicon carbide, the filling dielectric layer 510 can be made of a low-k oxide layer, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The doped region 520 of the second conductivity type refers to the region surrounding the sidewalls and bottom of the filling dielectric layer formed by implanting dopant ions of the first conductivity type into the epitaxial layer 200. The filling dielectric layer 510 includes two opposing sidewalls in the first direction (X direction) and two opposing sides in the second direction (Y direction), namely, a side closer to the substrate 100 and a side farther from the substrate 100. The doped region 520 surrounds the two opposing sidewalls of the filling dielectric layer 510 in the X direction and the side of the filling dielectric layer 510 closer to the substrate 100 (i.e., the side closer to the substrate 100 and the side farther from the substrate 100). Figure 1 (The bottom of the filling dielectric layer 510 shown). In the Y direction, the doped region 520 is spaced apart from the substrate 100, and the doped region 520 is also spaced apart from the well region 300. The orthogonal projection of the filling dielectric layer 510 on the substrate 100 lies within the orthogonal projection of the doped region 520 on the substrate 100.

[0063] In an optional embodiment, in the Y direction, the size of the doped region 520 is approximately 8 micrometers; the spacing between the doped region 520 and the substrate 100 is greater than 2 micrometers; and the distance between the side of the filling dielectric layer 510 near the substrate 100 and the side of the doped region 520 away from the filling dielectric layer 510 is in the range of 0.1 micrometers and 0.2 micrometers. In the X direction, the distance between the sidewall of the filling dielectric layer 510 and the side of the doped region 520 away from the filling dielectric layer 510 is in the range of 0.1 micrometers and 0.2 micrometers.

[0064] Specifically, the spacing between the doped region 520 and the substrate 100 is 2.5 micrometers, 3 micrometers, 4.5 micrometers, etc. The distance between the side of the filling dielectric layer 510 near the substrate 100 and the side of the doped region 520 away from the filling dielectric layer 510 is 0.12, 0.15, 0.16, 0.18, etc. The distance between the sidewall of the filling dielectric layer 510 and the side of the doped region 520 away from the filling dielectric layer 510 is 0.12, 0.15, 0.16, 0.18, etc.

[0065] The first trench gate structure 600 is located on the side of the second conductivity type pillar structure 500 away from the substrate 100; the first trench gate structure 600 includes a first trench gate 610 and a first gate dielectric layer 620; the first trench gate 610 extends from the source region 400 through the well region 300 into the epitaxial layer 200; the first gate dielectric layer 620 surrounds the sidewalls of the first trench gate 610 and the side close to the second conductivity type pillar structure 500.

[0066] The orthographic projection of the first trench gate structure 600 on the substrate 100 lies within the orthographic projection of the second conductivity type pillar structure 500 on the substrate 100; the orthographic projection of the first trench gate structure 600 on the substrate 100 overlaps with the orthographic projection of the filling dielectric layer 510 on the substrate 100, i.e. Figure 1 As shown, the first trench gate structure 600 can be located directly above the second conductivity type pillar structure 500. The material of the first trench gate 610 includes polysilicon. The material of the first gate dielectric layer 620 can be the same as the material of the filling dielectric layer 510. The first trench gate 610 includes two opposing sidewalls in the X direction and two opposing sides in the Y direction, namely a side closer to the second conductivity type pillar structure 500 and a side farther from the second conductivity type pillar structure 500. The first gate dielectric layer 620 surrounds the two opposing sidewalls of the first trench gate 610 in the X direction and the side of the first trench gate 610 closer to the second conductivity type pillar structure 500.

[0067] The second trench gate structure 700 is located on one side of the first trench gate structure 600 and has a gap with the first trench gate structure 600; the second trench gate structure 700 includes a second trench gate 710 and a second gate dielectric layer 720; the second trench gate 710 extends from the source region 400 through the well region 300 into the epitaxial layer 200; the second gate dielectric layer 720 surrounds the sidewalls of the second trench gate 710 and the side close to the substrate 100.

[0068] In the X direction, the first trench gate structure 600 includes two sides, and the second trench gate structure 700 is located on one side of the first trench gate structure 600. The material of the second trench gate 710 includes polysilicon, and the material of the second gate dielectric layer 720 can be the same as that of the first gate dielectric layer 620. The second trench gate 710 includes two opposing sidewalls in the X direction and two opposing sides in the Y direction, namely a side closer to the substrate 100 and a side farther from the substrate 100. The second gate dielectric layer 720 surrounds the two opposing sidewalls of the second trench gate 710 in the X direction and the side of the second trench gate 710 closer to the substrate 100.

[0069] The second conductivity type pillar structure 500 in the semiconductor device structure provided in this application embodiment includes a doped region 520. The doped region 520 can act as an "electric field shield" to protect the filling dielectric layer 510 in the second conductivity type pillar structure 500. The filling dielectric layer 510 in the second conductivity type pillar structure 500 can optimize the electric field strength of the first gate dielectric layer 620 and the second gate dielectric layer 720, and play the role of isolating cells and maintaining the breakdown voltage of cells, which can effectively improve the reliability of the first gate dielectric layer 620 and the second gate dielectric layer 720. The presence of the filling dielectric layer 510 in the second conductivity type pillar structure 500 can change the electric field peak distribution near the first trench gate 610 and the second trench gate 710 under high voltage, which helps to alleviate the hot carrier injection effect, thereby delaying the lifetime of the semiconductor device structure and improving the performance of the semiconductor device structure.

[0070] In addition, the material of the filling dielectric layer 510 is oxide. The relative permittivity of oxide is lower than that of the epitaxial layer 200. The filling dielectric layer 510 can effectively reduce the gate-drain capacitance (Miller capacitance) of the semiconductor device structure, thereby reducing Miller charge and significantly accelerating the switching speed of the semiconductor device structure and reducing switching losses.

[0071] In one embodiment, such as Figure 1 As shown, there are multiple second-conductivity pillar structures 500 and multiple first trench gate structures 600; the multiple second-conductivity pillar structures 500 are arranged at intervals along the first direction, and the multiple first trench gate structures 600 are arranged at intervals along the first direction.

[0072] In the Y direction, the first trench gate structure 600 is disposed directly above the second conductivity type pillar structure 500. The number of second conductivity type pillar structures 500 is the same as the number of first trench gate structures 600. In the X direction, there is a spacing between adjacent second conductivity type pillar structures 500, and there is also a spacing between adjacent first trench gate structures 600, and the spacing between adjacent second conductivity type pillar structures 500 is smaller than the spacing between first trench gate structures 600.

[0073] In this embodiment, the design of multiple second conductivity type pillar structures 500 and multiple first trench gate structures 600 can reduce on-resistance and optimize the density of the semiconductor device structure, thereby reducing the area of ​​the semiconductor device. Furthermore, it can further optimize the electric field strength of the first gate dielectric layer 620 and the second gate dielectric layer 720, improving the reliability of the semiconductor device structure.

[0074] In one embodiment, such as Figure 1As shown, there are multiple second trench gate structures 700, which are located between adjacent first trench gate structures 600 and are arranged at intervals along the first direction.

[0075] In the X direction, a plurality of second trench gate structures 700 are arranged at intervals between two adjacent first trench gate structures 600. The spacing between two adjacent second trench gate structures 700 and the spacing between a second trench gate structure 700 adjacent to a first trench gate structure 600 and the first trench gate structure 600 are the same. Specifically, the spacing between two adjacent second trench gate structures 700 is 0.2 micrometers.

[0076] In this embodiment, the multiple second trench gate structures 700 are three-dimensional fin-shaped channels and structures that surround the gate on three sides. This can form high-density cells. During the conduction process, the well region 300 will be completely inverted into N-type communication by the second trench gate structures on both sides, forming a fin field-effect transistor (FIN) effect. This can reduce the size, optimize the electric field distribution near the second trench gate, improve the breakdown voltage, reduce Miller capacitance, improve the switching speed of the semiconductor device structure, and reduce switching losses.

[0077] In one embodiment, such as Figure 1 As shown, along the second direction, the side of the first trench gate 610 away from the substrate 100 and the side of the second trench gate 710 away from the substrate 100 are both lower than the side of the source region 400 away from the substrate 100.

[0078] In the Y direction, the distance between the substrate 100 and the side of the first trench gate 610 away from the substrate 100 is less than the distance between the substrate 100 and the side of the source region 400 away from the substrate 100. Similarly, in the Y direction, the distance between the substrate 100 and the side of the second trench gate 710 away from the substrate 100 is less than the distance between the substrate 100 and the side of the source region 400 away from the substrate 100.

[0079] Based on this, such as Figure 2 As shown, the semiconductor device structure also includes an interlayer dielectric layer 800.

[0080] The interlayer dielectric layer 800 is located on the side of the first trench gate 610 away from the substrate 100 and the side of the second trench gate 710 away from the substrate 100; the side of the interlayer dielectric layer 800 away from the substrate 100 is flush with the side of the source region 400 away from the substrate 100; the first direction and the second direction intersect.

[0081] The material of the interlayer dielectric layer 800 can be the same as the material of the filling dielectric layer 510. The orthographic projection of the interlayer dielectric layer 800 located on the side of the first trench gate 610 away from the substrate 100 on the substrate 100 overlaps with the orthographic projection of the first trench gate 610 on the substrate 100. The orthographic projection of the interlayer dielectric layer 800 located on the side of the second trench gate 710 away from the substrate 100 on the substrate 100 overlaps with the orthographic projection of the second trench gate 710 on the substrate 100.

[0082] In the Y direction, the distance between the side of the interlayer dielectric layer 800 away from the substrate 100 and the substrate 100 is the same as the distance between the side of the source region 400 away from the substrate 100 and the substrate 100.

[0083] In this embodiment, by providing an interlayer dielectric layer 800 on the side of the first trench gate 610 away from the substrate 100 and on the side of the second trench gate 710 away from the substrate 100, the first trench gate 610 and the second trench gate 710 can be isolated from the source in the semiconductor device structure to ensure the performance of the semiconductor device structure.

[0084] In an optional embodiment, in the Y direction, the distance between the side of the doped region 520 away from the substrate 100 and the substrate 100 can be the same as the distance between the side of the second trench gate structure 700 closer to the substrate 100 and the substrate 100, or it can have a small error. Specifically, the error is... 0.5 micrometers.

[0085] In one embodiment, such as Figure 3 As shown, the semiconductor device structure also includes a source 900, a drain 910, and a first gate electrode. The source 900 is located on the side of the source region 400 away from the substrate 100 and is electrically connected to at least the source region. The drain 910 is located on the side of the substrate 100 away from the epitaxial layer 200 and is electrically connected to the substrate 100. The first gate electrode is electrically connected to the first trench gate 610.

[0086] The electrical contact between source 900 and source region 400 is an ohmic contact, meaning that a metal silicide is formed between source 900 and source region 400 as an ohmic contact structure, which can reduce contact resistance. The material of source 900 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials.

[0087] The electrical contact between the drain 910 and the epitaxial layer 200 is an ohmic contact, meaning that a metal silicide is formed between the drain 910 and the epitaxial layer 200 as an ohmic contact structure, which can reduce contact resistance. The drain 910 can be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials.

[0088] A first gate contact hole is formed in the interlayer dielectric layer 800 on the side of the first trench gate 610 away from the substrate 100. The first gate lead electrode is disposed in the first gate contact hole and electrically connected to the first trench gate 610, so that the first trench gate 610 is electrically connected to the driving circuit corresponding to the semiconductor device.

[0089] In an optional embodiment, the semiconductor device structure further includes a second gate lead-out electrode, which is connected to the second trench gate 710. It is understood that a second gate contact hole is formed on the interlayer dielectric layer 800 on the side of the second trench gate 710 away from the substrate 100, and the second gate lead-out electrode is disposed within the second gate contact hole and electrically connected to the second trench gate 710, so that the second trench gate 710 is electrically connected to the corresponding driving circuit of the semiconductor device.

[0090] In one embodiment, see Figure 4 The flowchart, and combined with Figure 5 and Figure 6 The diagram illustrates the fabrication process of a semiconductor device structure, which includes the following steps:

[0091] Step 400: Provide a substrate 100 and form a first sub-epieptaxial layer 210 of a first conductivity type on one side of the substrate 100.

[0092] like Figure 5 As shown in Figure (a), a first sub-epitaxial layer 210 is formed on substrate 100 using a chemical vapor phase epitaxy process. The description of the materials of the first sub-epitaxial layer 210 and substrate 100 can be found in the detailed description of epitaxial layer 200 and substrate 100 in the above embodiments, and will not be repeated here.

[0093] Step 410: Form a second conductivity type pillar structure 500 in the first sub-epipolar layer 210; the second conductivity type pillar structure 500 includes a filling dielectric layer 510 and a doped region 520 of the second conductivity type; the doped region 520 surrounds the sidewall of the filling dielectric layer 510 and the side close to the substrate 100, and has a gap with the substrate 100.

[0094] A second conductivity type dopant ions are implanted into the first sub-epitaxy layer 210 to form an initial doped region 1 of the second conductivity type. In other words, the initial doped region 1 is formed in the first sub-epitaxy layer 210 using a process of hard mask deposition, photolithography, etching, ion implantation, and hard mask removal. A second conductivity type pillar structure 500 is formed using a process of trench hard mask deposition, photolithography, etching, hard mask removal, oxide filling, and chemical mechanical polishing. The description of the second conductivity type pillar structure 500 can be found in the detailed description of the above embodiments, and will not be repeated here.

[0095] Specifically, such as Figure 5 As shown in Figure (b), a hard mask is first deposited on the first sub-epitaxy layer 210, and the window pattern to be injected is defined using photolithography; the hard mask in the window area is etched away to expose the underlying first sub-epitaxy layer 210, and dopant ions of the second conductivity type are injected into the window area; the hard mask is then removed to form the initial doped region 1. Figure 5 As shown in Figure (c), a hard mask is re-deposited, the trench region is defined using photolithography, the hard mask and part of the initial doped region in the trench region are etched away, and the hard mask is removed to form the doped region 520. Figure 5 As shown in Figure (d), an oxide layer is filled in the trench region, and the surface is planarized by chemical mechanical polishing to form a filled dielectric layer 510. The filled dielectric layer 510 and the doped region 520 together constitute a second conductivity type pillar structure 500.

[0096] Step 420: A second sub-epitaxial layer 220 of a first conductivity type is formed on the side of the first sub-epitaxial layer 210 away from the substrate 100; the second sub-epitaxial layer 220 and the first sub-epitaxial layer 210 together constitute the epitaxial layer 200.

[0097] like Figure 6 As shown in Figure (a), a second sub-epitaxy layer 220 is formed on one side of the first sub-epitaxy layer 210 by performing a secondary growth on the substrate 100 using a chemical vapor phase epitaxy process. The description of the epitaxial layer 200 can be found in the detailed description of the above embodiments, and will not be repeated here.

[0098] Step 430: A well region 300 of a second conductivity type is formed in the second sub-epipolar layer 220; the well region 300 and the pillar structure 500 of the second conductivity type are spaced apart.

[0099] Step 440: Form a source region 400 of the first conductivity type within a well region 300 of the second conductivity type.

[0100] P-type and N-type impurities are implanted into the second sub-epitaxial layer 220 to form a well region 300 and a source region 400.

[0101] Specifically, such as Figure 6 As shown in Figure (b), a photolithography / mask is used to define a doped ion implantation region of the second conductivity type, blocking other regions. Doped ions of the second conductivity type are implanted in the corresponding implantation region to form a well region 300 of the second conductivity type. A photolithography / mask is used to define an N-type impurity implantation region, blocking other regions. Doped ions of the first conductivity type are implanted in the corresponding implantation region to form a source region 400 of the first conductivity type. For a detailed description of the well region 300 and the source region 400, please refer to the above embodiments, and it will not be repeated here.

[0102] Step 450: A first trench gate structure 600 is formed on the side of the second conductivity type pillar structure 500 away from the substrate 100; the first trench gate structure 600 includes a first trench gate 610 and a first gate dielectric layer 620; the first trench gate 610 extends from the source region 400 through the well region 300 into the epitaxial layer 200; the first gate dielectric layer 620 surrounds the sidewall of the first trench gate 610 and the side close to the second conductivity type pillar structure 500.

[0103] Step 460: A second trench gate structure 700 is formed on the side adjacent to the first trench gate structure 600; the second trench gate structure 700 and the first trench gate structure 600 have a spacing; the second trench gate structure 700 includes a second trench gate 710 and a second gate dielectric layer 720; the second trench gate 710 extends from the source region 400 through the well region 300 into the epitaxial layer 200; the second gate dielectric layer 720 surrounds the sidewalls of the second trench gate 710 and the side close to the substrate 100.

[0104] like Figure 6 As shown in Figure (c), trench hard mask deposition, photolithography, etching, and hard mask removal are used to form the first trench 2 and the second trench 3. Figure 6 As shown in Figure (d), a gate oxide layer is filled in the first trench 2 and the second trench 3, and then polysilicon is filled in to form a first trench gate structure 600 and a second trench gate structure 700. A detailed description of the first trench gate structure 600 and the second trench gate structure 700 is given in the above embodiments and will not be repeated here.

[0105] In this embodiment, the semiconductor device structure formed includes a second conductivity type pillar structure 500. The doped region 520 in the second conductivity type pillar structure 500 can act as an "electric field shield" to protect the filled dielectric layer 510 in the second conductivity type pillar structure 500. The filled dielectric layer 510 in the second conductivity type pillar structure 500 can optimize the electric field strength of the first gate dielectric layer 620 and the second gate dielectric layer 720, and play the role of isolating cells and maintaining the breakdown voltage of cells, which can effectively improve the reliability of the first gate dielectric layer 620 and the second gate dielectric layer 720. The presence of the filled dielectric layer 510 in the second conductivity type pillar structure 500 can change the electric field peak distribution near the first trench gate 610 and the second trench gate 710 under high voltage, which helps to alleviate the hot carrier injection effect, thereby delaying the lifetime of the semiconductor device structure and improving the performance of the semiconductor device structure.

[0106] In addition, the material of the filling dielectric layer 510 is oxide. The relative permittivity of oxide is lower than that of the epitaxial layer 200. The filling dielectric layer 510 can effectively reduce the gate-drain capacitance (Miller capacitance), thereby reducing Miller charge and significantly accelerating the switching speed of the semiconductor device structure and reducing switching losses.

[0107] In one embodiment, the number of second conductive type pillar structures 500 and the number of first trench gate structures 600 are both multiple; the multiple second conductive type pillar structures 500 are arranged at intervals along a first direction, and the multiple first trench gate structures 600 are arranged at intervals along a first direction.

[0108] In the Y direction, the first trench gate structure 600 is disposed directly above the second conductivity type pillar structure 500. The number of second conductivity type pillar structures 500 is the same as the number of first trench gate structures 600. In the X direction, there is a spacing between adjacent second conductivity type pillar structures 500, and there is also a spacing between adjacent first trench gate structures 600, and the spacing between adjacent second conductivity type pillar structures 500 is smaller than the spacing between first trench gate structures 600.

[0109] In this embodiment, the design of multiple second conductivity type pillar structures 500 and multiple first trench gate structures 600 can reduce on-resistance and optimize the density of the semiconductor device structure, thereby reducing the area of ​​the semiconductor device. Furthermore, it can further optimize the electric field strength of the first gate dielectric layer 620 and the second gate dielectric layer 720, improving the reliability of the semiconductor device structure.

[0110] In one embodiment, the number of formed second trench gate structures 700 is multiple, the multiple second trench gate structures 700 are located between adjacent first trench gate structures 600, and the multiple second trench gate structures 700 are arranged at intervals along a first direction.

[0111] In the X direction, a plurality of second trench gate structures 700 are arranged at intervals between two adjacent first trench gate structures 600. The spacing between two adjacent second trench gate structures 700 and the spacing between a second trench gate structure 700 adjacent to a first trench gate structure 600 and the first trench gate structure 600 are the same. Specifically, the spacing between two adjacent second trench gate structures 700 is 0.2 micrometers.

[0112] In this embodiment, the multiple second trench gate structures 700 are three-dimensional fin-shaped channels and three-sided gate-surrounding structures, which can form high-density cells, optimize the electric field distribution near the second trench gate, improve the breakdown voltage, reduce Miller capacitance, improve the switching speed of the semiconductor device structure and reduce switching losses.

[0113] In one embodiment, along the second direction, the side of the first trench gate 610 away from the substrate 100 and the side of the second trench gate 710 away from the substrate 100 are both lower than the side of the source region 400 away from the substrate 100; the first direction and the second direction intersect.

[0114] In the Y direction, the distance between the substrate 100 and the side of the first trench gate 610 away from the substrate 100 is less than the distance between the substrate 100 and the side of the source region 400 away from the substrate 100. Similarly, in the Y direction, the distance between the substrate 100 and the side of the second trench gate 710 away from the substrate 100 is less than the distance between the substrate 100 and the side of the source region 400 away from the substrate 100.

[0115] Based on this, the preparation method also includes:

[0116] An interlayer dielectric layer 800 is formed on the side of the first trench gate 610 away from the substrate 100 and the side of the second trench gate 710 away from the substrate 100; the side of the interlayer dielectric layer 800 away from the substrate 100 is flush with the side of the source region 400 away from the substrate 100.

[0117] An initial interlayer dielectric is formed on the side of the first trench gate 610 and the second trench gate 710 away from the substrate 100 using an interlayer dielectric deposition and contact hole etching process. The initial interlayer dielectric is then etched to form an interlayer dielectric layer 800. Contact holes are also etched to expose the source region 400 for subsequent connection of the source 900.

[0118] In this embodiment, the interlayer dielectric layer 800 achieves electrical isolation, preventing short circuits and leakage between the first trench gate 610 and the second trench gate 710. It also allows for surface planarization of the semiconductor device structure, ensuring the smooth operation of subsequent processes. Furthermore, the interlayer dielectric layer 800 protects the underlying devices, improving the reliability of the semiconductor device structure.

[0119] In one embodiment, see Figure 7 The flowchart, and combined with Figure 6 The preparation process is shown in Figure (e), and the preparation method further includes:

[0120] Step 700: A first gate contact hole is formed on the side of the source region 400 away from the substrate 100; the first gate contact hole exposes the first trench gate 610.

[0121] A first gate contact hole is formed on the side of the source region 400 away from the substrate 100 using a mask and etching process to expose the first trench gate 610.

[0122] Step 710: A source electrode 900 and a first gate lead-out electrode are formed on the side of the source region 400 away from the substrate 100; the source electrode 900 is electrically connected to the source region 400; the first gate lead-out electrode is electrically connected to the first trench gate 610.

[0123] A metal layer is deposited on the side of the source region 400 away from the substrate 100 to form a source electrode 900, and a first gate lead electrode is formed in the first gate contact hole so that the first gate lead electrode is electrically connected to the first trench gate 610, so that the driving circuit of the semiconductor device can output a driving signal to the first trench gate 610.

[0124] Step 720: A drain 910 is formed on the side of the substrate 100 away from the epitaxial layer 200; the drain 910 is electrically connected to the substrate 100.

[0125] A metal layer is deposited on the side of the substrate 100 away from the epitaxial layer 200 to form a drain 910.

[0126] Similarly, in one embodiment, while a first gate contact hole is formed on the side of the source region 400 away from the substrate 100, a second gate contact hole is also formed on the side of the source region 400 away from the substrate 100; the second gate contact hole exposes the second trench gate 710. While a source electrode 900 and a first gate lead-out electrode are formed on the side of the source region 400 away from the substrate 100, a second gate lead-out electrode is also formed; the second gate lead-out electrode is electrically connected to the second trench gate 710.

[0127] For a detailed description of the source 900, drain 910, first gate lead-out electrode, and second gate lead-out electrode, please refer to the above embodiments, and they will not be repeated here.

[0128] In one embodiment, this application provides a semiconductor. The semiconductor includes the semiconductor device structure provided in the above embodiments, or a semiconductor device structure made by the fabrication method of the semiconductor device structure provided in the above embodiments.

[0129] The semiconductor provided in this embodiment includes the semiconductor device structure of the above embodiments. Therefore, the semiconductor has all the beneficial effects of the semiconductor device structure, which will not be repeated here.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate; An epitaxial layer of the first conductivity type is located on one side of the substrate; A well region of the second conductivity type is located within the epitaxial layer; The second conductivity type is the opposite of the first conductivity type; A source region of the first conductivity type is located within the well region; The second conductivity type pillar structure includes a filling dielectric layer and a doped region of the second conductivity type; The filling dielectric layer is located within the epitaxial layer; the doped region surrounds the sidewall of the filling dielectric layer and the side close to the substrate, and has a distance from both the substrate and the well region; A first trench gate structure is located on the side of the second conductivity type pillar structure away from the substrate; the first trench gate structure includes a first trench gate and a first gate dielectric layer; the first trench gate extends from the source region through the well region into the epitaxial layer; the first gate dielectric layer surrounds the sidewall of the first trench gate and the side close to the second conductivity type pillar structure. The second trench gate structure is located on one side of the first trench gate structure and has a gap with the first trench gate structure; the second trench gate structure includes a second trench gate and a second gate dielectric layer; the second trench gate extends from the source region through the well region into the epitaxial layer; the second gate dielectric layer surrounds the sidewall of the second trench gate and the side close to the substrate.

2. The semiconductor device structure according to claim 1, characterized in that, The number of the second conductive type pillar structure and the number of the first trench gate structure are both multiple; the multiple second conductive type pillar structures are arranged at intervals along the first direction, and the multiple first trench gate structures are arranged at intervals along the first direction.

3. The semiconductor device structure according to claim 2, characterized in that, The number of second trench gate structures is multiple, and the multiple second trench gate structures are located between adjacent first trench gate structures, and the multiple second trench gate structures are arranged at intervals along the first direction.

4. The semiconductor device structure according to claim 3, characterized in that, Along the second direction, the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate are both lower than the side of the source region away from the substrate; The semiconductor device structure also includes: An interlayer dielectric layer is located on the side of the first trench gate away from the substrate and on the side of the second trench gate away from the substrate; The side of the interlayer dielectric layer away from the substrate is flush with the side of the source region away from the substrate; the first direction and the second direction intersect.

5. The semiconductor device structure according to any one of claims 1 to 4, characterized in that, The semiconductor device structure also includes: The source electrode is located on the side of the source region away from the substrate and is at least electrically connected to the source region; The drain electrode is located on the side of the substrate away from the epitaxial layer and is electrically connected to the substrate. The first gate lead-out electrode is electrically connected to the first trench gate.

6. A method for fabricating a semiconductor device structure, characterized in that, The preparation method includes: A substrate is provided, and a first sub-epipolar layer of a first conductivity type is formed on one side of the substrate; A second conductivity type pillar structure is formed within the first sub-epitaxial layer; the second conductivity type pillar structure includes a filling dielectric layer and a doped region of the second conductivity type; the doped region surrounds the sidewall of the filling dielectric layer and the side close to the substrate, and has a spacing with the substrate; A second sub-epitaxial layer of a first conductivity type is formed on the side of the first sub-epitaxial layer away from the substrate; the second sub-epitaxial layer and the first sub-epitaxial layer together constitute an epitaxial layer; A well region of a second conductivity type is formed within the second sub-epitaxial layer; the well region is spaced from the pillar structure of the second conductivity type. A source region of the first conductivity type is formed within a well region of the second conductivity type; A first trench gate structure is formed on the side of the second conductivity type pillar structure away from the substrate; the first trench gate structure includes a first trench gate and a first gate dielectric layer; the first trench gate extends from the source region through the well region into the epitaxial layer; the first gate dielectric layer surrounds the sidewall of the first trench gate and the side close to the second conductivity type pillar structure. A second trench gate structure is formed on one side adjacent to the first trench gate structure; the second trench gate structure has a spacing with the first trench gate structure; the second trench gate structure includes a second trench gate and a second gate dielectric layer; the second trench gate extends from the source region through the well region into the epitaxial layer; the second gate dielectric layer surrounds the sidewall of the second trench gate and the side close to the substrate.

7. The preparation method according to claim 6, characterized in that, The number of the second conductive type pillar structures and the number of the first trench gate structures are both multiple; the multiple second conductive type pillar structures are arranged at intervals along the first direction, and the multiple first trench gate structures are arranged at intervals along the first direction.

8. The preparation method according to claim 7, characterized in that, The number of the second trench gate structures formed is multiple, and the multiple second trench gate structures are located between adjacent first trench gate structures, and the multiple second trench gate structures are arranged at intervals along the first direction.

9. The preparation method according to claim 8, characterized in that, Along the second direction, both the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate are lower than the side of the source region away from the substrate; the first direction and the second direction intersect. The preparation method further includes: An interlayer dielectric layer is formed on the side of the first trench gate away from the substrate and the side of the second trench gate away from the substrate, wherein the side of the interlayer dielectric layer away from the substrate is flush with the side of the source region away from the substrate.

10. The preparation method according to any one of claims 6 to 9, characterized in that, The preparation method further includes: A first gate contact hole is formed on the side of the source region away from the substrate; the first gate contact hole exposes the first trench gate; A source electrode and a first gate electrode are formed on the side of the source region away from the substrate; the source electrode is electrically connected to the source region; the first gate electrode is electrically connected to the first trench gate. A drain is formed on the side of the substrate away from the epitaxial layer; the drain is electrically connected to the substrate.

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