A charge-coupled device having a floating gate structure
Patent Information
- Application Number
- CN202610712229.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-22
- Publication Date
- 2026-08-11
AI Technical Summary
[0003]在CCD器件的实际工作过程中，信号电荷的转移依赖于移位寄存器的栅极电压控制，通过施加不同的驱动脉冲，引导电荷在电荷沟道内有序转移，但传统CCD结构存在两大核心技术痛点：一是电荷转移过程中，难以在不影响电荷正常转移的前提下，实现对电荷数量的无损感应，导致器件无法在信号输出前根据电荷数量选择合适的输出通道，动态范围受到限制；二是埋沟型电子倍增CCD等器件中，光生电荷在硅材料内部存储、转移并发生雪崩倍增，当单个光敏单元或器件整体达到电荷容量上限时，过剩电荷会发生溢出，进而干扰相邻像素的光电转换，引发光晕现象，导致图像清晰度降低、信号失真，严重时甚至无法正常成像
[0029]与现有技术相比，本申请所达到的有益效果：本申请提供一种具有浮置栅结构的电荷耦合器件，通过多晶与势垒的结构设计，在CCD电荷转移沟道中形成局部势垒，使CCD器件的信号电荷数量多时，可以由进入此处局部势垒，而不被浮置栅感应到；在CCD器件的信号电荷数量少时，不进入局部势垒。这种结构可以保证无论电荷多少，都可以正常转移无残留。这种结构只增加了一个无源的浮置栅，完全不改变器件本身的工作方式和时序，因此，本结构适用于帧转移CCD、行间转移CCD等不同类型的器件。本申请使得CCD器件在信号输出前具有无损的感应电荷数量的能力，使得器件可以在信号输出前选择不同的输出通道，增加器件的动态范围；对于具备电子倍增或电子泄放结构的CCD器件，也可以通过无损感应结果控制倍增增益、电荷泄放功能的开启时机。
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Figure CN122555199A_ABST
Abstract
Description
Technical Field
[0001] This application relates to a charge-coupled device with a floating gate structure, belonging to the field of semiconductor technology. Background Technology
[0002] Charge-coupled devices (CCDs), as a core semiconductor imaging device, function primarily through registers composed of MOS capacitors to generate, store, transfer, and detect photogenerated signal charges. They are widely used in various fields such as aerial remote sensing, high-precision imaging, and scientific exploration. The performance of a CCD device directly depends on the stability of charge transfer, the accuracy of charge detection, and the ability to handle excess charge. Among these factors, the structural design of the charge transfer channel and the efficiency of excess charge dissipation are key factors affecting the imaging quality and dynamic range of the CCD.
[0003] In the actual operation of CCD devices, the transfer of signal charge depends on the gate voltage control of the shift register. By applying different driving pulses, the charge is guided to transfer in an orderly manner within the charge channel. However, traditional CCD structures have two major technical pain points: First, during the charge transfer process, it is difficult to achieve lossless sensing of the charge quantity without affecting the normal charge transfer. This results in the device being unable to select the appropriate output channel based on the charge quantity before signal output, thus limiting the dynamic range. Second, in devices such as buried trench electron multiplier CCDs, photogenerated charge is stored, transferred, and avalanche multiplication occurs inside the silicon material. When a single photosensitive unit or the entire device reaches the upper limit of charge capacity, the excess charge will overflow, thereby interfering with the photoelectric conversion of adjacent pixels, causing halo phenomena, resulting in reduced image clarity, signal distortion, and in severe cases, even failure to form a normal image.
[0004] Currently, most structural designs for CCD charge detection and channel gating require changes to the original operating mode and timing of the devices, resulting in poor compatibility and inability to adapt to different types of devices such as frame-transfer CCDs and interline-transfer CCDs. Summary of the Invention
[0005] The purpose of this application is to overcome the shortcomings of the prior art and provide a charge-coupled device with a floating gate structure. By using a floating gate structure for CCD channel selection and a barrier structure for CCD excess charge discharge, the above-mentioned technical pain points are solved.
[0006] To achieve the above objectives, this application employs the following technical solution:
[0007] This application provides a charge-coupled device with a floating gate structure, comprising:
[0008] Epitaxial layer, disposed on substrate;
[0009] Charge channels are located on the epitaxial layer;
[0010] The channel barrier is set on the epitaxial layer and located on both sides of the charge channel;
[0011] A dielectric layer is disposed on the upper surface of the charge channel and the channel resistance;
[0012] The polycrystalline silicon gate, from bottom to top, comprises a first layer of polycrystalline silicon and a second layer of polycrystalline silicon, disposed on the upper surface of the dielectric layer, serving as the functional electrode of the charge-coupled device. The first layer of polycrystalline silicon includes a first layer of polycrystalline charge transfer gate one, a first layer of polycrystalline charge transfer gate two, a first layer of polycrystalline charge transfer gate three, a first layer of polycrystalline charge transfer gate four, and a first layer of polycrystalline floating gate. The second layer of polycrystalline silicon includes a second layer of polycrystalline charge transfer gate one, a second layer of polycrystalline charge transfer gate two, and a second layer of polycrystalline charge transfer gate three. The first layer of polycrystalline charge transfer gate one, the second layer of polycrystalline charge transfer gate two, the first layer of polycrystalline charge transfer gate two, the first layer of polycrystalline charge transfer gate three, the second layer of polycrystalline charge transfer gate three, and the first layer of polycrystalline charge transfer gate four are sequentially overlapped along the X direction. The first layer of polycrystalline floating gate and the first layer of polycrystalline charge transfer gate two are aligned and spaced apart along the Y direction, and the second layer of polycrystalline charge transfer gate one, the first layer of polycrystalline floating gate, and the second layer of polycrystalline charge transfer gate two are sequentially overlapped along the X direction.
[0013] The trench is also connected to a floating gate blocking layer, which is located in the charge channel and below the intersection of the first polycrystalline floating gate and the second polycrystalline charge transfer gate.
[0014] The barrier injection is located on the epitaxial layer, in the charge channel and below the first polycrystalline floating gate, and is connected to the floating gate barrier layer and located upstream of the charge of the floating gate barrier layer.
[0015] In some embodiments, the barrier injection causes the potential in the region below the first polycrystalline floating gate to be lower than the potential when the second polycrystalline charge transfer gate is at a high level, while being higher than the potential when the second polycrystalline charge transfer gate is at a low level.
[0016] In some embodiments, the bottom of the floating gate barrier layer is connected to the epitaxial layer, and the top is connected to the dielectric layer.
[0017] In some embodiments, the barrier injection is connected to the epitaxial layer at the bottom and to the dielectric layer at the top. In this embodiment, the height of the barrier injection is equal to the height of the charge channel.
[0018] In some embodiments, the width of the floating gate barrier layer and the barrier injection along the Y direction is smaller than the width of the charge channel.
[0019] In some embodiments, the channel resistance is flush with the upper surface of the charge channel.
[0020] In some embodiments, the charge channel is a buried channel, achieved by doping the silicon material with n-type impurities.
[0021] In some embodiments, the trench barrier and floating gate barrier layer are implemented by heavily doping p+ type impurities in silicon material.
[0022] In some embodiments, the substrate is a wafer.
[0023] In some embodiments, the dielectric layer is a composite of at least one or more layers of silicon dioxide dielectric layer and silicon nitride dielectric layer.
[0024] In some embodiments, when the second layer polycrystalline charge transfer gate 1 is connected to a high-level drive to form a potential well to store charge, the drive voltage connected to the first layer polycrystalline charge transfer gate 1 and the first layer polycrystalline charge transfer gate 2 is at a low level, forming a potential barrier to prevent charge movement; when the level of the first layer polycrystalline charge transfer gate 2 increases, the level of the second layer polycrystalline charge transfer gate 1 decreases, and the charge moves below the first layer polycrystalline charge transfer gate 2; and so on, by switching between high and low levels, the signal charge moves in the order of the second layer polycrystalline charge transfer gate 1, the first layer polycrystalline charge transfer gate 2, the second layer polycrystalline charge transfer gate 3, the second layer polycrystalline charge transfer gate 4, and the first layer polycrystalline charge transfer gate 4.
[0025] In some embodiments, the charge-coupled device with a floating gate structure forms a non-uniform potential distribution in the Y direction of the charge channel at the barrier injection site by adding a floating gate blocking layer, a first polycrystalline floating gate, and barrier injection.
[0026] When the signal charge of the charge-coupled device is low, the barrier injection acts as a simple barrier, the charge transfer mechanism remains unchanged, and the first layer of polycrystalline floating gate cannot sense any charge.
[0027] When the signal charge of the charge-coupled device is high, the barrier injection acts as a potential well, and part of the signal charge is stored below the first polycrystalline floating gate, which can be detected non-destructively. The floating gate barrier layer prevents charge leakage. When the signal level of the first polycrystalline charge transfer gate 2 and the second polycrystalline charge transfer gate 1 switches, the charge below the first polycrystalline floating gate will naturally flow to the second polycrystalline charge transfer gate 1 and then transfer to the first polycrystalline charge transfer gate 2. Therefore, the charge transfer mechanism remains unchanged.
[0028] In this embodiment, the X direction is the length direction of the charge channel, and the Y direction is the width direction of the charge channel.
[0029] Compared with existing technologies, the beneficial effects achieved by this application are as follows: This application provides a charge-coupled device (CCD) with a floating gate structure. Through the structural design of polycrystalline material and a potential barrier, a local potential barrier is formed in the CCD charge transfer channel. When the signal charge quantity of the CCD device is large, it can enter this local potential barrier without being sensed by the floating gate; when the signal charge quantity of the CCD device is small, it will not enter the local potential barrier. This structure can ensure normal transfer without residue regardless of the charge quantity. This structure only adds a passive floating gate and does not change the device's operating mode or timing. Therefore, this structure is suitable for different types of devices such as frame-transfer CCDs and interline-transfer CCDs. This application enables the CCD device to have the ability to sense the amount of charge without loss before signal output, allowing the device to select different output channels before signal output and increasing the device's dynamic range. For CCD devices with electron multiplication or electron discharge structures, the timing of the activation of the multiplication gain and charge discharge functions can also be controlled through the lossless sensing results. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the charge-coupled device in an embodiment of this application.
[0031] Figure 2 for Figure 1 A schematic diagram of the cross-section in the vertical direction (Y direction).
[0032] Figure 3 for Figure 1 A schematic diagram of the horizontal (X-direction) cross-section.
[0033] Figure reference numerals: 1. Charge channel; 2. Channel resistance; 2-1. Floating gate barrier layer; 3. First layer polysilicon; 3-1. First layer polysilicon charge transfer gate one; 3-2. First layer polysilicon charge transfer gate two; 3-3. First layer polysilicon charge transfer gate three; 3-4. First layer polysilicon floating gate; 3-5. Second layer polysilicon; 4. Second layer polysilicon charge transfer gate one; 4-1. Second layer polysilicon charge transfer gate two; 4-2. Second layer polysilicon charge transfer gate three; 4-3. Barrier implantation; 5. Dielectric layer; 6. Epitaxial layer; 7. Detailed Implementation
[0034] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and should not be used to limit the scope of protection of the present application.
[0035] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] Charge channel 1, channel resistance 2, floating gate barrier layer 2-1, first layer polysilicon 3, first layer polysilicon charge transfer gate one 3-1, first layer polysilicon charge transfer gate two 3-2, first layer polysilicon charge transfer gate three 3-3, first layer polysilicon charge transfer gate four 3-4, first layer polysilicon floating gate 3-5, second layer polysilicon 4, second layer polysilicon charge transfer gate one 4-1, second layer polysilicon charge transfer gate two 4-2, second layer polysilicon charge transfer gate three 4-3, barrier implantation 5, dielectric layer 6, epitaxial layer 7.
[0038] Example 1, such as Figure 1 As shown in the figure, this embodiment introduces a charge-coupled device with a floating gate structure, including:
[0039] Epitaxial layer 7 is disposed on the substrate;
[0040] A charge channel 1 is disposed on the epitaxial layer 7;
[0041] The trench barrier 2 is disposed on the epitaxial layer 7 and located on both sides of the charge channel 1;
[0042] Dielectric layer 6 is disposed on the upper surface of the charge channel 1 and the channel resistance 2;
[0043] The polysilicon gate, from bottom to top, comprises a first polysilicon layer 3 and a second polysilicon layer 4, disposed on the upper surface of the dielectric layer 6, serving as the functional electrode of the charge-coupled device; wherein, the first polysilicon layer 3 includes a first polysilicon charge transfer gate 3-1, a first polysilicon charge transfer gate 3-2, a first polysilicon charge transfer gate 3-3, a first polysilicon charge transfer gate 4-4, and a first polysilicon floating gate 3-5; the second polysilicon layer 4 includes a second polysilicon charge transfer gate 4-1, a second polysilicon charge transfer gate 4-2, and a second polysilicon charge transfer gate 4-3; the first layer... Polycrystalline charge transfer gate 1 3-1, second layer polycrystalline charge transfer gate 1 4-1, second layer polycrystalline charge transfer gate 2 4-2, first layer polycrystalline charge transfer gate 2 3-2, first layer polycrystalline charge transfer gate 3-3, second layer polycrystalline charge transfer gate 3-3 and first layer polycrystalline charge transfer gate 4-4 are sequentially overlapped along the X direction, and the first layer polycrystalline floating gate 3-5 and the first layer polycrystalline charge transfer gate 2 3-2 are aligned and spaced apart along the Y direction. The second layer polycrystalline charge transfer gate 1 4-1, the first layer polycrystalline floating gate 3-5 and the second layer polycrystalline charge transfer gate 2 4-2 are sequentially overlapped along the X direction.
[0044] The trench barrier 2 is also connected to a floating gate barrier layer 2-1, which is located in the charge channel 1 and below the intersection of the first polycrystalline floating gate 3-5 and the second polycrystalline charge transfer gate 4-2.
[0045] The barrier injection 5 is disposed on the epitaxial layer 7, located in the charge channel 1 and below the first layer polycrystalline floating gate 3-5, and connected to the floating gate barrier layer 2-1 and located upstream of the charge of the floating gate barrier layer 2-1.
[0046] The potential injection 5 causes the potential in the region below the first polycrystalline floating gate 3-5 to be lower than the potential when the second polycrystalline charge transfer gate 4-1 is at a high level, while being higher than the potential when the first polycrystalline charge transfer gate 3-2 is at a low level.
[0047] In this embodiment, the X direction is the charge transfer direction (i.e., the length direction of the charge channel 1), and the Y direction is the width direction of the charge channel 1.
[0048] In some embodiments, the bottom of the floating gate barrier layer 2-1 is connected to the epitaxial layer 7, and the top is connected to the dielectric layer 6.
[0049] In some embodiments, the barrier injection 5 is connected to the epitaxial layer at the bottom and to the dielectric layer at the top. In this embodiment, the height of the barrier injection 5 is equal to the height of the charge channel 1. Figure 2 , Figure 3 As shown, the upper and lower surfaces of the barrier injection 5 are flush with the upper and lower surfaces of the charge channel 1, respectively.
[0050] It should be noted that the width of the floating gate barrier layer 2-1 and the barrier injection 5 along the Y direction is smaller than the width of the charge channel 1. Further, the width of the floating gate barrier layer 2-1 and the barrier injection 5 along the Y direction does not exceed 0.6 times the width of the charge channel 1, preferably 0.05 to 0.5 times, and more preferably about 0.4 times in this embodiment.
[0051] In some embodiments, the channel barrier 2 is flush with the upper surface of the charge channel 1.
[0052] In some embodiments, the substrate is a wafer. The epitaxial layer is a functional layer made of a semiconductor wafer.
[0053] In this embodiment, the charge channel 1 is a buried channel, achieved by doping the silicon material with n-type impurities. The channel barrier 2 and the floating gate barrier layer 2-1 are achieved by heavily doping the silicon material with p+ type impurities. The barrier injection 5 is achieved by additional doping the charge channel with p- type impurities in the silicon material.
[0054] In some embodiments, the dielectric layer 6 is composed of at least one or more layers of silicon dioxide dielectric layer and silicon nitride dielectric layer. It should be noted that the dielectric layer may be a single layer of silicon dioxide or silicon nitride, or it may be a composite of multiple layers, in different CCD devices or at different locations of the same CCD device. This does not affect the implementation of this patent, so it is not explicitly defined.
[0055] For example, the dielectric layer 6 includes a silicon dioxide dielectric layer and a silicon nitride dielectric layer arranged sequentially from bottom to top; the silicon dioxide dielectric layer is disposed on the upper surface of the charge channel 1 and the channel resistance 2, forming electrical isolation between the polysilicon gate and the silicon surface (including the charge channel 1 and the channel resistance 2), and serving to buffer the stress of the silicon nitride dielectric layer; the silicon nitride dielectric layer is disposed between the silicon dioxide dielectric layer and the polysilicon gate, and is used to improve the breakdown voltage between the polysilicon gate and the silicon surface.
[0056] The charge signal transfer of a CCD is achieved by a shift register, which typically includes a charge channel 1, a channel resistor 2, and a multilayer silicon gate (this application uses two layers, a first layer of polysilicon 3 and a second layer of polysilicon 4). The charge signal transfer is then achieved by applying different driving pulses to the polysilicon or by adding additional doping below the polysilicon.
[0057] To detect charge quantity non-destructively during CCD charge transfer without affecting the original charge transfer process, this application adds a floating gate barrier layer 2-1, a first polycrystalline floating gate 3-5, and a potential barrier injection 5 to create a non-uniform potential distribution at the vertical dashed line, such as... Figure 1 As shown. By adding an additional barrier injection 5 to the charge channel 1, the channel doping distribution is precisely controlled as follows. Figure 2 As shown.
[0058] The final CCD shift register, at the position where non-destructive signal detection is required, is divided into two parts by a multilayer silicon gate (first layer polycrystalline charge transfer gate 2 3-2 and first layer polycrystalline floating gate 3-5). The first layer polycrystalline charge transfer gate 2 3-2 is connected to the original drive signal to ensure that the original charge transfer operation is not affected; the first layer polycrystalline floating gate 3-5 acts as a floating gate, non-destructively sensing the amount of charge under the floating gate, and amplifying and reading out the signal through a connected amplifier.
[0059] A horizontal cross-sectional view of the floating grid structure is shown below. Figure 3 As shown, assuming the signal charge is transferred from right to left in the shift register (this is just an example; the structure does not affect the transfer direction), the working mechanism of this structure is as follows: When the second layer polycrystalline charge transfer gate 4-1 is connected to a high-level drive, it forms a potential well to store the charge; the drive voltage connected to the first layer polycrystalline charge transfer gate 3-1 and the first layer polycrystalline charge transfer gate 3-2 is low-level, forming a potential barrier and preventing the charge from moving left or right; when the level of the first layer polycrystalline charge transfer gate 3-2 increases, the level of the second layer polycrystalline charge transfer gate 4-1 decreases, and the charge moves below the first layer polycrystalline charge transfer gate 3-2; and so on. By switching between high and low levels, the signal charge moves from right to left in the order of the second layer polycrystalline charge transfer gate 4-1, the first layer polycrystalline charge transfer gate 3-2, the second layer polycrystalline charge transfer gate 4-2, the first layer polycrystalline charge transfer gate 3-3, the second layer polycrystalline charge transfer gate 3-3, and the first layer polycrystalline charge transfer gate 4-4.
[0060] This application creates a non-uniform potential distribution at the vertical dashed line (Y) by adding a floating gate barrier layer 2-1, a first layer of polycrystalline floating gate 3-5, and a potential barrier injection 5.
[0061] Specifically, the potential injection 5 ensures that the potential in this region is lower than the potential of the second polycrystalline charge transfer gate 4-1 when it is at a high level, and higher than the potential of the first polycrystalline charge transfer gate 3-2 when it is at a low level. Therefore, when the signal charge of the CCD is low, the potential injection 5 acts as a simple barrier, the charge transfer mechanism remains unchanged, and the first polycrystalline floating gate 3-5 cannot sense any charge. When the signal charge of the CCD is high, the potential injection 5 acts as a potential well, and part of the signal charge is stored below the first polycrystalline floating gate 3-5, which can be detected non-destructively. The floating gate barrier layer 2-1 prevents charge leakage. When the signal levels of the first polycrystalline charge transfer gate 3-2 and the second polycrystalline charge transfer gate 4-1 switch, the charge below the first polycrystalline floating gate 3-5 will naturally flow to the second polycrystalline charge transfer gate 4-1 and then transfer to the first polycrystalline charge transfer gate 3-2, thus the charge transfer mechanism remains unchanged.
[0062] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. A charge-coupled device with a floating gate structure, characterized in that, include: Epitaxial layer, disposed on substrate; Charge channels are located on the epitaxial layer; The channel barrier is set on the epitaxial layer and located on both sides of the charge channel; A dielectric layer is disposed on the upper surface of the charge channel and the channel resistance; The polycrystalline silicon gate, from bottom to top, comprises a first layer of polycrystalline silicon and a second layer of polycrystalline silicon, disposed on the upper surface of the dielectric layer, serving as the functional electrode of the charge-coupled device. The first layer of polycrystalline silicon includes a first layer of polycrystalline charge transfer gate one, a first layer of polycrystalline charge transfer gate two, a first layer of polycrystalline charge transfer gate three, a first layer of polycrystalline charge transfer gate four, and a first layer of polycrystalline floating gate. The second layer of polycrystalline silicon includes a second layer of polycrystalline charge transfer gate one, a second layer of polycrystalline charge transfer gate two, and a second layer of polycrystalline charge transfer gate three. The first layer of polycrystalline charge transfer gate one, the second layer of polycrystalline charge transfer gate two, the first layer of polycrystalline charge transfer gate two, the first layer of polycrystalline charge transfer gate three, the second layer of polycrystalline charge transfer gate three, and the first layer of polycrystalline charge transfer gate four are sequentially overlapped along the X direction. The first layer of polycrystalline floating gate and the first layer of polycrystalline charge transfer gate two are aligned and spaced apart along the Y direction, and the second layer of polycrystalline charge transfer gate one, the first layer of polycrystalline floating gate, and the second layer of polycrystalline charge transfer gate two are sequentially overlapped along the X direction. The trench is also connected to a floating gate blocking layer, which is located in the charge channel and below the intersection of the first polycrystalline floating gate and the second polycrystalline charge transfer gate. The barrier injection is located on the epitaxial layer, in the charge channel and below the first polycrystalline floating gate, and is connected to the floating gate barrier layer and located upstream of the charge of the floating gate barrier layer.
2. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The barrier injection causes the potential in the region below the first polycrystalline floating gate to be lower than the potential when the second polycrystalline charge transfer gate is at a high level, while being higher than the potential when the second polycrystalline charge transfer gate is at a low level.
3. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The bottom of the floating gate barrier layer is connected to the epitaxial layer, and the top is connected to the dielectric layer; And / or, the barrier injection bottom connection is connected to the epitaxial layer, and the top connection is connected to the dielectric layer.
4. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The width of the floating gate barrier layer and the barrier injection along the Y direction is smaller than the width of the charge channel.
5. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The channel resistance is flush with the upper surface of the charge channel.
6. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The charge channel is a buried channel, which is achieved by doping silicon material with n-type impurities; And / or, the trench barrier and floating gate barrier layer are achieved by heavily doping p+ type impurities in silicon material; And / or, the substrate is a wafer.
7. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, The dielectric layer is composed of at least one or more layers of silicon dioxide dielectric layer and silicon nitride dielectric layer.
8. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, When the second layer of polycrystalline charge transfer gate 1 is connected to a high-level drive to form a potential well to store charge, the driving voltage connected to the first layer of polycrystalline charge transfer gate 1 and the first layer of polycrystalline charge transfer gate 2 is low-level, forming a potential barrier to prevent charge movement. When the voltage level of the first layer polycrystalline charge transfer gate 2 increases, the voltage level of the second layer polycrystalline charge transfer gate 1 decreases, and the charge moves below the first layer polycrystalline charge transfer gate 2. In this way, by switching between high and low voltage levels, the signal charge moves in the order of the second layer polycrystalline charge transfer gate 1, the first layer polycrystalline charge transfer gate 2, the second layer polycrystalline charge transfer gate 2, the first layer polycrystalline charge transfer gate 3, the second layer polycrystalline charge transfer gate 4, and so on.
9. The charge-coupled device with a floating gate structure according to claim 1, characterized in that, By adding a floating gate barrier layer, a first-layer polycrystalline floating gate, and barrier injection, a non-uniform potential distribution in the Y direction of the charge channel at the barrier injection site is formed. When the signal charge of the charge-coupled device is low, the barrier injection acts as a simple barrier, the charge transfer mechanism remains unchanged, and the first layer of polycrystalline floating gate cannot sense any charge. When the signal charge of the charge-coupled device is high, the barrier injection acts as a potential well, and part of the signal charge is stored below the first polycrystalline floating gate, which can be detected non-destructively. The floating gate barrier layer prevents charge leakage. When the signal level of the first polycrystalline charge transfer gate 2 and the second polycrystalline charge transfer gate 1 switches, the charge below the first polycrystalline floating gate will naturally flow to the second polycrystalline charge transfer gate 1 and then transfer to the first polycrystalline charge transfer gate 2. Therefore, the charge transfer mechanism remains unchanged.
10. The charge-coupled device with a floating gate structure according to any one of claims 1-9, characterized in that, The X direction is the length direction of the charge channel, and the Y direction is the width direction of the charge channel.