A high-voltage-resistant low-loss super-junction MOS device and a preparation method thereof

Abstract

The application relates to the technical field of super-junction MOS, and discloses a high-voltage-resistant and low-loss super-junction MOS device and a preparation method thereof, which comprises the following steps: a bottom layer of a substrate has an N-type heavily doped region, the N-type heavily doped region has a drain electrode below, the N-type heavily doped region has an N-type buffer region above, the N-type buffer region has a P-type well region and an N-type well region above, the P-type well region is arranged on both sides of the N-type well region, the P-type well region has a P-type heavily doped region above, the N-type well region has an N-type extension region and a gate region above, the N-type extension region is arranged on both sides of the gate region, the P-type heavily doped region and the N-type extension region have a P-type shallow doped region above, the P-type shallow doped region is arranged on both sides of the gate region, the P-type shallow doped region has an N-type electrode region and a P-type electrode region above, the N-type electrode region and the P-type electrode region are arranged on both sides of the gate region, the N-type electrode region is in contact with the gate region, the P-type electrode region is in contact with the N-type electrode region, the N-type electrode region and the P-type electrode region have a source electrode above, and the gate region has a gate electrode above. The super-junction MOS realizes the effects of high-voltage resistance and low loss.

Description

Technical Field

[0001] This invention relates to the field of superjunction MOS technology, specifically to a high-voltage, low-loss superjunction MOS device and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of the electronics industry, power semiconductor devices have played an important role in modern power electronic systems. These power semiconductor devices are mainly based on silicon substrates. However, silicon substrates are easily limited by the material itself. There is a "silicon limit" relationship between its specific on-resistance and breakdown voltage. When the voltage withstand requirement of the device (such as increasing from 600V to 1200V or higher) increases exponentially, the thickened low-doped region to achieve the voltage withstand will cause its on-resistance to increase exponentially. This leads to a situation where high voltage withstand and low conduction loss are mutually exclusive in traditional silicon devices. In other words, a large amount of conduction loss is paid for improving the voltage withstand, which seriously restricts the efficiency improvement under high voltage applications. Later, the superjunction structure was applied to MOS chips. However, the existing superjunction structure has some defects. Although it has improved the on-resistance, the reduction of on-resistance in high-voltage applications will result in a reduction of losses, but at the cost of sacrificing the high-voltage margin. If the high voltage is increased, the on-resistance will increase and the losses will increase, affecting the performance of power devices. For example, common power devices with a high voltage of no more than 1200V and a current of no more than 60A will have an on-resistance higher than 35mΩ.

[0003] Therefore, existing power device technologies need further improvement. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage, low-loss superjunction MOS device and its fabrication method. By using a compound semiconductor substrate, N-type heavily doped region, drain electrode, N-type buffer region, P-type well region and N-type well region, P-type heavily doped region, N-type extended region and gate region, P-type lightly doped region, N-type electrode region and P-type electrode region, source electrode and gate electrode are fabricated on it. Combined with the fabrication process, this forms a superjunction MOS chip, which can achieve the advantages of trench gate MOS devices, as well as better high-voltage resistance and low loss.

[0005] The specific technical solution of the present invention is as follows: A high-voltage, low-loss superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well region being disposed on both sides of the N-type well region; a P-type heavily doped region on the P-type well region; and an N-type extended region and a gate region on the N-type well region. On both sides of the gate region, a lightly doped P-type region is provided on the upper surface of the heavily doped P-type region and the extended N-type region. The lightly doped P-type region is located on both sides of the gate region. An N-type electrode region and a P-type electrode region are provided on the upper surface of the lightly doped P-type region. The N-type electrode region and the P-type electrode region are located on both sides of the gate region, and the N-type electrode region is in contact with the gate region. The P-type electrode region is in contact with the N-type electrode region, and the P-type electrode region is located away from the gate region. A source electrode is provided on the N-type electrode region and the P-type electrode region, and a gate electrode is provided on the gate region.

[0006] Furthermore, the drain electrode, source electrode, and gate electrode are all made of aluminum or copper. As electrode materials for power devices, they can be deposited well on the substrate surface, form conductive interconnects with the doped regions on the substrate, and balance conductivity and thermal conductivity, thereby reducing costs and improving reliability.

[0007] Furthermore, the substrate is selected from semiconductor silicon carbide material, semiconductor gallium nitride material, or semiconductor gallium oxide material; it has the advantages of wide bandgap semiconductor materials and can withstand high voltage, high frequency, and high temperature environments.

[0008] Furthermore, the substrate is selected from 6-inch, 8-inch, 12-inch, and other specifications.

[0009] Furthermore, the gate region includes an insulating layer and a polysilicon layer. The insulating layer wraps around the side and bottom surfaces of the polysilicon layer and is in contact with the N-type well region, N-type extended region, P-type shallow doped region, and N-type electrode region. A gate electrode is provided on the upper surface of the polysilicon layer. This trench gate structure allows for the formation of a conductive channel through the vertical gate sidewalls, enabling the current to flow directly downwards, shortening the path, eliminating JFET region losses, and helping to reduce on-resistance.

[0010] Furthermore, the insulating layer is a high-k insulating material of elemental composition, a high-k insulating material of compound composition, or an insulating oxide material. This can reduce gate leakage current, improve the withstand voltage and reliability of the insulating layer, etc. Examples include hafnium oxynitride.

[0011] Furthermore, the thickness of the insulating layer is less than the thickness of the polycrystalline silicon layer.

[0012] Furthermore, the P-type well region is symmetrically arranged with respect to the centerline of the N-type well region. When the N-type well region dominates the operation, the symmetrical P-type well region facilitates symmetrical and balanced conduction, avoiding the impact of asymmetry in the P-type well region on the N-type well region, such as compression or displacement, which would lead to unbalanced current paths, increased on-resistance, and increased losses.

[0013] Furthermore, the center line of the N-type well region coincides with the center line of the gate region.

[0014] Furthermore, the height of the P-type well region is equal to the height of the N-type well region.

[0015] Furthermore, each of the P-type well regions has the same width, which is half the width of the N-type well region.

[0016] It can make the internal electric field distribution of the device uniform, and help improve the breakdown voltage. It avoids the uneven electric field caused by height difference, which causes differences in the reception of the N-type buffer and leads to uneven high voltage resistance.

[0017] Furthermore, the N-type ion concentration in the heavily doped N-type region is greater than the N-type ion concentration in the N-type buffer zone, which is greater than the N-type ion concentration in the N-type well region. The heavily doped N-type region provides an ohmic contact for the drain electrode and facilitates carrier inflow; the N-type buffer zone reduces on-resistance, mitigates carrier impacts (such as positive and negative charges), and protects the device.

[0018] Furthermore, both the P-type heavily doped region and the N-type extended region are symmetrically arranged with respect to the center line of the gate region. This symmetrical arrangement facilitates balanced conduction and avoids the effects of asymmetry.

[0019] Furthermore, the thickness of the heavily doped P-type region and the extended N-type region are the same. This helps to balance the lightly doped P-type region and the P-type well region and the N-type well region. The extended N-type region facilitates rapid conduction with the N-type well region after the formation of the N-channel in the trench gate. The heavily doped P-type region can also supply corresponding charge carriers to the P-type well region and the lightly doped P-type region.

[0020] Furthermore, the width of the P-type heavily doped region is greater than the width of the N-type extended region.

[0021] Furthermore, both the N-type electrode region and the P-type electrode region are symmetrically arranged with respect to the center line of the gate region. This symmetrical arrangement facilitates balanced conduction and avoids the effects of asymmetry. Since the source electrodes need to be connected to the N-type and P-type electrode regions, the symmetrical arrangement helps ensure balanced operation of the two source electrodes. The P-type electrode region also facilitates low-resistance ohmic contact with the lightly doped P-type region, enabling the extraction of hole current at the source electrode.

[0022] Furthermore, the thicknesses of the N-type electrode region and the P-type electrode region are the same.

[0023] Furthermore, the width of the N-type electrode region is smaller than the width of the P-type electrode region.

[0024] Furthermore, the P-type shallow doped region is symmetrically arranged with respect to the center line of the gate region. This symmetrical arrangement facilitates balanced conduction and avoids the effects of asymmetry; it also ensures that the trench gate channel is uniformly formed, contributing to lower voltage withstand and lower losses.

[0025] Furthermore, the thickness of the shallowly doped P-type region is greater than the thickness of the heavily doped P-type region and the extended N-type region.

[0026] Furthermore, a P-type well extension region is provided above the P-type well region, which is located above the N-type well region and on the lower surface of the N-type extension region. The P-type well extension region is in contact with the P-type well region. This can help reduce gate-drain capacitance, improve the high electric field at the bottom of the gate trench, and enhance device reliability.

[0027] Furthermore, the P-type ion concentration in the P-type well extension region is greater than the P-type ion concentration in the P-type well region.

[0028] Furthermore, the width of the P-type well extension region is smaller than the width of the N-type extension region.

[0029] Furthermore, a method for fabricating a high-voltage, low-loss superjunction MOS device, the steps of which are as follows: Step 1: Structural Design of Superjunction MOS Devices The superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well regions being disposed on both sides of the N-type well regions; a P-type heavily doped region on the P-type well regions; and an N-type extended region and a gate region on the N-type well regions, the N-type extended regions being disposed on both sides of the gate region. The upper surfaces of the heavily doped P-type region and the extended N-type region are provided with the lightly doped P-type region, which is disposed on both sides of the gate region. The upper surfaces of the lightly doped P-type region are provided with the N-type electrode region and the P-type electrode region, which are disposed on both sides of the gate region. The N-type electrode region is in contact with the gate region, and the P-type electrode region is in contact with the N-type electrode region. The P-type electrode region is far away from the gate region. The source electrode is provided on the N-type electrode region and the P-type electrode region, and the gate electrode is provided on the gate region. Step 2: Formation of the substrate with an N-type buffer Based on the structural design in step 1, a semiconductor wafer is selected as the substrate. The upper and lower surfaces of the substrate are cleaned to remove surface oxides and oil stains. RCA cleaning agent is used for cleaning, followed by rinsing with deionized water and drying in a nitrogen environment. After drying, a layer of positive photoresist is coated on the lower surface of the substrate. The substrate is exposed using a photolithography machine according to a pre-designed mask pattern with an N-type buffer. The exposed photoresist area is then developed and removed to expose the N-type buffer to be implanted by ions. The substrate is then transferred to an N-type ion implanter, where N-type ions are lightly doped into the substrate to obtain a substrate with an N-type buffer. Step 3: Formation of a substrate with heavily doped N-type regions Based on step 2, on the substrate with an N-type buffer, and located at the lower part of the N-type buffer, N-type ions are heavily doped using an N-type ion implanter. The N-type ions are heavily doped into the lower part of the substrate with the N-type buffer and extend to the lower surface of the substrate. Then, the remaining unexposed photoresist is removed using a photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a heavily doped N-type region. Step 4: Formation of the substrate with drain electrode Based on step 3, a substrate with heavily N-type doped regions is selected and transferred to a wafer electroplating machine. A conductive metal layer is electroplated on the lower surface of the substrate, and then a negative photoresist layer is coated on the conductive metal layer. Exposure is performed using a photolithography machine with a mask pattern for the drain electrode. Here, the mask pattern for the drain electrode is the same as the mask pattern for the N-type buffer. Figure 1 Then, the non-exposed photoresist is developed and cleaned to expose the non-drain electrode area. The metal conductive layer of the non-drain electrode area is cleaned by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution. After cleaning with deionized water, it is dried in a nitrogen atmosphere to form a substrate with a drain electrode. Step 5: Formation of the substrate with N-type well regions Based on step 4, a substrate with a drain electrode is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type well region. The exposed photoresist is then developed, cleaned and removed to expose the N-type well region. The substrate is then transferred to an N-type ion implanter, and N-type ions are lightly doped into the N-type well region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type buffer zone is reached. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type well region. Step 6: Formation of the substrate with P-type well regions Based on step 5, a substrate with an N-type well region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type well region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type well region. The substrate is then transferred to a P-type ion implanter, and P-type ions are lightly doped into the P-type well region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type buffer zone is reached. At this point, the N-type well region and the P-type well region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type well region. Step 7: Formation of the substrate with the gate region Based on step 6, a substrate with a P-type well region is selected. A silicon dioxide layer is deposited on the upper surface of the substrate using PECVD (Plasma Enhanced Chemical Vapor Deposition). A silicon nitride layer is then deposited on the upper surface of the silicon dioxide layer, and a positive photoresist layer is coated on its upper surface. Photolithography is performed according to the pre-designed mask pattern of the gate region. The exposed photoresist is then developed and cleaned to remove it, exposing the gate region. This exposed region is then placed in an ion etching machine, where the gate region is etched from the upper surface of the silicon nitride layer of the substrate onto the upper surface of the N-type well region using the ion etching machine. The remaining unexposed photoresist is removed using a photoresist stripping solution, then cleaned with deionized water, and dried in a nitrogen atmosphere to form a gate trench region. An insulating layer is then deposited on the inner wall of the gate trench region using HDPCVD (high-density plasma chemical vapor deposition) technology. A polysilicon layer is then deposited on the inner wall of the insulating layer to fill the gate trench region. Finally, CMP (chemical mechanical polishing) technology is used to polish away the polysilicon, insulating layer, silicon nitride, and silicon dioxide until the upper surface of the substrate is reached, forming a substrate with the gate region. Step 8: Formation of the substrate with the N-type extended region Based on step 7, a substrate with a gate region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type extended region. The exposed photoresist is then developed and cleaned to remove it, exposing the N-type extended region. The N-type extended region is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type extended region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type well region is reached. At this point, the N-type extended region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with an N-type extended region. Step 9: Formation of a substrate with heavily p-type doped regions Based on step 8, a substrate with an N-type extended region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type heavily doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type heavily doped region. The region is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type heavily doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the P-type well region is reached. At this point, the P-type heavily doped region and the N-type extended region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type heavily doped region. Step 10: Formation of a substrate with shallow p-type doped regions Based on step 9, a substrate with a heavily P-type doped region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the lightly P-type doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the lightly P-type doped region. The substrate is then placed in a P-type ion implanter, and P-type ions are lightly doped into the lightly P-type doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type extended region and the heavily P-type doped region. At this point, the lightly P-type doped region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with a lightly P-type doped region. Step 11: Formation of the substrate with N-type electrode regions Based on step 10, a substrate with a lightly doped P-type region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the N-type electrode region. The substrate is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type electrode region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the N-type electrode region and the gate region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type electrode region. Step 12: Formation of the substrate with P-type electrode regions Based on step 11, a substrate with an N-type electrode region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the P-type electrode region. The substrate is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type electrode region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the P-type electrode region and the N-type electrode region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with a P-type electrode region. Step 13: Formation of the substrate with source and gate electrodes Based on step 12, a substrate with a P-type electrode region is selected and transferred to a wafer electroplating device. A metal conductive layer is electroplated on the upper surface of the substrate, and then a negative photoresist is coated on the metal conductive layer. Photolithography is performed according to the pre-designed mask pattern of the source electrode and the gate electrode. Then, the unexposed photoresist is developed and cleaned to remove it, exposing the areas of non-source electrode and non-gate electrode. The metal conductive layer of the non-source electrode and non-gate electrode areas is cleaned away by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with source electrode and gate electrode, thus fabricating a superjunction MOS device. Beneficial effects

[0030] This invention utilizes a compound semiconductor substrate on which N-type heavily doped regions, drain electrodes, N-type buffers, P-type and N-type well regions, heavily doped P-type regions, N-type extended regions and gate regions, lightly doped P-type regions, N-type and P-type electrode regions, source electrodes, and gate electrodes are fabricated. Combined with specific fabrication processes, a superjunction MOS chip is formed, possessing the advantages of trench-gate MOS devices while achieving better high-voltage withstand and low-loss performance. The trench gate region, combined with a lightly doped P-type region, improves high-voltage withstand characteristics while reducing specific on-resistance losses. The N-type extended region further reduces specific on-resistance losses. The combination of an N-type well region and two P-type well regions enhances high-voltage withstand performance. The N-type buffer further enhances high-voltage withstand. Furthermore, the combination of a P-type well extension region reduces gate-drain capacitance, further improving the performance of the superjunction MOS device. Its withstand voltage reaches 1700V and its on-resistance is 29mΩ. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of a high-voltage, low-loss superjunction MOS device according to the present invention.

[0032] Figure 2 This is a schematic diagram of the fabrication process of a high-voltage, low-loss superjunction MOS device according to the present invention.

[0033] Figure 3 This is a schematic diagram of another fabrication method for a high-voltage, low-loss superjunction MOS device according to the present invention.

[0034] Figure 4 This is a test diagram of the on-resistance of a high-voltage, low-loss superjunction MOS device according to the present invention.

[0035] Figure 5This is a breakdown voltage test diagram of a high-voltage, low-loss superjunction MOS device according to the present invention.

[0036] Figure descriptions: 01. Drain electrode; 02. Heavy N-type doped region; 03. N-type buffer zone; 04. P-type well region; 05. N-type well region; 06. P-type well extension region; 07. Heavy P-type doped region; 08. N-type extension region; 09. Light P-type doped region; 10. P-type electrode region; 11. N-type electrode region; 12. Insulating layer; 13. Polysilicon layer; 14. Gate electrode; 15. Source electrode. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] See Figure 1 As shown, this invention provides a high-voltage, low-loss superjunction MOS device and its fabrication method. The superjunction MOS device includes: a substrate, the substrate being made of a semiconductor material, specifically, silicon carbide, gallium nitride, or gallium oxide, and the substrate being a 6-inch, 8-inch, or 12-inch substrate; an N-type heavily doped region 02 is provided on the bottom layer of the substrate, a drain electrode 01 is provided on the lower surface of the N-type heavily doped region 02, an N-type buffer zone 03 is provided on the upper surface of the N-type heavily doped region 02, and a P-type well region 04 and an N-type well region 05 are respectively provided on the upper surface of the N-type buffer zone 03, with the P-type well region 04 located on both sides of the N-type well region 05, a P-type heavily doped region 07 on the P-type well region 04, and a P-type heavily doped region 07 on the N-type well region 05. An N-type extended region 08 and a gate region are provided. The N-type extended region 08 is disposed on both sides of the gate region. A P-type lightly doped region 09 is provided on the upper surface of the P-type heavily doped region 07 and the N-type extended region 08. The P-type lightly doped region 09 is disposed on both sides of the gate region. An N-type electrode region 11 and a P-type electrode region 10 are provided on the upper surface of the P-type lightly doped region 09. The N-type electrode region 11 and the P-type electrode region 10 are disposed on both sides of the gate region, and the N-type electrode region 11 is in contact with the gate region. The P-type electrode region 10 is in contact with the N-type electrode region 11, and the P-type electrode region 10 is far away from the gate region. A source electrode 15 is provided on the N-type electrode region 11 and the P-type electrode region 10. A gate electrode 14 is provided on the gate region. The drain electrode 01, the source electrode 15 and the gate electrode 14 are all made of aluminum or copper. The gate region includes an insulating layer 12 and a polysilicon layer 13. The insulating layer 12 wraps around the sides and bottom of the polysilicon layer 13. The insulating layer 12 is in contact with the N-type well region 05, the N-type extended region 08, the P-type shallow doped region 09, and the N-type electrode region 11. The insulating layer 12 is a high-k insulating material of elemental composition, a high-k insulating material of compound composition, or an insulating oxide material. The insulating layer 12 can be selected from hafnium oxynitride or silicon oxide. The thickness of the insulating layer 12 is less than the thickness of the polysilicon layer 13, and the thickness of the insulating layer 12 is selected to be 80 nm. The width of the polysilicon layer 13 is selected to be 2.5 μm. Specifically, the N-type ion concentration in the heavily doped N-type region 02 is greater than that in the N-type buffer zone 03, which is greater than that in the N-type well region 05; the N-type ion concentration in the heavily doped N-type region 02 is selected as 1.2 × 10⁻⁶. 19 cm -3 The N-type ion concentration in the N-type buffer zone 03 was selected to be 1.4 × 10⁻⁶. 17 cm -3 The N-type ion concentration in the N-type trap region 05 was selected to be 6 × 10⁵. 15 cm -3 The thickness of the heavily doped N-type region 02 is 300 nm; the thickness of the N-type buffer zone 03 is 500 nm; the height of the N-type well region 05 is 15 μm; and the width of the N-type well region 05 is 6 μm. The P-type well region 04 is symmetrically arranged around the centerline of the N-type well region 05; the height of each P-type well region 04 is equal to the height of the N-type well region 05, and the width of each P-type well region 04 is the same and half the width of the N-type well region 05; the height of each P-type well region 04 is 15 μm, the width of each P-type well region 04 is 3 μm, and the P-type ion concentration of each P-type well region 04 is selected as 8 × 10⁻⁶. 15 cm -3 ; In this design, both the P-type heavily doped region 07 and the N-type extended region 08 are symmetrically arranged around the centerline of the gate region; both the P-type heavily doped region 07 and the N-type extended region 08 have the same thickness, which is 1 μm; the width of the P-type heavily doped region 07 is greater than the width of the N-type extended region 08; and the P-type ion concentration of the P-type heavily doped region 07 is selected as 5 × 10⁻⁶. 17 cm -3 The N-type ion concentration in the N-type extension region 08 was selected to be 1.1 × 10⁸. 16 cm -3 ; Specifically, the P-type shallow doped region 09 is symmetrically arranged with the center line of the gate region as the reference point; the thickness of the P-type shallow doped region 09 is greater than the thickness of the P-type heavily doped region 07 and the N-type extended region 08; the thickness of the P-type shallow doped region 09 is selected as 1.3 μm, and the P-type ion concentration of the P-type shallow doped region 09 is selected as 1 × 10⁻⁶. 16cm -3 ; In this configuration, both the N-type electrode region 11 and the P-type electrode region 10 are symmetrically arranged with respect to the center line of the gate region; both the N-type electrode region 11 and the P-type electrode region 10 have the same thickness, which is 200 nm; the width of the N-type electrode region 11 is smaller than the width of the P-type electrode region 10; and the N-type ion concentration of the N-type electrode region 11 is selected as 1 × 10⁻⁶. 19 cm -3 The P-type ion concentration in the P-type electrode region 10 is selected to be 1×10⁻⁶. 19 cm -3 ; The P-type well region 04 has a P-type well extension region 06 located above the N-type well region 05 and on the lower surface of the N-type extension region 08. The P-type well extension region 06 is in contact with the P-type well region 04. The P-type ion concentration in the P-type well extension region 06 is greater than that in the P-type well region 04. The width of the P-type well extension region 06 is less than the width of the N-type extension region 08. The width of the P-type well extension region 06 is 1 μm. The height of the P-type well extension region 06 is 1 μm. The P-type ion concentration in the P-type well extension region 06 is 1.5 × 10⁻⁶. 17 cm -3 ; Among them, see Figure 2 As shown, one embodiment is described: a method for fabricating a high-voltage, low-loss superjunction MOS device, the steps of which are as follows: Step 1: Structural Design of Superjunction MOS Devices The superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well regions being disposed on both sides of the N-type well regions; a P-type heavily doped region on the P-type well regions; and an N-type extended region and a gate region on the N-type well regions, the N-type extended regions being disposed on both sides of the gate region. The upper surfaces of the heavily doped P-type region and the extended N-type region are provided with the lightly doped P-type region, which is disposed on both sides of the gate region. The upper surfaces of the lightly doped P-type region are provided with the N-type electrode region and the P-type electrode region, which are disposed on both sides of the gate region. The N-type electrode region is in contact with the gate region, and the P-type electrode region is in contact with the N-type electrode region. The P-type electrode region is far away from the gate region. The source electrode is provided on the N-type electrode region and the P-type electrode region, and the gate electrode is provided on the gate region. Step 2: Formation of the substrate with an N-type buffer Based on the structural design in step 1, a semiconductor wafer is selected as the substrate. The upper and lower surfaces of the substrate are cleaned to remove surface oxides and oil stains. RCA cleaning agent is used for cleaning, followed by rinsing with deionized water and drying in a nitrogen environment. After drying, a layer of positive photoresist is coated on the lower surface of the substrate. The substrate is exposed using a photolithography machine according to a pre-designed mask pattern with an N-type buffer. The exposed photoresist area is then developed and removed to expose the N-type buffer to be implanted by ions. The substrate is then transferred to an N-type ion implanter, where N-type ions are lightly doped into the substrate to obtain a substrate with an N-type buffer. Step 3: Formation of a substrate with heavily doped N-type regions Based on step 2, on the substrate with an N-type buffer, and located at the lower part of the N-type buffer, N-type ions are heavily doped using an N-type ion implanter. The N-type ions are heavily doped into the lower part of the substrate with the N-type buffer and extend to the lower surface of the substrate. Then, the remaining unexposed photoresist is removed using a photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a heavily doped N-type region. Step 4: Formation of the substrate with drain electrode Based on step 3, a substrate with heavily N-type doped regions is selected and transferred to a wafer electroplating machine. A conductive metal layer is electroplated on the lower surface of the substrate, and then a negative photoresist layer is coated on the conductive metal layer. Exposure is performed using a photolithography machine with a mask pattern for the drain electrode. Here, the mask pattern for the drain electrode is the same as the mask pattern for the N-type buffer. Figure 1 Then, the non-exposed photoresist is developed and cleaned to expose the non-drain electrode area. The metal conductive layer of the non-drain electrode area is cleaned by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution. After cleaning with deionized water, it is dried in a nitrogen atmosphere to form a substrate with a drain electrode. Step 5: Formation of the substrate with N-type well regions Based on step 4, a substrate with a drain electrode is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type well region. The exposed photoresist is then developed, cleaned and removed to expose the N-type well region. The substrate is then transferred to an N-type ion implanter, and N-type ions are lightly doped into the N-type well region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type buffer zone is reached. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type well region. Step 6: Formation of the substrate with P-type well regions Based on step 5, a substrate with an N-type well region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type well region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type well region. The substrate is then transferred to a P-type ion implanter, and P-type ions are lightly doped into the P-type well region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type buffer zone is reached. At this point, the N-type well region and the P-type well region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type well region. Step 7: Formation of the substrate with the gate region Based on step 6, a substrate with a P-type well region is selected. A silicon dioxide layer is deposited on the upper surface of the substrate using PECVD technology. A silicon nitride layer is deposited on the upper surface of the silicon dioxide layer, and a positive photoresist layer is coated on the upper surface of the silicon dioxide layer. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the gate region. The exposed photoresist is then developed and cleaned to remove it, exposing the gate region. The substrate is then placed in an ion etching machine, and the gate region is etched from the upper surface of the silicon nitride region of the substrate to the upper surface of the N-type well region using the ion etching machine. The remaining unexposed photoresist is then removed using a photoresist stripping solution, and the substrate is cleaned with deionized water. The substrate is then dried in a nitrogen atmosphere to form a gate trench region. An insulating layer is then deposited on the inner wall of the gate trench region using HDPCVD technology. A polysilicon layer is then deposited on the inner wall of the insulating layer to fill the gate trench region. Finally, the polysilicon, insulating layer, silicon nitride, and silicon dioxide are ground away using CMP technology until the upper surface of the substrate is reached, forming a substrate with a gate region. Step 8: Formation of the substrate with the N-type extended region Based on step 7, a substrate with a gate region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type extended region. The exposed photoresist is then developed and cleaned to remove it, exposing the N-type extended region. The N-type extended region is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type extended region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type well region is reached. At this point, the N-type extended region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with an N-type extended region. Step 9: Formation of a substrate with heavily p-type doped regions Based on step 8, a substrate with an N-type extended region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type heavily doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type heavily doped region. The region is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type heavily doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the P-type well region is reached. At this point, the P-type heavily doped region and the N-type extended region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type heavily doped region. Step 10: Formation of a substrate with shallow p-type doped regions Based on step 9, a substrate with a heavily P-type doped region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the lightly P-type doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the lightly P-type doped region. The substrate is then placed in a P-type ion implanter, and P-type ions are lightly doped into the lightly P-type doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type extended region and the heavily P-type doped region. At this point, the lightly P-type doped region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with a lightly P-type doped region. Step 11: Formation of the substrate with N-type electrode regions Based on step 10, a substrate with a lightly doped P-type region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the N-type electrode region. The substrate is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type electrode region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the N-type electrode region and the gate region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type electrode region. Step 12: Formation of the substrate with P-type electrode regions Based on step 11, a substrate with an N-type electrode region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the P-type electrode region. The substrate is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type electrode region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the P-type electrode region and the N-type electrode region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with a P-type electrode region. Step 13: Formation of the substrate with source and gate electrodes Based on step 12, a substrate with a P-type electrode region is selected and transferred to a wafer electroplating device. A metal conductive layer is electroplated on the upper surface of the substrate, and then a negative photoresist is coated on the metal conductive layer. Photolithography is performed according to the pre-designed mask pattern of the source electrode and the gate electrode. Then, the unexposed photoresist is developed and cleaned to remove it, exposing the areas of non-source electrode and non-gate electrode. The metal conductive layer of the non-source electrode and non-gate electrode areas is cleaned away by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with source electrode and gate electrode, thus fabricating a superjunction MOS device.

[0039] Among them, see Figure 3 As shown, another embodiment: a method for fabricating a high-voltage, low-loss superjunction MOS device, the steps of which are as follows: Step 1: Structural Design of Superjunction MOS Devices The superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well regions being disposed on both sides of the N-type well regions; a P-type heavily doped region on the P-type well regions; and an N-type extended region and a gate region on the N-type well regions, the N-type extended regions being disposed on both sides of the gate region. The upper surfaces of the heavily doped P-type region and the extended N-type region are provided with the lightly doped P-type region, which is disposed on both sides of the gate region. The upper surfaces of the lightly doped P-type region are provided with the N-type electrode region and the P-type electrode region, which are disposed on both sides of the gate region. The N-type electrode region is in contact with the gate region, and the P-type electrode region is in contact with the N-type electrode region. The P-type electrode region is far away from the gate region. The source electrode is provided on the N-type electrode region and the P-type electrode region, and the gate electrode is provided on the gate region. Step 2: Formation of the substrate with an N-type buffer Based on the structural design in step 1, a semiconductor wafer is selected as the substrate. The upper and lower surfaces of the substrate are cleaned to remove surface oxides and oil stains. RCA cleaning agent is used for cleaning, followed by rinsing with deionized water and drying in a nitrogen environment. After drying, a layer of positive photoresist is coated on the lower surface of the substrate. The substrate is exposed using a photolithography machine according to a pre-designed mask pattern with an N-type buffer. The exposed photoresist area is then developed and removed to expose the N-type buffer to be implanted by ions. The substrate is then transferred to an N-type ion implanter, where N-type ions are lightly doped into the substrate to obtain a substrate with an N-type buffer. Step 3: Formation of a substrate with heavily doped N-type regions Based on step 2, on the substrate with an N-type buffer, and located at the lower part of the N-type buffer, N-type ions are heavily doped using an N-type ion implanter. The N-type ions are heavily doped into the lower part of the substrate with the N-type buffer and extend to the lower surface of the substrate. Then, the remaining unexposed photoresist is removed using a photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a heavily doped N-type region. Step 4: Formation of the substrate with drain electrode Based on step 3, a substrate with heavily N-type doped regions is selected and transferred to a wafer electroplating machine. A conductive metal layer is electroplated on the lower surface of the substrate, and then a negative photoresist layer is coated on the conductive metal layer. Exposure is performed using a photolithography machine with a mask pattern for the drain electrode. Here, the mask pattern for the drain electrode is the same as the mask pattern for the N-type buffer. Figure 1 Then, the non-exposed photoresist is developed and cleaned to expose the non-drain electrode area. The metal conductive layer of the non-drain electrode area is cleaned by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution. After cleaning with deionized water, it is dried in a nitrogen atmosphere to form a substrate with a drain electrode. Step 5: Formation of the substrate with N-type well regions Based on step 4, a substrate with a drain electrode is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type well region. The exposed photoresist is then developed, cleaned and removed to expose the N-type well region. The substrate is then transferred to an N-type ion implanter, and N-type ions are lightly doped into the N-type well region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type buffer zone is reached. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type well region. Step 6: Formation of the substrate with P-type well regions Based on step 5, a substrate with an N-type well region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type well region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type well region. The substrate is then transferred to a P-type ion implanter, and P-type ions are lightly doped into the P-type well region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type buffer zone is reached. At this point, the N-type well region and the P-type well region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type well region. Step 7: Formation of the substrate with P-type well extension region Based on step 6, a substrate with a P-type well region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type well extension region. Then, the exposed photoresist is developed and cleaned to remove it, exposing the P-type well extension region. The substrate is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type well extension region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type well region is reached. At this point, the P-type well extension region and the P-type well region are in contact with each other. Then, the remaining unexposed photoresist is removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with a P-type well extension region. Step 8: Formation of the substrate with the gate region Based on step 7, a substrate with a P-type well extension region is selected. A silicon dioxide layer is deposited on the upper surface of the substrate using PECVD technology. A silicon nitride layer is deposited on the upper surface of the silicon dioxide layer, and a positive photoresist layer is coated on the upper surface of the silicon dioxide layer. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the gate region. The exposed photoresist is then developed and cleaned to remove it, exposing the gate region. The substrate is then placed in an ion etching machine, and the gate region is etched from the upper surface of the silicon nitride region of the substrate to the upper surface of the N-type well region using the ion etching machine. The remaining unexposed photoresist is then removed using a photoresist stripping solution, and the substrate is cleaned with deionized water. The substrate is then dried in a nitrogen atmosphere to form a gate trench region. An insulating layer is then deposited on the inner wall of the gate trench region using HDPCVD technology. A polysilicon layer is then deposited on the inner wall of the insulating layer to fill the gate trench region. Finally, the polysilicon, insulating layer, silicon nitride, and silicon dioxide are ground away using CMP technology until the upper surface of the substrate is reached, forming a substrate with a gate region. Step 9: Formation of the substrate with the N-type extended region Based on step 8, a substrate with a gate region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type extended region. The exposed photoresist is then developed and cleaned to remove it, exposing the N-type extended region. The N-type extended region is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type extended region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type well region is reached. At this point, the N-type extended region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with an N-type extended region. Step 10: Formation of a substrate with heavily p-type doped regions Based on step 9, a substrate with an N-type extended region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type heavily doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type heavily doped region. The region is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type heavily doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the P-type well region is reached. At this point, the P-type heavily doped region and the N-type extended region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type heavily doped region. Step 11: Formation of a substrate with shallow p-type doped regions Based on step 10, a substrate with a heavily doped P-type region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the lightly doped P-type region. The exposed photoresist is then developed, cleaned, and removed to expose the lightly doped P-type region. The substrate is then placed in a P-type ion implanter, and P-type ions are lightly doped into the lightly doped P-type region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type extended region and the heavily doped P-type region. At this point, the lightly doped P-type region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a lightly doped P-type region. Step 12: Formation of the substrate with N-type electrode regions Based on step 11, a substrate with a lightly doped P-type region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the N-type electrode region. The substrate is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type electrode region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the N-type electrode region and the gate region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type electrode region. Step 13: Formation of the substrate with P-type electrode regions Based on step 13, a substrate with an N-type electrode region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the P-type electrode region. The substrate is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type electrode region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the P-type electrode region and the N-type electrode region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with a P-type electrode region. Step 14: Formation of a substrate with source and gate electrodes Based on step 13, a substrate with a P-type electrode region is selected and transferred to a wafer electroplating device. A metal conductive layer is electroplated on the upper surface of the substrate, and then a negative photoresist is coated on the metal conductive layer. Photolithography is performed according to the pre-designed mask pattern of the source electrode and the gate electrode. Then, the unexposed photoresist is developed and cleaned to remove it, exposing the areas of non-source electrode and non-gate electrode. The metal conductive layer of the non-source electrode and non-gate electrode areas is cleaned away by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with source electrode and gate electrode, thus fabricating a superjunction MOS device.

[0040] pass Figure 3 The fabrication process was used to fabricate the superjunction MOS device on a silicon carbide substrate, and the parameters of the device were measured using a semiconductor parameter analyzer. Figure 4 On-resistance test diagram and Figure 5 From the breakdown voltage test diagram, it can be seen that the on-resistance is about 29mΩ and the breakdown voltage is about 1700V.

[0041] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-voltage tolerant low-loss super-junction MOS device, characterized in that, The superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well regions being disposed on both sides of the N-type well regions; a P-type heavily doped region on the P-type well regions; and an N-type extended region and a gate region on the N-type well regions, the N-type extended regions being disposed on both sides of the gate region. The upper surfaces of the heavily doped P-type region and the extended N-type region are provided with the lightly doped P-type region, which is disposed on both sides of the gate region. The upper surfaces of the lightly doped P-type region are provided with the N-type electrode region and the P-type electrode region, which are disposed on both sides of the gate region. The N-type electrode region is in contact with the gate region, and the P-type electrode region is in contact with the N-type electrode region. The P-type electrode region is far away from the gate region. The N-type electrode region and the P-type electrode region are provided with the source electrode, and the gate region is provided with the gate electrode. 2.The super-junction MOS device of claim 1, wherein, The upper part of the P-type well region is provided with a P-type well extension region, which is located on the upper part of the N-type well region and on the lower surface of the N-type extension region. The P-type well extension region is in contact with the P-type well region. 3.The super-junction MOS device of claim 1, wherein, The gate region includes an insulating layer and a polysilicon layer. The insulating layer wraps around the side and bottom surfaces of the polysilicon layer and is in contact with the N-type well region, the N-type extended region, the P-type shallow doped region, and the N-type electrode region.

4. The super junction MOS device of claim 3, wherein, The insulating layer is a single-element high-K insulating material, a compound high-K insulating material, or an insulating oxide material.

5. The super junction MOS device of claim 1, wherein, The P-type well region is arranged symmetrically with respect to the centerline of the N-type well region.

6. The super junction MOS device of claim 1, wherein, Both the P-type heavily doped region and the N-type extended region are symmetrically arranged with respect to the centerline of the gate region.

7. The super junction MOS device of claim 1, wherein, Both the N-type electrode region and the P-type electrode region are symmetrically arranged with respect to the center line of the gate region.

8. The super junction MOS device of claim 1, wherein, The P-type shallow doped region is arranged symmetrically with the center line of the gate region as the reference.

9. The super junction MOS device of claim 1, wherein, The drain electrode, source electrode, and gate electrode are all made of aluminum or copper.

10. A method for manufacturing a high-voltage-resistant low-loss super-junction MOS device, characterized in that, The preparation method comprises the following steps: Step 1: Structural Design of Superjunction MOS Devices The superjunction MOS device includes: a substrate made of semiconductor material; an N-type heavily doped region on the bottom layer of the substrate; a drain electrode on the lower surface of the N-type heavily doped region; an N-type buffer on the upper surface of the N-type heavily doped region; a P-type well region and an N-type well region on the upper surface of the N-type buffer region; the P-type well regions being disposed on both sides of the N-type well regions; a P-type heavily doped region on the P-type well regions; and an N-type extended region and a gate region on the N-type well regions, the N-type extended regions being disposed on both sides of the gate region. The upper surfaces of the heavily doped P-type region and the extended N-type region are provided with the lightly doped P-type region, which is disposed on both sides of the gate region. The upper surfaces of the lightly doped P-type region are provided with the N-type electrode region and the P-type electrode region, which are disposed on both sides of the gate region. The N-type electrode region is in contact with the gate region, and the P-type electrode region is in contact with the N-type electrode region. The P-type electrode region is far away from the gate region. The source electrode is provided on the N-type electrode region and the P-type electrode region, and the gate electrode is provided on the gate region. Step 2: Formation of the substrate with an N-type buffer Based on the structural design in step 1, a semiconductor wafer is selected as the substrate. The upper and lower surfaces of the substrate are cleaned to remove surface oxides and oil stains. RCA cleaning agent is used for cleaning, followed by rinsing with deionized water and drying in a nitrogen environment. After drying, a layer of positive photoresist is coated on the lower surface of the substrate. The substrate is exposed using a photolithography machine according to a pre-designed mask pattern with an N-type buffer. The exposed photoresist area is then developed and removed to expose the N-type buffer to be implanted by ions. The substrate is then transferred to an N-type ion implanter, where N-type ions are lightly doped into the substrate to obtain a substrate with an N-type buffer. Step 3: Formation of a substrate with heavily doped N-type regions Based on step 2, on the substrate with an N-type buffer, and located at the lower part of the N-type buffer, N-type ions are heavily doped using an N-type ion implanter. The N-type ions are heavily doped into the lower part of the substrate with the N-type buffer and extend to the lower surface of the substrate. Then, the remaining unexposed photoresist is removed using a photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a heavily doped N-type region. Step 4: Formation of the substrate with drain electrode Based on step 3, a substrate with a heavily doped N-type region is selected and transferred to a wafer electroplating device. A metal conductive layer is electroplated on the lower surface of the substrate, and then a negative photoresist is coated on the metal conductive layer. Exposure is performed using a photolithography machine with a mask pattern of drain electrodes. The mask pattern of the drain electrodes is the same as that of the N-type buffer. Then, development and cleaning are performed to remove the non-exposed photoresist, exposing the non-drain electrode area. The metal conductive layer of the non-drain electrode area is cleaned by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution. After cleaning with deionized water, it is dried in a nitrogen atmosphere to form a substrate with a drain electrode. Step 5: Formation of the substrate with N-type well regions Based on step 4, a substrate with a drain electrode is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type well region. The exposed photoresist is then developed, cleaned and removed to expose the N-type well region. The substrate is then transferred to an N-type ion implanter, and N-type ions are lightly doped into the N-type well region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type buffer zone is reached. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type well region. Step 6: Formation of the substrate with P-type well regions Based on step 5, a substrate with an N-type well region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type well region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type well region. The substrate is then transferred to a P-type ion implanter, and P-type ions are lightly doped into the P-type well region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type buffer zone is reached. At this point, the N-type well region and the P-type well region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type well region. Step 7: Formation of the substrate with the gate region Based on step 6, a substrate with a P-type well region is selected. A silicon dioxide layer is deposited on the upper surface of the substrate using PECVD technology. A silicon nitride layer is deposited on the upper surface of the silicon dioxide layer, and a positive photoresist layer is coated on the upper surface of the silicon dioxide layer. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the gate region. The exposed photoresist is then developed and cleaned to remove it, exposing the gate region. The substrate is then placed in an ion etching machine, and the gate region is etched from the upper surface of the silicon nitride region of the substrate to the upper surface of the N-type well region using the ion etching machine. The remaining unexposed photoresist is then removed using a photoresist stripping solution, and the substrate is cleaned with deionized water. The substrate is then dried in a nitrogen atmosphere to form a gate trench region. An insulating layer is then deposited on the inner wall of the gate trench region using HDPCVD technology. A polysilicon layer is then deposited on the inner wall of the insulating layer to fill the gate trench region. Finally, the polysilicon, insulating layer, silicon nitride, and silicon dioxide are ground away using CMP technology until the upper surface of the substrate is reached, forming a substrate with a gate region. Step 8: Formation of the substrate with the N-type extended region Based on step 7, a substrate with a gate region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type extended region. The exposed photoresist is then developed and cleaned to remove it, exposing the N-type extended region. The N-type extended region is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type extended region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the N-type well region is reached. At this point, the N-type extended region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with an N-type extended region. Step 9: Formation of a substrate with heavily p-type doped regions Based on step 8, a substrate with an N-type extended region is selected, and a layer of positive photoresist is coated on the upper surface of the substrate. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type heavily doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the P-type heavily doped region. The region is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type heavily doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the P-type well region is reached. At this point, the P-type heavily doped region and the N-type extended region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen atmosphere to form a substrate with a P-type heavily doped region. Step 10: Formation of a substrate with shallow p-type doped regions Based on step 9, a substrate with a heavily P-type doped region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the lightly P-type doped region. The exposed photoresist is then developed and cleaned to remove it, exposing the lightly P-type doped region. The substrate is then placed in a P-type ion implanter, and P-type ions are lightly doped into the lightly P-type doped region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the N-type extended region and the heavily P-type doped region. At this point, the lightly P-type doped region is in contact with the gate region. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with a lightly P-type doped region. Step 11: Formation of the substrate with N-type electrode regions Based on step 10, a substrate with a lightly doped P-type region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the N-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the N-type electrode region. The substrate is then placed in an N-type ion implanter, and N-type ions are re-doped into the N-type electrode region from the upper surface of the substrate through the N-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the N-type electrode region and the gate region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with an N-type electrode region. Step 12: Formation of the substrate with P-type electrode regions Based on step 11, a substrate with an N-type electrode region is selected, and a layer of positive photoresist is coated on its upper surface. The substrate is exposed by a photolithography machine according to the pre-designed mask pattern of the P-type electrode region. The exposed photoresist is then developed, cleaned, and removed to expose the P-type electrode region. The substrate is then placed in a P-type ion implanter, and P-type ions are re-doped into the P-type electrode region from the upper surface of the substrate through the P-type ion implanter until the upper surface of the lightly doped P-type region is reached. At this point, the P-type electrode region and the N-type electrode region are in contact with each other. The remaining unexposed photoresist is then removed by photoresist stripping solution, and the substrate is cleaned with deionized water. Finally, the substrate is dried in a nitrogen atmosphere to form a substrate with a P-type electrode region. Step 13: Formation of the substrate with source and gate electrodes Based on step 12, a substrate with a P-type electrode region is selected and transferred to a wafer electroplating device. A metal conductive layer is electroplated on the upper surface of the substrate, and then a negative photoresist is coated on the metal conductive layer. Photolithography is performed according to the pre-designed mask pattern of the source electrode and the gate electrode. Then, the unexposed photoresist is developed and cleaned to remove it, exposing the areas of non-source electrode and non-gate electrode. The metal conductive layer of the non-source electrode and non-gate electrode areas is cleaned away by wet chemical etching with chemical reagents. Then, the remaining exposed photoresist is removed by another photoresist stripping solution, and then cleaned with deionized water. Finally, it is dried in a nitrogen environment to form a substrate with source electrode and gate electrode, thus fabricating a superjunction MOS device.

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