Method of forming a semiconductor structure

Abstract

This disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of first trenches on the substrate; forming a dielectric material layer covering the bottom and sidewalls of the first trenches; filling a portion of the first trenches to form a first shielding gate; and employing a multi-round deposition and etching process to fill the first shielding gate within the first trenches with a first dielectric layer, each round of the process comprising at least: employing an HDPCVD process to form a sub-dielectric layer on the first shielding gate within the first trenches, wherein each sub-dielectric layer, starting from a second sub-dielectric layer, covers the previous sub-dielectric layer, and the top of the sub-dielectric layer has a protruding extension toward the central axis of the first trench; employing dry etching to remove part or all of the protruding extension of the current sub-dielectric layer, thereby forming a first sub-trench above the current sub-dielectric layer within the first trench; wherein the radio frequency bias power in the HDPCVD process is less than or equal to 5000W. Using the above method, the quality of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, shielded gate trench (SGT) devices are widely used in power semiconductors due to their excellent switching characteristics and low on-resistance. Filling the dielectric layer between the gates is a critical process step. As device dimensions continue to shrink, the linewidth of SGT trenches is becoming smaller and the aspect ratio is becoming larger, placing stringent requirements on the filling capability of high-density plasma chemical vapor deposition (HDPCVD).

[0003] However, the conventional HDPCVD growth method, which involves simultaneous deposition and bombardment, tends to prematurely seal the top of trenches in high aspect ratio trenches, resulting in voids at the bottom and failing to meet the requirement of defect-free filling. On the other hand, while the high-bombardment mode of HDPCVD can force filling, its high-energy ions can severely damage the gate oxide (GOX) layer on the trench sidewalls, leading to an increase in interface states, a rise in gate leakage current, and ultimately, device leakage failure.

[0004] Therefore, how to provide technical solutions to fully fill the trenches and improve the quality of semiconductor structures has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a method for forming a semiconductor structure that can improve the quality of the semiconductor structure.

[0006] This disclosure provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of first trenches on the substrate; forming a dielectric material layer covering the bottom and sidewalls of the first trenches; filling a portion of the first trenches to form a first shielding gate; and employing a multi-round deposition and etching process to fill a first dielectric layer on the first shielding gate within the first trenches, wherein each round of the process includes at least: employing an HDP chemical vapor deposition process to form a layer covering the substrate and forming a sub-dielectric layer on the first shielding gate in the first trenches, wherein each sub-dielectric layer, starting from the second sub-dielectric layer, covers the previous sub-dielectric layer. The sub-dielectric layer has a raised extension at its top facing the central axis of the first trench. Dry etching is used to remove part or all of the raised extension of the current sub-dielectric layer, forming a first sub-trench above the current sub-dielectric layer located within the first trench. The first sub-dielectric layer covers the dielectric material layer located on the sidewall of the first trench, and the thickness of the sub-dielectric layer covering the sidewall of the first trench is less than the thickness of the sub-dielectric layer located on the first shielding gate. The radio frequency bias power in the HDP chemical vapor deposition process is less than or equal to 5000W.

[0007] Optionally, the protrusions are located above the same first groove, and the distance between adjacent protrusions is greater than the width of the protrusion.

[0008] Optionally, the material of the sub-dielectric layer is the same in each deposition and etching process.

[0009] Optionally, the step of filling the first dielectric layer further includes: forming a first sacrificial layer that covers the last sub-dielectric layer and fills the first sub-trench to obtain the first dielectric layer; the thickness of the first sacrificial layer is 100 nm to 300 nm, and the material of the first sacrificial layer is the same as the material of the sub-dielectric layer.

[0010] Optionally, a hard mask layer is provided on the substrate between adjacent first trenches; the method further includes: planarizing the first dielectric layer and the dielectric material layer to expose the hard mask layer; and removing a portion of the first dielectric layer to obtain an inter-gate dielectric layer.

[0011] Optionally, it further includes: forming at least one control gate on the top of the first trench, the control gate being located above the first shielding gate or on both sides of the first shielding gate; wherein the inter-gate dielectric layer is located between the control gate and the first shielding gate.

[0012] Optionally, the dielectric material layer has a multilayer structure; the step of forming the dielectric material layer includes: forming an inner oxide layer covering the sidewalls and bottom of the first trench; forming an intermediate silicon nitride layer covering the inner oxide layer; and / or forming a field oxide layer covering the intermediate silicon nitride layer; wherein the inner oxide layer, the intermediate silicon nitride layer, and the field oxide layer are all formed in a conformal manner.

[0013] Optionally, the step of forming the first shielding gate further includes: forming a shielding gate material layer that fills the first trench and covers the adjacent first trench; etching back the shielding gate material layer, or etching back the field oxide layer and the shielding gate material layer to obtain the first shielding gate.

[0014] Optionally, the method further includes: forming a plurality of second trenches on the substrate; forming a dielectric material layer covering the bottom and sidewalls of the second trenches; filling a portion of the second trenches to form a second shielding gate; and forming a second dielectric layer covering the substrate and filling the second trenches using an HDP chemical vapor deposition process; wherein the method for forming the second dielectric layer is the same as or different from the method for forming the first dielectric layer.

[0015] Optionally, the method satisfies one or more of the following: the depth of the second trench is the same as the depth of the first trench; the second trench and the first trench are formed in the same step; the length of the second shielding gate is greater than the length of the first shielding gate.

[0016] Compared with the prior art, the technical solution of the present disclosure has the following advantages: The method for forming a semiconductor structure provided in this disclosure includes: providing a substrate; forming a plurality of first trenches on the substrate; forming a dielectric material layer covering the bottom and sidewalls of the first trenches; filling a portion of the first trenches to form a first shielding gate; and using a multi-round deposition etching process to fill a first dielectric layer on the first shielding gate within the first trenches, each round of the process including at least: using an HDPCVD process to form a sub-dielectric layer on the first shielding gate in the first trenches, each sub-dielectric layer covering the previous sub-dielectric layer starting from the second sub-dielectric layer, the top of the sub-dielectric layer having a protruding extension toward the central axis of the first trench; using dry etching to remove part or all of the protruding extension of the current sub-dielectric layer, forming a first sub-trench above the current sub-dielectric layer within the first trench; the first sub-dielectric layer covering the dielectric material layer located on the sidewalls of the first trenches; and the radio frequency bias power in the HDPCVD process being less than or equal to 5000W. By employing a multi-round deposition and etching process, each round first uses HDPCVD to form a sub-dielectric layer with protruding extensions, and then dry etching promptly removes the protruding extensions, effectively avoiding the bottom void problem caused by premature sealing of the trench top in traditional processes. The sub-dielectric layer covering the dielectric material layer located on the sidewall of the first trench protects the dielectric material layer during bombardment and etching processes. Simultaneously, controlling the RF bias power of HDPCVD below 5000W ensures ion bombardment to assist filling while preventing damage to the gate oxide layer on the trench sidewall from excessive bombardment energy, thus achieving both void-free filling and low leakage current performance. Therefore, this semiconductor structure formation method can fully fill the trench and improve the quality of the semiconductor structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments disclosed in this specification, the drawings used in the description of the embodiments disclosed in this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0019] Figure 2 This is a schematic diagram of a multi-round deposition etching process in an embodiment of this disclosure.

[0020] Figures 3 to 15 This is a cross-sectional structural schematic diagram of some steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0021] The technical solutions described herein will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of this disclosure and are used to illustrate the concept of this disclosure. These descriptions are illustrative and exemplary and should not be construed as limiting the implementation methods or the scope of protection of this disclosure. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0022] It should be noted that the accompanying drawings in this embodiment are schematic diagrams used to illustrate the concept of this disclosure, and to schematically show the shape and interrelationship of each part. It should be understood that, in order to clearly show the structure of each component of this disclosure, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.

[0023] As described in the background section, shielded gate trench (SGT) devices are widely used in power semiconductors due to their excellent switching characteristics and low on-resistance. Filling the dielectric layer between the gates is a critical process step. With the continuous miniaturization of device dimensions, the linewidth of SGT trenches is becoming smaller and the aspect ratio is becoming larger, which places stringent requirements on the filling capability of high-density plasma chemical vapor deposition (HDPCVD).

[0024] However, the conventional HDPCVD growth method, which involves simultaneous deposition and bombardment, tends to prematurely seal the top of trenches in high aspect ratio trenches, resulting in voids at the bottom and failing to meet the requirement of defect-free filling. On the other hand, while the high-bombardment mode of HDPCVD can force filling, its high-energy ions can severely damage the gate oxide (GOX) layer on the trench sidewalls, leading to an increase in interface states, a rise in gate leakage current, and ultimately, device leakage failure.

[0025] Therefore, how to provide technical solutions to fully fill the trenches and improve the quality of semiconductor structures has become an urgent technical problem to be solved.

[0026] The method for forming a semiconductor structure provided in this disclosure includes: providing a substrate; forming a plurality of first trenches on the substrate; forming a dielectric material layer covering the bottom and sidewalls of the first trenches; filling a portion of the first trenches to form a first shielding gate; and using a multi-round deposition etching process to fill a first dielectric layer on the first shielding gate within the first trenches, each round of the process including at least: using an HDPCVD process to form a sub-dielectric layer on the first shielding gate in the first trenches, each sub-dielectric layer covering the previous sub-dielectric layer starting from the second sub-dielectric layer, the top of the sub-dielectric layer having a protruding extension toward the central axis of the first trench; using dry etching to remove part or all of the protruding extension of the current sub-dielectric layer, forming a first sub-trench above the current sub-dielectric layer within the first trench; the first sub-dielectric layer covering the dielectric material layer located on the sidewalls of the first trenches; and the radio frequency bias power in the HDPCVD process being less than or equal to 5000W. By employing a multi-round deposition and etching process, each round first uses HDPCVD to form a sub-dielectric layer with protruding extensions, and then dry etching promptly removes the protruding extensions, effectively avoiding the bottom void problem caused by premature sealing of the trench top in traditional processes. The sub-dielectric layer covering the dielectric material layer located on the sidewall of the first trench protects the dielectric material layer during bombardment and etching processes. Simultaneously, controlling the RF bias power of HDPCVD below 5000W ensures ion bombardment to assist filling while preventing damage to the gate oxide layer on the trench sidewall from excessive bombardment energy, thus achieving both void-free filling and low leakage current performance. Therefore, this semiconductor structure formation method can fully fill the trench and improve the quality of the semiconductor structure.

[0027] To make the above-described objects, features and advantages of this disclosure more apparent and understandable, the disclosure is illustrated below with reference to the accompanying drawings.

[0028] See Figure 1 , Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method may perform the following steps S110 to S150.

[0029] In step S110, a substrate is provided.

[0030] In step S120, a plurality of first trenches are formed on the substrate.

[0031] In step S130, a dielectric material layer is formed covering the bottom and sidewalls of the first trench.

[0032] In step S140, a portion of the first trench is filled to form a first shielding grid.

[0033] In step S150, a multi-round deposition etching process is used to fill the first dielectric layer on the first shielding gate in the first trench.

[0034] The following combination Figures 2 to 15 The above methods will be explained.

[0035] See Figure 3 Substrate 200 is provided.

[0036] The substrate 200 is used to provide a process platform for the formation of semiconductor structures.

[0037] The substrate 200 is made of single-crystal silicon. In other embodiments, the substrate 200 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 200 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, an epitaxial layer with the same crystal structure as the substrate may also be formed on the surface of the substrate 200.

[0038] In some embodiments, the substrate 200 is doped polycrystalline silicon.

[0039] In some embodiments, a hard mask layer 203 is formed on the substrate 200.

[0040] The hard mask layer 203 can be a single-layer structure or a multi-layer structure.

[0041] When the hard mask layer 203 is a single-layer structure, the material of the hard mask layer 203 can be silicon oxide, silicon nitride, etc.

[0042] When the hard mask layer 203 has a multilayer structure, the material of the hard mask layer 203 can be silicon oxide, silicon nitride, an ONO stack of silicon oxide, or a stack of other high dielectric constant materials.

[0043] In this embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially formed on the substrate 200, and the three thin films serve as a hard mask layer 203.

[0044] In the hard mask layer 203 of the ONO stack, the silicon nitride layer has a higher dry etching selectivity compared to silicon dioxide and single-crystal silicon. During deep trench etching, it effectively maintains the integrity of the mask pattern, resulting in trench morphologies with higher verticality and smoother sidewalls, providing a precise template for the subsequent formation of gradient thickness field oxide layers. Secondly, the composite structure formed by the upper and lower silicon oxide layers and the intermediate silicon nitride can balance the mechanical stress between the layers, reducing the impact of overall film stress on wafer warpage, which is beneficial for process uniformity and lithography alignment accuracy on large-size wafers. Thirdly, the ONO hard mask can act as an effective barrier layer during ion implantation, preventing implanted ions from entering non-target areas. Simultaneously, it can serve as a clear stop layer during chemical mechanical polishing (CMP) planarization, facilitating precise control of the polysilicon etch-back endpoint. Furthermore, during high-temperature thermal oxidation or annealing, the ONO stack can protect the underlying silicon surface from unnecessary oxidation or contamination, improving device reliability and consistency.

[0045] The hard mask layer 203 is graphically represented.

[0046] A specific trench pattern is formed on the hard mask layer 203 using photolithography and other processes, and the hard mask layer 203 exposed by photoresist is etched to transfer the specific pattern onto the hard mask layer 203.

[0047] Trench etching is performed on substrate 200 using a hard mask layer 203 with a specific pattern etched on it to obtain first trench 201 and second trench 202. In other words, a plurality of first trenches 201 are formed on substrate 200, and a plurality of second trenches 202 are formed on substrate 200.

[0048] In some embodiments, the hard mask layer 203 has a multilayer structure, and the silicon oxide on the top layer of the hard mask layer 203 is removed during the formation of the first trench 201 and the second trench 202.

[0049] The first trench 201 and the second trench 202 can be formed using a dry etching process.

[0050] The first trench 201 and the second trench 202 can be formed in the same step.

[0051] The depth of the first trench 201 is the same as the depth of the second trench 202.

[0052] The first trench 201 is a nearly vertically downward deep trench structure with an inner sidewall and a bottom. The cross-section of the first trench 201 is rectangular or inverted trapezoidal, and the connection between the sidewall and the bottom of the first trench 201 can be rounded.

[0053] In some embodiments, the ratio of the depth to the width of the first trench 201 is greater than 5:1, and a mesa is provided between adjacent first trenches 201, or between the first trench 201 and the second trench 202, or between the second trench 202.

[0054] The second trench 202 is a nearly vertically downward deep trench structure with an inner sidewall and a bottom. The cross-section of the second trench 202 is rectangular or inverted trapezoidal, and the connection between the sidewall and the bottom of the second trench 202 can be rounded.

[0055] In some embodiments, the angle between the sidewalls of the first trench 201 and / or the second trench 202 and the vertical direction is between 80 and 90 degrees.

[0056] See Figure 4 A dielectric material layer 210 is formed.

[0057] The dielectric material layer 210 covers the bottom and sidewalls of the first trench 201.

[0058] The dielectric material layer 210 covers the bottom and sidewalls of the second trench 202.

[0059] The dielectric material layer 210 has a multilayer structure.

[0060] The steps of forming the dielectric material layer 210 include: An inner oxide layer 211 is formed covering the sidewalls and bottom of the first trench 201 and / or the second trench 202.

[0061] Specifically, wet etching is used to remove residual silicon oxide on the top of the hard mask layer 203 to ensure interface cleanliness for subsequent film growth. Then, a layer of silicon oxide is formed on the surface of the substrate 200, the surface of the hard mask layer 203, and the bottom and sidewalls of the first trench 201 and / or the second trench 202 as an inner oxide layer 211.

[0062] The inner oxide layer 211 is formed using processes such as thermal growth or atomic layer deposition. The thickness of the inner oxide layer 211 is typically tens to hundreds of angstroms. The silicon oxide obtained by thermal growth is dense and has low interface states, which can effectively repair silicon surface damage introduced during etching trenches and provide a good stress buffer substrate for subsequent silicon nitride deposition.

[0063] An intermediate silicon nitride layer 212 is formed covering the inner oxide layer 211.

[0064] Specifically, a silicon nitride layer is deposited on the surface of the inner oxide layer 211 as an intermediate silicon nitride layer 212. The silicon nitride layer has a high dielectric constant and excellent etching resistance, and can serve as an etching stop layer in subsequent wet or dry etching processes to protect the underlying inner oxide layer and substrate. Simultaneously, its high hardness can also regulate the overall stress of the multilayer dielectric film, preventing the trench sidewalls from bending or the film from cracking due to excessive tensile or compressive stress in a single oxide layer.

[0065] The intermediate silicon nitride layer 212 is formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes.

[0066] In some embodiments, a field oxide layer (not shown) is formed covering the intermediate silicon nitride layer 212.

[0067] The field oxide layer is made of silicon oxide and can be formed using processes such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma-enhanced chemical vapor deposition (HDP-CVD), and sub-atmospheric pressure chemical vapor deposition (SACVD). The field oxide layer further increases the thickness of the dielectric material layer 210, thereby enhancing the quality of the dielectric material layer 210.

[0068] It should be noted that the inner oxide layer 211, the intermediate silicon nitride layer 212, and the field oxide layer are all formed by conformal covering.

[0069] See also Figure 5 and Figure 6 This forms the first shielding grid 221.

[0070] A portion of the first trench 201 is filled to form a first shielding grid 221.

[0071] A portion of the second trench 202 is filled to form a second shielding grid 222.

[0072] Specifically, a shielding grid material layer 220 is formed to fill the first trench 201 and the second trench 202, and to cover the adjacent first trench 201. The shielding grid material layer 220 fills the first trench 201 and the second trench 202, and covers the platform area.

[0073] The shielding grid material layer 220 is formed using a low-pressure chemical vapor deposition (LPCVD) process.

[0074] Specifically, intrinsic polycrystalline silicon is deposited at a certain temperature using silane as a precursor gas. During the deposition process, phosphine or arsine can be introduced in situ to induce N-type heavy doping in the polycrystalline silicon during deposition, thereby reducing the resistivity of the shielding gate. Alternatively, intrinsic polycrystalline silicon can be deposited first, followed by doping via solid-state source diffusion or high-dose ion implantation, and then high-temperature annealing to activate impurities.

[0075] The shielding gate material layer 220 is etched back, or the field oxide layer and the shielding gate material layer 220 are etched back to obtain the first shielding gate 221.

[0076] The shielding gate material layer 220 is etched back to obtain the second shielding gate 222.

[0077] Specifically, the upper surface of the shielding gate material layer 220 is etched back to be flush with the top of the first trench 201 and the second trench 202, or the upper surface of the shielding gate material layer 220 is etched back to be slightly lower than the top plane of the first trench 201 and the second trench 202, thus obtaining the second shielding gate 222 in the second trench 202. In other words, the top surface of the shielding gate material layer 220 is etched back to be flush with the top of the first trench 201 and the second trench 202, or the top surface of the shielding gate material layer 220 is etched back to be lower than the top position of the first trench 201 and the second trench 202, thus obtaining the second shielding gate 222.

[0078] The method for etching back the shielding gate material layer 220 can be one or a combination of dry plasma etching, wet etching, and chemical mechanical polishing.

[0079] A masking layer is spin-coated on top of the second shielding grid 222 within the second trench 202.

[0080] The positions of the first shielding gate 221 and the second shielding gate 222 of the device are defined using a photolithography process and a masking layer. Specifically, a masking layer is spin-coated onto the wafer surface that has been filled with the shielding gate material layer 220 and preliminarily planarized. After exposure and development, the masking layer covers the second trench region, exposing the first trench region. Using the masking layer as a shield, the exposed shielding gate material layer 220 is selectively etched, for example, using wet etching or dry plasma etching, to remove part of the polysilicon within the first trench 201, retaining the polysilicon at the bottom of the trench, thereby forming the first shielding gate 221. In other words, using the masking layer as a mask, part of the shielding gate material layer 220 within the first trench 201 is removed to obtain the first shielding gate 221. The shielding gate material layer 220 in the isolation region 102 covered by the masking layer is completely retained, forming the second shielding gate 222.

[0081] The length of the second shielding gate 222 (i.e., the vertical dimension from the bottom to the top of the trench) is greater than the length of the first shielding gate 221. The first shielding gate 221, located at the bottom of the first trench 201, primarily serves to shield the local electric field and provide voltage withstand support, offering a low-capacitance environment for the control gate above. Its shorter length helps reduce gate leakage charge and improve switching speed. The second shielding gate 222, located within the second trench 202, is typically connected to the source potential or an independent low potential, used to create a deeper potential barrier between adjacent devices, suppressing punch-through effects and increasing breakdown voltage. Its greater depth can more effectively isolate lateral electric fields and reduce crosstalk between devices.

[0082] See Figure 2 , Figure 2 This is a schematic flowchart of a multi-round deposition and etching process according to an embodiment of the present disclosure. The method can perform the following steps S151 to S152.

[0083] In step S151, HDP chemical vapor deposition is used to form a layer covering the substrate 200, and a sub-dielectric layer 230 is formed on the first shielding gate 221 in the first trench 201. Starting from the second sub-dielectric layer, each sub-dielectric layer covers the previous sub-dielectric layer. The top of the sub-dielectric layer 230 has a protruding extension 2311 facing the central axis of the first trench 201.

[0084] In step S152, dry etching is used to remove part or all of the protrusion extension 2311 of the current sub-dielectric layer, and a first sub-trench 204 is formed above the current sub-dielectric layer located in the first trench 201.

[0085] See below for reference. Figures 7 to 12 The above methods will be explained.

[0086] A first dielectric layer 231 is filled on the first shielding gate 221 in the first trench 201 using a multi-stage deposition etching process.

[0087] Each process cycle includes at least: forming a sub-dielectric layer 230 covering the substrate 200 using HDP chemical vapor deposition, and forming a sub-dielectric layer 230 on the first shielding gate 221 in the first trench 201, with each sub-dielectric layer covering the previous sub-dielectric layer starting from the second sub-dielectric layer, wherein the top of the sub-dielectric layer 230 has a protruding extension 2311 facing the central axis of the first trench 201; removing part or all of the protruding extension 2311 of the current sub-dielectric layer using dry etching, and forming a first sub-trench 204 above the current sub-dielectric layer located in the first trench 201.

[0088] Specifically, in the deposition step, HDP chemical vapor deposition is used to form a sub-dielectric layer 230 on the substrate 200. The sub-dielectric layer covers the entire surface of the substrate 200 and covers the top of the first shielding gate 221 in the first trench 201 and the sidewalls of the first trench 201. From the second deposition round onwards, each round of sub-dielectric layer covers the previous sub-dielectric layer.

[0089] In each deposition and etching process, the sub-dielectric layers are made of the same material, typically silicon oxide, to ensure uniform interfaces and no stress mismatch between the multiple layers.

[0090] In this embodiment, the radio frequency bias power in the HDP chemical vapor deposition process is less than or equal to 5000W. Due to the low bombardment energy in the HDP chemical vapor deposition process, and the directionality of ion bombardment and trench geometry constraints in the HDP process, a raised extension 2311 naturally forms on the top of the sub-dielectric layer 230, facing the central axis of the first trench 201. The raised extension 2311 prevents plasma from depositing into the bottom of the first trench 201; therefore, the raised extension 2311 is the primary target for subsequent etching removal.

[0091] The radio frequency bias power in the HDP chemical vapor deposition process is less than or equal to 5000W, ensuring moderate ion bombardment energy that assists in sputtering to open the top opening without causing unacceptable damage to the gate oxide (GOX) layer on the trench sidewalls. If the bias exceeds 5000W, although the filling capability is enhanced, the risk of sidewall leakage will increase.

[0092] In the etching step, dry etching is used to remove part or all of the protrusion extension 2311 in the current sub-dielectric layer. After etching, a first sub-trench 204 is formed above the current sub-dielectric layer within the first trench 201. The opening size of the first sub-trench 204 is enlarged again, creating a new channel for the next deposition to enter the bottom.

[0093] The etching amount needs to be precisely controlled, so as to remove the protrusions to avoid sealing, but not to over-etch away the effective medium on the sidewalls and bottom.

[0094] In some embodiments, photoresist is coated and patterned over the sub-dielectric layer 230 to expose part or all of the protrusion extensions 2311, and then dry etching is used to remove part or all of the protrusion extensions 2311. It should be noted that the patterned etching window is smaller than the width of the first trench 201, such that the photoresist covers the sub-dielectric layer 230 located on the sidewall of the first trench 201, thereby protecting the sub-dielectric layer 230 covering the sidewall of the first trench 201. Therefore, the sub-dielectric layer 230 located on the sidewall of the first trench 201 can protect the dielectric material layer 210 located on the sidewall of the first trench 201, improving the quality of the semiconductor structure.

[0095] The first sub-dielectric layer 230 covers the dielectric material layer 210 located on the sidewall of the first trench 201, and the thickness of the sub-dielectric layer 230 covering the sidewall of the first trench 201 is less than the thickness of the sub-dielectric layer 230 located on the first shielding gate 221. This is because the vertical deposition rate and ion-assisted sputtering are strong in HDPCVD, while the sidewalls are bombarded less, resulting in a thinner sidewall deposition. This helps subsequent etching to preferentially remove the top protrusion extension 2311 while retaining sufficient dielectric thickness at the bottom.

[0096] The protruding extensions 2311 are located above the same first trench 201, and the distance between adjacent protruding extensions 2311 (i.e., the remaining opening width) is greater than the width of the protruding extension 2311 (i.e., the lateral dimension of a single protrusion). This geometric relationship ensures that after etching away the protruding extensions 2311, the opening can be fully opened, preventing permanent sealing due to excessively large protrusions contacting each other, or material collapse of the protruding extensions 2311 to the bottom of the first trench 201 due to etching. In one specific embodiment, the remaining opening width is controlled between 50 nm and 200 nm, while the width of the protruding extensions 2311 is less than 50 nm to 200 nm, thereby ensuring that multiple cycles can continue until the trench is filled.

[0097] In some embodiments, the thickness of the sub-dielectric layer 230 located above the mesa region is 400 nm to 600 nm.

[0098] In some embodiments, a two-stage deposition and etching process is used to fill the first shielding gate 221 within the first trench 201 with a first dielectric layer 231. This two-stage deposition and etching process allows for the full filling of the first trench 201 while minimizing the number of etching operations, thus preventing damage to the dielectric material layer 210 located on the sidewalls of the first trench 201.

[0099] See also Figure 10 and Figure 11A first sacrificial layer 233 is formed to cover the last sub-dielectric layer 230 and fill the first sub-trench 204, thus obtaining the first dielectric layer 231.

[0100] Specifically, after completing multiple rounds of deposition and etching processes, the final sub-dielectric layer 230 can completely fill the first trench 201, and the surface of the final sub-dielectric layer 230 contains the first sub-trench 204. To obtain a flat, defect-free first dielectric layer 231, a first sacrificial layer 233 needs to be further applied. The first sacrificial layer 233 can fill the first sub-trench 204 left after the final etching round (i.e., any small openings or depressions that may exist at the top), thereby forming a complete and flat first dielectric layer 231 and second dielectric layer 232 (e.g., ...). Figure 11 (The portion of the sub-dielectric layer and the first sacrificial layer within the dashed box).

[0101] The thickness of the first sacrificial layer 233 is 100nm to 300nm, which can fill the first sub-trench 204 while reserving sufficient grinding allowance for subsequent planarization.

[0102] The material of the first sacrificial layer 233 is the same as that of the sub-dielectric layer 230, which is typically silicon oxide. Using the same material ensures that there is no abrupt material change at the interface between the first sacrificial layer 233 and the underlying sub-dielectric layer, avoiding stress or charge traps caused by differences in thermal expansion coefficients or dielectric constants. During subsequent CMP, the polishing rates of the sacrificial layer and the sub-dielectric layer are consistent, making it easier to achieve a smooth surface. If subsequent processes require removal of the sacrificial layer (e.g., back etching), the same material can be used with the same etching formula, simplifying the process.

[0103] The method of forming the second dielectric layer 232 may be the same as or different from the method of forming the first dielectric layer 231.

[0104] In some embodiments, a second dielectric layer 232 is formed by using HDP chemical vapor deposition to cover the substrate 200 and fill the second trench 202.

[0105] Specifically, because the length of the second shielding gate 222 (i.e., the vertical dimension from the bottom to the top of the trench) is greater than the length of the first shielding gate 221, the second dielectric layer 232 needs to be filled in the second trench 202 with a thinner thickness, which can be completed in one round of filling.

[0106] In some embodiments, the second dielectric layer 232 needs to be filled in the second trench 202 with a thickness greater than or equal to 90 nm, or in some cases where the aspect ratio of the required filling is greater than 6, the method for forming the first dielectric layer 231 can be referenced, and a multi-round deposition and etching process can be used to form the second dielectric layer 232.

[0107] See also Figure 11 and Figure 12 This forms an inter-gate dielectric layer.

[0108] A hard mask layer 203 is provided on the substrate 200 between adjacent first trenches 201.

[0109] Planarize the first dielectric layer 231 and the dielectric material layer 210 to expose the hard mask layer 203.

[0110] Specifically, using the hard mask layer 203 as a stop layer, a chemical mechanical polishing (CMP) process is employed for global planarization. This removes redundant portions of the first dielectric layer 231 (and the second dielectric layer 232) and the dielectric material layer 210 located above the hard mask layer 203, until the upper surface of the hard mask layer 203 is exposed. This ensures the flatness of the dielectric layer filling the trench while avoiding excessive polishing that could damage the underlying substrate or trench structure.

[0111] Remove part of the first dielectric layer 231 to obtain the inter-gate dielectric layer.

[0112] Specifically, a portion of the first dielectric layer 231 is removed to obtain a first inter-gate dielectric layer 234; a portion of the second dielectric layer 232 is removed to obtain a second inter-gate dielectric layer 235. After planarization and exposing the hard mask layer 203, the upper portion of the first dielectric layer 231 within the first trench 201 needs to be further removed to form an inter-gate dielectric layer for isolating the shield gate and the control gate. Using wet etching or dry etching back processes, the first dielectric layer 231 is etched to a depth controllable manner, removing a certain thickness of material from its top, thereby leaving a first inter-gate dielectric layer 234 of the required thickness within the trench. The remaining thickness of the first inter-gate dielectric layer 234 determines the insulation capability between the subsequent control gate and the underlying first shield gate 221.

[0113] In some embodiments, the thickness of the first inter-gate dielectric layer 234 ranges from 100 nm to 300 nm.

[0114] In some embodiments, the upper portion of the second dielectric layer 232 within the second trench 202 is removed using the same or independent etching steps to obtain the second inter-gate dielectric layer 235. Since the second shielding gate 222 within the second trench 202 performs different functions in the device (e.g., isolation or auxiliary shielding), the remaining thickness of the second inter-gate dielectric layer 235 can be the same as or different from that of the first inter-gate dielectric layer 234, depending on the electrical design requirements. During the etching process, the etching rate and uniformity must be precisely controlled to prevent over-etching from damaging the underlying shielding gate or sidewall structure.

[0115] It should be noted that the hard mask layer is also removed during the formation of the inter-gate dielectric layer. The removal method for the hard mask layer can be one or more of chemical mechanical polishing and wet etching.

[0116] See Figure 13 This forms a control gate 240.

[0117] At least one control gate 240 is formed on the top of the first trench 201.

[0118] The control gate 240 is located in the top region of the first trench 201 and is electrically isolated from the first shielding gate 221 below it through an inter-gate dielectric layer (i.e., the first inter-gate dielectric layer 234). The inter-gate dielectric layer is located between the control gate 240 and the first shielding gate 221.

[0119] Specifically, a layer of polysilicon (or a conductive material such as a metal silicide) is deposited on the surface of the inter-gate dielectric layer to fill the remaining space at the top of the first trench 201. The deposition method can be low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD), with in-situ doping using phosphine or arsine to reduce the resistivity of the control gate. Then, excess polysilicon on the wafer surface is removed by etch-back (dry plasma etching or chemical mechanical polishing), leaving only the conductive material in the top region of the first trench 201 to form the control gate 240.

[0120] The control gate 240 is located above the first shielding gate 221 or on both sides of the first shielding gate 221.

[0121] The control gate 240 is located above the first shielding gate 221. The control gate 240 is aligned with the first shielding gate 221 in the vertical direction, and the two are separated by a first inter-gate dielectric layer 234.

[0122] The control gate 240 is located on both sides of the first shielding gate 221. In some split-gate or dual-gate structures, the control gate 240 does not completely cover the top of the trench, but is divided into two independent gates, located on the left and right sides of the first shielding gate 221 respectively (i.e., near the two sidewalls of the trench). In this configuration, the top plane of the control gate 240 and the first shielding gate 221 are still separated by the inter-gate dielectric layer, but the projection of the control gate 240 is located on both horizontal sides of the first shielding gate 221. This design can further reduce the gate leakage capacitance or achieve independent dual-channel control.

[0123] Figure 14 and Figure 15 This is a cross-sectional structural diagram of some steps in another method for forming a semiconductor structure in an embodiment of the present disclosure.

[0124] See Figure 14 This forms the first inter-gate dielectric layer 234.

[0125] Specifically, a dry etching method is used to perform depth-controlled etching on the first dielectric layer 231, removing a certain thickness of material from its top, thereby leaving the first dielectric layer 231 of the required thickness in the trench. Then, a wet etching method is used to remove part of the first dielectric layer 231, obtaining the first inter-gate dielectric layer 234. In the wet etching step, the dielectric material layer 210 not covered by the first inter-gate dielectric layer 234 and the hard mask layer 203 are removed.

[0126] See Figure 15 This forms a control gate 240.

[0127] A gate oxide layer 241 is formed.

[0128] The gate oxide layer 241 is formed by thermal oxidation or deposition process.

[0129] The gate oxide layer 241 can be made of silicon oxide.

[0130] The gate oxide layer 241 conformally covers all exposed silicon substrate and dielectric layer surfaces without interruptions or holes. This conformal coverage ensures a uniform insulation thickness between the subsequently formed control gate and body region, thereby achieving a consistent threshold voltage and reliable gate control capability. The gate oxide layer 241 covers the body region surface on the trench sidewalls to form an inversion channel when a gate voltage is applied; and covers the area between the source region and the body region terminals on the top surface of the mesa region (the area between adjacent channels), providing isolation and protection.

[0131] A polysilicon layer is formed covering the gate oxide layer 241. The polysilicon layer is etched back to obtain the control gate 240. The method for forming the polysilicon layer and etching back the polysilicon layer can be referred to the above. Figure 13 The relevant description of the control gate 240 in the text will not be repeated here.

[0132] The foregoing describes several embodiments of the method for forming a semiconductor structure. The various optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this disclosure.

[0133] It should be particularly noted that, in this specification and accompanying drawings, in order to clearly describe the core process scheme and structural features of this disclosure, the descriptions of geometric relationships, positional relationships, and morphological features such as "vertically downward deep trench structure," "angle between the sidewall and the vertical direction," "central axis towards the first trench," "conformal coverage," "protruding extension," and "uniform thickness" are all based on theoretical design conditions and ideal process conditions. Those skilled in the art should understand that, in actual semiconductor manufacturing processes, due to etching load effects, deposition non-uniformity, plasma bombardment angle distribution, chemical mechanical polishing planarization tolerances, thermal expansion effects, and unavoidable measurement errors, there may be acceptable minor deviations between the actual morphology, relative position, and dimensional proportions of the fabricated components and the theoretical design. Specifically, "vertically downward deep trench structure" can be understood as approximately vertical with the angle between the sidewall and the vertical direction between 80° and 90°; "protruding extensions facing the central axis of the first trench" should be understood as the protruding extensions mainly facing the central axis direction, but slight deviations due to plasma scattering or mask alignment errors are allowed; "conformal coverage" should be understood as the thickness differences of each thin film layer at the top, sidewall, and bottom of the trench being within the process allowable range, rather than being absolutely consistent; "the distance between adjacent protruding extensions is greater than the width of the protruding extensions" should be understood as the remaining opening width after actual etching meeting the target range of 50nm to 200nm, and reasonable variations due to etching rate fluctuations are allowed; "the thickness of the first sub-dielectric layer covering the dielectric material layer located on the sidewall of the first trench is less than the thickness of the sub-dielectric layer located on the first shielding gate" should be understood as the trend of thinner sidewall deposition being valid within process fluctuations, and relative differences due to changes in RF power and gas flow rate are allowed. These deviations, as long as they do not substantially affect the multi-stage deposition and etching filling principle disclosed in this disclosure and its beneficial effects such as void-free filling, low gate oxide damage, and improved semiconductor structure quality, shall be considered to be included within the scope of protection of this disclosure. Process deviations known in the semiconductor manufacturing industry and variations in dimensions, angles, and thicknesses permitted by industry standards are all covered within the scope of this description.

[0134] It should be noted that the illustrated embodiments only show some embodiments of the semiconductor structure formation method described in this disclosure. Those skilled in the art should understand that, based on the structure shown in the figures, other embodiments obtained by mirroring, flipping, rotating, or transforming the position, relative connection relationship, or orientation of the trenches, dielectric layers, shielding gates, control gates, etc., or by adaptively adjusting their shape, size, thickness, aspect ratio, and process parameters (such as the number of deposition and etching cycles, RF bias power, etc.), as long as they do not deviate from the core concept of multi-round deposition and etching filling and the beneficial effects of no voids and low damage, should all be considered to be included within the protection scope of this disclosure.

[0135] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0136] In the embodiments of this application, "multiple" refers to two or more.

[0137] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of objects in the embodiments of this application. They cannot constitute any limitation on the embodiments of this application.

[0138] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of first trenches are formed on the substrate; A dielectric material layer is formed covering the bottom and sidewalls of the first trench; A portion of the first trench is filled to form a first shielding grid; A multi-stage deposition and etching process is employed to fill the first shielding gate within the first trench with a first dielectric layer. Each stage of the process includes at least the following: HDP chemical vapor deposition process is used to form a substrate covering the substrate, and a sub-dielectric layer is formed on the first shielding gate in the first trench. Starting from the second sub-dielectric layer, each sub-dielectric layer covers the previous sub-dielectric layer. The top of the sub-dielectric layer has a protruding extension toward the central axis of the first trench. Dry etching is used to remove part or all of the protruding extension of the current sub-dielectric layer, and a first sub-trench is formed above the current sub-dielectric layer located in the first trench. Wherein, the first sub-dielectric layer covers the dielectric material layer located on the sidewall of the first trench, and the thickness of the sub-dielectric layer covering the sidewall of the first trench is less than the thickness of the sub-dielectric layer located on the first shielding gate; the radio frequency bias power in the HDP chemical vapor deposition process is less than or equal to 5000W.

2. The forming method according to claim 1, characterized in that, Located above the same first groove, and the distance between adjacent protruding extensions is greater than the width of the protruding extension.

3. The forming method according to claim 1, characterized in that, In each deposition and etching process, the material of the sub-dielectric layer is the same.

4. The forming method according to claim 1, characterized in that, The step of filling the first dielectric layer further includes: A first sacrificial layer is formed to cover the last sub-dielectric layer and fill the first sub-trench, thus obtaining the first dielectric layer; The thickness of the first sacrificial layer is 100 nm to 300 nm, and the material of the first sacrificial layer is the same as the material of the sub-dielectric layer.

5. The forming method according to claim 4, characterized in that, A hard mask layer is provided on the substrate between adjacent first trenches; The method further includes: Planarize the first dielectric layer and the dielectric material layer to expose the hard mask layer; A portion of the first dielectric layer is removed to obtain the inter-gate dielectric layer.

6. The forming method according to claim 5, characterized in that, Also includes: At least one control gate is formed on the top of the first trench, the control gate being located above the first shielding gate or on both sides of the first shielding gate; The inter-gate dielectric layer is located between the control gate and the first shielding gate.

7. The forming method according to claim 1, characterized in that, The dielectric material layer has a multilayer structure; The steps for forming the dielectric material layer include: An inner oxide layer is formed covering the sidewalls and bottom of the first trench; An intermediate silicon nitride layer is formed to cover the inner oxide layer; And / or, form a field oxide layer covering the intermediate silicon nitride layer; The inner oxide layer, the intermediate silicon nitride layer, and the field oxide layer are all formed using conformal covering.

8. The forming method according to claim 7, characterized in that, The step of forming the first shielding barrier further includes: A shielding grid material layer is formed to fill the first trench and cover the adjacent first trench. The shielding gate material layer is etched back, or the field oxide layer and the shielding gate material layer are etched back to obtain the first shielding gate.

9. The forming method according to claim 1, characterized in that, Also includes: A plurality of second trenches are formed on the substrate; A dielectric material layer is formed covering the bottom and sidewalls of the second trench; A portion of the second trench is filled to form a second shielding grid; A second dielectric layer is formed by using HDP chemical vapor deposition to cover the substrate and fill the second trench; The method for forming the second dielectric layer may be the same as or different from the method for forming the first dielectric layer.

10. The forming method according to claim 9, characterized in that, Meet one or more of the following: The depth of the second trench is the same as the depth of the first trench; The second trench is formed in the same step as the first trench; The length of the second shielding gate is greater than the length of the first shielding gate.

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