A field plate structure, a preparation method of a semiconductor device, and a semiconductor device

Abstract

This application discloses a field plate structure and a method for fabricating a semiconductor device, relating to the field of semiconductor technology. The method for fabricating the field plate structure includes: providing a substrate and sequentially forming a dielectric layer and a photoresist layer on the substrate, wherein the photoresist layer is made of a thermoplastic material; exposing and developing the photoresist layer to form multiple parallel strips arranged in a straight line, wherein the strips have the same width along a first direction, but the distance between adjacent strips gradually increases, or the distance between the strips is the same, but the width of the strips gradually decreases; heating the substrate with the strips to soften, deform, and flow the strips, and fusing them together through surface tension to form a tilted photoresist layer with gradually changing height; etching the upper surface of the photoresist layer to transfer the tilted surface of the photoresist layer onto the dielectric layer, forming a dielectric layer with a tilted interface; depositing a metal material to form an electrode and a field plate connected to the electrode, wherein the electrode is located on the exposed substrate, and the field plate covers the dielectric layer. This method for fabricating a field plate and a semiconductor device provides a simple method for fabricating tilted field plates and improves yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a field plate structure and a method for fabricating a semiconductor device, and the semiconductor device itself. Background Technology

[0002] In the field of semiconductor device fabrication, field plates are a commonly used method to improve device breakdown voltage. This is mainly achieved by altering the surface potential distribution of the device, specifically redistributing the electric field between the gate and drain electrodes, suppressing electric field concentration on the gate-drain side, and significantly reducing the peak electric field at that point, thereby improving the device's breakdown voltage. However, the edges of the field plate itself, especially the side near the drain, become new points of electric field concentration, generating secondary electric field spikes. This means that the electric field concentration problem is not fundamentally solved; it has merely shifted from the gate edge to the field plate edge. The overall improvement in the device's breakdown voltage remains limited by these secondary electric field spikes.

[0003] To suppress electric field concentration at the edges of field plates, existing technologies have proposed various improvement schemes, but all have significant drawbacks. One is the multi-layer stepped field plate: by stacking multiple field plates with increasing height and a stepped distribution, the electric field peaks of the previous layer are suppressed step by step. Although this method can effectively improve the breakdown voltage, its process flow is extremely complex, resulting in severely uneven chip surface morphology, which seriously affects subsequent integration processes such as metal interconnects and passivation layer deposition, significantly reducing manufacturing yield and making it difficult to apply to large-scale mass production. Tilted field plates: theoretically the optimal solution, its continuously changing slope structure can make the electric field distribution on the channel surface more uniform and gentle, greatly improving breakdown characteristics. However, its implementation depends on complex micro-nano fabrication processes, such as grayscale lithography or multi-step mask-etching combinations. Grayscale lithography requires customized special masks with varying transmittance gradients, which are costly and have narrow process windows, making them difficult to operate; while multi-step mask-etching schemes have extremely high requirements for overlay accuracy and have low yields. Summary of the Invention

[0004] The purpose of this application is to provide a field plate structure and a method for fabricating semiconductor devices, which can simplify the fabrication method of the field plate, facilitate operation, and improve yield.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a method for fabricating a field plate structure, comprising: providing a substrate and sequentially forming a dielectric layer and a photoresist layer on the substrate, wherein the photoresist layer is made of a thermoplastic material; exposing and developing the photoresist layer to form a plurality of parallel strips arranged in a straight line, wherein the direction from one end of the straight line to the other end is a first direction, and the strips have the same width along the first direction, with the distance between adjacent strips gradually increasing, or the strips have a gradually decreasing width along the first direction, but the distance between the strips is the same; heating the substrate on which the strips are formed, causing the strips to soften, deform, and flow, and fusing the strips by surface tension to form a photoresist layer with a gradually decreasing height along the first direction, wherein the upper surface of the photoresist layer is a first inclined surface relative to the substrate; etching the photoresist layer with the first inclined surface as a barrier layer, causing the thickness of the dielectric layer to gradually decrease along the first direction, forming a final dielectric layer with an inclined surface, and exposing the substrate, wherein the exposed substrate serves as an electrode contact surface; depositing a metal material to form an electrode and a field plate connected to the electrode, wherein the electrode is located on the exposed substrate, and the field plate covers the inclined surface of the final dielectric layer.

[0006] As one possible implementation, exposing and developing a photoresist layer to form multiple parallel stripes arranged in a straight line includes: exposing and developing the photoresist using a photomask, wherein the photomask includes multiple strip-shaped slit patterns, and the distance between the multiple strip-shaped slits gradually increases or remains constant along a first direction.

[0007] As one possible implementation method, the substrate on which the adhesive strip is formed is heated by hot baking at a temperature between 100-200°C for 2-5 minutes.

[0008] As one possible implementation, heating the substrate on which the adhesive strip is formed involves multiple heating processes.

[0009] As one possible implementation, a gap is formed between two adjacent adhesive strips, and the difference in width between the two adjacent gaps is determined based on the adhesive thickness, adhesive width, and tilt angle.

[0010] As one possible implementation, multiple adhesive strips may have the same width.

[0011] As one possible implementation, along the first direction, the width of the plurality of adhesive strips gradually decreases, and the gap width between two adjacent adhesive strips is the same.

[0012] As one possible implementation method, the photoresist is polymethyl methacrylate-based photoresist, etc.

[0013] A second aspect of this application provides a method for fabricating a semiconductor device, comprising: fabricating a field plate structure using the above-described fabrication method, the field plate structure including a substrate and electrodes and a dielectric layer disposed on the substrate, the dielectric layer having a second inclined surface that is inclined relative to the surface of the substrate, a field plate being formed on the second inclined surface, the electrodes including a source, a gate, and a drain, with the gate located between the source and the drain, the bottom of the second inclined surface being close to at least one of the gate, the source, and the drain, and connected to the corresponding electrode.

[0014] A third aspect of this application provides a semiconductor device fabricated using the above-described semiconductor device fabrication method, comprising a substrate and an epitaxial layer disposed on the substrate, wherein a source, a gate, and a drain are disposed at intervals on the epitaxial layer, and the gate is located between the source and the drain, the source, the gate, and the drain are isolated by a dielectric layer, and a field plate inclined relative to the surface of the epitaxial layer is connected to the gate, the source, or the drain.

[0015] The beneficial effects of the embodiments of this application include: The method for fabricating a field plate structure provided in this application includes: providing a substrate and sequentially forming a dielectric layer and a photoresist layer on the substrate, wherein the photoresist layer is made of a thermoplastic material; exposing and developing the photoresist layer to form a plurality of parallel strips arranged in a straight line, wherein the direction from one end of the straight line to the other end is a first direction, the width of the strips is consistent, but the distance between two adjacent strips gradually increases, or, along the first direction, the width of the strips gradually decreases, but the distance between the strips remains consistent; heating the substrate on which the strips are formed, causing the strips to soften, deform, and flow, and fusing and connecting the strips together by surface tension to form a photoresist layer with a gradually decreasing height along the first direction, wherein the upper surface of the photoresist layer is a first inclined surface relative to the substrate; etching the photoresist layer with the first inclined surface as a barrier layer, causing the thickness of the dielectric layer to gradually decrease along the first direction to form a final dielectric layer with an inclined surface, and exposing the substrate, wherein the exposed substrate serves as an electrode contact surface; depositing a metal material to form an electrode and a field plate connected to the electrode, wherein the electrode is located on the exposed substrate, and the field plate covers the inclined surface of the final dielectric layer. Requiring only one photolithography, heating, etching, and metal deposition step, this method significantly reduces process and equipment dependence compared to multi-stage field plates or grayscale lithography, simplifying the process flow, lowering costs, and making it easier to operate. Furthermore, it avoids the accumulation of alignment errors caused by multi-step overlay, thereby improving manufacturing yield and repeatability. In summary, the field plate structure fabrication method of this application simplifies the field plate fabrication process, facilitates operation, and improves yield. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a method for preparing a field plate structure provided in this application embodiment; Figure 2 This is one of the state diagrams for a method of preparing a field plate structure provided in an embodiment of this application; Figure 3 This is the second state diagram of a method for preparing a field plate structure according to an embodiment of this application; Figure 4 This is the third state diagram of a method for preparing a field plate structure according to an embodiment of this application; Figure 5 The fourth state diagram of a method for preparing a field plate structure provided in this application embodiment; Figure 6 Fifth state diagram of a method for preparing a field plate structure according to an embodiment of this application; Figure 7 A state diagram six illustrating a method for preparing a field plate structure according to an embodiment of this application; Figure 8 The seventh state diagram of a method for preparing a field plate structure provided in this application embodiment; Figure 9 This is the eighth state diagram of a method for preparing a field plate structure according to an embodiment of this application; Figure 10 State diagram nine of a method for preparing a field plate structure according to an embodiment of this application; Figure 11 The tenth state diagram of a method for preparing a field plate structure provided in this application embodiment; Figure 12 A flowchart illustrating a method for fabricating a semiconductor device as provided in this application embodiment; Figure 13 This is one of the state diagrams for a method of fabricating a semiconductor device provided in an embodiment of this application; Figure 14 A second state diagram of a method for fabricating a semiconductor device provided in an embodiment of this application; Figure 15 The third state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 16The fourth state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 17 The fifth state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 18 A sixth state diagram illustrating a method for fabricating a semiconductor device according to an embodiment of this application; Figure 19 The seventh state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 20 This is the eighth state diagram of a method for fabricating a semiconductor device according to an embodiment of this application. Figure 21 The ninth state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 22 The tenth state diagram is provided for a method of fabricating a semiconductor device according to an embodiment of this application; Figure 23 Eleventh of the state diagrams for a method of fabricating a semiconductor device provided in this application embodiment; Figure 24 The twelfth state diagram of a method for fabricating a semiconductor device provided in this application embodiment; Figure 25 This is diagram thirteen of a method for fabricating a semiconductor device according to an embodiment of this application. Figure 26 Fourteenth of the state diagrams for a method of fabricating a semiconductor device provided in this application embodiment; Figure 27 Electric field distribution curves for semiconductor devices with different field plate structures; Figure 28a The electric field distribution of semiconductor devices without field plates in the prior art; Figure 28b Electric field distribution of a semiconductor device with a field plate structure in the prior art; Figure 28c The electric field distribution of a semiconductor device having the tilted field plate structure of the present application embodiment; Figure 29 The breakdown electric field of semiconductor devices with different field plate structures.

[0018] Icons: 111-Substrate; 112-Dielectric layer; 113-Photoresist layer; 114-Resin strip; 115-Resin layer; 121-Field plate; 122-Gate; 210-Mask; 311-Source; 312-Drain; 321-Substrate; 322-Epipolar layer; 330-Isolation structure; 340-Cap layer. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0020] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Please refer to the reference. Figure 1 This application provides a method for preparing a field plate structure, comprising: S110: As Figure 2 and Figure 3 As shown, a substrate 111 is provided, and a dielectric layer 112 and a photoresist layer 113 are sequentially formed on the substrate 111, wherein the material of the photoresist layer 113 is thermoplastic.

[0023] It is understood that the field plate structure of this application embodiment is applied in a semiconductor device to change the electric field distribution on the device surface, and is disposed between the gate 122 and the drain 312. Specifically, the substrate 111 is the device body of the semiconductor device, and the semiconductor device can be formed by forming the source 311, the gate 122, the drain 312 and the field plate 121 on the device body. More specifically, the substrate 111 includes a substrate 321 and an epitaxial layer 322 disposed on the substrate 321.

[0024] The dielectric layer 112 is a silicon oxide layer or a silicon nitride layer.

[0025] S120: As Figure 4 and Figure 5As shown, the photoresist layer 113 is exposed and developed to form multiple parallel strips 114 arranged in a straight line, wherein the direction from one end of the straight line to the other end is the first direction (Rayet). Figure 5 In the first direction (a), the distance between two adjacent adhesive strips 114 gradually increases, or the width of the adhesive strip 114 gradually decreases.

[0026] The photoresist is exposed and developed to remove some of it, forming multiple strips 114 arranged in a straight line, with the strips 114 arranged in parallel. Specifically, the direction from one end of the line to the other is the first direction. In the first direction, the spacing between adjacent strips 114 gradually increases, or the width of the strips 114 gradually decreases. This is to create a uniformly varying distribution of the adhesive buildup height during subsequent softening, deformation, flow, and fusion.

[0027] S130: As Figure 6 , Figure 7 and Figure 8 As shown, the substrate 111 on which the adhesive strip 114 is formed is heated so that the adhesive strip 114 fuses to form an adhesive layer 115 whose height gradually decreases along the first direction, wherein the adhesive layer has a first inclined surface that is inclined relative to the substrate. The substrate 111 on which the adhesive strip 114 is formed is heated, specifically, heated to above the glass transition temperature of the photoresist, so that it softens, deforms, flows, and fuses due to surface tension, ultimately forming an adhesive layer 115 whose height continuously decreases along the first direction, and the adhesive layer has a first slope.

[0028] Specifically, the thermoplastic strip 114 softens upon heating, and surface tension drives it to evolve towards a flatter state. When the distance between two adjacent strips 114 gradually increases along the first direction, i.e., when the initial pattern is a non-uniformly distributed strip 114, a thickness gradient will be formed locally after fusion. The denser areas of the strips 114 will have a higher thickness, while the sparser areas will have a lower thickness. When the width of the strip 114 gradually decreases along the first direction, the wider areas of the strip 114 will have a higher thickness, while the narrower areas will have a lower thickness.

[0029] Understandably, in order to facilitate the fusion of the photoresist strip 114 during heating, a material with good thermoplasticity can be selected.

[0030] S140: As Figure 9 As shown, the adhesive layer with a first inclined surface is used as a barrier layer for etching, so that the thickness of the dielectric layer 112 gradually decreases along the first direction, forming a final dielectric layer with an inclined surface, and exposing part of the substrate 111. Anisotropic etching is used to etch from top to bottom. Due to the variation in the thickness of the adhesive layer 115 along the first direction, the etching stop time is different, resulting in the lower dielectric layer 112 being etched into a slope morphology with the thickness gradually decreasing along the first direction, exposing the substrate 111 as the contact surface of the electrode.

[0031] Specifically, due to the constant etching rate, the thicker adhesive layer 115 provides longer protection and retains more of the underlying dielectric; the thinner adhesive layer 115 is penetrated first, and the dielectric layer 112 is etched deeper, even exposing the substrate 111. Ultimately, the dielectric layer 112 exhibits a morphological profile with a continuously and uniformly varying thickness.

[0032] In practical applications, photoresist is typically applied across the entire dielectric layer 112. After etching, a portion of the photoresist layer 115 remains. Before proceeding to the next step, this remaining photoresist layer 115 can be removed, such as... Figure 10 As shown.

[0033] It is understood that in semiconductor devices, electrodes include three types: gate, source, and drain. A field plate can be disposed on one side of one of the three types of electrodes. For ease of description, this application uses the gate as an example for illustration. In practical applications, in order to suppress electric field spikes, the field plate can be disposed on the side of the source near the gate and connected to the source; or on the side of the gate near the drain and connected to the gate; or on the side of the drain near the gate and connected to the drain.

[0034] S150: As Figure 11 As shown, a metal material is deposited to form a gate 122 and a field plate 121 connected to the gate 122, wherein the gate 122 is located on the exposed substrate 111 and the field plate 121 covers the final dielectric layer.

[0035] Metal is deposited to form a gate 122 on the exposed substrate 111, and a field plate 121 connected to the gate 122 is formed on the final dielectric layer. Since the final dielectric layer is sloped, the field plate 121 naturally forms an inclined structure.

[0036] The surface is covered with metal, but a continuous transition metal layer is formed on the dielectric layer 112 of different thicknesses. That is, the field plate 121 and the gate 122 are integrally formed and have a smooth slope, which effectively avoids the electric field from changing abruptly at the edge of the field plate 121.

[0037] As can be seen from the above field plate structure fabrication process, the fabrication method of this application embodiment requires only one photolithography, heating, etching, and metal deposition step. Compared with multi-stage field plates or grayscale photolithography, it significantly reduces process and equipment dependence, simplifies the process flow, reduces costs, and is easier to operate. Furthermore, it avoids the accumulation of alignment errors caused by multi-step overlay, thereby improving manufacturing yield and repeatability. In summary, the field plate structure fabrication method of this application embodiment simplifies the field plate fabrication method, facilitates operation, and improves yield.

[0038] Optional, such as Figure 4 As shown, the photoresist layer 113 is exposed and developed to form multiple parallel strips 114 arranged in a straight line, including: The photoresist is exposed and developed using a mask 210, wherein the mask 210 includes multiple strip slits, and the distance between the multiple strip slits gradually increases along a first direction.

[0039] Specifically, the photomask 210 has multiple strip-shaped slits as its light-transmitting areas. These strip-shaped slits are parallel to each other and linearly arranged along a first direction. The spacing between adjacent strip-shaped slits gradually increases along the first direction. During exposure, the exposure beam passes through these strip-shaped slits to irradiate the photoresist layer 113 below. After development, the photoresist in the exposed area is removed, leaving unexposed strips 114 on the substrate 111, whose positions correspond to the opaque areas on the photomask 210. The spacing of the resulting strips 114 is complementary to the spacing of the strip-shaped slits on the photomask 210. If the slit spacing increases, the spacing of the strips 114 also increases accordingly.

[0040] It should be noted that the above explanation uses positive photoresist as an example. In practical applications, when negative photoresist is used, the exposure and development are reversed.

[0041] As one feasible approach, when heating the substrate 111 on which the adhesive strip 114 is formed, the heating temperature is between 100-200°C and the heating time is between 2-5 minutes.

[0042] When the photoresist layer 113 is made of polymethyl methacrylate photoresist, its glass transition temperature (Tg) is typically 105°C. In this embodiment, the heating temperature is set between 100-200°C, slightly higher than Tg, to ensure that the colloid is sufficiently softened and has fluidity, but is far below the decomposition temperature. The heating time is set between 2-5 minutes, which is sufficient to complete the softening, deformation, surface tension-driven flow, and morphology stabilization of the colloid, while avoiding excessive diffusion that could lead to pattern distortion.

[0043] Specifically, when the heating temperature exceeds the Tg of the photoresist layer 113, the polymer chains of the photoresist strip 114 gain sufficient energy, and the colloid changes from a glassy state to a viscous flow state, exhibiting good fluidity. If the temperature is too low, the colloid will not soften sufficiently, resulting in insufficient flow and an inability to form a smooth slope; if the temperature is too high, it may cause excessive flow of the colloid, pattern collapse, or even thermal decomposition to produce bubbles or carbonization.

[0044] Two minutes is the minimum effective time to ensure that heat is evenly conducted to the entire adhesive layer 115 and initial fusion is completed; five minutes is the upper limit to prevent the adhesive from spreading excessively to lower areas due to prolonged heating, which could cause distortion of the slope contour or blurring of the edges. Between 2 and 5 minutes, the adhesive tends to the configuration of lowest energy under the action of surface tension. The high-density adhesive strip 114 region fuses into a thick film, while the low-density region forms a thin film, ultimately forming a continuous adhesive layer 115 with a height gradient along the first direction.

[0045] Understandably, both the heating temperature and heating time are related to the material of the photoresist layer 113. For other photoresist materials, the heating temperature and heating time can be set according to their melting point.

[0046] Optional, such as Figure 6 , Figure 7 and Figure 8 As shown, the substrate 111 on which the adhesive strip 114 is formed is heated multiple times.

[0047] Multiple heating refers to heat-treating the same substrate 111 in two or more heating steps after the photoresist layer 113 is patterned. Each heating can have different temperature, time or atmosphere conditions. For example, the first heating is a low-temperature pre-leveling and the second heating is a high-temperature precision forming. The purpose of multiple heating is to control the flow behavior of the adhesive strip 114 in steps and avoid pattern distortion or uncontrollable diffusion caused by violent flow in a single heating.

[0048] Multiple heating stages, through phased regulation of the flow dynamics driven by the viscoelasticity and surface tension of the colloidal molecules, achieve a more refined morphological evolution: specifically, in the first stage, such as... Figure 6 and Figure 7 As shown, low-temperature preheating and leveling (e.g., 120°C, 2 min) softens the colloid but the viscosity remains high, and adjacent strips 114 partially fuse, eliminating sharp edges and micro-gaps; forming a preliminary continuous but undulating rough outline; preventing sudden collapse of the colloid at subsequent high temperatures; the second stage, as... Figure 8 As shown, during high-temperature precision molding (e.g., 160℃ for 3 min), the viscosity of the colloid is further reduced and the fluidity is enhanced; under the dominance of surface tension, the colloid evolves towards the configuration with the lowest energy; since the initial pattern has been pre-leveled, the flow is more uniform and predictable at this time, forming a smooth and continuous sloping colloid layer 115; which can effectively suppress non-ideal phenomena such as overflow or backflow.

[0049] By setting up multiple heating cycles, the problem of inconsistent flow caused by local heat accumulation or uneven glue thickness due to single heating is avoided, which can lead to ripples, plateaus, or abrupt changes. Multiple heating cycles achieve a slope that is closer to the ideal linear or customized curve through gradual morphological evolution, improving the accuracy and smoothness of the slope profile and making it more conducive to the uniform distribution of the electric field.

[0050] As one feasible approach, a gap is formed between two adjacent adhesive strips 114, with the difference in width between the two adjacent gaps being between 0.1 and 0.5 micrometers.

[0051] A gap is formed between two adjacent adhesive strips 114, such as Figure 5 In the context of b1, b2, b3, b4, and b5, the difference Δb between the widths of two adjacent slits refers to b1-b2, b2-b3, b3-b4, and b4-b5. A difference between 0.1 and 0.5 micrometers means that the change in slit width at each step is controlled within the range of 0.1–0.5 micrometers.

[0052] The wider the gap, the sparser the adhesive strips 114, and the smaller the adhesive volume per unit area; the narrower the gap, the denser the adhesive strips 114, the more fully they fuse, and the higher they accumulate; when the width of adjacent gaps increases at a constant step size, the density of the adhesive strips 114 decreases linearly, and the height of the adhesive layer 115 formed after fusion also decreases approximately linearly, thereby achieving a high-precision, smooth profile of the inclined field plate 121.

[0053] If Δb < 0.1 μm, the density change of the adhesive strip 114 is too slow, and the height gradient after fusion is too small, which cannot form a slope with a sufficiently steep slope, resulting in insufficient tilting of the field plate 121 and weak electric field control effect. If Δb > 0.5 μm, the distribution of the adhesive strip 114 changes drastically, and the local flow is discontinuous during fusion, which easily produces step residue, ripples or fractures, and destroys the smoothness of the slope. Experiments have shown that when Δb is between 0.1 and 0.5 μm, the height change rate of the adhesive layer 115 after heat flow can be moderate, which ensures the existence of the slope and maintains the surface continuity.

[0054] It should be noted that the difference in width between two adjacent gaps is related to the width of the adhesive strip 114, the width of the gap, the number of adhesive strips 114, the thickness of the adhesive, and the tilt angle of the field plate 121. Those skilled in the art can set it according to the actual situation.

[0055] For example, such as Figure 5 , Figure 8 As shown, the tilt angle is =30°, the horizontal length of the inclined surface L=10μm, and 5 adhesive strips 114 are designed. Each adhesive strip 114 has the same width, W=1μm, and the height H of the adhesive strip 114 is 5μm. The gaps b follow an arithmetic sequence relationship, where b5=0.2μm, b4=0.483μm, b3=0.649μm, b2=0.815μm, and b1=0.981μm.

[0056] In practical applications, the tilt angle of the field plate 121 is between 15° and 60°. Those skilled in the art can set the number, width, and gap size of the adhesive strips 114 according to the tilt angle. It is understood that multiple adhesive strips 114 fuse together to form an inclined adhesive layer 115, and the two layers have equal volumes.

[0057] Optional, such as Figure 5 As shown, the width of the multiple adhesive strips 114 is the same.

[0058] Specifically, the width of the adhesive strip 114 remains constant, while the width of the gap gradually increases. That is, the width of the adhesive strip 114 itself remains constant, and the density gradient is achieved only by adjusting its spacing. The density of the colloid distribution is controlled only by the change in the gap, thus avoiding the process complexity caused by the coupling of the two variables of width and spacing.

[0059] The adhesive strips 114 have the same width, meaning that the initial volume of each adhesive strip 114 is the same as its cross-sectional area. The gap width increases along the first direction, causing the linear density (volume of adhesive per unit length) of the adhesive strip 114 to decrease linearly. During fusion, the photoresist material mainly flows laterally to the adjacent gap area. Since each adhesive strip 114 has the same supply capacity, the flow behavior is determined only by the size of the local gap, thus forming a slope of adhesive layer 115 with a height that decreases monotonically and smoothly along the first direction, and the contour is highly predictable.

[0060] As one feasible approach, along the first direction, the width of the plurality of adhesive strips 114 gradually decreases, and the gap width between two adjacent adhesive strips 114 is the same.

[0061] The width of the multiple adhesive strips 114 gradually decreases, meaning the size of each adhesive strip 114 decreases sequentially in the first direction. The same gap width between any two adjacent adhesive strips 114 means the gap between any two adjacent adhesive strips 114 remains constant. Therefore, the center-to-center distance of the adhesive strips 114 gradually decreases along the first direction, resulting in an overall distribution with increasing adhesive density. This embodiment of the application achieves a gradient change in photoresist volume per unit length by adjusting the width of the adhesive strips 114 themselves, thereby forming a gradient slope adhesive layer 115 after heat flow.

[0062] Specifically, the gaps are constant and the adhesive strips 114 are equidistant; the width decreases, that is, the cross-sectional area and volume of each adhesive strip 114 decreases sequentially; during fusion, the wider adhesive strip 114 provides more material and stacks higher; the narrower adhesive strip 114 contributes less and has a lower height; finally, a continuous adhesive layer 115 with a gradually decreasing height along the first direction is formed.

[0063] Optionally, the photoresist is a polymethyl methacrylate-based photoresist.

[0064] Polymethyl methacrylate (PMMA) is a typical thermoplastic polymer; PMMA is used here as a dual-purpose material for patterning and hot flow forming; high molecular weight PMMA is usually used to balance film-forming properties, resolution and thermal flow stability.

[0065] PMMA has a glass transition temperature of approximately 100–110°C, and it softens sufficiently within a heating temperature range of 100–200°C, reducing its viscosity to 10³–10⁻⁶. 5 Pa·s; and the smooth flow driven by surface tension; the absence of chemical cross-linking or decomposition, etc., make it an ideal heat flow material that can transform the initial discrete strip 114 pattern into a continuous slope.

[0066] This application also provides a method for fabricating a semiconductor device, such as... Figure 12 As shown, it includes: S210: As Figures 13 to 24 As shown, a field plate structure is fabricated using the above-described method. The field plate structure includes a substrate 111 and electrodes and a dielectric layer 112 disposed on the substrate 111. The dielectric layer 112 has a second inclined surface relative to the substrate surface, and a field plate 121 connected to the electrodes is formed on the second inclined surface. The substrate 111 includes a substrate 321 and an epitaxial layer 322 stacked together. The electrodes include a source, a gate, and a drain, with the gate located between the source and the drain. The bottom of the second inclined surface is close to at least one of the gate, the source, and the drain, and is connected to the corresponding electrode.

[0067] Taking the gate as an example, using the aforementioned field plate structure fabrication method, a dielectric layer 112 and a photoresist layer 113 are formed on a substrate 111, wherein the substrate 111 includes a substrate 321 and an epitaxial layer 322. The thickness of the dielectric layer 112 gradually decreases along a first direction, wherein the first direction is from the gate 122 to the drain 312; metal is deposited on the dielectric layer 112 to form a field plate 121 electrically connected to the gate 122, and the field plate 121 covers the inclined dielectric layer 112; the gate 122 directly contacts the epitaxial layer 322, that is, it is usually located in the area where the dielectric layer 112 is completely etched and exposed.

[0068] The specific structure of the semiconductor device is not limited in this application embodiment, nor is the corresponding epitaxial layer 322 limited, as long as it is a semiconductor device that requires electric field balance by the field plate 121.

[0069] For example, this application uses an existing HEMT device as an example for illustration. Figure 13As shown, the epitaxial layer 322 of the HEMT device includes a channel layer and a barrier layer, and a buffer layer is also disposed between the channel layer and the substrate 321. In practical applications, a cap layer 340 is also disposed between the gate 122 and the epitaxial layer 322 of the HEMT device, specifically, as shown... Figure 13 As shown, a P-GaN layer is deposited on the epitaxial layer 322 and etched to form a cap layer 340, as follows. Figure 14 As shown. In addition, to isolate adjacent devices, an isolation structure 330 is also provided, such as... Figure 15 As shown, the whole serves as the substrate 111 of the semiconductor device.

[0070] Figure 16 and Figure 17 As shown, a dielectric layer 112 and a photoresist layer 113 are formed on a substrate 111; as Figure 18 As shown, photoresist is exposed and developed using a photomask 210 to remove part of the photoresist, forming multiple strips 114 arranged in a straight line, and the multiple strips 114 are arranged in parallel, as shown. Figure 19 As shown; then the substrate 111 on which the adhesive strip 114 is formed is heated, causing the adhesive strip 114 to fuse, forming an adhesive layer 115 whose height gradually decreases along the first direction, as shown. Figure 20 and Figure 21 As shown; etching is performed on the upper surface of the adhesive layer 115, causing the thickness of the dielectric layer 112 to gradually decrease along the first direction, exposing part of the substrate 111, as shown. Figure 22 As shown; remove the remaining photoresist, such as Figure 23 As shown; depositing metallic material to form a gate 122 and a field plate 121 connected to the gate 122, as... Figure 24 As shown.

[0071] S220: A source 311 and a drain 312 are formed on both sides of the gate 122, and a field plate 121 is located on the side of the gate 122 facing the drain 312, wherein the source 311 and the drain 312 pass through the dielectric layer 112 of the field plate 121 and contact the epitaxial layer.

[0072] Specifically, the dielectric layer 112 covers the surface of the overall substrate 111. Before forming the source 311 and drain 312, connection holes are etched on opposite sides of the gate 122, such as... Figure 25 As shown, a metal material is disposed within the connection hole to form the source electrode 311 and the drain electrode 312, as follows. Figure 26 As shown.

[0073] This application also provides a semiconductor device, which is fabricated using the above-described semiconductor device fabrication method, such as... Figure 26As shown, it includes a substrate 321 and an epitaxial layer 322 disposed on the substrate 321. A source 311, a gate 122 and a drain 312 are disposed on the epitaxial layer 322 at intervals, and the gate 122 is located between the source 311 and the drain 312. The source 311, the gate 122 and the drain 312 are isolated by a dielectric layer 112. The gate 122, the source 311 or the drain 312 are also connected to a field plate 121 that is inclined relative to the surface of the epitaxial layer.

[0074] To further verify the beneficial effects of the tilted field plate in the embodiments of this application, the embodiments of this application used TCAD software to simulate the influence of different gate field plate structures on the electric field distribution and breakdown field strength of semiconductor devices, such as... Figure 27 , Figure 28a , Figure 28b as well as Figure 28c The electric field distribution curves and diagrams of semiconductor devices with three different field plate structures are shown, specifically the electric field distribution between the gate and drain at a source-drain voltage of 400V. Figure 28a It is evident that in the gateless field plate structure, the electric field is concentrated at the gate edge, and the peak electric field is very high; Figure 28b It is evident that in existing parallel field plate structures, the electric field distribution has shifted, concentrating at the ends of the field plate structure, and the peak electric field remains very high; Figure 28c It is clearly visible that the tilted field plate structure in this embodiment exhibits a more uniform electric field distribution and suppressed peak field strength. Figure 29 As can be seen, the field plate structure of this application embodiment can significantly improve the breakdown field strength of semiconductor devices. Specifically, the inclined field plate structure improves the breakdown field strength by 539V compared to the parallel field plate in the prior art.

[0075] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0076] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A method for preparing a field plate structure, characterized in that, include: A substrate is provided, and a dielectric layer and a photoresist layer are sequentially formed on the substrate, wherein the photoresist layer is made of a thermoplastic material; The photoresist layer is exposed and developed to form a plurality of parallel strips arranged in a straight line. The direction from one end of the straight line to the other end is a first direction. Along the first direction, the strips have the same width and the distance between two adjacent strips gradually increases. Alternatively, along the first direction, the distance between the strips is the same and the strip width gradually decreases. The substrate on which the adhesive strips are formed is heated, causing the adhesive strips to soften, deform, and flow, and the adhesive strips are fused together by surface tension to form an adhesive layer with a gradually changing height along a first direction, the adhesive layer having a first inclined surface relative to the substrate; The adhesive layer with a first inclined surface is used as a barrier layer for etching, so that the thickness of the dielectric layer gradually decreases along the first direction, forming a final dielectric layer with an inclined surface and exposing the substrate, which serves as the electrode contact surface. A metallic material is deposited to form an electrode and a field plate connected to the electrode, wherein the electrode is located on an exposed substrate and the field plate covers the inclined surface of the final dielectric layer.

2. The method of claim 1, wherein The process of exposing and developing the photoresist layer to form multiple parallel stripes arranged in a straight line includes: The photoresist is exposed and developed using a photomask, wherein the photomask includes a plurality of strip slits, and the distance between the plurality of strip slits gradually increases or remains constant along a first direction.

3. The method of claim 1, wherein When heating the substrate on which the adhesive strip is formed, the heating temperature is between 100-200℃ and the heating time is between 2-5 minutes.

4. The method for preparing the field plate structure according to claim 3, characterized in that, The heating of the substrate on which the adhesive strip is formed includes multiple heating processes.

5. The method of claim 1, wherein A gap is formed between two adjacent adhesive strips, and the difference in width between two adjacent gaps is determined based on the adhesive thickness, adhesive width, and tilt angle.

6. The method of claim 5, wherein the field plate structure is formed by: The width of all of the adhesive strips is the same.

7. The method of claim 1, wherein Along the first direction, the width of the plurality of adhesive strips gradually decreases, and the gap width between two adjacent adhesive strips is the same.

8. The method of claim 1, wherein The photoresist is a polymethyl methacrylate-based photoresist.

9. A method of manufacturing a semiconductor device, characterized by, include: A field plate structure is prepared using the preparation method according to any one of claims 1-8. The field plate structure includes a substrate, an electrode disposed on the substrate, and a dielectric layer. The dielectric layer has a second inclined surface that is inclined relative to the surface of the substrate. A field plate connected to the electrode is formed on the second inclined surface. The electrode includes a source, a gate, and a drain. The gate is located between the source and the drain. The bottom of the second inclined surface is close to at least one of the gate, the source, and the drain, and is connected to the corresponding electrode.

10. A semiconductor device, characterized by comprising: The semiconductor device is fabricated using the method described in claim 9, comprising a substrate and an epitaxial layer disposed on the substrate. A source, a gate, and a drain are disposed at intervals on the epitaxial layer, and the gate is located between the source and the drain. The source, the gate, and the drain are isolated by a dielectric layer. The gate, the source, or the drain is further connected to a field plate that is inclined relative to the surface of the epitaxial layer.

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