GaN integrated circuit chips and their manufacturing methods

Abstract

This application provides a GaN integrated circuit chip, comprising: an epitaxial substrate including a channel layer and a barrier layer; a first ohm finger strip, a second ohm finger strip, and a third ohm finger strip formed on the epitaxial substrate, the first ohm finger strip, the second ohm finger strip, and the third ohm finger strip being arranged side by side along the width direction, the second ohm finger strip being located between the first ohm finger strip and the third ohm finger strip along the width direction; the first ohm finger strip and the second ohm finger strip both passing through the barrier layer and contacting the channel layer; a gate unit being disposed between the first ohm finger strip and the second ohm finger strip along the width direction, thereby forming a GaN FET; and the third ohm finger strip being formed above the barrier layer, thereby forming a diode with the second ohm finger strip.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a GaN integrated circuit chip and a method for manufacturing the same. Background Technology

[0002] The description in this section provides only background information relevant to the disclosure of this application and does not constitute prior art.

[0003] Current traditional gallium nitride IC chip layout, such as Figure 1 As shown, the main die area and the diode area are placed in different regions of the chip. That is, the main die area and the diode area are placed separately. This may lead to uneven heat dissipation and wasted chip area.

[0004] Furthermore, diodes in current gallium nitride ICs are typically implemented using LFERs (lateral field-effect rectifiers), such as... Figure 2 As shown, a three-electrode gallium nitride FET device is constructed by shorting the gate-source / drain terminals to form the diode anode, while the drain / source terminals serve as the diode cathode. This approach offers compatibility with the gallium nitride Emode platform process. However, this diode has a relatively high turn-on voltage, typically 1.7V. Especially in reverse conduction applications, a sufficiently low turn-on voltage is desirable to reduce reverse conduction power consumption and thus improve system efficiency.

[0005] Therefore, there is an urgent need for a GaN IC chip structure and its fabrication method that can optimize chip thermal distribution, improve area utilization, reduce diode turn-on voltage, and simplify the process.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] Based on the aforementioned deficiencies in the prior art, the GaN integrated circuit chip and its manufacturing method disclosed in this application have better performance and a simpler preparation method.

[0008] To achieve the above objectives, this application provides the following technical solution: a GaN integrated circuit chip, comprising: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer and a barrier layer; A first ohm finger strip, a second ohm finger strip, and a third ohm finger strip are formed on the outer epitaxial base layer. The first ohm finger strip, the second ohm finger strip, and the third ohm finger strip are arranged side by side along the width direction. The second ohm finger strip is located between the first ohm finger strip and the third ohm finger strip along the width direction. Both the first ohm finger and the second ohm finger pass through the barrier layer and contact the channel layer; A gate unit is disposed between the first ohm finger strip and the second ohm finger strip along the width direction, thereby forming a GaN FET by the first ohm finger strip, the gate unit and the second ohm finger strip; The third ohmic finger is formed above the barrier layer, thereby forming a diode with the second ohmic finger.

[0009] Preferably, the GaN FET and the diode share the same continuous active region, with continuous conduction of the two-dimensional electron gas and no electrical isolation structure.

[0010] This application discloses a GaN integrated circuit chip, including: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer and a barrier layer; A first ohm finger strip, a second ohm finger strip, a fourth ohm finger strip, and a third ohm finger strip are formed on the epitaxial base layer and arranged sequentially along the width direction; The first ohm finger, the second ohm finger, and the fourth ohm finger all pass through the barrier layer and contact the channel layer; A gate unit is disposed between the first ohm finger strip and the second ohm finger strip along the width direction, thereby forming a GaN FET by the first ohm finger strip, the gate unit and the second ohm finger strip; The third ohmic finger is formed above the barrier layer, thereby forming a diode with the fourth ohmic finger.

[0011] Preferably, the active region where the diode is located is isolated from the active region where the GaN FET is located.

[0012] Preferably, the barrier layer located below the third ohmic finger remains intact and without grooves.

[0013] Preferably, a PGaN anode layer is disposed below the third ohmic finger strip, the third ohmic finger strip and the PGaN anode layer form an ohmic contact, and the PGaN anode layer and the two-dimensional electron gas below form a heterojunction, which serves as the rectifier junction of the diode.

[0014] Preferably, the third ohmic finger strip passes through the gate metal-anode layer and contacts the PGaN anode layer; or, the bottom of the third ohmic finger strip contacts the PGaN anode layer, and the width of the bottom of the third ohmic finger strip is greater than that of the PGaN anode layer; or, there are two PGaN anode layers, with an anode insertion layer disposed between the two PGaN anode layers, and the lower surface of the third ohmic finger strip ends at the upper surface of the anode insertion layer; or, an anode insertion layer is disposed above the PGaN anode layers, and the lower surface of the third ohmic finger strip ends at the upper surface of the anode insertion layer.

[0015] Preferably, the third ohmic finger directly contacts the upper surface of the barrier layer, forming a Schottky contact with the barrier layer, and serves as the rectifier junction of the diode.

[0016] Preferably, the first ohmic finger strip, the second ohmic finger strip, and the third ohmic finger strip are formed from the same ohmic metal layer in the same ohmic metal deposition and etching process step.

[0017] This application discloses a method for fabricating a GaN integrated circuit chip, including the following steps: Provide substrate; An epitaxial layer is formed on the substrate, and a gate cell is formed after the epitaxial layer is formed; An opening is made in the anode region of the diode; Make an opening in the ohmic region; Ohmic metal is deposited at the openings in the ohmic region and at the openings in the anode region of the diode; After etching the ohmic metal, the source and drain of the GaN FET, as well as the anode and cathode of the diode, are formed.

[0018] The beneficial effects of this application, based on the above technical solutions, are as follows: 1. In this application, the diode's fingers and the GaN FET's fingers are arranged side by side, and the diode's fingers are even inserted between the fingers of multiple GaN FETs, which optimizes the chip's heat distribution and improves the area utilization.

[0019] 2. Both the anode and cathode of the diode are made of ohmic metal and are formed in the same layer and process as the source and drain ohmic metal of the FET, which simplifies the manufacturing process and reduces costs.

[0020] 3. The barrier layer beneath the diode remains intact without grooves, avoiding groove etching damage and electric field concentration, thus improving breakdown voltage and reliability.

[0021] 4. One diode in this application utilizes a PGaN / 2DEG heterojunction, which has an adjustable turn-on voltage and low reverse leakage current. Another diode in this application utilizes a planar metal-AlGaN Schottky junction, which has a simple manufacturing process.

[0022] 5. Different integration methods, such as shared active area (without isolation) or active area isolation, can be selected to flexibly adapt to different circuit requirements.

[0023] 6. The preparation process does not require high-temperature oxidation and wet corrosion, thus avoiding the problems of high thermal budget and pollution from wet processes.

[0024] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, illustrating how the principles of this application can be employed. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of this application include many changes, modifications, and equivalents.

[0025] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0026] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0027] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings: Figure 1 This illustrates the layout of a conventional gallium nitride IC chip in the prior art.

[0028] Figure 2 A schematic diagram of the equivalent diode based on a conventional LFER is shown.

[0029] Figure 3 The layout of a GaN integrated circuit chip according to one embodiment of this application is shown.

[0030] Figure 4 It shows Figure 3 A cross-sectional schematic diagram.

[0031] Figures 5A-5F It shows Figure 3 A schematic diagram of the manufacturing process of GaN integrated circuit chips.

[0032] Figure 6 The layout of a GaN integrated circuit chip according to another embodiment of this application is shown.

[0033] Figure 7 It shows Figure 6 A cross-sectional schematic diagram.

[0034] Figure 8 A cross-sectional schematic diagram of a GaN integrated circuit chip according to yet another embodiment of this application is shown.

[0035] Figure 9 A cross-sectional schematic diagram of a GaN integrated circuit chip according to another embodiment of this application is shown.

[0036] Figure 10 A cross-sectional schematic diagram of a GaN integrated circuit chip according to another embodiment of this application is shown.

[0037] Figure 11 It shows Figure 10 A cross-sectional schematic diagram.

[0038] Figure 12A-12F It shows Figure 10 A schematic diagram of the fabrication process of GaN integrated circuit chips.

[0039] Figure 13 The layout of a GaN integrated circuit chip is shown in another embodiment of this application.

[0040] Figure 14A A first application circuit based on a GaN integrated circuit chip in an embodiment of this application is shown.

[0041] Figure 14B A second application circuit based on a GaN integrated circuit chip in an embodiment of this application is shown.

[0042] Figure 14C A third application circuit based on a GaN integrated circuit chip in an embodiment of this application is shown.

[0043] The reference numerals in the above figures are as follows: 10, substrate; 11, buffer layer; 12, channel layer; 13, barrier layer; 15, gate cell; 151, gate metal layer; 152, PGaN gate layer; 16, gate metal-anode layer; 17, PGaN anode layer; 18, anode insertion layer; 19, gate insertion layer; 20, GaN FET; 21, diode; 31, first ohm finger strip; 32, second ohm finger strip; 33, third ohm finger strip; 34, fourth ohm finger strip; 41, PGaN layer; 42, gate metal material; 43, passivation layer. Detailed Implementation

[0044] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0045] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0048] It should be noted that in the description of this application, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more.

[0049] Reference Figure 3 and Figure 4 As shown in the figure, this application discloses a GaN integrated circuit chip, including: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer 12 and a barrier layer 13; A first ohm finger strip 31, a second ohm finger strip 32, and a third ohm finger strip 33 are formed on the outer extension base layer. The first ohm finger strip 31, the second ohm finger strip 32, and the third ohm finger strip 33 are arranged side by side along the width direction. The second ohm finger strip 32 is located between the first ohm finger strip 31 and the third ohm finger strip 33 along the width direction. Both the first ohmic finger strip 31 and the second ohmic finger strip 32 pass through the barrier layer 13 and contact the channel layer 12; A gate unit 15 is disposed between the first ohm finger strip 31 and the second ohm finger strip 32 along the width direction, thereby forming a GaN FET 20 with the first ohm finger strip 31, the gate unit 15 and the second ohm finger strip 32. The third ohmic finger strip 33 is formed above the barrier layer 13, thereby forming a diode 21 with the second ohmic finger strip 32.

[0050] Similar to existing technologies, the epitaxial layer can be formed on the substrate 10. The substrate 10 can be a silicon (Si) substrate 10, or a substrate 10 composed of several materials such as silicon on insulator (SOI). The thickness of the substrate 10 is generally in the range of 300µm-3000µm. When using a Si substrate 10, its resistivity ranges from 0.001 to 5000 Ω·cm.

[0051] The epitaxial base layer may include, from bottom to top, a buffer layer 11 formed on the substrate 10, a channel layer 12 formed on the buffer layer 11, and a barrier layer 13 formed on the channel layer 12.

[0052] The buffer layer 11 can be made of different materials depending on the substrate 10 and specific requirements. For example, when using a silicon substrate 10, it can be composed of an AlN nucleation layer, one or more AlGaN transition layers, a superlattice buffer layer 11 formed by alternating AlN and AlGaN, and a high-carbon layer (carbon concentration greater than 10). 18 cm-3 It can be composed of GaN layers, or sequentially of AlN nucleation layers, one or more AlGaN layers, and high carbon (carbon concentration greater than 10). 18 cm -3 It consists of GaN layers.

[0053] The channel layer 12 can be formed of a semiconductor material, for example, a low-carbon material (carbon concentration less than 10). 18 cm -3 The barrier layer 13 can be formed of a semiconductor material, such as a compound based on a gallium nitride ternary or quaternary alloy, such as Al. x Ga 1x N, AlInGaN, In x Ga 1x N, Al x In 1x Al, AlScN. In this embodiment, the gate unit 15 includes a P-GaN gate layer 14 and a gate metal layer 15115 formed above the barrier layer 13.

[0054] Reference Figure 3 and Figure 4 As shown, along the chip width direction ( Figure 3 The first ohm finger strip 31 and the second ohm finger strip 32 are disposed on both sides of the gate unit 15 (in the direction of the paper width). Specifically, the first ohm finger strip 31 is located on the left side of the gate unit 15, and the second ohm finger strip 32 is located on the right side of the gate unit 15. The gate unit 15, the first ohm finger strip 31, and the second ohm finger strip 32 are all along the length direction of the chip (in the direction of the paper width). Figure 3 The first ohm finger 31 and the second ohm finger 32 both pass through the passivation layer 43 and the barrier layer 13, and come into contact with the channel layer 12.

[0055] In this embodiment, the first ohm finger strip 31 is the source finger strip. The second ohm finger strip 32 is the drain and the cathode of the diode 21. The first ohm finger strip 31 is also connected to a field plate unit extending from the first ohm finger strip 31 toward the second ohm finger strip 32. The field plate unit includes a field plate connection portion connected to the first ohm finger strip 31 and a field plate body extending from the gate region toward the second ohm finger strip 32. Thus, the first ohm finger strip 31, the gate unit 15, and the second ohm finger strip 32 form a GaN FET 20.

[0056] A third ohm finger strip 33 is also provided to the right of the second ohm finger strip 32. The third ohm finger strip 33 is formed above the barrier layer 13, thereby forming the anode of the diode 21 in the region where the third ohm finger strip 33 is located, thus forming a diode 21 with the second ohm finger strip 32. In this embodiment, a PGaN anode layer 17 is provided below the third ohm finger strip 33. A gate metal-anode layer 16 is retained between the third ohm finger strip 33 and the PGaN anode layer 17, and the third ohm finger strip 33 contacts the PGaN anode layer 17 through the gate metal-anode layer 16. The third ohm finger strip 33 forms an ohmic contact with the PGaN anode layer 17, and the PGaN anode layer 17 forms a heterojunction with the underlying two-dimensional electron gas, serving as the rectifier junction of the diode 21. Furthermore, the barrier layer 13 located below the third ohm finger strip 33 remains intact and without grooves.

[0057] It is understood that the first ohmic finger strip 31, the second ohmic finger strip 32, and the third ohmic finger strip 33 are formed from the same ohmic metal layer in the same ohmic metal deposition and etching process. The PGaN anode layer 17 and the P-GaN gate layer 14 are simultaneously deposited using PGaN material. The PGaN material used is typically magnesium-doped. The gate metal layer 151 and the gate metal-anode layer 16 are simultaneously deposited and etched using the same metal material. The metal material can be TiN, a Ti-related combination, a Ni / Au combination, or other similar metal combinations.

[0058] In this embodiment, the GaN FET 20 and the diode 21 share the same continuous active region, allowing continuous conduction of the two-dimensional electron gas without an electrical isolation structure. The GaN FET 20 formed by the first ohmic finger strip 31, the gate unit 15, and the second ohmic finger strip 32 can be repeatedly arranged in the active region. The diode 21 can be arranged between two adjacent GaN FETs 20 as needed, or it can be arranged at a corresponding location as required.

[0059] In another alternative embodiment, the first ohm bar 31 is the drain, and the second ohm bar 32 is the source and the cathode of the diode 21. In other words, the source of the GaN FET 20 and the cathode of the diode 21 share the second ohm bar 32.

[0060] The manufacturing method in this application includes the following steps: Reference Figure 5AAs shown, a substrate 10 is provided, and an epitaxial layer is formed on the substrate 10 by MOCVD growth, wherein the epitaxial layer includes an epitaxial base layer and a PGaN layer 41. The substrate 10 can be made of Si / SOI / sapphire / SiC / GaN, the buffer layer 11 can be made of AlN / AlGaN, the channel layer 12 can be made of GaN, the barrier layer 13 can be made of AlGaN / AlN, and the PGaN layer 41 can be made of GaN / AlGaN.

[0061] A gate metal material 42, typically TiN, is deposited on the PGaN layer 41.

[0062] Reference Figure 5B As shown, the gate metal material 42 and the PGaN layer 41 after deposition are etched using the barrier layer 13 as the cutoff surface, retaining only the area where the gate cell 15 of the GaN FET20 and the diode anode are located, while the gate metal material 42 and the PGaN layer 41 in the remaining areas are etched away.

[0063] Reference Figure 5C As shown, a passivation layer 43 is deposited, which covers the PGaN layer 41 and gate metal material 42 in the regions where the gate cell 15 and the anode of the diode 21 are located, as well as a barrier layer 13 covering other regions (not covered by the PGaN layer 41 and gate metal material 42). A typical passivation layer 43 may include AlN / SiN / SiO2 / SiON / AlO, etc.

[0064] Reference Figure 5D As shown, SCO etching is performed to create openings in the passivation layer 43 above the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. The openings extend within the patterns of the gate metal material 42 and the PGaN layer 41. Specifically, the cross-sectional width of the opening is smaller than the width of the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. After the passivation layer 43 is etched, etching continues into the interior of the PGaN layer 41, thereby forming the gate metal-anode layer 16 and the PGaN anode layer 17.

[0065] Reference Figure 5E As shown, the OHO etching process removes the passivation layer 43 at the positions of the first ohm finger strip 31 (corresponding to the source of GaN FET 20) and the second ohm finger strip 32 (corresponding to the drain of GaN FET 20 and the cathode of diode 21), completely etches the barrier layer 13, and etches a portion of the channel layer 12.

[0066] Reference Figure 5FAs shown, OHM metal deposition and etching are performed, followed by ILD dielectric deposition. Finally, the overall chip manufacturing is completed using metal interconnect technology.

[0067] Reference Figure 6 and Figure 7 As shown, in another optional embodiment, the bottom of the third ohmic finger strip 33 contacts the PGaN anode layer 17, and the width of the bottom of the third ohmic finger strip 33 is greater than that of the PGaN anode layer 17. That is, the difference between this embodiment and the previous embodiment is that the outer periphery of the bottom of the third ohmic finger strip 33 is not surrounded by the gate metal-anode layer 16. In fabricating the GaN integrated circuit chip in this embodiment, in step SCO, a hole is made in the passivation layer 43 above the anode GM / PGaN of diode 21. The hole range is larger than the gate metal material 42 and the PGaN layer 41 at the anode region of diode 21, that is, the cross-sectional width of the hole is larger than the width of the gate metal material 42 and the PGaN layer 41 at the anode region of diode 21. After SCO etching, all of the gate metal material 42 at the anode region of diode 21 is etched, and part of the PGaN layer 41 at the anode region of diode 21 is etched.

[0068] Reference Figure 8 As shown, in another optional embodiment, there can be two PGaN layers 41, with an insertion layer disposed between the two PGaN layers 41. That is, during the epitaxial layer forming process, one PGaN layer 41 is first grown, then an insertion layer is grown on the PGaN layer 41, and then another PGaN layer 41 is grown on the insertion layer.

[0069] Correspondingly, after etching, there can be two PGaN anode layers 17 and two PGaN gate layers 152. An anode insertion layer 18 (AlGaN material) and a gate insertion layer 19 are respectively disposed between the two PGaN anode layers 17 and between the two PGaN gate layers 152.

[0070] In this embodiment, SCO creates an opening in the passivation layer 43 above the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. The opening extends within the pattern of the gate metal material 42 and the PGaN layer 41. That is, the cross-sectional width of the opening is smaller than the width of the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. After the passivation layer 43 is created, etching is performed with the anode insertion layer 18 as the cutoff surface, thereby forming the gate metal-anode layer 16 and the upper PGaN anode layer 17. The gate metal-anode layer 16 and the upper PGaN anode layer 17 cover the outer periphery of the bottom of the third ohm finger strip 33. The bottom of the third ohm finger strip 33 contacts the upper surface of the anode insertion layer 18.

[0071] In the SCO process, etching self-stop is achieved by detecting the Al signal during the SCO etching process, which can effectively improve the stability of the etching process.

[0072] Reference Figure 9 As shown, in another optional embodiment, SCO makes an opening in the passivation layer 43 above the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. The opening extends outside the pattern of the gate metal material 42 and the PGaN layer 41. That is, the cross-sectional width of the opening is greater than the width of the gate metal material 42 and the PGaN layer 41 in the anode region of diode 21. After the passivation layer 43 is made open, etching is performed with the anode insertion layer 18 as the cutoff surface to completely etch away the gate metal-anode layer 16 and the upper PGaN anode layer 17, leaving only the anode insertion layer 18 and the PGaN anode layer 17 below the anode insertion layer 18.

[0073] In the SCO process, etching self-stop is achieved by detecting the Al signal during the SCO etching process, which can effectively improve the stability of the etching process.

[0074] Reference Figure 10 and Figure 11 As shown, in another optional embodiment, the third ohmic finger 33 directly contacts the upper surface of the barrier layer 13, forming a Schottky contact with the barrier layer 13, and serves as the rectifier junction of the diode 21.

[0075] The manufacturing method in this application includes the following steps: Reference Figure 12A As shown, a substrate 10 is provided, and an epitaxial layer is formed on the substrate 10 by MOCVD growth, wherein the epitaxial layer includes an epitaxial base layer and a PGaN layer 41. The substrate 10 can be made of Si / SOI / sapphire / SiC / GaN, the buffer layer 11 can be made of AlN / AlGaN, the channel layer 12 can be made of GaN, the barrier layer 13 can be made of AlGaN / AlN, and the PGaN layer 41 can be made of GaN / AlGaN.

[0076] A gate metal material 42, typically TiN, is deposited on the PGaN layer 41.

[0077] Reference Figure 12B As shown, the gate metal material 42 and the PGaN layer 41 after deposition are etched using the barrier layer 13 as the cutoff surface, leaving only the gate unit 15 of the GaN FET 20, while the gate metal material 42 and the PGaN layer 41 in the remaining areas are etched away.

[0078] Reference Figure 12C As shown, a passivation layer 43 is deposited, which covers the PGaN layer 41 and the gate metal material 42 in the region where the gate cell 15 is located, as well as the barrier layer 13 covering other regions (not covered by the PGaN layer 41 and the gate metal material 42). A typical passivation layer 43 may include AlN / SiN / SiO2 / SiON / AlO, etc.

[0079] Reference Figure 12D As shown, SCO etching is performed with the upper surface of the barrier layer 13 as the cutoff surface. SCO creates an opening in the passivation layer 43 above the barrier layer 13 in the anode region of the diode 21.

[0080] Reference Figure 12E As shown, the OHO etching process removes the passivation layer 43 at the positions of the first ohm finger strip 31 (corresponding to the source of GaN FET 20) and the second ohm finger strip 32 (corresponding to the drain of GaN FET 20 and the cathode of diode 21), completely etches the barrier layer 13, and etches a portion of the channel layer 12.

[0081] Reference Figure 12F As shown, OHM metal deposition and etching form the first ohmic finger strip 31, the second ohmic finger strip 32, and the third ohmic finger strip 33, followed by ILD dielectric deposition. Finally, the overall chip manufacturing is completed through metal interconnect technology.

[0082] In the above embodiment, the GaN integrated circuit chip achieves the following through a diode 21: Figure 14A The first application circuit is shown. In this application circuit, the drain and the cathode of diode 21 share the second ohm bar 32. Therefore, the cathode of diode 21 is electrically connected to the drain, and the anode of diode 21 can be electrically connected to the source using a metal interconnect process.

[0083] The GaN integrated circuit chip can also implement a second application circuit as shown in 14B using two diodes 21. In this application circuit, the two diodes 21 are located on either side of one of the GaN FETs 20. The source / drain of the GaN FET 20 and the cathode of one of the diodes 21 share an ohm bar, and the source / drain of the GaN FET 20 and the cathode of the other diode 21 share an ohm bar. The anodes of the two diodes 21 are electrically connected to the substrate 10 via a metal interconnect process.

[0084] Reference Figure 13 As shown in the embodiments, this application also discloses a GaN integrated circuit chip, including: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer 12 and a barrier layer 13; A first ohm finger strip 31, a second ohm finger strip 32, a fourth ohm finger strip 34, and a third ohm finger strip 33 are formed on the epitaxial base layer and arranged sequentially along the width direction; The first ohm finger strip 31, the second ohm finger strip 32 and the fourth ohm finger strip 34 all pass through the barrier layer 13 and contact the channel layer 12; A gate unit 15 is disposed between the first ohm finger strip 31 and the second ohm finger strip 32 along the width direction, thereby forming a GaN FET 20 with the first ohm finger strip 31, the gate unit 15 and the second ohm finger strip 32. The third ohmic finger strip 33 is formed above the barrier layer 13, thereby forming a diode 21 with the fourth ohmic finger strip 34.

[0085] In this embodiment, the structure of the anode of diode 21 can refer to the above embodiment. Unlike the above embodiment, in this embodiment, the cathode of diode 21 does not share the same ohm fingers as the source and / or drain of GaN FET 20. Instead, the first ohm fingers 31 (source), the second ohm fingers 32 (drain), the third ohm fingers 33 (anode of diode 21), and the fourth ohm fingers 34 (cathode of diode 21) are arranged side-by-side along the width direction of the chip (the width direction of the drawing) and all extend along the length direction of the chip (the length direction of the drawing). The first ohm fingers 31, the second ohm fingers 32, the third ohm fingers 33, and the fourth ohm fingers 34 are formed from the same ohm metal layer in the same ohm metal deposition and etching process. The active region where diode 21 is located is isolated from the active region where GaN FET 20 is located. In this embodiment, diode 21 and GaN FET 20 can be interconnected through an interconnect metal layer to achieve different application circuits.

[0086] In the above embodiment, the GaN integrated circuit chip achieves the following through a diode 21: Figure 14A The first application circuit is shown. In this application circuit, the cathode of diode 21 is electrically connected to the drain via a metal interconnect process, and the anode of diode 21 is electrically connected to the source via a metal interconnect process.

[0087] GaN integrated circuit chips can also achieve, for example, through two diodes 21. Figure 14B The second application circuit is shown. In this application circuit, the source / drain of GaN FET20 and the cathode of one of the diodes 21 are electrically connected via a metal interconnect process, the source / drain of GaN FET20 and the cathode of the other diode 21 are electrically connected via a metal interconnect process, and the anodes of the two diodes 21 are electrically connected to the substrate 10 via a metal interconnect process.

[0088] GaN integrated circuit chips can also achieve, for example, through a diode 21. Figure 14C The third application circuit is shown. In this application circuit, the cathode of diode 21 is electrically connected to the gate of GaN FET 20 through a metal interconnect process, and the anode of diode 21 is electrically connected to substrate 10 through a metal interconnect process.

[0089] This invention proposes a GaN IC layout and integration process embodiment, in which diode 21 is inserted into the main die region to disperse the diode 21 current, optimize chip heat distribution, and improve chip area utilization. Simultaneously, based on a gallium nitride emode platform-compatible process, a diode 21 with a lower turn-on voltage is integrated and fabricated, effectively reducing the diode 21's forward voltage drop and improving system efficiency.

[0090] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. A GaN integrated circuit chip, characterized by, include: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer and a barrier layer; A first ohm finger strip, a second ohm finger strip, and a third ohm finger strip are formed on the outer epitaxial base layer. The first ohm finger strip, the second ohm finger strip, and the third ohm finger strip are arranged side by side along the width direction. The second ohm finger strip is located between the first ohm finger strip and the third ohm finger strip along the width direction. Both the first ohm finger and the second ohm finger pass through the barrier layer and contact the channel layer; A gate unit is disposed between the first ohm finger strip and the second ohm finger strip along the width direction, thereby forming a GaN FET by the first ohm finger strip, the gate unit and the second ohm finger strip; The third ohmic finger is formed above the barrier layer, thereby forming a diode with the second ohmic finger.

2. The GaN integrated circuit chip of claim 1, wherein, The GaN FET and the diode share the same continuous active region, with continuous conduction of two-dimensional electron gas and no electrical isolation structure.

3. A GaN integrated circuit chip, characterized by, include: An epitaxial base layer, wherein the epitaxial base layer includes a channel layer and a barrier layer; A first ohm finger strip, a second ohm finger strip, a fourth ohm finger strip, and a third ohm finger strip are formed on the epitaxial base layer and arranged sequentially along the width direction; The first ohm finger, the second ohm finger, and the fourth ohm finger all pass through the barrier layer and contact the channel layer; A gate unit is disposed between the first ohm finger strip and the second ohm finger strip along the width direction, thereby forming a GaN FET by the first ohm finger strip, the gate unit and the second ohm finger strip; The third ohmic finger is formed above the barrier layer, thereby forming a diode with the fourth ohmic finger.

4. The GaN integrated circuit chip of claim 3, wherein, The active region of the diode is isolated from the active region of the GaN FET.

5. The GaN integrated circuit chip according to claim 1 or 3, wherein The barrier layer located below the third ohmic finger remains intact and without grooves.

6. The GaN integrated circuit chip according to claim 1 or 3, wherein A PGaN anode layer is disposed below the third ohmic finger strip. The third ohmic finger strip and the PGaN anode layer form an ohmic contact. The PGaN anode layer and the two-dimensional electron gas below form a heterojunction, which serves as the rectifier junction of the diode.

7. The GaN integrated circuit chip of claim 6, wherein, The third ohmic finger passes through the gate metal-anode layer and contacts the PGaN anode layer; or, the bottom of the third ohmic finger contacts the PGaN anode layer, and the width of the bottom of the third ohmic finger is greater than that of the PGaN anode layer. Alternatively, there may be two PGaN anode layers, with an anode insertion layer between the two PGaN anode layers, and the lower surface of the third ohmic finger bar ending at the upper surface of the anode insertion layer; Alternatively, an anode insertion layer may be provided above the PGaN anode layer, and the lower surface of the third ohmic finger bar may terminate at the upper surface of the anode insertion layer.

8. The GaN integrated circuit chip according to claim 1 or 3, characterized by, The third ohmic finger directly contacts the upper surface of the barrier layer, forming a Schottky contact with the barrier layer, and serves as the rectifier junction of the diode.

9. The GaN integrated circuit chip according to claim 1 or 3, wherein, The first ohmic finger strip, the second ohmic finger strip, and the third ohmic finger strip are formed from the same ohmic metal layer in the same ohmic metal deposition and etching process.

10. A method of fabricating a GaN integrated circuit chip, comprising: Includes the following steps: Provide substrate; An epitaxial layer is formed on the substrate, and a gate cell is formed after the epitaxial layer is formed; An opening is made in the anode region of the diode; Make an opening in the ohmic region; Ohmic metal is deposited at the openings in the ohmic region and at the openings in the anode region of the diode; After etching the ohmic metal, the source and drain of the GaN FET, as well as the anode and cathode of the diode, are formed.

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