A high surge density TVS device and method of manufacture

Abstract

The application provides a high surge density TVS device, which comprises a heavily doped semiconductor substrate of a first conductive type and a drift region of the first conductive type; at least one closed isolation deep trench structure arranged at the periphery of the drift region of the first conductive type; a plurality of active deep trench structures embedded and arranged in the main active region in a dense array; an in-situ doped polysilicon structure arranged in the active deep trench structure; a non-planar three-dimensional longitudinal PN junction structure formed around the sidewall and the bottom of the active deep trench structure and extending longitudinally along the active deep trench structure; a semiconductor silicon ridge region formed between two adjacent active deep trench structures; the semiconductor silicon ridge region forms a laterally overlapping depletion region in a reverse blocking state; and the semiconductor silicon ridge region between the plurality of active deep trench structures forms a longitudinal main conduction area of a main surge current in a longitudinal direction under a transient overvoltage condition. The application can improve the effective conduction volume and the effective heat diffusion volume of the device, thereby improving the surge carrying capacity per unit area.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor transient overvoltage protection devices, and in particular to a high surge density TVS device and its manufacturing method. Background Technology

[0002] Transient voltage suppressors (TVS) are widely used in power interfaces, communication interfaces, consumer electronics, automotive electronics and industrial systems to absorb electrostatic discharge (ESD) and surge overvoltage energy.

[0003] With the development of mobile terminals, high-density integrated modules, and CSP / WLCSP packaging technologies, the physical footprint of protection devices continues to shrink, while the requirements for surge current carrying capacity at the system level are constantly increasing. Therefore, how to improve the surge carrying capacity per unit area within a limited chip area has become a crucial technical problem that urgently needs to be solved in the current TVS device field.

[0004] Traditional planar TVS devices primarily rely on surface PN junction regions for avalanche conduction. In this type of device structure, surge currents caused by transient overvoltages mainly propagate in the surface region of the device, resulting in a limited effective conduction volume. As device dimensions are further reduced to accommodate miniaturized packaging, local current density and transient thermal power density increase significantly, easily leading to localized hot spots, thermal runaway, and device failure.

[0005] Some existing technologies employ deep trench structures or polysilicon-filled structures to achieve device isolation, multi-path integration, or local PN junction formation. However, such structures typically do not construct high surge density conduction paths by expanding the overall effective conduction volume of the device, increasing the effective thermal diffusion volume, or guiding the surge current to spread three-dimensionally within the device.

[0006] Furthermore, in the field of semiconductor protection devices, deep trench structures are generally considered more suitable for peripheral isolation or local junction formation, rather than for high-density arrangement within the main active region that bears the main surge current. This is because deep trench structures are prone to forming local electric field peaks in the curvature region at the bottom of the trench under high reverse bias conditions; and under high current surge conditions, dense trench regions may also introduce reliability issues such as localized heat concentration, insulation layer breakdown, or limited thermal conductivity of polysilicon.

[0007] Chinese invention patent CN102592995B discloses a method for manufacturing a Zener diode, which uses deep trench filling of in-situ doped polysilicon and annealing to form a diffusion region. However, the main purpose of this scheme is to use the deep trench structure to achieve device formation and impurity diffusion. The deep trenches are mainly used as longitudinal diffusion channels, and multiple active deep trenches are not densely arranged inside the main active region that bears the main surge current. The diffusion region formed is mainly used to form a local junction structure, and the semiconductor silicon ridge region between multiple deep trenches is not used as the bulk longitudinal main conduction region for the main surge current. Summary of the Invention

[0008] To address at least one technical problem in the prior art, embodiments of the present invention provide a high surge density TVS device and its manufacturing method, which can increase the effective conduction volume and effective heat dissipation volume of the device, thereby improving the surge carrying capacity per unit area and overcoming the problems of insufficient surge capacity per unit area, significant local heat concentration, and difficulty in adapting to small-size CSP / WLCSP packages in traditional planar TVS devices. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows: In a first aspect, embodiments of the present invention provide a high surge density TVS device, comprising: Heavy doped semiconductor substrate of the first conductivity type; A first conductivity type drift region is disposed on a first conductivity type semiconductor substrate, and the two together form a first conductivity type semiconductor region; At least one closed isolation deep trench structure is disposed outside the drift region of the first conductivity type to define the boundary of the main active region of the device; Multiple active deep trench structures are densely embedded within the main active region; An in-situ doped polysilicon structure is disposed within and completely or partially fills the active deep trench structure; the in-situ doped polysilicon structure has a second conductivity type opposite to the first conductivity type; the in-situ doped polysilicon structure serves as a longitudinal doping source, causing a non-planar three-dimensional longitudinal PN junction structure extending longitudinally along the active deep trench structure to be formed around the sidewalls and bottom of the active deep trench structure in the semiconductor region of the first conductivity type. An interlayer dielectric layer disposed on the front side of the drift region of the first conductivity type; A first electrode is disposed on the interlayer dielectric layer, and the first electrode is connected to the in-situ doped polysilicon structure in the plurality of active deep trench structures through a contact hole disposed in the interlayer dielectric layer. A second electrode disposed on the back side of a semiconductor substrate of the first conductivity type; in, A semiconductor silicon ridge region is formed between two adjacent active deep trench structures; the lateral spacing of the semiconductor silicon ridge region is matched with the lateral junction depth of the non-planar three-dimensional longitudinal PN junction structure, so that the semiconductor silicon ridge region forms a laterally overlapping depletion region in the reverse blocking state; so that the semiconductor silicon ridge region between two adjacent active deep trench structures forms a continuous high electric field distribution region extending longitudinally. Under transient overvoltage conditions, the non-planar three-dimensional longitudinal PN junction structure forms multiple longitudinally distributed avalanche conduction channels within the semiconductor region of the first conductivity type. The semiconductor silicon ridge regions between the multiple active deep trench structures constitute the longitudinal dominant conduction region of the main surge current in the longitudinal direction, so that the main surge current expands laterally and flows longitudinally within the semiconductor region between adjacent active deep trench structures, thereby forming a three-dimensional current expansion path within the semiconductor region between adjacent active deep trench structures.

[0009] As a result, the surge current is no longer limited to propagating near the PN junction on the surface of the device, but forms a three-dimensional conductive network with longitudinal penetration and lateral coupling in the bulk silicon region inside the main active region, thereby realizing longitudinal volume dissipation and lateral current sharing diffusion, reducing the unit volume current density and local transient thermal power density, and improving the surge carrying capacity per unit area of ​​the device.

[0010] Furthermore, the longitudinal physical depth of the active deep trench structure is greater than the longitudinal thickness of the first conductivity type drift region, and the bottom of the active deep trench structure penetrates downward through the first conductivity type drift region and enters the top of the first conductivity type semiconductor substrate; Accordingly, the bottom of the closed-loop isolation deep trench structure penetrates downward through the first conductivity type drift region and enters the top of the first conductivity type semiconductor substrate.

[0011] Furthermore, the lateral spacing of the semiconductor silicon ridge regions formed between two adjacent active deep trench structures is 0.5 μm to 5 μm.

[0012] Furthermore, the lateral spacing of the semiconductor silicon ridge regions formed between two adjacent active deep trench structures is 1.0 μm to 3 μm.

[0013] Furthermore, the opening width of the active deep trench structure is 0.5μm to 2μm, and the longitudinal physical depth is 5μm to 50μm; the depth-to-width ratio of the longitudinal physical depth of the active deep trench structure to the opening width is 20:1 to 60:1.

[0014] Furthermore, the opening width of the active deep trench structure is 0.8μm to 1.2μm, and the longitudinal physical depth is 10μm to 30μm; the depth-to-width ratio of the longitudinal physical depth of the active deep trench structure to the opening width is 30:1 to 50:1.

[0015] Furthermore, the in-situ doped polycrystalline silicon structure can be a fully filled structure, a partially filled structure, a bottom-filled structure, or a sidewall-covered structure.

[0016] Furthermore, the in-situ doped polysilicon structure is a gradient doped polysilicon structure, that is, as the depth of the active deep trench structure increases, the doping concentration of the in-situ doped polysilicon structure decreases; thereby making the non-planar three-dimensional longitudinal PN junction structure have an impurity concentration gradient that decreases along the longitudinal depth direction.

[0017] Furthermore, the bottom contour of the active deep trench structure adopts a rounded corner transition structure.

[0018] Furthermore, the plurality of active deep trench structures are arranged in one or more combinations of strip array, two-dimensional matrix array, grid array, honeycomb array or concentric ring array on the device plane.

[0019] Secondly, embodiments of the present invention provide a method for manufacturing a high surge density TVS device, used to manufacture the high surge density TVS device as described above, comprising the following steps: Step S1: Provide a heavily doped semiconductor substrate of the first conductivity type; Step S2: A first conductivity type drift region is formed on the front side of the first conductivity type semiconductor substrate; Step S3: Etch the first conductivity type drift region and part of the first conductivity type semiconductor substrate to form at least one closed isolation deep trench around the boundary of the main active region. Step S4: Deposit insulating medium within the closed-loop isolation deep trench to form a closed-loop isolation deep trench structure; and planarize using CMP. Step S5: Inside the main active region surrounded by the closed isolation deep trench structure, the first conductivity type drift region and part of the first conductivity type semiconductor substrate are etched to form multiple active deep trenches. Step S6: Deposit an in-situ doped polysilicon structure with a second conductivity type inside the active deep trench, and completely or partially fill the active deep trench to form multiple active deep trench structures. Step S7: Through annealing diffusion or doping advance process, the second conductivity type impurities in the in-situ doped polycrystalline silicon structure diffuse to the surrounding first conductivity type semiconductor region, thereby forming a non-planar three-dimensional longitudinal PN junction structure extending longitudinally along the active deep trench structure around the sidewalls and bottom of the active deep trench structure. Step S8: Etch back or perform CMP on the in-situ doped polysilicon structure to remove excess in-situ doped polysilicon structure outside the opening of the active deep trench structure. Step S9: Deposit an interlayer dielectric layer on the front side of the drift region of the first conductivity type, and etch to form contact holes; Step S10: Deposit and pattern a metal layer on the interlayer dielectric layer to form a first electrode connected to the in-situ doped polysilicon structure. Step S11: Thin the back side of the first conductivity type semiconductor substrate and deposit metal to form a second electrode.

[0020] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: 1) This invention constructs a non-planar three-dimensional longitudinal PN junction structure extending longitudinally along the active deep trench structure by densely embedding multiple active deep trench structures inside the main active region, combined with the in-situ doped polysilicon structure doping advancement process filled inside them; thereby expanding the surge conduction area of ​​the device from the traditional PN junction area on the device surface to the longitudinal main conduction area inside the device body, thus forming a three-dimensional current expansion path and improving the surge carrying capacity per unit area of ​​the device.

[0021] Under the same 0.12mm² chip effective working area, the maximum peak surge current (IPP, 8 / 20μs) of traditional planar devices is about 10A, corresponding to a surge density of about 80A / mm² per unit area; while the IPP of the device structure in this invention can reach about 30A, corresponding to a surge density of about 250A / mm² per unit area, indicating that the device proposed in this invention has a significant improvement in surge carrying capacity per unit area.

[0022] 2) The present invention limits the lateral spacing of the semiconductor silicon ridge regions between adjacent active deep trench structures to a micrometer range that is compatible with the lateral junction depth of the non-planar three-dimensional longitudinal PN junction structure, preferably 1.0 μm to 3 μm; so that the depletion layers inside the semiconductor silicon ridge region of the main active region form lateral overlaps in the reverse blocking state; by forming a continuous high electric field region through the overlap of depletion layers, the concentration of the local electric field in the curvature region at the bottom of the trench can be reduced, thereby improving the problem of local electric field peaks; Meanwhile, in the transient conduction state, the main surge current can extend laterally and flow longitudinally within the semiconductor region between adjacent active deep trench structures, thereby increasing the effective conduction volume and effective heat dissipation volume of the device, thus reducing the local current density and the risk of heat concentration, and improving the high current surge stability of the device.

[0023] 3) Because the effective conduction volume and transient heat dissipation area of ​​the device are no longer limited to the chip surface, but extend longitudinally throughout the entire drift region, the physical depth of the longitudinally dominant conduction region within the device can reach 10μm to 30μm; thus, the effective heat diffusion volume of the device is increased. This allows the device to maintain good stability of dynamic impedance when subjected to multiple, continuous transient surge impacts; improving the reliability and thermal stability of the device under repeated surge impacts.

[0024] 4) The device proposed in this invention can achieve miniaturization of chip area while maintaining high surge protection capability; it is suitable for high-density integration scenarios such as wafer-level chip-scale packaging (WLCSP), chip-scale packaging (CSP), fan-out packaging, and system-in-package (SiP), and has good process compatibility and application adaptability.

[0025] 5) Multiple active deep trench structures offer high flexibility in arrangement on the device plane. They can be designed as one or more combinations of strip arrays, two-dimensional matrix arrays, grid arrays, honeycomb arrays, or concentric ring arrays, depending on the device's shape and current distribution requirements. The main surge current can be paralleled and shunt among multiple non-planar three-dimensional longitudinal PN junction structures, forming a more balanced parallel current-sharing network in the device plane, thereby reducing the risk of local current concentration and current fission. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the TVS device structure in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram illustrating the working principle of the TVS device in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0031] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] This invention is illustrated using an example where the first conductivity type is P-type and the second conductivity type is N-type. Those skilled in the art should understand that, without departing from the essential technical concept of this invention, a complementary structure with the first conductivity type being N-type and the second conductivity type being P-type can also be used.

[0033] (a) such as Figure 1 As shown, an embodiment of the present invention proposes a high surge density TVS device, comprising: Heavy doped first conductivity type semiconductor substrate 600; A first conductivity type drift region 500 is disposed on a first conductivity type semiconductor substrate 600, and the two together form a first conductivity type semiconductor region; At least one closed isolation deep trench structure 800 is disposed around the first conductivity type drift region 500 to define the boundary of the main active region of the device. Multiple active deep trench structures 200 are densely embedded within the main active region; An in-situ doped polysilicon structure 202 is disposed within the active deep trench structure 200 and completely or partially fills the active deep trench structure 200; the in-situ doped polysilicon structure 202 has a second conductivity type opposite to the first conductivity type; the in-situ doped polysilicon structure 202 serves as a longitudinal doping source, causing a non-planar three-dimensional longitudinal PN junction structure 300 extending longitudinally along the active deep trench structure to be formed around the sidewalls and bottom of the active deep trench structure 200 in the semiconductor region of the first conductivity type. Interlayer dielectric layer 900 disposed on the front side of drift region 500 of first conductivity type; A first electrode 100 is disposed on the interlayer dielectric layer 900, and the first electrode 100 is connected to the in-situ doped polysilicon structure 202 in the plurality of active deep trench structures 200 through a contact hole disposed in the interlayer dielectric layer 900. A second electrode 700 is disposed on the back side of a first conductivity type semiconductor substrate 600; in, A semiconductor silicon ridge region 400 is formed between two adjacent active deep trench structures 200; the lateral spacing of the semiconductor silicon ridge region 400 matches the lateral junction depth of the non-planar three-dimensional longitudinal PN junction structure 300, so that the semiconductor silicon ridge region 400 forms a laterally overlapping depletion region in the reverse blocking state; so that the semiconductor silicon ridge region 400 between two adjacent active deep trench structures 200 forms a continuous high electric field distribution region extending longitudinally. Under transient overvoltage conditions, the non-planar three-dimensional longitudinal PN junction structure 300 forms multiple longitudinally distributed avalanche conduction channels within the semiconductor region of the first conductivity type. The semiconductor silicon ridge region 400 between the multiple active deep trench structures 200 constitutes the longitudinal dominant conduction region of the main surge current in the longitudinal direction, so that the main surge current expands laterally and flows longitudinally within the semiconductor region between adjacent active deep trench structures 200, thereby forming a three-dimensional current expansion path within the semiconductor region between adjacent active deep trench structures 200.

[0034] (II) The following is a detailed introduction to each component of the device.

[0035] 1) Overall Structure The in-situ doped polysilicon structure 202 filled within the active deep trench structure 200 is diffused to the surrounding P-type semiconductor region by annealing diffusion or doping advance process, thereby forming a non-planar three-dimensional longitudinal PN junction structure 300 extending longitudinally along the active deep trench structure around the sidewalls and bottom of the active deep trench structure 200.

[0036] A semiconductor silicon ridge region 400 is formed between two adjacent active deep trench structures 200, and the lateral spacing of the ridge region matches the lateral junction depth of the non-planar three-dimensional longitudinal PN junction structure 300; in the reverse blocking state of the device, Figure 1 or Figure 2 In the process, depletion regions are formed on the left and right sides of the semiconductor silicon ridge region 400 between two adjacent active deep trench structures 200. The two depletion regions can overlap laterally, thereby forming a continuous high electric field region extending longitudinally between the semiconductor silicon ridge region 400 between two adjacent active deep trench structures 200.

[0037] When the device is under transient overvoltage conditions, the non-planar three-dimensional longitudinal PN junction structure 300 forms multiple longitudinally distributed avalanche conduction channels within the semiconductor region of the first conductivity type. The semiconductor silicon ridge regions 400 between the multiple active deep trench structures 200 constitute the longitudinally dominant conduction region of the main surge current in the longitudinal direction, such as... Figure 2As shown, the main surge current extends laterally and flows longitudinally within the semiconductor region between adjacent active deep trench structures 200, forming a three-dimensional current extension path in the main active region.

[0038] Therefore, when the device is reverse-biased, the main surge current is no longer confined to the vicinity of the PN junction on the device surface. Instead, it is shunt in parallel among the non-planar three-dimensional longitudinal PN junction structures 300 formed around multiple active deep trench structures 200, and extends laterally and flows longitudinally within the semiconductor region between adjacent active deep trench structures 200. This increases the effective conduction volume and effective heat dissipation volume of the device, thereby reducing the local current density and the risk of heat concentration; and improves the surge carrying capacity per unit area of ​​the device as a whole.

[0039] 2) Heavily doped first conductivity type semiconductor substrate 600 The resistivity of the first conductivity type semiconductor substrate 600 is preferably from 0.005 Ω·cm to 0.020 Ω·cm to reduce the substrate parasitic resistance.

[0040] 3) First conductivity type drift region 500 The first conductivity type drift region 500 is formed by growing a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate 600; the thickness and doping concentration of the first conductivity type drift region 500 can be set according to the target breakdown voltage and dynamic impedance.

[0041] 4) Active deep trench structure 200, closed isolation deep trench structure 800, and semiconductor silicon ridge region 400 Preferably, the longitudinal physical depth of the active deep trench structure 200 is greater than the longitudinal thickness of the first conductivity type drift region 500, and the bottom of the active deep trench structure 200 penetrates downward through the first conductivity type drift region 500 and enters the top of the first conductivity type semiconductor substrate 600. Accordingly, the bottom of the closed isolation deep trench structure 800 penetrates downward through the first conductivity type drift region 500 and enters the top of the first conductivity type semiconductor substrate 600.

[0042] Preferably, the lateral spacing of the semiconductor silicon ridge regions 400 formed between two adjacent active deep trench structures 200 is 0.5 μm to 5 μm, more preferably 1.0 μm to 3 μm, so that the semiconductor silicon ridge regions 400 form laterally overlapping depletion regions in the reverse blocking state.

[0043] The opening width of the active deep trench structure 200 is 0.5μm to 2μm, preferably 0.8μm to 1.2μm; the longitudinal physical depth of the active deep trench structure 200 is 5μm to 50μm, preferably 10μm to 30μm; the depth-to-width ratio of the longitudinal physical depth of the active deep trench structure 200 to the opening width is 20:1 to 60:1, preferably 30:1 to 50:1.

[0044] Preferably, the in-situ doped polycrystalline silicon structure 202 can be a fully filled structure, or a partially filled structure, a bottom filled structure, or a sidewall covered structure, to adjust the longitudinal electric field distribution, parasitic capacitance, and conduction path; the in-situ doped polycrystalline silicon structure 202 is usually an in-situ heavily doped second conductivity type polycrystalline silicon structure.

[0045] Preferably, the in-situ doped polysilicon structure 202 is a gradient doped polysilicon structure, that is, the doping concentration of the in-situ doped polysilicon structure 202 decreases as the depth of the active deep trench structure 200 increases; thereby making the non-planar three-dimensional longitudinal PN junction structure 300 have an impurity concentration gradient that decreases along the longitudinal depth direction; so as to form an electric field distribution that varies along the longitudinal depth direction, further improving the surge resistance of the device.

[0046] Preferably, the bottom contour of the active deep trench structure 200 can adopt a rounded corner transition structure to reduce the local electric field concentration at the bottom of the trench.

[0047] Preferably, the plurality of active deep trench structures 200 are arranged in one or more combinations of strip array, two-dimensional matrix array, grid array, honeycomb array or concentric ring array on the device plane; this can form a more balanced parallel current sharing network in the device plane direction, thereby reducing the risk of local current concentration and current filamentation.

[0048] (III) This invention also proposes a method for manufacturing a high surge density TVS device, comprising the following steps: Step S1, providing a heavily doped first conductivity type semiconductor substrate 600; In this embodiment, the first conductivity type semiconductor substrate 600 is a P+ type single crystal silicon substrate; its resistivity is preferably from 0.005 Ω·cm to 0.020 Ω·cm; Step S2: A first conductivity type drift region 500 is formed on the front side of the first conductivity type semiconductor substrate 600; In this step, an epitaxial growth process can be used to grow a first conductivity type epitaxial layer on the front side of the first conductivity type semiconductor substrate 600 to form a first conductivity type drift region 500. Step S3: Etch the first conductivity type drift region 500 and a portion of the first conductivity type semiconductor substrate 600 to form at least one closed isolation deep trench surrounding the boundary of the main active region. Specifically, a hard mask is formed in the first conductivity type drift region 500, and after photolithography, the first conductivity type drift region 500 and part of the first conductivity type semiconductor substrate 600 are etched using deep reactive ion etching (RIE) process. Step S4: Deposit insulating medium within the closed-loop isolation deep trench to form a closed-loop isolation deep trench structure 800; and planarize it using CMP. The insulating medium deposited in the closed-loop isolation deep trench can be silicon dioxide or other insulating media, and it is planarized by chemical mechanical polishing (CMP). Step S5: Inside the main active region surrounded by the closed isolation deep trench structure 800, the first conductivity type drift region 500 and part of the first conductivity type semiconductor substrate 600 are etched to form a plurality of active deep trenches. Multiple active deep trenches are arranged in one or more combinations of strip array, two-dimensional matrix array, grid array, honeycomb array or concentric ring array on the device plane; Step S6: Deposit an in-situ doped polysilicon structure 202 with a second conductivity type inside the active deep trench, and completely or partially fill the active deep trench to form a plurality of active deep trench structures 200. In this step, a low-pressure chemical vapor deposition process can be used to deposit an in-situ doped polycrystalline silicon structure 202 with a second conductivity type inside the active deep trench; and to completely or partially fill the active deep trench. Optionally, in this step, the in-situ doped polysilicon structure 202 is made to have different doping concentrations at different depths in the active deep trench structure 200 by controlling the deposition parameters; that is, the deeper the active deep trench structure 200, the lower the doping concentration of the in-situ doped polysilicon structure 202. Step S7: Through annealing diffusion or doping advance process, the second conductivity type impurities in the in-situ doped polysilicon structure 202 diffuse to the surrounding first conductivity type semiconductor region, thereby forming a non-planar three-dimensional longitudinal PN junction structure 300 extending longitudinally along the active deep trench structure around the sidewalls and bottom of the active deep trench structure 200. Step S8: The in-situ doped polysilicon structure 202 is etched back or CMP is performed to remove excess in-situ doped polysilicon structure outside the opening of the active deep trench structure. Step S9: Deposit an interlayer dielectric layer 900 on the front side of the first conductivity type drift region 500, and etch to form contact holes; Step S10: Deposit and pattern a metal layer on the interlayer dielectric layer 900 to form a first electrode 100 connected to the in-situ doped polysilicon structure 202. Step S11: Thin the back side of the first conductivity type semiconductor substrate 600 and deposit metal to form the second electrode 700.

[0049] Through the above manufacturing method, a three-dimensional in-situ conductive network is formed inside the main active region, consisting of multiple active deep trench structures 200, a non-planar three-dimensional longitudinal PN junction structure 300, and semiconductor silicon ridge regions 400 between adjacent active deep trench structures 200.

[0050] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high surge density TVS device, characterized in that, include: Heavily doped first conductivity type semiconductor substrate (600); A first conductivity type drift region (500) is disposed on a first conductivity type semiconductor substrate (600), and the two together form a first conductivity type semiconductor region; At least one closed isolation deep trench structure (800) is disposed around the first conductivity type drift region (500) to define the boundary of the main active region of the device; Multiple active deep trench structures (200) are densely embedded within the main active region; An in-situ doped polysilicon structure (202) is disposed within the active deep trench structure (200) and completely or partially fills the active deep trench structure (200); the in-situ doped polysilicon structure (202) has a second conductivity type opposite to the first conductivity type; the in-situ doped polysilicon structure (202) serves as a longitudinal doping source, such that a non-planar three-dimensional longitudinal PN junction structure (300) extending longitudinally along the active deep trench structure is formed around the sidewalls and bottom of the active deep trench structure (200) in the semiconductor region of the first conductivity type. Interlayer dielectric layer (900) disposed on the front side of the drift region (500) of the first conductivity type; A first electrode (100) is disposed on the interlayer dielectric layer (900), and the first electrode (100) is connected to the in-situ doped polysilicon structure (202) in the plurality of active deep trench structures (200) through a contact hole disposed in the interlayer dielectric layer (900). A second electrode (700) is disposed on the back side of a semiconductor substrate (600) of the first conductivity type; in, A semiconductor silicon ridge region (400) is formed between two adjacent active deep trench structures (200); the lateral spacing of the semiconductor silicon ridge region (400) matches the lateral junction depth of the non-planar three-dimensional longitudinal PN junction structure (300), so that the semiconductor silicon ridge region (400) forms a laterally overlapping depletion region in the reverse blocking state; so that the semiconductor silicon ridge region (400) between two adjacent active deep trench structures (200) forms a continuous high electric field distribution region extending longitudinally; Under transient overvoltage conditions, the non-planar three-dimensional longitudinal PN junction structure (300) forms multiple longitudinally distributed avalanche conduction channels in the semiconductor region of the first conductivity type. The semiconductor silicon ridge region (400) between the multiple active deep trench structures (200) constitutes the longitudinal dominant conduction region of the main surge current in the longitudinal direction, so that the main surge current expands laterally and flows longitudinally in the semiconductor region between adjacent active deep trench structures (200) to form a three-dimensional current expansion path in the semiconductor region between adjacent active deep trench structures (200).

2. The high surge density TVS device as described in claim 1, characterized in that, The longitudinal physical depth of the active deep trench structure (200) is greater than the longitudinal thickness of the first conductivity type drift region (500), and the bottom of the active deep trench structure (200) penetrates downward through the first conductivity type drift region (500) and enters the top of the first conductivity type semiconductor substrate (600). Accordingly, the bottom of the closed isolation deep trench structure (800) penetrates downward through the first conductivity type drift region (500) and enters the top of the first conductivity type semiconductor substrate (600).

3. The high surge density TVS device as described in claim 1, characterized in that, The lateral spacing of the semiconductor silicon ridge region (400) formed between two adjacent active deep trench structures (200) is 0.5 μm to 5 μm.

4. The high surge density TVS device as described in claim 3, characterized in that, The lateral spacing of the semiconductor silicon ridge region (400) formed between two adjacent active deep trench structures (200) is 1.0 μm to 3 μm.

5. The high surge density TVS device as described in claim 1, characterized in that, The active deep trench structure (200) has an opening width of 0.5 μm to 2 μm and a longitudinal physical depth of 5 μm to 50 μm; the ratio of the longitudinal physical depth of the active deep trench structure (200) to the opening width is 20:1 to 60:

1.

6. The high surge density TVS device as described in claim 5, characterized in that, The active deep trench structure (200) has an opening width of 0.8 μm to 1.2 μm and a longitudinal physical depth of 10 μm to 30 μm; the ratio of the longitudinal physical depth of the active deep trench structure (200) to the opening width is 30:1 to 50:

1.

7. The high surge density TVS device as described in claim 1, characterized in that, The in-situ doped polycrystalline silicon structure (202) can be a fully filled structure, a partially filled structure, a bottom-filled structure, or a sidewall-covered structure.

8. The high surge density TVS device as described in claim 1, characterized in that, The in-situ doped polysilicon structure (202) is a gradient doped polysilicon structure, that is, as the depth of the active deep trench structure (200) increases, the doping concentration of the in-situ doped polysilicon structure (202) decreases; thereby making the non-planar three-dimensional longitudinal PN junction structure (300) have an impurity concentration gradient that decreases along the longitudinal depth direction.

9. The high surge density TVS device as described in claim 1, characterized in that, The bottom contour of the active deep trench structure (200) adopts a rounded corner transition structure.

10. The high surge density TVS device as described in claim 1, characterized in that, The plurality of active deep trench structures (200) are arranged in one or more combinations of strip array, two-dimensional matrix array, grid array, honeycomb array or concentric ring array on the device plane.

11. A method for manufacturing a high surge density TVS device, used to manufacture the high surge density TVS device as described in any one of claims 1 to 10, characterized in that, Includes the following steps: Step S1, providing a heavily doped first conductivity type semiconductor substrate (600); Step S2: A first conductivity type drift region (500) is formed on the front side of the first conductivity type semiconductor substrate (600); Step S3: Etch the first conductivity type drift region (500) and a portion of the first conductivity type semiconductor substrate (600) to form at least one closed isolation deep trench surrounding the boundary of the main active region; Step S4: Deposit insulating medium within the closed-loop isolation deep trench to form a closed-loop isolation deep trench structure (800); and planarize it using CMP. Step S5: Inside the main active region surrounded by the closed isolation deep trench structure (800), the first conductivity type drift region (500) and part of the first conductivity type semiconductor substrate (600) are etched to form a plurality of active deep trenches. Step S6: Deposit an in-situ doped polysilicon structure (202) with a second conductivity type inside the active deep trench and completely or partially fill the active deep trench to form a plurality of active deep trench structures (200). Step S7: Through annealing diffusion or doping advance process, the second conductivity type impurities in the in-situ doped polysilicon structure (202) diffuse to the surrounding first conductivity type semiconductor region, thereby forming a non-planar three-dimensional longitudinal PN junction structure (300) extending longitudinally along the active deep trench structure around the sidewalls and bottom of the active deep trench structure (200). Step S8: The in-situ doped polysilicon structure (202) is etched back or CMP is performed to remove excess in-situ doped polysilicon structure outside the opening of the active deep trench structure. Step S9: Deposit an interlayer dielectric layer (900) on the front side of the first conductivity type drift region (500) and etch to form contact holes; Step S10: Deposit and pattern a metal layer on the interlayer dielectric layer (900) to form a first electrode (100) connected to the in-situ doped polysilicon structure (202); Step S11: Thin the back side of the first conductivity type semiconductor substrate (600) and deposit metal to form a second electrode (700).

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