Deep trench mis integrated high frequency electromagnetic interference coupling bypass tvs device and method of manufacturing the same

Abstract

This invention discloses a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device and its manufacturing method, comprising a semiconductor substrate, a drift region of a first conductivity type, a well region of a second conductivity type, a contact region of a second conductivity type, a deep trench shielding structure, an interlayer dielectric layer, a first electrode, and a second electrode; wherein, the conductive shielding layer, the trench insulating layer, and the semiconductor substrate together constitute a three-dimensional deep trench MIS coupling structure, used to form a displacement current coupling bypass path through the trench insulating layer to perform high-frequency coupling bypass of high-frequency electromagnetic interference signals; the displacement current coupling bypass path is at least partially spatially separated from the ESD or surge transient high current discharge path within the device. This invention balances high-speed signal integrity, electromagnetic compatibility performance, and transient overvoltage protection capabilities, while reducing system-level interconnect parasitic parameters, suppressing high-frequency impedance discontinuities, and reducing additional parasitic inductance in high-speed return paths.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor transient overvoltage protection and electromagnetic compatibility technology, and specifically relates to a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device and its manufacturing method. Background Technology

[0002] With the development of high-speed electronic systems, the data transmission rates of high-speed interfaces such as USB4, HDMI 2.1, PCIe, automotive Ethernet, and high-speed SerDes are constantly increasing, with some high-speed links reaching data rates in the tens of Gbps range. These high-speed electronic systems place higher demands on signal integrity (SI) and electromagnetic compatibility (EMC). They require protection devices to possess electrical characteristics such as low parasitic capacitance, low parasitic inductance, and low dynamic resistance to reduce high-speed signal distortion. Furthermore, the system must simultaneously possess strong high-frequency electromagnetic interference (EMI) suppression capabilities and transient overvoltage protection capabilities.

[0003] In existing technologies, EMI filtering and TVS transient discharge functions are typically handled by different devices, usually employing a combination of multiple discrete filtering devices and transient protection devices to construct a high-speed interface protection network. However, this type of traditional planar cascaded structure has the following problems: (1) The pins, pads and PCB traces of discrete components introduce additional parasitic inductance and parasitic capacitance. Under GHz-level high-frequency conditions, the above parasitic parameters can easily cause signal reflection, increased return loss and increased insertion loss, thereby destroying the impedance continuity of high-speed differential signals and reducing signal integrity.

[0004] (2) Since the external EMI filter and the TVS device are physically separated, the transient overvoltage pulse needs to go through a long PCB interconnection path before it is transmitted to the TVS device, which increases the parasitic inductance of the circuit and causes additional transient voltage overshoot, suppressing the transient response speed of the TVS device, making it difficult to achieve fast in-situ overvoltage clamping, and causing the core chip to be susceptible to overshoot voltage impact.

[0005] (3) There is usually a PCB-level space gap between the traditional external EMI filter and the TVS protection device, which separates the EMI filter reference point from the ESD discharge reference point, thereby increasing the risk of common-mode noise coupling and ground bounce noise in the high-speed interface, and further deteriorating the EMC performance in the high-speed link. In the high-speed differential interface, the above-mentioned reference point separation can also easily form additional common-mode current loops, thereby increasing common-mode radiation and mode conversion loss in the high-speed link.

[0006] (4) In high-speed differential lines, it is difficult to achieve completely consistent parasitic parameters and capacitance matching between external filtering devices, which can easily lead to differential impedance imbalance and mode conversion noise, and further increase common-mode interference, reducing the electromagnetic interference immunity of high-speed differential interfaces. In addition, traditional board-level EMI filtering devices usually require additional pads, traces and return paths. Their additional parasitic parameters can easily form impedance discontinuities in high-speed interfaces, thereby limiting the bandwidth of high-speed signal transmission and increasing insertion loss and mode conversion noise in high-speed links.

[0007] (5) Using multiple discrete components not only increases the PCB area and system assembly complexity, but also increases the bill of materials (BOM) cost and the risk of soldering failure, which is not conducive to the miniaturization and high-density integration of high-speed interface systems. Moreover, traditional external EMI filter structures and TVS protection structures usually lack a unified integrated design mechanism, making it difficult to simultaneously optimize high-frequency filtering performance, transient discharge capability, parasitic parameter control and chip area utilization.

[0008] Therefore, how to achieve in-situ integration of high-frequency electromagnetic interference coupling bypass structure and TVS protection structure within a single chip, while simultaneously ensuring high-speed signal integrity, electromagnetic compatibility performance, and transient overvoltage protection capability, and reducing system-level interconnect parasitic parameters, high-frequency impedance discontinuity effects, and additional parasitic inductance in high-speed return paths, has become an important technical problem that urgently needs to be solved in the field of high-speed differential interface protection. Summary of the Invention

[0009] The purpose of this invention is to provide a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device and its manufacturing method. This method forms a displacement current coupling bypass path and an ESD / surge high current discharge path in situ within the TVS chip, achieving spatial separation, reference ground sharing, and joint optimization of parasitic parameters. This integrates high-speed signal integrity, electromagnetic compatibility performance, and transient overvoltage protection capabilities. Furthermore, this invention effectively reduces system-level interconnect parasitic parameters, suppresses high-frequency impedance discontinuities, and reduces additional parasitic inductance in high-speed return paths, making it suitable for high-speed differential interface protection applications.

[0010] The main technical solution adopted in this invention is as follows: A deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device includes: A semiconductor substrate having a first type of conductivity; A first conductivity type drift region is disposed on the semiconductor substrate; A second conductivity type well region is formed in the surface layer of the first conductivity type drift region. An avalanche PN junction structure is formed between the second conductivity type well region and the first conductivity type drift region to form an ESD or surge transient large current discharge path. A second type of conductive contact area is disposed in the surface layer of the second type of conductive well area; A deep trench shielding structure is disposed in the first conductivity type drift region. The deep trench shielding structure includes a trench insulating layer and a conductive shielding layer. The trench insulating layer covers the inner wall and bottom of the deep trench, and the conductive shielding layer fills the space inside the trench insulating layer. The projection of the deep trench shielding structure on the plane surrounds or separates the second conductivity type well region. An interlayer dielectric layer is disposed on the surface of the first conductivity type drift region. The interlayer dielectric layer has source region contact holes and conductive shielding layer contact holes, respectively exposing the contact region of the second conductivity type and the contact area of ​​the deep trench shielding structure. The first electrode is electrically connected to the contact area of ​​the second conductivity type and the conductive shielding layer, and the conductive shielding layer and the first electrode are at the same potential; and The second electrode is electrically connected to the semiconductor substrate; The conductive shielding layer, the trench insulating layer, and the semiconductor substrate together constitute a three-dimensional deep trench MIS coupling structure, which is used to form a displacement current coupling bypass path through the trench insulating layer to couple and bypass high-frequency electromagnetic interference signals. The displacement current coupling bypass path and the ESD or surge transient high current discharge path form at least partially spatially separated transmission paths within the device.

[0011] Preferably, the deep trench shielding structure extends downward from the surface of the first conductivity type drift region into the interior of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate, forming a fully isolated structure.

[0012] Preferably, the deep trench shielding structure extends downward from the surface of the first conductivity type drift region in a direction perpendicular to the surface of the semiconductor substrate and terminates inside the first conductivity type drift region, forming a shallow isolation structure.

[0013] Preferably, the thickness of the first conductivity type drift region is 5 μm to 50 μm.

[0014] Preferably, the projection of the deep trench shielding structure onto the plane is a closed ring structure or a mesh structure.

[0015] Preferably, the depth of the deep trench shielding structure is 5.5μm to 55μm, and the trench width is 0.2μm to 5μm.

[0016] Preferably, a locally heavily doped buffer layer is further provided on the trench sidewall adjacent to the first conductivity type drift region of the deep trench shielding structure; the conductivity type of the locally heavily doped buffer layer is the same as that of the first conductivity type drift region, and its doping concentration is higher than that of the first conductivity type drift region.

[0017] A method for manufacturing a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device includes the following steps: Step 1: Provide a semiconductor substrate of a first conductivity type, and form a drift region of the first conductivity type on the surface of the semiconductor substrate; Step 2: Form a deep trench in the drift region of the first conductivity type; Step 3: Continuously form a trench insulation layer on the inner wall and bottom surface of the deep trench; Step 4: Fill the trench insulation layer with conductive material to form a conductive shielding layer; Step 5: Form a second conductivity type well region in the surface active region of the first conductivity type drift region, so that the second conductivity type well region and the first conductivity type drift region form an avalanche PN junction structure; Step 6: Form a heavily doped contact region of the second conductivity type on the surface of the well region of the second conductivity type; Step 7: An interlayer dielectric layer is formed on the surface of the device, and source region contact holes and conductive shielding layer contact holes are formed. Then, a first electrode is formed on the surface of the interlayer dielectric layer, which is electrically connected to the heavily doped contact region of the second conductivity type and the conductive shielding layer. Step 8: Form a second electrode on the back side of the semiconductor substrate.

[0018] Preferably, the deep trench is formed using a deep reactive ion etching process, and the deep trench serves as a lateral impurity diffusion barrier structure during the thermal activation process of forming the second conductivity type well region, thereby limiting the lateral expansion range of the second conductivity type well region.

[0019] Preferably, in step 3, before forming the trench insulating layer, the first conductivity type drift region adjacent to the sidewall of the deep trench is subjected to first conductivity type impurity ion implantation and thermal activation diffusion treatment to form a locally heavily doped buffer layer in the region adjacent to the sidewall of the deep trench.

[0020] Beneficial effects: This invention provides a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device and its manufacturing method, which has the following advantages: (1) This invention constructs a deep trench MIS coupling structure inside the TVS device, so that the displacement current coupling bypass path and the ESD / surge current discharge path share the same signal input node and the same reference ground, realizing the synergistic integration of the two functions within a single chip. Compared with the traditional discrete device cascading scheme, no external EMI filter is required, which significantly reduces the number of peripheral devices and PCB area occupied, and is conducive to the miniaturization and high-density integration of high-speed interface systems.

[0021] (2) In this invention, the high-frequency coupling path is entirely located inside the chip, avoiding the additional parasitic inductance and capacitance introduced by PCB traces, pads, and pins. This enables the device to exhibit low impedance bypass characteristics in the GHz band, thereby significantly improving the coupling bypass efficiency of high-frequency electromagnetic interference signals. At the same time, transient overvoltage pulses can trigger the avalanche PN junction to conduct without passing through a long external interconnect path. Combined with the lateral electric field modulation effect of the deep trench structure, the dynamic resistance of the device is effectively reduced, significantly improving the transient response speed and overvoltage clamping capability.

[0022] (3) This invention uses a deep trench MIS coupling structure to form a low-impedance bypass for common-mode high-frequency interference, while maintaining a low additional load on the differential-mode effective signal, effectively reducing insertion loss and mode conversion noise, and ensuring the integrity of high-speed signal transmission. At the same time, the deep trench shielding structure precisely defines the high-current carrying area of ​​the avalanche PN junction in the longitudinal direction and improves the uniformity of the edge electric field distribution in the lateral direction, thereby improving the device's high-current surge carrying capacity and long-term operational reliability, and meeting the protection requirements of high-speed interfaces. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall structure of the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the displacement current coupling bypass path provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the ESD / surge current discharge path provided in an embodiment of the present invention; Figure 4 A schematic diagram of the equivalent circuit of the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device provided in an embodiment of the present invention; Figure 5 This is a locally enlarged schematic diagram of the deep trench structure with a locally heavily doped buffer layer in Embodiment 3 of the present invention.

[0024] The diagram labels are as follows: semiconductor substrate 100, drift region of first conductivity type 200, well region of second conductivity type 300, contact region of second conductivity type 400, first electrode 500, second electrode 600, deep trench shielding structure 700, trench insulating layer 710, conductive shielding layer 720, locally heavily doped buffer layer 730, interlayer dielectric layer 800, active region contact hole 810, and conductive shielding layer contact hole 820. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application. Example 1

[0026] like Figures 1 to 4 As shown, taking P-type as the first conductivity type and N-type as the second conductivity type as an example, this embodiment provides a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device. The device includes: a semiconductor substrate 100, a drift region of the first conductivity type 200, a well region of the second conductivity type 300, a contact region of the second conductivity type 400, a first electrode 500, a second electrode 600, a deep trench shielding structure 700, and an interlayer dielectric layer 800.

[0027] The semiconductor substrate 100 is a heavily doped single-crystal semiconductor substrate of a first conductivity type. By way of example and not limitation, the semiconductor substrate 100 may be one of a P-type single-crystal silicon substrate, an N-type single-crystal silicon substrate, an SOI substrate, a SiC substrate, or a GaN-on-Si substrate. In this embodiment, the semiconductor substrate 100 is a P-type single-crystal silicon substrate. + The doping concentration of the monocrystalline silicon substrate is preferably 1×10⁻⁶. 18 cm⁻³~5×10 19 cm⁻³.

[0028] The first conductivity type drift region 200 is disposed on the upper surface of the semiconductor substrate 100. In this embodiment, the first conductivity type drift region 200 is a low-doped first conductivity type epitaxial layer, the doping concentration of which is lower than that of the semiconductor substrate 100, and its thickness ranges from 1 μm to 80 μm.

[0029] In this embodiment, the doping concentration of the first conductivity type drift region 200 is 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3The first conductivity type drift region 200 is preferably a low-defect epitaxial layer to improve avalanche uniformity and high-current surge reliability.

[0030] The second conductivity type well region 300 is disposed within the surface active region of the first conductivity type drift region 200. In this embodiment, the second conductivity type well region 300 is an N-type well region, formed by ion implantation and thermal activation processes. An avalanche PN junction is formed between the second conductivity type well region 300 and the first conductivity type drift region 200 to form an ESD or surge transient high current discharge path, such as... Figure 3 As shown.

[0031] The second conductivity type contact region 400 is disposed in a local area on the surface of the second conductivity type well region 300. In this embodiment, the second conductivity type contact region 400 is a heavily doped contact region, and its doping concentration is higher than that of the second conductivity type well region 300, so as to form a low impedance ohmic contact region.

[0032] A deep trench shielding structure 700 is disposed in the first conductivity type drift region 200 and located in the peripheral region of the second conductivity type well region 300. The deep trench shielding structure 700 extends from the surface of the first conductivity type drift region 200 into the interior of the semiconductor substrate 100 along a direction perpendicular to the surface of the semiconductor substrate 100, forming a fully isolated structure. Its projection on the plane surrounds or separates the second conductivity type well region 300. In this embodiment, the projection of the deep trench shielding structure 700 on the plane is a closed loop structure. In other embodiments, the projection of the deep trench shielding structure 700 on the plane may also be a mesh structure.

[0033] To balance thermal stress control in the first conductivity type drift region and void-free filling of the high aspect ratio deep trench, the thickness of the first conductivity type drift region 200 is preferably 5 μm to 50 μm. The vertical etching depth of the deep trench shielding structure 700 is preferably 5.5 μm to 55 μm, so as to completely penetrate the first conductivity type drift region 200 longitudinally and extend into the interior of the semiconductor substrate 100. The trench width of the deep trench shielding structure 700 is 0.2 μm to 5 μm.

[0034] like Figure 1As shown, the deep trench shielding structure 700 specifically includes a trench insulating layer 710 and a conductive shielding layer 720. The trench insulating layer 710 covers the inner wall and bottom surface of the deep trench. The trench insulating layer 710 can be a single-layer dielectric structure, a multilayer stacked dielectric structure, or a high-dielectric-constant composite dielectric structure, and its material is one or more of silicon dioxide, silicon nitride, aluminum oxide, tantalum oxide, or hafnium oxide. The sidewall profile of the deep trench can be one of a vertical sidewall, a positive conical sidewall, an inverted conical sidewall, or a sidewall with rounded corners. The total physical thickness of the trench insulating layer 710 is 10 nm to 200 nm. Preferably, the trench insulating layer 710 includes an interface-stabilizing dielectric layer near the semiconductor side and a high-dielectric-constant-enhancing dielectric layer near the conductive shielding layer 720.

[0035] The conductive shielding layer 720 fills the space enclosed by the trench insulating layer 710. The conductive shielding layer 720 is electrically connected to the first electrode 500 and is at the same potential as the first electrode 500, thus serving as the signal side electrode of the MIS coupling structure. The material of the conductive shielding layer 720 is a heavily doped polycrystalline silicon, a heavily doped amorphous silicon thin film, or a single-layer or multi-layer composite conductive structure composed of one or more of tungsten, aluminum, copper, titanium, and titanium nitride.

[0036] An interlayer dielectric layer 800 is disposed on the upper surface of the first conductivity type drift region 200. Source region contact holes 810 and conductive shielding layer contact holes 820 are respectively formed in the interlayer dielectric layer 800, exposing the contact areas of the second conductivity type contact region 400 and the deep trench shielding structure 700, for forming a surface metal interconnect structure.

[0037] The first electrode 500 forms an ohmic connection with the second conductivity type contact area 400 for connecting to an external signal terminal. Simultaneously, the conductive shielding layer 720 is electrically connected to the first electrode 500 to reduce the contact resistance and high-frequency parasitic inductance between the conductive shielding layer 720 and the first electrode 500.

[0038] The second electrode 600 is disposed on the back side of the semiconductor substrate 100 and is electrically connected to the semiconductor substrate 100 as a back metal layer. In this embodiment, the first electrode 500 serves as the cathode of the device, and the second electrode 600 serves as the anode of the device; when the potential of the first electrode 500 is higher than the potential of the second electrode 600, the avalanche PN junction is in a reverse bias state.

[0039] In this embodiment, the deep trench shielding structure 700 and the semiconductor substrate 100 together constitute a three-dimensional deep trench MIS coupling structure, used to form a displacement current coupling bypass path for high-frequency electromagnetic interference signals between the first electrode 500 and the second electrode 600 (e.g., Figure 2 (As shown). The displacement current coupling bypass path is at least partially separated from the ESD or surge transient high current discharge path within the device.

[0040] Based on the above structure, in this embodiment, the deep trench depth is greater than the thickness of the first conductivity type drift region 200, forming a three-dimensional functional partition structure inside the device, as detailed below: (1) The deep trench shielding structure 700 located inside the first conductivity type drift region 200 mainly acts as a physical barrier in the lateral direction to suppress the lateral diffusion of the second conductivity type well region 300 during the thermal activation process, thereby precisely defining and protecting the longitudinal high current carrying area of ​​the avalanche PN junction.

[0041] (2) The deep trench shielding structure 700, which extends into the interior of the highly doped semiconductor substrate 100, forms a three-dimensional MIS coupling interface with the highly doped semiconductor substrate 100 through the trench insulating layer 710. Since the highly doped semiconductor substrate 100 has a low resistivity, it helps to reduce the series resistance on the semiconductor side of the MIS coupling structure and weaken the effect of semiconductor depletion on high-frequency coupling characteristics.

[0042] Under high-frequency electromagnetic interference (EMI) conditions, the EMI signal enters the conductive shielding layer 720 via the first electrode 500 and is coupled to the highly doped semiconductor substrate 100 via the trench insulating layer 710 in a high-frequency coupling manner. It then bypasses to the anode terminal, which serves as the reference ground, via the second electrode 600. Meanwhile, ESD or surge transient currents are discharged longitudinally through the avalanche PN junction, forming a vertical discharge path via the first conductivity type drift region 200 and the semiconductor substrate 100. Thus, the displacement current coupling bypass path and the ESD or surge transient current discharge path form at least partially spatially separated transmission paths within the device, and are potential-coupled by sharing the first electrode 500 and the semiconductor substrate 100. This achieves single-chip co-integration of EMI coupling bypass function and transient overvoltage protection function.

[0043] Meanwhile, compared to the traditional PCB-level discrete EMI filter and TVS cascade structure, the displacement current coupling bypass path does not need to pass through the external PCB-level interconnect structure, which helps to reduce the parasitic inductance of the high-frequency loop; and the MIS coupling structure and the avalanche PN junction share the same reference ground terminal, which helps to reduce the loop parasitic inductance between the high-frequency return path and the transient overvoltage large current discharge path.

[0044] The above structure achieves single-chip three-dimensional collaborative integration of the transient overvoltage longitudinal discharge path and the displacement current coupling bypass path without increasing the chip planar area or introducing additional manufacturing processes, thus taking into account both high-current transient protection capability and high-frequency electromagnetic interference suppression capability in high-speed interfaces.

[0045] The working principle of this embodiment is as follows: (1) High-frequency electromagnetic interference coupling bypass principle In this embodiment, the conductive shielding layer 720, the trench insulating layer 710, and the semiconductor substrate 100 together constitute a deep trench MIS coupling structure. The conductive shielding layer 720 is electrically connected to the first electrode 500, serving as the signal-side electrode of the MIS coupling structure; the trench insulating layer 710 serves as an insulating dielectric layer; and the semiconductor substrate 100 serves as the semiconductor-side electrode of the MIS coupling structure and is connected to a reference ground terminal via the second electrode 600.

[0046] When a high-frequency electromagnetic interference (EMI) signal is present in the input line connected to the first electrode 500, the EMI signal enters the conductive shielding layer 720. Since the conductive shielding layer 720 and the semiconductor substrate 100 are isolated by a trench insulating layer 710, there is no DC conduction path between them; instead, a high-frequency coupling path is formed through the trench insulating layer 710. As the frequency of the EMI signal increases, the MIS coupling structure exhibits a lower high-frequency coupling impedance. The EMI signal is coupled to the semiconductor substrate 100 via the trench insulating layer 710 in the form of a displacement current, and then bypasses to the reference ground terminal through the second electrode 600.

[0047] Therefore, as Figure 2 As shown, the displacement current coupling bypass path of the present invention is: first electrode 500 → conductive shielding layer 720 → trench insulating layer 710 → semiconductor substrate 100 → second electrode 600 → reference ground terminal.

[0048] Since the displacement current coupling bypass path is formed inside the single chip and is set in parallel with the TVS transient discharge path, it can reduce the interconnect parasitic parameters in the traditional PCB-level external filter structure, thereby improving the high-frequency electromagnetic interference coupling bypass capability.

[0049] (II) Principle of ESD / Surge Transient Overvoltage Protection When the first electrode 500 is subjected to transient overvoltage impacts such as electrostatic discharge (ESD), surge, or electrical fast transient pulse (EFT), the transient voltage applied across the avalanche PN junction rapidly increases. When this transient voltage exceeds the reverse breakdown voltage of the avalanche PN junction, the avalanche PN junction enters a low-impedance conduction state, thereby forming a longitudinal ESD / surge high-current discharge path inside the device.

[0050] The ESD / surge current discharge path is as follows: first electrode 500 → second conductivity type heavily doped contact region 400 → second conductivity type well region 300 → first conductivity type region 200 → semiconductor substrate 100 → second electrode 600 → reference ground terminal.

[0051] Through the aforementioned vertical discharge path, transient overvoltage energy is rapidly discharged, thereby reducing residual overvoltage applied to subsequent chips and improving the system's anti-static and surge protection capabilities.

[0052] (III) Path space separation and cooperation mechanism Under high-frequency electromagnetic interference (EMI) operating conditions, EMI signals mainly form a displacement current coupling bypass path through the deep trench MIS coupling structure. Under ESD or surge operating conditions, transient large currents mainly form an ESD or surge large current discharge path after the avalanche PN junction is turned on. The displacement current coupling bypass path and the ESD or surge large current discharge path are at least partially spatially separated within the device.

[0053] like Figure 4 As shown, the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device in this embodiment can be equivalent to an integrated protection network composed of a deep trench MIS coupling branch and an avalanche PN junction TVS branch connected in parallel.

[0054] Among them, the deep trench MIS coupling branch is used to form a displacement current coupling bypass path for high-frequency electromagnetic interference signals, exhibiting low impedance coupling characteristics under high-frequency conditions; the avalanche PN junction TVS branch is used to form a large current discharge path for ESD / surge under ESD or surge transient overvoltage conditions.

[0055] The two types of branches share the first electrode 500 as the input node and the semiconductor substrate 100 and the second electrode 600 as the reference ground return node, thereby realizing the synergistic integration of high-frequency electromagnetic interference coupling bypass function and transient overvoltage protection function within a single chip.

[0056] (iv) Principle of transverse electric field regulation The deep trench shielding structure 700 also forms a lateral electric field coupling modulation effect on the first conductivity type drift region 200 through the trench insulating layer 710. When the device is in the operating bias state, the conductive shielding layer 720 is at the same potential as the first electrode 500, and forms an electric field coupling effect with the surrounding semiconductor region through the trench insulating layer 710, thereby adjusting the uniformity of the local electric field distribution around the active region. This lateral electric field modulation effect can adjust the surface electric field distribution in the avalanche PN junction edge region, suppress local premature breakdown, reduce the dynamic resistance of the device, improve the uniformity of the electric field distribution in the avalanche PN junction edge region, reduce the local electric field concentration effect, and improve the high-current transient reliability of the device.

[0057] Meanwhile, this structure helps improve the reverse withstand voltage uniformity and high current surge carrying capacity of the device. Furthermore, the deep trench shielding structure 700 can also reduce the edge electric field coupling effect in multi-unit array structures.

[0058] The comprehensive electrical performance parameters of this embodiment 1 are as follows: The high-frequency electromagnetic interference coupling network constructed by the deep trench MIS coupling structure in Embodiment 1 has an equivalent coupling capacitance per unit area of ​​1fF / μm² to 10fF / μm². Based on this capacitance range, the overall equivalent series inductance (ESL) of the structure is preferably controlled below 50pH to enable it to exhibit low impedance bypass characteristics in the GHz frequency band and achieve efficient high-frequency coupling discharge.

[0059] Meanwhile, the reverse breakdown voltage range of the TVS device is 3.3V to 48V; under the 8 / 20 μs standard surge waveform, its dynamic resistance is preferably less than 0.5Ω to ensure excellent transient surge clamping capability.

[0060] Application of Example 1 The deep trench MIS structure in this embodiment is used for common-mode electromagnetic interference suppression in high-speed differential interfaces. This structure can form a low-impedance coupling bypass path for common-mode high-frequency interference signals, while maintaining a low additional load on effective high-speed differential signals, thereby reducing mode-switching noise and improving the integrity of high-speed differential signals.

[0061] This structure can be preferentially applied to interfaces including but not limited to USB4, HDMI, PCIe, DisplayPort, automotive Ethernet, high-speed SerDes, and high-speed optoelectronic interconnects to implement common-mode high-frequency electromagnetic interference coupling bypass and transient overvoltage protection. In summary, the deep trench MIS structure can significantly improve the electromagnetic compatibility performance of the interface system while ensuring the integrity of high-speed and effective signal transmission.

[0062] In this invention, the first conductivity type and the second conductivity type are semiconductor conductivity types that are opposite to each other. In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type; however, the invention is not limited thereto, and in other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type accordingly.

[0063] Based on the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device provided in the above embodiments, this embodiment also provides its manufacturing method, including the following steps: Step 1: Provide a highly doped semiconductor substrate 100 of a first conductivity type, and form a drift region 200 of the first conductivity type on the surface of the semiconductor substrate 100 using an epitaxial growth process. In this embodiment, the doping concentration of the drift region 200 of the first conductivity type is lower than that of the semiconductor substrate 100, and its thickness is preferably 1 μm to 80 μm.

[0064] Step 2: A trench pattern mask is formed on the surface of the first conductivity type drift region 200, and a deep trench is formed using anisotropic etching. In this embodiment, a deep reactive ion etching (DRIE) process is used to form the deep trench, and its projection on the plane can be a closed ring structure (including a circular ring structure, a side ring structure, etc.) or a mesh structure.

[0065] Furthermore, after the deep trench etching is completed, the trench sidewalls and bottom can be repaired or rounded to improve the subsequent dielectric interface quality and electric field uniformity.

[0066] Step 3: A trench insulation layer 710 is continuously formed on the inner sidewalls and bottom surface of the deep trench. The trench insulation layer 710 can be formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof.

[0067] Step 4: After forming the trench insulating layer 710, conductive material is completely or partially filled into the deep trench to form a conductive shielding layer 720. There is no DC conductivity between this conductive shielding layer 720 and the trench insulating layer 710. Subsequently, a planarization process is used to remove excess conductive material from the outside of the deep trench, leaving the conductive shielding layer 720 only inside the trench. The planarization process is preferably a chemical mechanical polishing (CMP) process or a dry etching process.

[0068] Step 5: Within the surface active region of the first conductivity type region 200, a second conductivity type well region 300 is formed through ion implantation and thermal activation processes. This introduces impurities of the opposite conductivity type to the first conductivity type, creating an avalanche PN junction between the second conductivity type well region 300 and the first conductivity type region 200. During thermal diffusion, the deep trench shielding structure 700 blocks the lateral diffusion of impurities, thus limiting the lateral expansion range of the active region.

[0069] Step 6: A heavily doped second conductivity type contact region 400 is formed in a localized area on the surface of the second conductivity type well region 300. The doping concentration of the second conductivity type contact region 400 is higher than that of the second conductivity type well region 300, and it is used to form a low impedance ohmic contact.

[0070] Step 7: An interlayer dielectric layer 800 is formed on the device surface, and source region contact holes 810 and conductive shielding layer contact holes 820 are formed, followed by the formation of a surface metal interconnect structure. The first electrode 500 is simultaneously electrically connected to the second conductivity type heavily doped contact region 400 and the conductive shielding layer 720, and a parallel cooperative structure is formed inside the device for displacement current coupling bypass path and ESD or surge transient high current discharge path.

[0071] Step 8: Thin the back side of the semiconductor substrate 100 and form a back metal layer on the thinned back side to form the second electrode 600.

[0072] Through the above steps, the fabrication of the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device is completed. Example 2

[0073] The difference between this embodiment and Embodiment 1 is that the longitudinal depth of the deep trench shielding structure 700 does not penetrate the first conductivity type drift region 200, and a drift region material of a predetermined thickness is retained between its bottom and the upper surface of the semiconductor substrate 100, thereby forming a shallow isolation structure. In this embodiment, although the deep trench shielding structure 700 does not extend into the interior of the semiconductor substrate 100, the deep trench MIS coupling structure can still form a high-frequency displacement current coupling path through the semiconductor continuous region between the first conductivity type drift region 200 and the semiconductor substrate 100, thereby realizing the high-frequency electromagnetic interference coupling bypass function.

[0074] Compared with the fully isolated structure in Example 1, the shallow isolation structure in this example retains a portion of the drift region material of the first conductivity type as a continuous semiconductor region between the bottom of the deep trench and the semiconductor substrate 100, thereby helping to reduce the influence of the deep trench shielding structure 700 on the longitudinal current distribution of the active region and reduce the additional parasitic capacitance introduced by the deep trench structure.

[0075] Therefore, a fully isolated structure is more conducive to improving lateral isolation capability and high-frequency coupling efficiency, while a shallow isolation structure is more conducive to balancing low parasitic parameters and high-speed signal integrity requirements. Example 3

[0076] Based on Example 1 or 2, as a further preferred embodiment, such as Figure 5 As shown, a locally heavily doped buffer layer 730 is further disposed on the trench sidewall adjacent to the first conductivity type drift region 200 of the deep trench shielding structure 700. The conductivity type of the locally heavily doped buffer layer 730 is the same as that of the first conductivity type drift region 200, and its doping concentration is higher than that of the first conductivity type drift region 200. This locally heavily doped buffer layer is used to reduce the high-frequency series resistance on the semiconductor side of the MIS coupling structure, improve the coupling efficiency of high-frequency electromagnetic interference signals, and improve the carrier transport characteristics on the semiconductor side under high-frequency operating conditions.

[0077] The method for preparing the locally heavily doped buffer layer is based on the method in Example 1. Before forming the trench insulating layer 710 in step 3, the drift region 200 of the first conductivity type adjacent to the sidewall of the deep trench is subjected to ion implantation and thermal activation diffusion treatment of the first conductivity type impurity, thereby forming a locally heavily doped buffer layer 730 in the region adjacent to the sidewall of the deep trench.

[0078] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device, characterized in that, include: Semiconductor substrate (100) having a first conductivity type; A first conductivity type drift region (200) is disposed on the semiconductor substrate (100); A second conductivity type well region (300) is formed in the surface layer of the first conductivity type drift region (200). An avalanche PN junction structure is formed between the second conductivity type well region (300) and the first conductivity type drift region (200) to form an ESD or surge transient large current discharge path. A second conductive contact region (400) is disposed in the surface layer of the second conductive well region (300); A deep trench shielding structure (700) is disposed in the first conductivity type drift region (200). The deep trench shielding structure (700) includes a trench insulating layer (710) and a conductive shielding layer (720). The trench insulating layer (710) covers the inner wall and bottom of the deep trench, and the conductive shielding layer (720) fills the space inside the trench insulating layer (710). The projection of the deep trench shielding structure (700) on the plane surrounds or separates the second conductivity type well region (300). An interlayer dielectric layer (800) is disposed on the surface of the first conductivity type drift region (200). The interlayer dielectric layer (800) has a source region contact hole (810) and a conductive shielding layer contact hole (820) to expose the contact areas of the second conductivity type contact region (400) and the deep trench shielding structure (700), respectively. The first electrode (500) is electrically connected to the second conductivity type contact area (400) and the conductive shielding layer (720), and the conductive shielding layer (720) and the first electrode (500) are at the same potential; and The second electrode (600) is electrically connected to the semiconductor substrate (100); The conductive shielding layer (720), the trench insulating layer (710), and the semiconductor substrate (100) together constitute a three-dimensional deep trench MIS coupling structure, which is used to form a displacement current coupling bypass path through the trench insulating layer (710) to couple and bypass high-frequency electromagnetic interference signals. The displacement current coupling bypass path and the ESD or surge transient high current discharge path form at least partially spatially separated transmission paths within the device.

2. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, The deep trench shielding structure (700) extends downward from the surface of the first conductivity type drift region (200) into the interior of the semiconductor substrate (100) in a direction perpendicular to the surface of the semiconductor substrate (100), forming a fully isolated structure.

3. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, The deep trench shielding structure (700) extends downward from the surface of the first conductivity type drift region (200) in a direction perpendicular to the surface of the semiconductor substrate (100) and terminates inside the first conductivity type drift region (200) to form a shallow isolation structure.

4. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, The thickness of the first conductivity type drift region (200) is 5 μm to 50 μm.

5. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, The deep trench shielding structure (700) is projected onto a plane as a closed ring structure or a mesh structure.

6. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, The depth of the deep trench shielding structure (700) is 5.5μm to 55μm, and the trench width is 0.2μm to 5μm.

7. The deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 1, characterized in that, On the trench sidewall of the deep trench shielding structure (700) adjacent to the first conductivity type drift region (200), a locally heavily doped buffer layer is also provided; the conductivity type of the locally heavily doped buffer layer is the same as that of the first conductivity type drift region (200), and its doping concentration is higher than that of the first conductivity type drift region (200).

8. A method for manufacturing a deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device as described in any one of claims 1-7, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate (100) of a first conductivity type, and form a drift region (200) of the first conductivity type on the surface of the semiconductor substrate (100); Step 2: Form a deep trench in the first conductivity type drift region (200); Step 3: A trench insulation layer (710) is continuously formed on the inner wall and bottom surface of the deep trench; Step 4: Fill the trench insulation layer (710) with conductive material to form a conductive shielding layer (720). Step 5: Form a second conductivity type well region (300) in the surface active region of the first conductivity type drift region (200), so that the second conductivity type well region (300) and the first conductivity type drift region (200) form an avalanche PN junction structure; Step 6: Form a heavily doped contact region (400) of the second conductivity type on the surface of the well region (300) of the second conductivity type. Step 7: An interlayer dielectric layer (800) is formed on the surface of the device, and a source region contact hole (810) and a conductive shielding layer contact hole (820) are formed. Then, a first electrode (500) electrically connected to the second conductivity type heavily doped contact region (400) and the conductive shielding layer (720) is formed on the surface of the interlayer dielectric layer (800). Step 8: Form a second electrode (600) on the back side of the semiconductor substrate (100).

9. The manufacturing method of the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 8, characterized in that, The deep trench is formed using a deep reactive ion etching process, and during the thermal activation process of forming the second conductivity type well region (300), the deep trench serves as a lateral impurity diffusion barrier structure to limit the lateral expansion range of the second conductivity type well region (300).

10. The manufacturing method of the deep trench MIS integrated high-frequency electromagnetic interference coupling bypass TVS device according to claim 8, characterized in that, In step 3, before forming the trench insulating layer (710), the first conductivity type drift region (200) adjacent to the sidewall of the deep trench is subjected to first conductivity type impurity ion implantation and thermal activation diffusion treatment to form a locally heavily doped buffer layer (730) in the region adjacent to the sidewall of the deep trench.

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