Bidirectional diode triggered thyristor device and method of making same

Abstract

The application provides a bidirectional diode triggered thyristor device and a preparation method thereof. The bidirectional diode triggered thyristor device comprises a semiconductor layer, first to sixth contact regions and electrodes. The semiconductor layer comprises a substrate, a deep well region, a first well region and a second well region on the top layer of the deep well region, and the first well region is adjacent to the second well region. The first and second contact regions are located on the top layer of the first well region. The third contact region is located on the top layer of the first well region between the first and second contact regions. The fourth and fifth contact regions are located on the top layer of the second well region. The sixth contact region is located on the top layer of the second well region between the fourth and fifth contact regions. The first electrode is electrically connected with the first and fifth contact regions respectively. The interconnection electrode is electrically connected with the third and sixth contact regions respectively. The second electrode is electrically connected with the second and fourth contact regions respectively. The application optimizes the arrangement of the contact regions and uses SAB instead of STI, thereby reducing the on-resistance of the device, reducing the area of the device and improving the robustness of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a bidirectional diode-triggered thyristor device and its fabrication method. Background Technology

[0002] In low-voltage processes, bidirectional diode-triggered silicon controlled rectifiers (DTSCRs) are characterized by small area, low capacitance, and strong discharge current capability. Currently, to improve device resilience, shallow trench isolation (STI) structures are commonly used to isolate N-wells from P-wells, P+ doped regions from N-wells, and P+ doped regions from P-wells, such as... Figure 1 As shown. In this structure, the ESD pulse current needs to bypass the STI to reach the cathode. Although this improves the failure resistance of the DTSCR device, its area is large and the on-resistance is large due to the long current path, resulting in poor robustness of the device.

[0003] Therefore, there is an urgent need to find a bidirectional diode-triggered thyristor device that can reduce device area and on-resistance while improving device robustness. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a bidirectional diode-triggered silicon controlled rectifier (DTSCR) device and its fabrication method, so as to solve the problems of large area, high on-resistance and poor robustness of DTSCR devices in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a bidirectional diode-triggered silicon controlled rectifier device, comprising:

[0006] The semiconductor layer includes a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region and a second conductivity type second well region located on the upper surface of the deep well region and adjacent to it.

[0007] The first contact area and the second contact area of ​​the second conductivity type, which are arranged at intervals along the arrangement direction of the first well area and the second well area, are both located on the upper surface layer of the first well area;

[0008] The third contact region of the first conductivity type is located on the upper surface of the first well region between the first contact region and the second contact region.

[0009] The first conductive type fourth contact area and fifth contact area, which are arranged at intervals along the arrangement direction of the first well area and the second well area, are both located on the upper surface layer of the second well area.

[0010] The sixth contact region of the second conductivity type is located on the upper surface of the second well region between the fourth contact region and the fifth contact region;

[0011] The first electrode is electrically connected to the first contact area and the fifth contact area, respectively;

[0012] Interconnecting electrodes are electrically connected to the third contact area and the sixth contact area, respectively;

[0013] The second electrode is electrically connected to both the second contact area and the fourth contact area.

[0014] Optionally, the device further includes a second conductive type isolation well region located on the side of the first well region away from the second well region. The bottom surface of the isolation well region is flush with the upper surface of the deep well region, and the isolation well region is spaced at a predetermined distance from the side of the first contact region away from the second well region.

[0015] Optionally, the device further includes an isolation structure, which is embedded in the upper surface layer of the edge region where the first well region and the second well region are located, and the sidewall of the isolation structure located at the edge of the first well region extends into the isolation well region.

[0016] Optionally, the device further includes a self-aligned silicide barrier layer located on the upper surfaces of the first well region and the second well region.

[0017] Optionally, the self-aligned silicide barrier layer further includes a first opening, a second opening, and a third opening. The first opening penetrates the self-aligned silicide barrier layer directly above the first contact area and the fifth contact area. The second opening penetrates the self-aligned silicide barrier layer directly above the second contact area and the fourth contact area. The third opening penetrates the self-aligned silicide barrier layer directly above the third contact area and the sixth contact area.

[0018] Optionally, a silicide layer is provided on the upper surface of the area exposed by the bottom surfaces of the first opening, the second opening, and the third opening. The first electrode is electrically connected to the first contact area and the fifth contact area through the silicide layer at the bottom of the first opening, respectively. The second electrode is electrically connected to the second contact area and the fourth contact area through the silicide layer at the bottom of the second opening, respectively. The interconnect electrode is electrically connected to the third contact area and the sixth contact area through the silicide layer at the bottom of the third opening, respectively.

[0019] Optionally, the device further includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the upper surface of the silicide layer and the self-aligned silicide barrier layer. The first contact hole penetrates the interlayer dielectric layer directly above the first contact area and the fifth contact area, and exposes the silicide layer on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the second contact area and the fourth contact area, and exposes the silicide layer on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the third contact area and the sixth contact area, and exposes the silicide layer on its bottom surface. The first electrode fills the first contact hole, the second electrode fills the second contact hole, and the interconnect electrode fills the third contact hole.

[0020] Optionally, the contact type between the first contact area and the fifth contact area and the first electrode is ohmic contact; or the contact type between the second contact area and the fourth contact area and the second electrode is ohmic contact.

[0021] Optionally, the doping concentration of the third contact region is greater than the doping concentration of the first well region, and the contact type between the third contact region and the interconnect electrode is an ohmic contact; or the doping concentration of the sixth contact region is greater than the doping concentration of the second well region, and the contact type between the sixth contact region and the interconnect electrode is an ohmic contact.

[0022] This invention also provides a method for fabricating a bidirectional diode-triggered silicon-controlled device, comprising the following steps:

[0023] A semiconductor layer is provided, comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and the first conductivity type first well region and the second conductivity type second well region located on the upper surface of the deep well region and adjacent to it;

[0024] A first contact area of ​​a second conductivity type, a second contact area of ​​a second conductivity type, and a third contact area of ​​a first conductivity type are respectively formed on the upper surface of the first well region, and a fourth contact area of ​​a first conductivity type, a fifth contact area of ​​a first conductivity type, and a sixth contact area of ​​a second conductivity type are respectively formed on the upper surface of the second well region. Along the arrangement direction of the first well region and the second well region, the first contact area, the third contact area, the second contact area, the fourth contact area, the sixth contact area, and the fifth contact area are arranged in sequence at intervals.

[0025] A first electrode, an interconnect electrode, and a second electrode are formed. The first electrode is electrically connected to the first contact area and the fifth contact area, respectively. The interconnect electrode is electrically connected to the third contact area and the sixth contact area, respectively. The second electrode is electrically connected to the second contact area and the fourth contact area, respectively.

[0026] As described above, the bidirectional diode-triggered thyristor device and its fabrication method of the present invention utilize a self-aligned silicide barrier layer to replace the shallow trench isolation structure that isolates each contact region, reducing the distance between the first and second electrodes of the device. Simultaneously, it allows the ESD pulse current to flow through the surfaces of the first and second well regions, reducing the on-resistance of the device and improving its robustness. Adjusting the arrangement of each contact region creates multiple ESD pulse current discharge paths within the device, including diodes, PNP transistors, NPN transistors, and SCRs, enhancing the device's failure resistance. Furthermore, since the device contains only PN junction capacitance, parasitic capacitance is low, making it suitable for low-voltage, high-speed applications and possessing significant industrial application value. Attached Figure Description

[0027] Figure 1 This is a cross-sectional view of a bidirectional DTSCR device.

[0028] Figure 2 This is a cross-sectional view of the bidirectional diode-triggered thyristor device of the present invention.

[0029] Figure 3 This is the equivalent circuit diagram of the bidirectional diode-triggered thyristor device of the present invention when it is in forward operation.

[0030] Figure 4 This is the equivalent circuit diagram of the bidirectional diode-triggered thyristor device of the present invention when it operates in reverse.

[0031] Figure 5 This is a simulation diagram of the current density of the bidirectional diode-triggered thyristor device of the present invention when the forward diode is turned on.

[0032] Figure 6 This is a simulation diagram of the current density of the bidirectional diode-triggered thyristor device when it is fully forward-biased.

[0033] Figure 7 This is a simulation diagram of the current density of the bidirectional diode-triggered thyristor device of the present invention when the reverse diode is turned on.

[0034] Figure 8 This is a simulation diagram of the current density of the bidirectional diode-triggered thyristor device of the present invention when it is fully reverse-biased.

[0035] Figure 9 This is a process flow diagram of the bidirectional diode-triggered thyristor device fabrication method of the present invention.

[0036] Figure 10 This is a cross-sectional view of the semiconductor layer in the method for fabricating a bidirectional diode-triggered thyristor device according to the present invention.

[0037] Figure 11This is a cross-sectional view of the bidirectional diode-triggered thyristor device fabrication method of the present invention after forming the isolation structure.

[0038] Figure 12 This is a cross-sectional view of the bidirectional diode-triggered thyristor device fabrication method of the present invention after forming each contact region.

[0039] Figure 13 This is a cross-sectional view of the bidirectional diode-triggered thyristor device fabrication method of the present invention after forming a self-aligned silicide barrier layer.

[0040] Explanation of reference numerals: 01 P-type substrate, 011 N-type deep well, 012 N-well, 013 P-well, 014 N-type isolation well, 015 STI isolation structure, 02 P+ anode region, 021 P+ cathode region, 022 N+ interconnect region, 023 P+ interconnect region, 024 N+ cathode region, 025 N+ anode region, 026 anode, 027 cathode, 028 interconnect electrode, 1 substrate, 11 deep well region, 12 first well region, 13 second well region, 14 isolation well region, 15 isolation structure, 2 first contact region, 21 second contact region, 22 third contact region, 23 fourth contact region, 24 fifth contact region, 25 sixth contact region, 26 self-aligned silicide barrier layer, 3 first electrode, 31 interconnect electrode, 32 second electrode. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figures 2 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] Example 1

[0044] This embodiment provides a bidirectional diode-triggered silicon controlled rectifier device, such as... Figures 2 to 4The figures shown are a cross-sectional view of the bidirectional diode-triggered thyristor device, an equivalent circuit diagram of the bidirectional diode-triggered thyristor device in forward operation, and an equivalent circuit diagram of the bidirectional diode-triggered thyristor device in reverse operation. The device includes a semiconductor layer, a first contact region 2 of the second conductivity type, a second contact region 21 of the second conductivity type, a third contact region 22 of the first conductivity type, a fourth contact region 23 of the first conductivity type, a fifth contact region 24 of the first conductivity type, a sixth contact region 25 of the second conductivity type, a first electrode 3, an interconnect electrode 31, and a second electrode 32. The semiconductor layer includes a first conductivity type substrate 1 and a second conductivity type deep well region 11 stacked sequentially, and a first conductivity type first well region 12 and a second conductivity type second well region 12 located on the upper surface of the deep well region 11 and adjacent to it. 3; The first contact area 2 and the second contact area 21 are spaced apart along the arrangement direction of the first well area 12 and the second well area 13 and are both located on the upper surface of the first well area 12; the third contact area 22 is located on the upper surface of the first well area 12 between the first contact area 2 and the second contact area 21; the fourth contact area 23 and the fifth contact area 24 are spaced apart along the arrangement direction of the first well area 12 and the second well area 13 and are both located on the upper surface of the second well area 13; the sixth contact area 25 is located on the upper surface of the second well area 13 between the fourth contact area 23 and the fifth contact area 24; the first electrode 3 is electrically connected to the first contact area 2 and the fifth contact area 24 respectively; the interconnecting electrode 31 is electrically connected to the third contact area 22 and the sixth contact area 25 respectively; the second electrode 32 is electrically connected to the second contact area 21 and the fourth contact area 23 respectively.

[0045] It should be noted that the first conductivity type typically includes either N-type or P-type, and the second conductivity type also includes either N-type or P-type. The doping type of the first conductivity type is opposite to that of the second conductivity type; that is, when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

[0046] Specifically, the substrate 1 in the semiconductor layer is usually the process platform for fabricating the deep well region 11. While ensuring device performance, the size, shape, thickness and doping concentration of the substrate 1 can be selected according to the actual situation.

[0047] Specifically, the deep well region 11 is typically used to achieve electrical isolation between the well region (i.e., the first well region 12) of the thyristor device triggered by a bidirectional diode and the substrate 1. While ensuring device performance, the doping concentration and thickness of the deep well region 11 can be selected according to the actual situation.

[0048] Specifically, while ensuring device performance, the size, shape, thickness, and doping concentration of the first well region 12 can be selected according to actual conditions; the size, shape, thickness, and doping concentration of the second well region 13 can also be selected according to actual conditions. In this embodiment, the first well region 12 and the second well region 13 have the same thickness.

[0049] As an example, the device also includes a second conductive type isolation well region 14 located on the side of the first well region 12 away from the second well region 13. The bottom surface of the isolation well region 14 is flush with the upper surface of the deep well region 11, and the isolation well region 14 is spaced apart from the side of the first contact region 2 away from the second well region 13 by a predetermined distance.

[0050] Specifically, while ensuring device performance, the size, shape, and doping concentration of the first isolation well region 14 can be selected according to the actual situation.

[0051] As an example, the device also includes an isolation structure 15, which is embedded in the upper surface layer of the edge region of the first well region 12 and the second well region 13. The sidewall of the isolation structure 15 located at the edge of the first well region 12 extends into the isolation well region 14.

[0052] Specifically, the isolation structure 15 is used to prevent devices on the periphery of the first well region 12 and the second well region 13 from affecting the devices in the first well region 12 and the second well region 13. The isolation structure 15 includes shallow trenches embedded in the edges of the areas where the first well region 12 and the second well region 13 are located and an insulating filler layer filling the shallow trenches.

[0053] Specifically, while ensuring device performance, the opening size and depth of the shallow trench can be selected according to the actual situation. Here, the depth refers to the distance between the bottom surface of the shallow trench and the upper surface of the first well region 12 and the second well region 13.

[0054] Specifically, the insulating filler layer may be made of silicon dioxide or other suitable dielectric material.

[0055] As an example, the contact type between the first contact region 2 and the fifth contact region 24 and the first electrode 3 is ohmic contact, that is, the first contact region 2 and the fifth contact region 24 are both heavily doped regions.

[0056] Specifically, while ensuring device performance, the size, shape, thickness, and doping concentration of the first contact area 2 can be selected according to actual conditions; the size, shape, thickness, and doping concentration of the fifth contact area 24 can be selected according to actual conditions; the distance between the first contact area 2 and the adjacent isolation structure 15 can be selected according to actual conditions; the distance between the fifth contact area 24 and the adjacent isolation structure 15 can be selected according to actual conditions. In this embodiment, the first contact area 2 is adjacent to the adjacent isolation structure 15, and the fifth contact area 24 is adjacent to the adjacent isolation structure 15.

[0057] As an example, the contact type between the second contact region 21 and the fourth contact region 23 and the second electrode 32 is ohmic contact, that is, the second contact region 21 and the fourth contact region 23 are both heavily doped regions.

[0058] Specifically, the second contact area 21 and the sidewall of the second well area 13 near the first well area 12 are spaced apart by a preset distance, and the fourth contact area 23 and the sidewall of the first well area 12 near the second well area 13 are spaced apart by a preset distance.

[0059] Specifically, while ensuring device performance, the size, shape, thickness, and doping concentration of the second contact region 21 can be selected according to actual conditions; the size, shape, thickness, and doping concentration of the fourth contact region 23 can be selected according to actual conditions; the distance between the second contact region 21 and the sidewall of the second well region 13 near the first well region 12 can be selected according to actual conditions; the distance between the fourth contact region 23 and the sidewall of the first well region 12 near the second well region 13 can be selected according to actual conditions.

[0060] As an example, the doping concentration of the third contact region 22 is greater than that of the first well region 12, and the contact type between the third contact region 22 and the interconnect electrode 31 is an ohmic contact, that is, the third contact region 22 is a heavily doped region.

[0061] Specifically, while ensuring device performance, the distance between the third contact region 22 and the first contact region 2 and the second contact region 21 in the arrangement direction of the first well region 12 and the second well region 13 can be selected according to the actual situation; the size, shape, thickness and doping concentration of the third contact region 22 can be selected according to the actual situation.

[0062] As an example, the doping concentration of the sixth contact region 25 is greater than that of the second well region 13, and the contact type between the sixth contact region 25 and the interconnect electrode 31 is an ohmic contact, that is, the sixth contact region 25 is a heavily doped region.

[0063] Specifically, while ensuring device performance, the distance between the sixth contact region 25 and the fourth contact region 23 and the fifth contact region 24 in the arrangement direction of the first well region 12 and the second well region 13 can be selected according to actual conditions; the size, shape, thickness and doping concentration of the sixth contact region 25 can be selected according to actual conditions. In this embodiment, the thicknesses of the first contact region 2, the second contact region 21, the third contact region 22, the fourth contact region 23, the fifth contact region 24 and the sixth contact region 25 are the same.

[0064] As an example, the device also includes a self-aligned silicide barrier layer 26 located on the upper surfaces of the first well region 12 and the second well region 13.

[0065] Specifically, the material of the self-aligned silicide barrier layer 26 includes silicon oxide, silicon oxynitride, silicon nitride, or other suitable materials. Preferably, a patterned silicon oxide layer is used as the self-aligned silicide barrier layer 26.

[0066] As an example, the self-aligned silicide barrier layer 26 is further provided with a first opening, a second opening and a third opening. The first opening penetrates the self-aligned silicide barrier layer 26 directly above the first contact area 2 and the fifth contact area 24. The second opening penetrates the self-aligned silicide barrier layer 26 directly above the second contact area 21 and the fourth contact area 23. The third opening penetrates the self-aligned silicide barrier layer 26 directly above the third contact area 22 and the sixth contact area 25.

[0067] Specifically, the first opening, the second opening, and the third opening are provided to facilitate the formation of a low-resistance silicide layer on the upper surface of the first contact area 2, the second contact area 21, the third contact area 22, the fourth contact area 23, the fifth contact area 24, and the sixth contact area 25, thereby reducing the contact resistance between the first electrode 3, the second electrode 32, and the interconnect electrode 31 and the corresponding areas.

[0068] Specifically, while ensuring device performance, the size and shape of the first opening can be selected according to the actual situation; the size and shape of the second opening can be selected according to the actual situation; and the size and shape of the third opening can be selected according to the actual situation.

[0069] As an example, a silicide layer is provided on the upper surface of the area exposed at the bottom of the first opening, the second opening, and the third opening. The first electrode 3 is electrically connected to the first contact area 2 and the fifth contact area 24 through the silicide layer at the bottom of the first opening, respectively. The second electrode 32 is electrically connected to the second contact area 21 and the fourth contact area 23 through the silicide layer at the bottom of the second opening, respectively. The interconnecting electrode 31 is electrically connected to the third contact area 22 and the sixth contact area 25 through the silicide layer at the bottom of the third opening, respectively.

[0070] Specifically, the silicide layer is used to reduce the contact resistance between the first electrode 3, the second electrode 32 and the interconnect electrode 31 and the corresponding regions. While ensuring device performance, the thickness of the silicide layer on the upper surface of the area exposed by the bottom of the first opening, the second opening and the third opening can be selected according to the actual situation.

[0071] As an example, the device also includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the silicide layer and the upper surface of the self-aligned silicide barrier layer 26. The first contact hole penetrates the interlayer dielectric layer directly above the first contact area 2 and the fifth contact area 24 and exposes the silicide layer on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the second contact area 21 and the fourth contact area 23 and exposes the silicide layer on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the third contact area 22 and the sixth contact area 25 and exposes the silicide layer on its bottom surface. The first electrode 3 fills the first contact hole, the second electrode 32 fills the second contact hole, and the interconnect electrode 31 fills the third contact hole.

[0072] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer can be selected according to the actual situation; the opening shape and opening size of the first contact hole can be selected according to the actual situation; the opening shape and opening size of the second contact hole can be selected according to the actual situation; and the opening shape and opening size of the third contact hole can be selected according to the actual situation.

[0073] Specifically, the material of the interlayer dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Preferably, a silicon oxide layer is used as the interlayer dielectric layer.

[0074] Specifically, the material of the first electrode 3 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; the material of the second electrode 32 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials; and the material of the interconnect electrode 31 includes tantalum, tantalum nitride, titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum, or other suitable conductive materials.

[0075] It should be noted that the first electrode 3 is usually the anode of the device, and the second electrode 32 is the cathode of the device.

[0076] Specifically, when an ESD pulse is applied to the first electrode 3 of the device and the second electrode 32 is grounded, the first well region 12 and the second contact region 21 form diode D1, the fifth contact region 24 and the second well region 13 form diode D2, the first contact region 2, the first well region 12 and the second contact region 21 form NPN transistor T1, the second well region 13, the first well region 12 and the second contact region 21 form NPN transistor T2, and the fifth contact region 24, the second well region 13 and the fourth contact region 23 form PNP transistor T3. Diode D1 and diode D2 form a trigger path and first discharge the ESD pulse current. Simultaneously, as the ESD pulse current increases, when the voltage drop across the well resistor in the first well region 12 reaches the turn-on voltage of NPN transistors T1 and T2, NPN transistors T1 and T2 conduct. This simultaneously provides base current to PNP transistor T3, causing it to turn on. The conduction of PNP transistor T3 provides current to the collector of NPN transistor T2, resulting in positive feedback among the three transistors (e.g., ...). Figure 5 As shown), the SCR (Silicon Controlled Rectifier) ​​path conducts to discharge the ESD pulse current (e.g. Figure 6 As shown in the figure, multiple ESD pulse current discharge paths are formed for diodes, NPN transistors, PNP transistors, and SCRs, which enhances the device's resistance to failure.

[0077] Specifically, when an ESD pulse is applied to the second electrode 32 of the device and the first electrode 3 is grounded, the first contact region 2 and the first well region 12 form a diode D1, the fourth contact region 23 and the second well region 13 form a diode D2, the first contact region 2, the first well region 12 and the second contact region 21 form an NPN transistor T1, the second well region 13, the first well region 12 and the first contact region 2 form an NPN transistor T2, and the fifth contact region 24, the second well region 13 and the fourth contact region 23 form a PNP transistor T3. Transistor D1 and diode D2 form a trigger path and first discharge the ESD pulse current. Simultaneously, as the ESD pulse current increases, when the voltage drop across the well resistor in the first well region 12 reaches the turn-on voltage of NPN transistors T1 and T2, NPN transistors T1 and T2 conduct. This simultaneously provides base current to PNP transistor T3, causing it to turn on. The conduction of PNP transistor T3 provides current to the collector of NPN transistor T2, resulting in positive feedback among the three transistors (e.g., ...). Figure 7 As shown), the SCR path conducts to discharge the ESD pulse current (e.g. Figure 8 As shown in the figure, multiple ESD pulse current discharge paths are formed for diodes, NPN transistors, PNP transistors, and SCRs, which enhances the device's resistance to failure.

[0078] Specifically, in the arrangement direction of the first well region 12 and the second well region 13, the first contact region 2, the third contact region 22 and the second contact region 21 are arranged sequentially on the upper surface of the first well region 12, and the fourth contact region 23, the sixth contact region 25 and the fifth contact region 24 are arranged sequentially on the upper surface of the second well region 13. The first electrode 3 is electrically connected to the first contact region 2 and the fifth contact region 24 respectively, the second electrode 32 is electrically connected to the second contact region 21 and the fourth contact region 23 respectively, and the interconnect electrode 31 is electrically connected to the third contact region 22 and the sixth contact region 25 respectively. This allows the device to discharge ESD current in both directions, ensuring device performance while having a small area. There is no need for shallow trench isolation structures between the contact regions, resulting in low on-resistance, strong robustness, and only PN junction capacitance in the device, with low parasitic capacitance, making it suitable for low-voltage, high-speed applications.

[0079] The bidirectional diode-triggered silicon controlled rectifier (SCR) device of this embodiment improves the device structure by removing the shallow trench isolation structure 15 and using a self-aligned silicide barrier layer 26 to isolate each electrode, thus reducing the distance between the first electrode 3 and the second electrode 32 and consequently reducing the device size. Simultaneously, it allows the ESD pulse current to flow through the surfaces of the first well region 12 and the second well region 13, reducing the on-resistance of the bidirectional DTSCR and improving robustness. Furthermore, the device contains multiple ESD pulse current discharge paths, including diodes, PNP transistors, NPN transistors, and an SCR, enhancing its failure resistance. Moreover, the device contains only PN junction capacitance, resulting in low parasitic capacitance, making it suitable for low-voltage, high-speed applications.

[0080] Example 2

[0081] This embodiment also provides a method for fabricating a bidirectional diode-triggered silicon-controlled device, such as... Figure 9 The diagram shown is a process flow chart of the fabrication method of the bidirectional diode-triggered silicon controlled rectifier device, including the following steps:

[0082] S1: Provide a semiconductor layer comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region and a second conductivity type second well region located on the upper surface of the deep well region and adjacent to it;

[0083] S2: A first contact area of ​​the second conductivity type, a second contact area of ​​the second conductivity type, and a third contact area of ​​the first conductivity type are respectively formed on the upper surface of the first well area, and a fourth contact area of ​​the first conductivity type, a fifth contact area of ​​the first conductivity type, and a sixth contact area of ​​the second conductivity type are respectively formed on the upper surface of the second well area. The first contact area, the third contact area, the second contact area, the fourth contact area, the sixth contact area, and the fifth contact area are arranged in sequence at intervals along the arrangement direction of the first well area and the second well area.

[0084] S3: Form a first electrode, an interconnect electrode, and a second electrode. The first electrode is electrically connected to the first contact area and the fifth contact area, respectively. The interconnect electrode is electrically connected to the third contact area and the sixth contact area, respectively. The second electrode is electrically connected to the second contact area and the fourth contact area, respectively.

[0085] Please see Figures 10 to 12 Steps S1 and S2 are performed as follows: A semiconductor layer is provided, comprising a first conductivity type substrate 1 and a second conductivity type deep well region 11 stacked sequentially, and a first conductivity type first well region 12 and a second conductivity type second well region 13 located on the upper surface of the deep well region 11 and adjacent to it; a second conductivity type first contact region 2, a second conductivity type second contact region 21 and a first conductivity type third contact region 22 located on the upper surface of the first well region 12, and a first conductivity type fourth contact region 23, a first conductivity type fifth contact region 24 and a second conductivity type sixth contact region 25 located on the upper surface of the second well region 13, wherein the first contact region 2, the third contact region 22, the second contact region 21, the fourth contact region 23, the sixth contact region 25 and the fifth contact region 24 are arranged sequentially at intervals along the arrangement direction of the first well region 12 and the second well region 13.

[0086] Specifically, such as Figure 10 The diagram shows a cross-sectional view of the semiconductor layer. The substrate 1 in the semiconductor layer is made of silicon, silicon germanium, or other suitable semiconductor materials. Preferably, a silicon wafer is used as the substrate 1.

[0087] Specifically, the deep well region 11 in the semiconductor layer can be formed on the upper surface of the substrate 1 by epitaxial process or by ion implantation process.

[0088] Specifically, the method for forming the first well region 12 in the semiconductor layer includes ion implantation or other suitable methods; the method for forming the second well region 13 in the semiconductor layer includes ion implantation or other suitable methods.

[0089] Specifically, before forming the first contact area 2, the second contact area 21, the third contact area 22, the fourth contact area 23, the fifth contact area 24, and the sixth contact area 25, the method further includes forming a second conductive type isolation trap area 14 and an isolation structure 15. The isolation trap area 14 is located on the side of the first trap area 12 away from the second trap area 13 and its bottom surface is flush with the upper surface of the deep trap area 11. The isolation structure 15 is embedded in the upper surface layer of the edge area of ​​the area where the first trap area 12 and the second trap area 13 are located. The isolation structure 15 on the side away from the second trap area 13 is embedded in the upper surface layer of the boundary area between the isolation trap area 14 and the first trap area 12. The sidewalls of the isolation structure 15 embedded in the upper surface layer of the boundary area between the isolation trap area 14 and the first trap area 12 extend into the first trap area 12 and the isolation trap area 14, respectively.

[0090] Specifically, the methods for forming the isolation trap region 14 include ion implantation or other suitable methods.

[0091] Specifically, such as Figure 11 The diagram shows a cross-sectional view after the isolation structure 15 is formed. The formation of the isolation structure 15 includes the following steps: forming a shallow trench on the upper surface of the edge region of the first well region 12 and the second well region 13; forming a filling material layer that fills the shallow trench and covers the upper surface of the semiconductor layer; and removing the filling material layer covering the upper surface of the semiconductor layer to obtain an insulating filling layer that fills the shallow trench.

[0092] Specifically, methods for forming shallow trenches include dry etching, wet etching, or other suitable methods; methods for forming a filler material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; and methods for removing the filler material layer covering the upper surface of the semiconductor layer include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0093] Specifically, such as Figure 12 The diagram shown is a cross-sectional view after the formation of each contact region. The method for forming each contact region (first contact region 2, second contact region 21, third contact region 22, fourth contact region 23, fifth contact region 24, and sixth contact region 25) includes ion implantation or other suitable methods. In this embodiment, the first contact region 2, the second contact region 21, and the sixth contact region 25 are formed simultaneously using an ion implantation process. Then, the third contact region 22, the fourth contact region 23, and the fifth contact region 24 are formed using an ion implantation process. The fifth contact region 24 is adjacent to the sidewall of the isolation structure 15 at the edge of the second well region 13 near the side of the first well region 12, and the first contact region 2 is adjacent to the sidewall of the isolation structure 15 at the edge of the first well region 12 near the side of the second well region 13.

[0094] Please see Figure 13 Step S3 is executed: a first electrode 3, an interconnecting electrode 31 and a second electrode 32 are formed. The first electrode 3 is electrically connected to the first contact area 2 and the fifth contact area 24 respectively. The interconnecting electrode 31 is electrically connected to the third contact area 22 and the sixth contact area 25 respectively. The second electrode 32 is electrically connected to the second contact area 21 and the fourth contact area 23 respectively.

[0095] Specifically, before forming the first electrode 3, the interconnect electrode 31 and the second electrode 32, the step of forming a self-aligned silicide barrier layer 26 is also included.

[0096] Specifically, forming the self-aligned silicide barrier layer 26 includes the following steps: forming a self-aligned silicide barrier layer 26 covering the upper surface of the semiconductor layer; patterning the self-aligned silicide barrier layer 26 based on a photolithography process to obtain a self-aligned silicide barrier layer 26 having a first opening, a second opening, and a third opening, wherein the first opening penetrates the self-aligned silicide barrier layer 26 and exposes the upper surfaces of the first contact area 2 and the fifth contact area 24 on its bottom surface, the second opening penetrates the self-aligned silicide barrier layer 26 and exposes the upper surfaces of the second contact area 21 and the fourth contact area 23 on its bottom surface, and the third opening penetrates the self-aligned silicide barrier layer 26 and exposes the upper surfaces of the third contact area 22 and the sixth contact area 25 on its bottom surface.

[0097] Specifically, the method for forming the self-aligned silicide barrier layer 26 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Preferably, the self-aligned silicide barrier layer 26 is formed using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0098] Specifically, after forming the first opening, the second opening, and the third opening, and before forming the first electrode 3, the second electrode 32, and the interconnect electrode 31, the process also includes forming a silicide layer on the upper surface of each contact area exposed at the bottom of the first opening, the second opening, and the third opening.

[0099] Specifically, forming the silicide layer includes the following steps: forming a metal layer covering the self-aligned silicide barrier layer 26 and the exposed surfaces of each contact area; performing two rapid annealing processes on the structure after the metal layer is formed using the Salicide process, and removing the metal layer that has not reacted with the surface silicon in each contact area, so as to obtain the silicide layer located on the upper surface of each contact area.

[0100] Specifically, methods for forming a metal layer include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for removing unreacted metal layers include wet etching or other suitable methods.

[0101] Specifically, after the silicide layer is formed but before the first electrode 3, the second electrode 32, and the interconnect electrode 31 are formed, the steps of forming an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole are also included. The interlayer dielectric layer covers the silicide layer and the upper surface of the self-aligned silicide barrier layer 26. The first contact hole penetrates the interlayer dielectric layer directly above the first contact area 2 and the fifth contact area 24 and exposes the silicide layer on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the second contact area 21 and the fourth contact area 23 and exposes the silicide layer on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the third contact area 22 and the sixth contact area 25 and exposes the silicide layer on its bottom surface.

[0102] Specifically, the methods for forming the interlayer dielectric layer include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the first contact hole, the second contact hole, and the third contact hole include dry etching, wet etching, or other suitable methods.

[0103] Specifically, the first electrode 3 fills the first contact hole, the second electrode 32 fills the second contact hole, and the interconnecting electrode 31 fills the third contact hole.

[0104] Specifically, forming the first electrode 3, the second electrode 32, and the interconnect electrode 31 includes the following steps: forming an electrode material layer that fills the first contact hole, the second contact hole, and the third contact hole and covers the upper surface of the interlayer dielectric layer; removing the electrode material layer covering the upper surface of the interlayer dielectric layer to obtain the first electrode 3 filling the first contact hole, the second electrode 32 filling the second contact hole, and the interconnect electrode 31 filling the third contact hole.

[0105] Specifically, methods for forming electrode material layers include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; methods for removing electrode material layers from the surface of the interlayer dielectric layer include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0106] Specifically, by forming a self-aligned silicide barrier layer 26 to replace the shallow trench isolation structure 15 that isolates each contact area, the distance between the first electrode 3 and the second electrode 32 of the device is reduced, while the ESD pulse current flows through the surfaces of the first well region 12 and the second well region 13, thereby reducing the on-resistance of the device and improving its robustness.

[0107] The method for fabricating the bidirectional diode-triggered thyristor device in this embodiment replaces the shallow trench isolation structure 15 that isolates each contact area by forming a self-aligned silicide barrier layer 26. This reduces the distance between the first electrode 3 and the second electrode 32 of the device, while allowing the ESD pulse current to flow through the surfaces of the first well region 12 and the second well region 13, thereby reducing the on-resistance of the device and improving its robustness.

[0108] In summary, the bidirectional diode-triggered thyristor device and its fabrication method of the present invention improve the device structure by using a self-aligned silicide barrier layer to replace the shallow trench isolation structure that isolates each contact area, thus reducing the distance between the first and second electrodes of the device. Simultaneously, it allows the ESD pulse current to flow along the surfaces of the first and second well regions, reducing the on-resistance of the device and improving its robustness. Adjusting the arrangement of the contact areas creates multiple ESD pulse current discharge paths within the device, including diodes, PNP transistors, NPN transistors, and SCRs, enhancing the device's failure resistance. Furthermore, since the device contains only PN junction capacitance, parasitic capacitance is low, making it suitable for low-voltage, high-speed applications. Therefore, the present invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0109] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bidirectional diode triggered thyristor device, characterized by, include: The semiconductor layer includes a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and a first conductivity type first well region and a second conductivity type second well region located on the upper surface of the deep well region and adjacent to it. The first contact area and the second contact area of ​​the second conductivity type, which are arranged at intervals along the arrangement direction of the first well area and the second well area, are both located on the upper surface layer of the first well area; The third contact region of the first conductivity type is located on the upper surface of the first well region between the first contact region and the second contact region. The first conductive type fourth contact area and fifth contact area, which are arranged at intervals along the arrangement direction of the first well area and the second well area, are both located on the upper surface layer of the second well area. The sixth contact region of the second conductivity type is located on the upper surface of the second well region between the fourth contact region and the fifth contact region; The first electrode is electrically connected to the first contact area and the fifth contact area, respectively; Interconnecting electrodes are electrically connected to the third contact area and the sixth contact area, respectively; The second electrode is electrically connected to both the second contact area and the fourth contact area.

2. The bidirectional diode-triggered thyristor device according to claim 1, characterized in that: The device also includes a second conductive type isolation well region located on the side of the first well region away from the second well region. The bottom surface of the isolation well region is flush with the upper surface of the deep well region, and the isolation well region is spaced at a predetermined distance from the side of the first contact region away from the second well region.

3. The bidirectional diode triggered thyristor device of claim 2, wherein: The device also includes an isolation structure, which is embedded in the upper surface layer of the edge region where the first well region and the second well region are located. The sidewall of the isolation structure located at the edge of the first well region extends into the isolation well region on the side away from the first well region.

4. The bidirectional diode triggered thyristor device of claim 1, wherein: The device also includes a self-aligned silicide barrier layer, which is located on the upper surface of the first well region and the second well region.

5. The bidirectional diode triggered thyristor device of claim 4, wherein: The self-aligned silicide barrier layer is further provided with a first opening, a second opening and a third opening. The first opening penetrates the self-aligned silicide barrier layer directly above the first contact area and the fifth contact area. The second opening penetrates the self-aligned silicide barrier layer directly above the second contact area and the fourth contact area. The third opening penetrates the self-aligned silicide barrier layer directly above the third contact area and the sixth contact area.

6. The bidirectional diode triggered thyristor device of claim 5, wherein: A silicide layer is provided on the upper surface of the area exposed by the bottom surfaces of the first opening, the second opening, and the third opening. The first electrode is electrically connected to the first contact area and the fifth contact area through the silicide layer at the bottom of the first opening, respectively. The second electrode is electrically connected to the second contact area and the fourth contact area through the silicide layer at the bottom of the second opening, respectively. The interconnect electrode is electrically connected to the third contact area and the sixth contact area through the silicide layer at the bottom of the third opening, respectively.

7. The bidirectional diode triggered thyristor device of claim 6, wherein: The device also includes an interlayer dielectric layer, a first contact hole, a second contact hole, and a third contact hole. The interlayer dielectric layer covers the upper surface of the silicide layer and the self-aligned silicide barrier layer. The first contact hole penetrates the interlayer dielectric layer directly above the first contact area and the fifth contact area, and exposes the silicide layer on its bottom surface. The second contact hole penetrates the interlayer dielectric layer directly above the second contact area and the fourth contact area, and exposes the silicide layer on its bottom surface. The third contact hole penetrates the interlayer dielectric layer directly above the third contact area and the sixth contact area, and exposes the silicide layer on its bottom surface. The first electrode fills the first contact hole, the second electrode fills the second contact hole, and the interconnect electrode fills the third contact hole.

8. The bidirectional diode triggered thyristor device of claim 1, wherein: The contact type between the first contact area and the fifth contact area and the first electrode is ohmic contact; Alternatively, the contact type between the second contact area and the fourth contact area and the second electrode can both be ohmic contact.

9. The bidirectional diode-triggered thyristor device according to claim 1, characterized in that: The doping concentration of the third contact region is greater than that of the first well region, and the contact type between the third contact region and the interconnect electrode is an ohmic contact. Alternatively, the doping concentration of the sixth contact region is greater than the doping concentration of the second well region, and the contact type between the sixth contact region and the interconnect electrode is an ohmic contact.

10. A method of manufacturing a bidirectional diode triggered thyristor device, characterized by, Includes the following steps: A semiconductor layer is provided, comprising a first conductivity type substrate and a second conductivity type deep well region stacked sequentially, and the first conductivity type first well region and the second conductivity type second well region located on the upper surface of the deep well region and adjacent to it; A first contact area of ​​a second conductivity type, a second contact area of ​​a second conductivity type, and a third contact area of ​​a first conductivity type are respectively formed on the upper surface of the first well region, and a fourth contact area of ​​a first conductivity type, a fifth contact area of ​​a first conductivity type, and a sixth contact area of ​​a second conductivity type are respectively formed on the upper surface of the second well region. Along the arrangement direction of the first well region and the second well region, the first contact area, the third contact area, the second contact area, the fourth contact area, the sixth contact area, and the fifth contact area are arranged in sequence at intervals. A first electrode, an interconnect electrode, and a second electrode are formed. The first electrode is electrically connected to the first contact area and the fifth contact area, respectively. The interconnect electrode is electrically connected to the third contact area and the sixth contact area, respectively. The second electrode is electrically connected to the second contact area and the fourth contact area, respectively.

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