Single photon avalanche diode device and method of manufacturing the same, photosensor

Abstract

This disclosure provides a SPAD device and its manufacturing method, as well as a photoelectric sensor, relating to the field of photoelectric detection technology. The SPAD device includes a semiconductor layer on a substrate and a PN junction located in the semiconductor layer, comprising a first semiconductor region and a second semiconductor region with different doping types, the first semiconductor region being located above the second semiconductor region; a first well region located below the PN junction, the first well region having the same doping type as the first semiconductor region but a different doping type than the semiconductor layer, the orthogonal projection of the first well region on the substrate at least partially overlapping the orthogonal projection of the PN junction on the substrate; and a second well region located on the side of the PN junction, the second well region having the same doping type as the second semiconductor region, the doping concentration of the second well region being greater than the doping concentration of the semiconductor layer, the upper surface of the second well region being not lower than the lower surface of the first well region, and the lower surface of the second well region being not higher than the upper surface of the first well region.

Description

Technical Field

[0001] This disclosure relates to the field of photoelectric detection technology, and in particular to a single-photon avalanche diode (SPAD) device and its manufacturing method, as well as a photoelectric sensor. Background Technology

[0002] SPAD devices are high-sensitivity photodetectors that operate in Geiger mode (i.e., reverse bias voltage is higher than breakdown voltage) and are widely used in cutting-edge fields such as lidar, 3D sensing, and medical imaging.

[0003] Photon detection efficiency (PDE), dark count rate (DCR), and timing jitter are the core performance indicators of SPAD devices. Improving PDE and reducing DCR and timing jitter are beneficial to improving the performance of SPAD devices. Summary of the Invention

[0004] According to one aspect of the present disclosure, a SPAD device is provided, comprising a semiconductor layer on a substrate and a PN junction located in the semiconductor layer, including a first semiconductor region and a second semiconductor region with different doping types, the first semiconductor region being located above the second semiconductor region; a first well region located below the PN junction, the first well region having the same doping type as the first semiconductor region and a different doping type than the semiconductor layer, the orthographic projection of the first well region on the substrate at least partially overlapping the orthographic projection of the PN junction on the substrate; and a second well region located on the side of the PN junction, the second well region having the same doping type as the second semiconductor region, the doping concentration of the second well region being greater than the doping concentration of the semiconductor layer, the upper surface of the second well region being not lower than the lower surface of the first well region, and the lower surface of the second well region being not higher than the upper surface of the first well region.

[0005] In some embodiments, the second well region includes a plurality of first regions, wherein at least two of the plurality of first regions are symmetrically distributed on the substrate with respect to the orthogonal projection of the PN junction on the substrate.

[0006] In some embodiments, the orthogonal projection of the second well region onto the substrate is symmetrically distributed with respect to the orthogonal projection of the PN junction onto the substrate.

[0007] In some embodiments, the second well region is an annular region formed by connecting the plurality of first regions.

[0008] In some embodiments, the SPAD device satisfies at least one of a first condition, a second condition, and a third condition. The first condition is that the side of the second well region near the PN junction is covered by a third well region located in the semiconductor layer, the third well region serving as a protective ring for the PN junction. The second condition is that the doping concentration of the second semiconductor region is different from that of the semiconductor layer, and the upper surface of the second well region is flush with the lower surface of the second semiconductor region. The third condition is that the second well region is in contact with a fourth well region located in the semiconductor layer, the fourth well region being located on the side of the second well region away from the PN junction, and the fourth well region having the same doping type as the second semiconductor region.

[0009] In some embodiments, the SPAD device further includes a fifth well region located in the semiconductor layer, the fifth well region being located on the side of the PN junction and above the second well region, the fifth well region being spaced apart from the second well region, and the fifth well region having the same doping type as the second semiconductor region.

[0010] In some embodiments, the doping concentration of the fifth well region is less than that of the second well region.

[0011] In some embodiments, the SPAD device further includes: a fourth well region located in the semiconductor layer, the fourth well region being located on the side of the second well region and the fifth well region away from the PN junction, and the fourth well region having the same doping type as the second semiconductor region, wherein the second well region is in contact with the fourth well region, and the fifth well region is in contact with the fourth well region.

[0012] In some embodiments, the SPAD device further includes: a fourth well region located in the semiconductor layer, the fourth well region being located on the side of the second well region and the fifth well region away from the PN junction, and the fourth well region having the same doping type as the second semiconductor region, wherein at least a portion of the second well region is spaced apart from the fourth well region, and the orthogonal projection of the region between the at least a portion of the second well region and the fourth well region on the substrate at least partially overlaps with the orthogonal projection of the fifth well region on the substrate.

[0013] In some embodiments, the fifth well region includes a plurality of second regions, at least two of which have orthographic projections onto the substrate symmetrically distributed with respect to the orthographic projection of the PN junction onto the substrate.

[0014] In some embodiments, the orthogonal projection of the fifth well region onto the substrate is symmetrically distributed with respect to the orthogonal projection of the PN junction onto the substrate.

[0015] In some embodiments, the fifth well region is an annular region formed by connecting the plurality of second regions.

[0016] In some embodiments, when a reverse voltage is applied to the SPAD device, the potential changes monotonically in the direction from the first well region through the second semiconductor region back to the first semiconductor region.

[0017] In some embodiments, the second semiconductor region has a different doping concentration than the semiconductor layer, and the first well region is in contact with the second semiconductor region.

[0018] According to another aspect of the present disclosure, a method for manufacturing a SPAD device is provided, comprising: forming a first well region in a semiconductor layer on a substrate, the first well region having a different doping type than the semiconductor layer; after forming the first well region, forming a PN junction in the semiconductor layer, the PN junction including a first semiconductor region and a second semiconductor region having different doping types, the first semiconductor region being located above the second semiconductor region, the PN junction being located above the first well region, the first semiconductor region having the same doping type as the first well region, and the orthogonal projection of the PN junction on the substrate at least partially overlapping the orthogonal projection of the first well region on the substrate; and forming a second well region in the semiconductor layer, the second well region being located on the side of the PN junction, the second well region having the same doping type as the second semiconductor region, the doping concentration of the second well region being greater than the doping concentration of the semiconductor layer, the upper surface of the second well region being not lower than the lower surface of the first well region, and the lower surface of the second well region being not higher than the upper surface of the first well region.

[0019] According to another aspect of the present disclosure, a photoelectric sensor is provided, comprising: the SPAD device in any of the above embodiments. Attached Figure Description

[0020] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0021] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0022] Figure 1 This is a cross-sectional view of a SPAD device according to some embodiments of the present disclosure.

[0023] Figure 2 This is a diagram showing the relative positions of the second well region and the PN junction according to some embodiments of this disclosure.

[0024] Figure 3 This is a diagram showing the relative positions of the second well region and the PN junction according to other embodiments of this disclosure.

[0025] Figure 4 This is a diagram showing the relative positions of the second and fourth well regions according to some embodiments of the present disclosure.

[0026] Figure 5 This is a diagram showing the relative positions of the second and fourth well regions according to other embodiments of this disclosure.

[0027] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation

[0028] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0029] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0030] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0031] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0032] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0033] The inventors noted that the performance of the SPAD devices proposed in the related technologies is limited.

[0034] Analysis revealed that in SPAD devices, the depletion region is relatively small, while the area outside the depletion region occupies the majority of the device's area, and the electric field strength in this area is relatively low. Therefore, outside the depletion region, photogenerated carriers are difficult to effectively collect into the multiplication region (i.e., the area with the strongest electric field in the depletion region) to trigger avalanche multiplication, resulting in a low PDE (Power Depletion Efficiency) of the SPAD device. Furthermore, even if photogenerated carriers eventually reach the multiplication region, those that were initially located far from it take a longer time to reach it, leading to significant differences in the time taken for different photogenerated carriers to trigger avalanche multiplication, resulting in substantial time jitter in the SPAD device.

[0035] In view of this, the present disclosure proposes the following technical solutions to improve the performance of SPAD devices.

[0036] Figure 1 This is a cross-sectional view of a SPAD device according to some embodiments of the present disclosure.

[0037] like Figure 1 As shown, the SPAD device includes a semiconductor layer 110 on a substrate 100, and a PN junction 120, a first well region 121, and a second well region 122 located in the semiconductor layer 110. For example, the semiconductor layer 110 can be an epitaxial layer, i.e., formed by an epitaxial process. The material of the semiconductor layer 110 can be Si, and the doping concentration of the semiconductor layer 110 can be lightly doped, for example, the doping concentration of the semiconductor layer 110 is equal to or similar to the doping concentration of the substrate 100.

[0038] The PN junction 120 includes a first semiconductor region 120a and a second semiconductor region 120b with different doping types, wherein the first semiconductor region 120a is located above the second semiconductor region 120b. For example, the first semiconductor region 120a is n-type doped, and the second semiconductor region 120b is p-type doped. Alternatively, the first semiconductor region 120a may be p-type doped, and the second semiconductor region 120b may be n-type doped. The PN junction 120 has a multiplication region for generating avalanche current, located near the interface between the first semiconductor region 120a and the second semiconductor region 120b. The doping type of the second semiconductor region 120b of the PN junction 120 is the same as that of the semiconductor layer 110.

[0039] For example, when the doping type of the first semiconductor region 120a is n-type doping, the SPAD device is an n / p-type device, and the photogenerated carriers that trigger avalanche multiplication are electrons; when the doping type of the first semiconductor region 120a is p-type doping, the SPAD device is a p / n-type device, and the photogenerated carriers that trigger avalanche multiplication are holes.

[0040] In some embodiments, the first semiconductor region 120a is heavily doped, and the second semiconductor region 120b is lightly or moderately doped. For example, when the first semiconductor region 120a is heavily doped, the SPAD device is an n+ / p type device or a p+ / n type device.

[0041] The first well region 121 is located below the PN junction 120. The first well region 121 has the same doping type as the first semiconductor region 120a, but a different doping type than the semiconductor layer 110, and the orthogonal projection of the first well region 121 on the substrate 100 at least partially overlaps with the orthogonal projection of the PN junction 120 on the substrate 100. The first well region can be a deep well, for example, a deep N-well.

[0042] The specific location of the first well region 121 is not limited when the orthographic projections of the first well region 121 and the PN junction 120 on the substrate 100 at least partially overlap. For example, the width of the first well region 121 may be greater than, less than or equal to the width of the PN junction 120, and the first well region 121 may be offset in the horizontal plane relative to the PN junction 120.

[0043] In some embodiments, the second semiconductor region 120b has the same doping concentration as the semiconductor layer 110, meaning the second semiconductor region 120b is a part of the semiconductor layer 110. For example, a first well region 121 and a first semiconductor region 120a located above and spaced apart from the first well region 121 are formed in the semiconductor layer 110 through a doping process. In this case, the portion of the semiconductor layer 110 located between the first semiconductor region 120a and the first well region 121 is the second semiconductor region 120b.

[0044] In other embodiments, the doping concentration of the second semiconductor region 120b is different from that of the semiconductor layer 110. For example, the second semiconductor region 120b is formed in the semiconductor layer 110 by a doping process, and the doping concentration of the second semiconductor region 120b is greater than that of the semiconductor layer 110. In this case, the first well region 121 may or may not be in contact with the second semiconductor region 120b.

[0045] The second well region 122 is located on the side of the PN junction 120, and the second well region 122 has the same doping type as the second semiconductor region 120b. For example, the second well region 122 is also located on the side of the first well region 121, that is, considering the PN junction 120 and the first well region 121 as a whole, the second well region 122 is located on the side of both the PN junction 120 and the first well region 121.

[0046] Furthermore, the upper surface of the second well region 122 is not lower than the lower surface of the first well region 121, and the lower surface of the second well region 122 is not higher than the upper surface of the first well region 121. In other words, in a direction perpendicular to the substrate 100 (which may be referred to as the vertical direction), the area occupied by the second well region 122 at least partially overlaps with the area occupied by the first well region 121.

[0047] The second well region 122 can be formed in the semiconductor layer 110 by a doping process, and the doping concentration of the second well region 122 is greater than the doping concentration of the semiconductor layer 110.

[0048] In the aforementioned SPAD device, the first well region 121 has a different doping type than the semiconductor layer 110, thereby forming a depletion region with the surrounding semiconductor layer 110, thus expanding the range of the depletion region of the SPAD device. Figure 1 (The boundary of the depletion region is shown by a dashed line in the image), which increases the electric field intensity in the region below the PN junction 120. In this case, photogenerated carriers that were originally generated far from the multiplication region and needed to diffuse into the depletion region or could not enter the depletion region within a finite time interval can be generated directly in the depletion region. Then, under the influence of the electric field in the depletion region, they drift into the multiplication region. The difference in the time taken for different photogenerated carriers to trigger avalanche multiplication is reduced, which improves the PDE of the SPAD device and reduces the timing jitter of the SPAD device.

[0049] Furthermore, the second well region 122 can appropriately compress the boundary of the depletion region, thereby controlling the shape of the depletion region. For example... Figure 1 As shown, the depletion region indicated by the dashed line shrinks near the second well region 122. For example, in a certain cross section of a SPAD device, when there are second well regions 122 on both sides of the PN junction 120, the shape of the depletion region is gourd-shaped.

[0050] When the second well region 122 is absent, the first well region 121 can expand the depletion region. However, because the multiplication region (i.e., a small area near the interface between the first semiconductor region 120a and the second semiconductor region 120b) is relatively small, the width of the depletion region near the multiplication region is much larger than the width of the multiplication region. In this case, some photogenerated carriers will bypass the multiplication region from the side without effectively triggering avalanche multiplication. Therefore, the SPAD device loses a portion of its PDE.

[0051] When the second well region 122 is present, the depletion region shrinks appropriately. The shrunken depletion region has a converging effect on photogenerated carriers, promoting their movement into the multiplication region to trigger avalanche multiplication. The probability of photogenerated carriers bypassing the multiplication region from the side is reduced. Therefore, the PDE of the SPAD device is further improved.

[0052] Furthermore, a dielectric layer (e.g., SiO2) exists above the semiconductor layer 110. The surface of the semiconductor layer 110 (i.e., the interface between the semiconductor layer 110 and the dielectric layer) often contains a large number of defect charges. These defect charges have a certain probability of moving into the depletion region, thereby causing avalanche currents due to non-light-induced reasons, resulting in a high DCR of the SPAD device. The second well region 122 can block the defect charges above from moving into the depletion region, thus reducing the DCR of the SPAD device.

[0053] Taking an n / p type SPAD device as an example, the doping concentration of the p-type doped second well region 122 is higher than that of the surrounding semiconductor layer 110, therefore the potential of the second well region 122 is lower. For electrons, the second well region 122 acts as a potential barrier, preventing electrons from moving into the depletion region.

[0054] In summary, when a SPAD device has both a first well region 121 and a second well region 122, it can not only improve the PDE of the SPAD device and reduce the timing jitter of the SPAD device, but also reduce the DCR of the SPAD device, thereby improving the overall performance of the SPAD device.

[0055] In some embodiments, such as Figure 1 As shown, the SPAD device also includes a third well region 123 located in the semiconductor layer 110, where the third well region 123 serves as a protective ring for the PN junction 120. The third well region 123 can contact and surround the first semiconductor region 120a. For example, the third well region 123 has the same doping type as the first semiconductor region 120a, and the doping concentration of the third well region 123 is lower than that of the first semiconductor region 120a.

[0056] In some embodiments, such as Figure 1 As shown, the SPAD device also includes a fourth well region 124 located in the semiconductor layer 110. The fourth well region 124 is located on the side of the second well region 122 away from the PN junction 120, and the fourth well region 124 has the same doping type as the second semiconductor region 120b. The fourth well region 124 can be used to form an ohmic contact with the electrodes of the SPAD device to reduce the contact resistance of the SPAD device. As some implementations, the fourth well region 124 can be a ring-shaped region. Alternatively, the fourth well region 124 can be a deep well.

[0057] For example, the doping concentration of the fourth well region 124 gradually decreases from top to bottom, and the doping concentration of the second well region 122 lies between the doping concentration of the uppermost part of the fourth well region 124 and the doping concentration of the lowermost part of the fourth well region 124. For example, the doping concentration of the uppermost part of the fourth well region 124 can be heavily doped, and the doping concentration of the lowermost part of the fourth well region 124 can be lightly doped. The doping concentration of the second well region 122 can be greater than, equal to, or less than the doping concentration of the portion of the fourth well region 124 at the same depth as the second well region 122.

[0058] The fourth well region 124 may include a first electrode contact region 126 that is in direct contact with the electrodes of the SPAD device, and the doping concentration of the first electrode contact region 126 is greater than the doping concentration of other regions in the fourth well region 124.

[0059] When the SPAD device includes a third well region 123, the above-mentioned SPAD device also has the following advantages.

[0060] In related technologies, to improve the PDE of SPAD devices, the area of ​​the PN junction 120 is increased (i.e., the area of ​​the multiplication region is increased), thereby increasing the collection range of photogenerated carriers. However, as... Figure 1 As shown, when the area of ​​the PN junction 120 is increased, the distance between the guard ring (i.e., the third well region 123) and the first electrode contact region 126 decreases. Since the doping concentration of the first electrode contact region 126 is high, usually heavily doped, when the guard ring and the first electrode contact region 126 are too close, a strong electric field will be formed between them, which may cause the charge carriers to gain a large amount of energy between the guard ring and the first electrode contact region 126, triggering avalanche multiplication (this phenomenon is called edge breakdown).

[0061] In the aforementioned SPAD device, due to the presence of a first well region 121 and a second well region 122, the SPAD device can achieve a high PDE even with a relatively small area of ​​the PN junction 120. Therefore, the aforementioned SPAD device can effectively reduce the risk of edge breakdown between the guard ring and the first electrode contact area 126.

[0062] In some embodiments, such as Figure 1 As shown, the SPAD device also includes a second electrode contact region 127 located in the semiconductor layer 110. The second electrode contact region 127 has the same doping type as the first semiconductor region 120a, and the second electrode contact region 127 can directly contact the electrodes of the SPAD device to form an ohmic contact.

[0063] The doping concentration of the second electrode contact region 127 can be greater than the doping concentration of the first semiconductor region 120a. For example, the doping concentration of the second electrode contact region 127 is a higher doping concentration than that of the first semiconductor region 120a.

[0064] When the SPAD device is an n / p type device, the first electrode contact area 126 is in contact with the anode, and the second electrode contact area 127 is in contact with the cathode. When the SPAD device is a p / n type device, the first electrode contact area 126 is in contact with the cathode, and the second electrode contact area 127 is in contact with the anode.

[0065] In some embodiments, such as Figure 1 As shown, the SPAD device may also include an isolation region 130 (e.g., other components surrounding the SPAD device) to isolate the SPAD device from other SPAD devices. For example, the material of the isolation region 130 may include SiO2. As some implementations, the isolation region 130 may be referred to as a deep trench isolation (DTI) structure.

[0066] The second well region 122 may include one or more regions, and the location of the second well region 122 will be described below.

[0067] Figure 2 This is a diagram showing the relative positions of the second well region 122 and the PN junction 120 according to some embodiments of this disclosure. Figure 2 The relative positional relationship between the second well region 122 and the PN junction 120 is represented by the orthogonal projection of the second well region 122 and the PN junction 120 onto the substrate 100.

[0068] In some embodiments, the second well region 122 includes a plurality of regions (represented by the first region).

[0069] Figure 2 An exemplary illustration shows that the second well region 122 includes four first regions 1221, 1222, 1223, and 1224. Two adjacent first regions may be in contact with each other or spaced apart from each other.

[0070] The second well region 122 can be formed by performing a doping process on multiple first regions. In some implementations, the doping process can be performed sequentially on each first region to form the second well region 122. In other implementations, the doping process can be performed on multiple first regions simultaneously to form the second well region 122.

[0071] As one implementation, in the plurality of first regions of the second well region 122, at least two of the first regions have their orthographic projections on the substrate 100 symmetrically distributed with respect to the orthographic projection of the PN junction 120 on the substrate 100. Here, symmetrical distribution means that they are centrally symmetrical with respect to the orthographic projection of the PN junction 120. Figure 2For example, the orthographic projections of the first region 1221 and the first region 1223 on the substrate 100 are symmetrically distributed with respect to the orthographic projection of the PN junction 120 on the substrate 100, and the orthographic projections of the first region 1222 and the first region 1224 on the substrate 100 are symmetrically distributed with respect to the orthographic projection of the PN junction 120 on the substrate 100.

[0072] With the two first regions symmetrically distributed on the substrate 100 with respect to the PN junction 120 on the substrate 100, the performance of the SPAD device is improved and more stable in the space including the two first regions and the PN junction 120.

[0073] For example, in the aforementioned space, the second well region 122 can facilitate the movement of photogenerated carriers generated on either side of the PN junction 120 into the multiplication region to trigger avalanche multiplication. For example, in the aforementioned space, the second well region 122 can prevent defect charges on either side of the surface of the semiconductor layer 110 from moving into the depletion region, thus avoiding triggering avalanche multiplication for non-light-induced reasons.

[0074] For example, when a SPAD device is rotated 180° in the horizontal plane, the positions of the two first regions symmetrically distributed relative to the PN junction 120 are interchanged, and the performance of the SPAD device changes little.

[0075] In some implementations, the orthographic projection of the second well region 122 onto the substrate 100 is symmetrically distributed with respect to the orthographic projection of the PN junction 120 onto the substrate 100. Figure 2 For example, the orthographic projection of the second well region 122, which consists of four first regions 1221, 1222, 1223 and 1224, is centrally symmetrical with respect to the orthographic projection of the PN junction 120.

[0076] In this configuration, within the multiple first regions of the second well region 122, each first region has a corresponding second first region, and each first region and its corresponding first region are symmetrically distributed relative to the PN junction 120. When the SPAD device is rotated 180° in the horizontal plane, the positions of each first region and its corresponding first region are interchanged, while the overall positional distribution of the second well region 122 remains unchanged. Therefore, the performance stability of the SPAD device is further improved.

[0077] In some embodiments, the second well region 122 is an annular region, meaning that the second well region 122 completely surrounds the PN junction 120. In this case, the second well region 122 can promote the movement of photogenerated carriers into the multiplication region in the space on each side of the PN junction 120, and prevent defect charges on the surface of the semiconductor layer 110 from moving into the depletion region. Therefore, the performance of the SPAD device is further improved.

[0078] In some implementations, when the second well region 122 includes multiple first regions, the second well region 122 is a ring-shaped region formed by connecting the multiple first regions. For example, when performing a doping process on multiple first regions to form the second well region 122, the size of the first regions or the number of first regions can be increased, such that each first region overlaps with an adjacent first region, thereby connecting the multiple first regions to form a ring-shaped region.

[0079] Figure 3 An exemplary illustration shows that the second well region 122 includes eight first regions 1221, 1222, 1223, 1224, 1225, 1226, 1227 and 1228. Each of these eight first regions overlaps with two adjacent first regions (for example, first region 1221 overlaps with first region 1225 and first region 1228 respectively), so that these eight first regions are connected to form a ring-shaped region.

[0080] In some embodiments, the orthographic projection of the second well region 122 onto the substrate 100 is symmetrically distributed with respect to the orthographic projection of the PN junction 120 onto the substrate 100, and the second well region 122 is an annular region. In this case, the performance of the SPAD device is further improved.

[0081] The location of the second well region 122 in the SPAD device will now be described with reference to some embodiments.

[0082] In some embodiments, the SPAD device satisfies at least one of the first condition, the second condition, and the third condition.

[0083] like Figure 1 As shown, the first condition is that the side of the second well region 122 near the PN junction 120 is covered by the third well region 123 (i.e., the protective ring of the PN junction 120), meaning that the orthographic projection of the side of the second well region 122 near the PN junction 120 onto the substrate 100 is located inside the orthographic projection of the third well region 123 onto the substrate 100. This ensures that the second well region 122 and the PN junction 120 are not too far apart, guaranteeing that the depletion region has sufficient contraction under the influence of the second well region 122, preventing photogenerated carriers from bypassing the multiplication region from its sides.

[0084] The second condition is that the doping concentration of the second semiconductor region 120b is different from that of the semiconductor layer 110 (for example, the second semiconductor region 120b is formed in the semiconductor layer 110 by a doping process), and the upper surface of the second well region 122 is flush with the lower surface of the second semiconductor region 120b.

[0085] If the upper surface of the second well region 122 is too high, the second well region 122 will be too close to or even in contact with the third well region 123, which serves as a protective ring. A large electric field will be formed between the second well region 122 and the third well region 123 or near the contact surface between the second well region 122 and the third well region 123, which can easily cause edge breakdown.

[0086] If the upper surface of the second well region 122 is too low, the location where the depletion region shrinks will shift to a position far from the multiplication region of the PN junction 120. In this case, the depletion region still has a large width near the multiplication region. After photogenerated carriers pass through the region with the smallest depletion region width (which is far from the multiplication region), they may still bypass the multiplication region from the side when they reach the vicinity of the multiplication region, thus failing to effectively trigger avalanche multiplication.

[0087] The lower boundary of the multiplication region is usually close to the lower surface of the second semiconductor region 120b. When the doping concentration of the first semiconductor region 120a is much greater than that of the second semiconductor region 120b, the second semiconductor region 120b can be completely depleted. At this time, the lower boundary of the multiplication region basically coincides with the lower surface of the second semiconductor region 120b.

[0088] Therefore, under the second condition, setting the upper surface of the second well region 122 to be flush with the lower surface of the second semiconductor region 120b can avoid the formation of a large electric field between the second well region 122 and the third well region 123 or near the contact surface between the second well region 122 and the third well region 123, and can also make the depletion region have the greatest degree of contraction in the lower region closer to the multiplication region. The effect of the depletion region in gathering photogenerated carriers into the multiplication region is further enhanced, thereby improving the PDE of the SPAD device.

[0089] like Figure 1 As shown, the third condition is: the second well region 122 is in contact with the fourth well region 124.

[0090] The second well region 122 is in at least partial contact with the fourth well region 124, and the second well region 122 may contact the fourth well region 124 in different ways.

[0091] When the second well region 122 comprises a plurality of first regions spaced apart from each other, at least one of the plurality of first regions is in contact with the fourth well region 124. For example, each first region is in contact with the fourth well region 124. Or, for example, at least one first region is in contact with the fourth well region 124, and at least one first region is spaced apart from the fourth well region 124.

[0092] When the second well region 122 is an annular region, the outer surface of the second well region 122 (i.e. the side away from the PN junction 120) can be in complete contact with the inner surface of the fourth well region 124 (i.e. the side near the PN junction 120); or, the outer surface of the second well region 122 can be in partial contact with the inner surface of the fourth well region 124, that is, a part of the outer surface of the second well region 122 is in contact with the inner surface of the fourth well region 124, and another part of the outer surface of the second well region 122 is spaced apart from the inner surface of the fourth well region 124.

[0093] Figure 4 This is a diagram showing the relative positions of the second well region 122 and the fourth well region 124 according to some embodiments of the present disclosure.

[0094] like Figure 4 As shown in (a), the outer surface of the second well region 122 is in complete contact with the inner surface of the fourth well region 124. Figure 4 As shown in (b), a portion of the outer surface of the second well region 122 on the right side is spaced apart from the inner surface of the fourth well region 124, while the remaining portion of the outer surface of the second well region 122 is in contact with the inner surface of the fourth well region 124.

[0095] At the location where the second well region 122 and the fourth well region 124 are spaced apart, there is a gap between the second well region 122 and the fourth well region 124, which is filled with a semiconductor layer 110. Therefore, defect charges on the surface of the semiconductor layer 110 may pass through the gap between the second well region 122 and the fourth well region 124 and reach the depletion region below, thereby triggering avalanche multiplication for non-light-induced reasons.

[0096] Under the third condition, the second well region 122 and the fourth well region 124 are at least partially in contact. Therefore, at the point where the second well region 122 and the fourth well region 124 are in contact, there is no gap between them, and the second well region 122 can better prevent defect charges on the surface of the semiconductor layer 110 from moving to the underlying depletion region. For example, if the outer surface of the second well region 122 is in complete contact with the inner surface of the fourth well region 124, then there is no gap between them, and the second well region 122 further prevents defect charges from moving to the underlying depletion region, thereby significantly reducing the DCR of the SPAD device.

[0097] As some implementations, the SPAD device at least satisfies the first condition, namely, the side of the second well region 122 near the PN junction 120 is covered by the third well region 123.

[0098] As some implementations, the SPAD device, in addition to satisfying the first condition, also satisfies at least one of the second and third conditions, namely, the doping concentration of the second semiconductor region 120b is different from that of the semiconductor layer 110 and the upper surface of the second well region 122 is flush with the lower surface of the second semiconductor region 120b, and / or the second well region 122 is in contact with the fourth well region 124.

[0099] As some implementations, SPAD devices satisfy the first, second, and third conditions.

[0100] In some embodiments, such as Figure 1 As shown, the SPAD device also includes a fifth well region 125 located in the semiconductor layer 110.

[0101] The fifth well region 125 is located on the side of the PN junction 120 and above the second well region 122. The fifth well region 125 is spaced apart from the second well region 122, and the fifth well region 125 has the same doping type as the second semiconductor region 120b. For example, the upper surface of the fifth well region 125 is flush with the upper surface of the semiconductor layer 110, that is, the fifth well region 125 extends downward from the upper surface of the semiconductor layer 110.

[0102] Similar to the second well region 122, the fifth well region 125 can also prevent defect charges on the surface of the semiconductor layer 110 from moving downward to the depletion region, thereby further reducing the DCR of the SPAD device.

[0103] In some implementations, the doping concentration of the fifth well region 125 is lower than that of the second well region 122. Thus, for charge carriers, the second well region 122 acts as a higher barrier than the fifth well region 125.

[0104] For example, when the SPAD device is an n / p type device, the second well region 122 has a lower potential than the fifth well region 125 due to its higher doping concentration. Therefore, the second well region 122 can block electrons that cross the surface of the semiconductor layer 110 of the fifth well region 125 from entering the depletion region.

[0105] For example, when the SPAD device is a p / n type device, the second well region 122 has a higher potential than the fifth well region 125 due to its higher doping concentration. Therefore, the second well region 122 can block holes from entering the depletion region by crossing the surface of the semiconductor layer 110 of the fifth well region 125.

[0106] Similar to the second well region 122, the fifth well region 125 may also include one or more regions.

[0107] As some implementations, the fifth well region 125 includes multiple regions (referred to as second regions), and two adjacent second regions may be in contact with each other or spaced apart from each other. For example, in the multiple second regions of the fifth well region 125, at least two second regions have their orthogonal projections on the substrate 100 symmetrically distributed with respect to the orthogonal projection of the PN junction 120 on the substrate 100.

[0108] In some implementations, the orthographic projection of the fifth well region 125 onto the substrate 100 is symmetrically distributed with respect to the orthographic projection of the PN junction 120 onto the substrate 100.

[0109] In some implementations, the fifth well region 125 is an annular region, for example, the fifth well region 125 is an annular region formed by connecting multiple second regions.

[0110] In the case where the SPAD device also includes a fifth well region 125, the fourth well region 124 is located on the side of the second well region 122 and the fifth well region 125 away from the PN junction 120.

[0111] For example, the fifth well region 125 includes a plurality of second regions spaced apart from each other, and the second well region 122 includes a plurality of first regions spaced apart from each other. In this case, the orthographic projection of the fifth well region 125 on the substrate 100 may at least partially overlap (e.g., coincide) or not overlap with the orthographic projection of the second well region 122 on the substrate 100.

[0112] In some embodiments, the second well region 122 is in contact with the fourth well region 124, and the fifth well region 125 is in contact with the fourth well region 124. This can further reduce the DCR of the SPAD device.

[0113] The specific form of contact between the fifth well region 125 and the fourth well region 124 can be referred to the description of the specific form of contact between the second well region 122 and the fourth well region 124 above, and will not be repeated here. It should be understood that the form of contact between the fifth well region 125 and the fourth well region 124 may be the same as or different from the form of contact between the second well region 122 and the fourth well region 124.

[0114] In other embodiments, at least a portion of the second well region 122 is spaced apart from the fourth well region 124.

[0115] When the second well region 122 comprises a plurality of first regions spaced apart from each other, at least one of the plurality of first regions is spaced apart from the fourth well region 124. For example, each first region is spaced apart from the fourth well region 124.

[0116] When the second well region 122 is an annular region, the outer surface of the second well region 122 (i.e. the side away from the PN junction 120) can be completely separated from the inner surface of the fourth well region 124 (i.e. the side near the PN junction 120); or, the outer surface of the second well region 122 can be partially separated from the inner surface of the fourth well region 124, that is, a part of the outer surface of the second well region 122 is separated from the inner surface of the fourth well region 124, and another part of the outer surface of the second well region 122 is in contact with the inner surface of the fourth well region 124.

[0117] Figure 5 This is a diagram showing the relative positions of the second well region 122 and the fourth well region 124 according to other embodiments of this disclosure.

[0118] like Figure 5 As shown, the outer surface of the second well region 122 is completely spaced from the inner surface of the fourth well region 124. Figure 4 As shown in (b), a portion of the outer surface of the second well region 122 on the right side is spaced apart from the inner surface of the fourth well region 124, while the remaining portion of the outer surface of the second well region 122 is in contact with the inner surface of the fourth well region 124.

[0119] Furthermore, when at least a portion of the second well region 122 is spaced apart from the fourth well region 124, the orthographic projection of the region between the second well region 122 and the fourth well region 124 onto the substrate 100 at least partially overlaps with the orthographic projection of the fifth well region 125 onto the substrate 100, that is, the fifth well region 125 at least partially covers the gap between the second well region 122 and the fourth well region 124.

[0120] In the above embodiment, at least a portion of the second well region 122 is spaced apart from the fourth well region 124. Therefore, the second well region 122 does not completely block the carriers (including defect charges on the surface of the semiconductor layer 110 and photogenerated carriers generated above the second well region 122) above it. Furthermore, the fifth well region 125 at least partially covers the gap between the second well region 122 and the fourth well region 124. Therefore, the fifth well region 125 blocks defect charges on the surface of the semiconductor layer 110 from passing through the gap, while simultaneously not affecting the passage of photogenerated carriers generated above the second well region 122 through the gap. This positional distribution of the second well region 122 and the fifth well region 125 can further improve the PDE of the SPAD while suppressing the rise in DCR.

[0121] For example, the orthogonal projection of the region between the second well region 122 and the fourth well region 124 onto the substrate 100 lies inside the orthogonal projection of the fifth well region 125 onto the substrate 100, meaning that the fifth well region 125 completely covers the gap between the second well region 122 and the fourth well region 124. In this way, the increase in DCR can be further suppressed while improving PDE.

[0122] In some embodiments, when a reverse voltage is applied to the SPAD device, the potential changes monotonically in the direction from the first well region 121 through the second semiconductor region 120b to the first semiconductor region 120a (hereinafter referred to as the reference direction).

[0123] For example, in an n / p type SPAD device, a reverse voltage causes the potential of the second electrode contact area 127 to be higher than the potential of the first electrode contact area 126. In this case, the potential monotonically increases in the reference direction. Conversely, in a p / n type SPAD device, a reverse voltage causes the potential of the second electrode contact area 127 to be lower than the potential of the first electrode contact area 126. In this case, the potential monotonically decreases in the reference direction.

[0124] Next, taking the SPAD device as an n / p type device (i.e., the first well region 121, the second semiconductor region 120b, and the first semiconductor region 120a are n-type doped, p-type doped, and n-type doped, respectively) as an example, we will explain the monotonic change of potential.

[0125] If no reverse voltage is applied to the SPAD device, the redistribution of charge will cause the electric field to point from the n-type doped region to the p-type doped region. Therefore, in the case of an n / p-type SPAD device, in the reference direction, the potential will monotonically decrease in a certain region near the interface between the first well region 121 and the second semiconductor region 120b (or, if the first well region 121 and the second semiconductor region 120b are separated, the interface between the first well region 121 and the semiconductor layer 110), and monotonically increase in other regions. That is, the potential exhibits a distribution curve in the reference direction that first rises, then falls, and then rises again.

[0126] After applying a reverse voltage to a SPAD device, the potential may still maintain the aforementioned distribution curve of rising, falling, and rising again. In this case, electrons moving along the reference direction to the multiplication region will be hindered in the region where the potential decreases, which affects the PDE and time response speed of the SPAD device.

[0127] In the above embodiments, through reasonable design of the SPAD device, the potential of the SPAD device monotonically increases in the reference direction when a reverse voltage is applied. Therefore, electrons can move smoothly and unimpeded to the multiplication region, improving the PDE and time response speed of the SPAD device.

[0128] The following are some ways to achieve a monotonically increasing potential.

[0129] As one implementation method, the thickness of the first semiconductor region 120a can be appropriately reduced. In this way, the second semiconductor region 120b can be closer to the electrode connected to the first semiconductor region 120a (this electrode is a cathode and is subjected to a positive voltage), and the potential of the second semiconductor region 120b can be pulled up by the external positive voltage, thereby transforming a descending curve in the potential distribution curve into an ascending curve.

[0130] As one implementation method, the thickness of the second semiconductor region 120b can be appropriately reduced. This reduces the impact of the second semiconductor region 120b on the potential distribution curve, decreasing both the width and the degree of decline of a segment of the curve. When a reverse voltage is applied to the SPAD device, an external positive voltage can transform this declining segment of the curve into a rising segment.

[0131] As one implementation method, the doping concentration of the first well region 121 and / or the second semiconductor region 120b can be appropriately reduced. Reducing the doping concentration of the first well region 121 lowers its overall potential. Reducing the doping concentration of the second semiconductor region 120b raises its overall potential. Therefore, reducing the doping concentration of both the first well region 121 and the second semiconductor region 120b helps to reduce the degree of decline in a segment of the distribution curve, so that when a reverse voltage is applied to the SPAD device, an external positive voltage can transform this declining segment into an rising segment.

[0132] As one implementation, the first well region 121 and the second semiconductor region 120b can be spaced apart to maintain a certain distance, that is, a portion of the semiconductor layer 110 exists between the first well region 121 and the second semiconductor region 120b. In this way, the first well region 121 is further away from the external positive voltage, the potential of the first well region 121 decreases, and the potential distribution curve can be transformed into a monotonically increasing curve in the reference direction.

[0133] In some embodiments, such as Figure 1 As shown, the second semiconductor region 120b has a different doping concentration than the semiconductor layer 110 (for example, the second semiconductor region 120b is formed in the semiconductor layer 110 through a doping process), and the first well region 121 is in contact with the second semiconductor region 120b. Thus, the first well region 121 is closer to the external positive voltage, and the potential of the first well region 121 increases, which is more conducive to collecting electrons around the first well region 121 into the multiplication region, thereby improving the PDE of the SPAD device.

[0134] It should be understood that when the SPAD device is a p / n type device, the charge carriers mentioned above change from electrons to holes, and the trend of potential change is opposite to that when the SPAD device is an n / p type device (that is, potential rise becomes potential fall, potential fall becomes potential rise, positive voltage becomes negative voltage, and negative voltage becomes positive voltage).

[0135] This disclosure also proposes a method for manufacturing a SPAD device, comprising the following steps.

[0136] A first well region is formed in a semiconductor layer on a substrate, the first well region having a different doping type than the semiconductor layer. After forming the first well region, a PN junction is formed in the semiconductor layer, the PN junction comprising a first semiconductor region and a second semiconductor region having different doping types, the first semiconductor region being located above the second semiconductor region, the PN junction being located above the first well region, the first semiconductor region having the same doping type as the first well region, and the orthogonal projection of the PN junction onto the substrate at least partially overlapping the orthogonal projection of the first well region onto the substrate. A second well region is then formed in the semiconductor layer, located to the side of the PN junction, the second well region having the same doping type as the second semiconductor region, the doping concentration of the second well region being greater than the doping concentration of the semiconductor layer, the upper surface of the second well region being not lower than the lower surface of the first well region, and the lower surface of the second well region not higher than the upper surface of the first well region. The formation order of the second well region and the first well region is not limited; for example, the second well region may be formed before or after the first well region.

[0137] It should be understood that the method for manufacturing a SPAD device may also include other steps to obtain the SPAD device in any of the above embodiments.

[0138] This disclosure also proposes a photoelectric sensor, including the SPAD device in any of the above embodiments. For example, this photoelectric sensor can be used in consumer electronics, medical devices, autonomous driving, intelligent robots, and other fields.

[0139] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0140] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A single-photon avalanche diode (SPAD) device, comprising a semiconductor layer on a substrate and a structure located in the semiconductor layer: A PN junction includes a first semiconductor region and a second semiconductor region with different doping types, wherein the first semiconductor region is located above the second semiconductor region. A first well region is located below the PN junction. The first well region has the same doping type as the first semiconductor region but a different doping type than the semiconductor layer. The orthogonal projection of the first well region on the substrate at least partially overlaps with the orthogonal projection of the PN junction on the substrate. as well as The second well region is located on the side of the PN junction. The second well region has the same doping type as the second semiconductor region. The doping concentration of the second well region is greater than that of the semiconductor layer. The upper surface of the second well region is not lower than the lower surface of the first well region, and the lower surface of the second well region is not higher than the upper surface of the first well region.

2. The SPAD device according to claim 1, wherein, The second well region includes a plurality of first regions, wherein at least two of the plurality of first regions are symmetrically distributed on the substrate with respect to the orthogonal projection of the PN junction on the substrate.

3. The SPAD device according to claim 2, wherein, The orthogonal projection of the second well region onto the substrate is symmetrically distributed with respect to the orthogonal projection of the PN junction onto the substrate.

4. The SPAD device according to claim 3, wherein, The second well region is an annular region formed by connecting the plurality of first regions.

5. The SPAD device according to any one of claims 1-4, wherein, The SPAD device satisfies at least one of the first, second, and third conditions. The first condition is that the side of the second well region near the PN junction is covered by a third well region located in the semiconductor layer, and the third well region acts as a protective ring for the PN junction. The second condition is that the doping concentration of the second semiconductor region is different from that of the semiconductor layer, and the upper surface of the second well region is flush with the lower surface of the second semiconductor region. The third condition is that the second well region is in contact with a fourth well region located in the semiconductor layer, the fourth well region is located on the side of the second well region away from the PN junction, and the fourth well region has the same doping type as the second semiconductor region.

6. The SPAD device of any one of claims 1-4, further comprising: Located in the fifth well region of the semiconductor layer, The fifth well region is located on the side of the PN junction and above the second well region. The fifth well region is spaced apart from the second well region, and the fifth well region has the same doping type as the second semiconductor region.

7. The SPAD device according to claim 6, wherein, The doping concentration of the fifth well region is less than that of the second well region.

8. The SPAD device according to claim 6, further comprising: A fourth well region is located in the semiconductor layer, on the side of the second and fifth well regions away from the PN junction, and the fourth well region has the same doping type as the second semiconductor region. The second well region is in contact with the fourth well region, and the fifth well region is in contact with the fourth well region.

9. The SPAD device according to claim 6, further comprising: A fourth well region is located in the semiconductor layer, on the side of the second and fifth well regions away from the PN junction, and the fourth well region has the same doping type as the second semiconductor region. Wherein, at least a portion of the second well region is spaced apart from the fourth well region, and the orthographic projection of the region between the at least a portion of the second well region and the fourth well region on the substrate at least partially overlaps with the orthographic projection of the fifth well region on the substrate.

10. The SPAD device according to claim 6, wherein, The fifth well region includes a plurality of second regions, and at least two of the plurality of second regions are symmetrically distributed on the substrate with respect to the orthogonal projection of the PN junction on the substrate.

11. The SPAD device according to claim 10, wherein, The orthographic projection of the fifth well region onto the substrate is symmetrically distributed relative to the orthographic projection of the PN junction onto the substrate.

12. The SPAD device according to claim 11, wherein, The fifth well region is a ring-shaped region formed by connecting the plurality of second regions.

13. The SPAD device according to any one of claims 1-4, wherein, When a reverse voltage is applied, the potential of the SPAD device changes monotonically in the direction from the first well region through the second semiconductor region back to the first semiconductor region.

14. The SPAD device of any one of claims 1-4, wherein, The second semiconductor region has a different doping concentration than the semiconductor layer. The first well region is in contact with the second semiconductor region.

15. A method for manufacturing a single-photon avalanche diode (SPAD) device, comprising: A first well region is formed in a semiconductor layer on a substrate, the first well region having a different doping type than the semiconductor layer; After the first well region is formed, a PN junction is formed in the semiconductor layer. The PN junction includes a first semiconductor region and a second semiconductor region with different doping types. The first semiconductor region is located above the second semiconductor region, and the PN junction is located above the first well region. The first semiconductor region and the first well region have the same doping type. The orthogonal projection of the PN junction on the substrate and the orthogonal projection of the first well region on the substrate at least partially overlap. as well as A second well region is formed in the semiconductor layer. The second well region is located on the side of the PN junction. The second well region has the same doping type as the second semiconductor region. The doping concentration of the second well region is greater than that of the semiconductor layer. The upper surface of the second well region is not lower than the lower surface of the first well region, and the lower surface of the second well region is not higher than the upper surface of the first well region.

16. A photoelectric sensor, comprising: The SPAD device according to any one of claims 1-14.

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