Dual-mesa infrared focal plane pixel structure, isolation chip and its fabrication method

Abstract

This invention relates to the field of infrared focal plane detector technology, specifically to a dual-mesa infrared focal plane pixel structure, a barrier-type chip, and its fabrication method. The structure includes a pixel protrusion having a mesa, a bottom surface, and a sidewall connecting the mesa and the bottom surface. A contact layer is disposed on the bottom surface, and a recess is disposed on the sidewall, extending from the mesa to the contact layer and forming a contact mesa on the contact layer. A first electrode is disposed on the mesa, and a second electrode is disposed on the contact mesa. This invention forms a dual-mesa infrared focal plane pixel structure by creating a recess on the sidewall of the pixel protrusion that extends from the mesa to the contact layer, forming a contact mesa on the contact layer. The first and second electrodes are respectively disposed on the mesa and the contact mesa, allowing each pixel to form an independent electrical circuit. This completely solves the problem of inconsistent pixel turn-on voltage in the middle and edge regions of large-area and ultra-large-area infrared focal plane chips.

Description

Technical Field

[0001] This invention relates to the field of infrared focal plane detector technology, specifically to a dual-mesa infrared focal plane pixel structure, a partitioned chip, and its fabrication method. Background Technology

[0002] Infrared focal plane array chips typically interconnect the readout circuitry and the infrared focal plane array via flip-flop bonding, with encapsulating adhesive filling the gaps between the chips. The infrared focal plane array is a two-dimensional pixel array composed of individual pixels. A metal first electrode and an indium pillar bump are grown on top of each working pixel for flip-flop bonding. All pixels share a common lower contact layer, which is led out to the first electrode of the outermost common pixel of the infrared focal plane array via a bottom metal ramp, and connected to the second electrode of the circuit, ultimately forming a complete electrical circuit.

[0003] As infrared focal plane arrays (FLAS) chips evolve towards larger array sizes and smaller pixel dimensions, the size of FLAS arrays continues to increase, and the number of pixels multiplies. This not only increases the difficulty of chip fabrication but also affects the overall performance of the chip. On the one hand, after using flip-chip and underfill packaging processes for ultra-large-scale FLAS arrays, the difference in thermal expansion coefficients between the materials of different flip-chip modules becomes more significant, leading to severe stress concentration inside the chip. This not only makes the chip more prone to cracking, affecting the reliability of the infrared chip, but also increases the dark current of the device, affecting the chip's photoelectric detection performance. On the other hand, larger-scale FLAS arrays result in a significant increase in the length of the second electrode loop for the effective pixels in the central region of the infrared FLAS array. This leads to a larger difference in the operating turn-on voltage between the effective pixels in the central region and the effective pixels near the common electrode, severely affecting the imaging uniformity of the infrared FLAS chip. In addition, larger-scale FLAS arrays, especially planar junction FLAS arrays, exhibit more severe crosstalk problems between pixels. Summary of the Invention

[0004] The purpose of this invention is to provide a dual-mesa infrared focal plane pixel structure, a partitioned chip, and a method for fabricating the same, which can at least solve some of the defects in the prior art.

[0005] To achieve the above objectives, the technical solution of the present invention is a dual-platform infrared focal plane pixel structure, including a pixel boss. The pixel boss has a pixel platform, a bottom surface, and a sidewall connecting the pixel platform and the bottom surface. A contact layer is provided on the bottom surface, and a recess is provided on the sidewall. The recess extends from the pixel platform to the contact layer and forms a contact platform on the contact layer. A first electrode is provided on the pixel platform, and a second electrode is provided on the contact platform.

[0006] As one embodiment, the second electrode includes a main body portion and an extension portion. The main body portion is disposed on the contact platform surface. One end of the extension portion is connected to the main body portion, and the other end extends to the pixel platform surface through the recessed portion and is electrically isolated from the first electrode.

[0007] As one embodiment, the inner wall of the recess is inclined, and the inclination direction is consistent with the inclination direction of the side wall; the extension portion extends along the inner wall of the recess to the pixel platform.

[0008] As one embodiment, a passivation layer is provided on the side of the contact layer and on the pixel platform and sidewall of the pixel boss. A first contact hole and a second contact hole are respectively provided on the passivation layer at the positions corresponding to the pixel platform and the contact platform. The first electrode is electrically connected to the pixel platform through the first contact hole, and the main body of the second electrode is electrically connected to the contact layer through the second contact hole.

[0009] The present invention also provides an isolation type chip, including a readout circuit and an infrared focal plane array flip-soldered on the readout circuit. The infrared focal plane array includes a plurality of pixel structures arranged in an array. At least some of the pixel structures adopt the dual-mesa infrared focal plane pixel structure described in any of the above claims, and an isolation groove is provided between adjacent pixel protrusions. The isolation groove penetrates the contact layer. The first electrode and the second electrode are respectively flip-soldered to the readout circuit through an interconnect structure.

[0010] As one implementation, the readout circuit is provided with a common circuit electrode and circuit pixels that correspond one-to-one with the dual-mesa infrared focal plane pixel structure. Each circuit pixel is provided with a third electrode. Each first electrode is connected to the corresponding third electrode through an interconnection structure, and each second electrode is connected to the common electrode through an interconnection structure.

[0011] The present invention also provides a method for fabricating the isolation chip described in any one of the above claims, comprising the following steps:

[0012] An epitaxial material is provided, the epitaxial material comprising a substrate, a contact layer and an infrared sensitive layer sequentially stacked;

[0013] The epitaxial material is etched to obtain the infrared focal plane array;

[0014] The infrared focal plane array is flip-soldered to the readout circuit for interconnection.

[0015] Encapsulating adhesive is filled between the infrared focal plane array and the readout circuit;

[0016] Remove the substrate.

[0017] As one implementation method, the etching of the epitaxial material to obtain the infrared focal plane array includes:

[0018] A hard mask layer is grown and patterned on the surface of the infrared sensitive layer to obtain a mask pattern layer that defines the isolation grooves and recesses.

[0019] Dry etching is used to remove the infrared sensitive layer and the contact layer at the location of the isolation trench to obtain the isolation trench. At the same time, the infrared sensitive layer and the mask pattern layer at the location of the recess and the mask pattern layer on the pixel mesa are removed to obtain the contact mesa and the pixel mesa, thereby obtaining the structure of each pixel.

[0020] A first electrode and a second electrode are respectively fabricated on the pixel platform and the contact platform.

[0021] As one embodiment, the step of growing and patterning a hard mask layer on the surface of the infrared sensitive layer to obtain a mask pattern layer defining isolation grooves and recesses includes:

[0022] A second hard mask layer and a first hard mask layer are sequentially grown on the surface of the infrared sensitive layer to complete the fabrication of the hard mask layer;

[0023] Photolithography is performed on the first hard mask layer to define the isolation groove between the pixel protrusions and the recessed portion of the pixel protrusion, and the first hard mask layer at the location of the isolation groove and the recessed portion is etched away to form a first mask pattern layer.

[0024] Photolithography is performed on the second hard mask layer to define the isolation grooves between the pixel protrusions, and the second hard mask layer at the location of the isolation grooves is etched away to form the second mask pattern layer, thus completing the fabrication of the mask pattern layer.

[0025] As one embodiment, the step of fabricating a first electrode and a second electrode on the pixel mesa and the contact mesa respectively includes:

[0026] A passivation layer is deposited on the surface of multiple pixel bosses with pixel mezzanines and contact mezzanines.

[0027] The passivation layer is photolithographically and etched to form a first contact hole and a second contact hole on the pixel mesa and the contact mesa, respectively.

[0028] A metal layer is deposited on the surface of the passivation layer, in the first contact hole, and in the second contact hole;

[0029] The metal layer outside the first electrode and second electrode regions is removed by photolithography and etching, and the first electrode and the second electrode are formed on the pixel mesa and the contact mesa, respectively.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] (1) The present invention forms a double-mesa infrared focal plane pixel structure by setting a recess on the side wall of the pixel protrusion and extending it from the pixel mesa to the contact layer, forming a contact mesa on the contact layer, and setting a first electrode and a second electrode on the pixel mesa and the contact mesa respectively, so that a single pixel forms an independent electrical circuit, which completely solves the problem of inconsistent pixel turn-on voltage in the middle and edge areas of large-area array and ultra-large-area array infrared focal plane chips.

[0032] (2) By penetrating the contact layer through the isolation groove between the pixel protrusions, the present invention completely physically isolates the dual-platform infrared focal plane pixel structure, which not only effectively avoids the interference of electrical crosstalk between pixels, but also releases the internal stress of the large-area array chip, avoids the chip cracking problem, and solves the impact of stress concentration on chip performance.

[0033] (3) The present invention can prepare a dual-mesa infrared focal plane pixel structure by one-step dry etching. The process is simple and can be applied to the preparation of monochrome or multicolor infrared focal plane chips. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of a dual-platform infrared focal plane pixel structure provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of the isolation chip provided in an embodiment of the present invention;

[0037] Figure 3 A flowchart of the fabrication process of the barrier-type chip provided in an embodiment of the present invention (substrate not shown);

[0038] In the figure: 1. Pixel boss; 101. Pixel mesa; 102. Bottom surface; 103. Side wall; 104. Recess; 105. Contact mesa; 2. Contact layer; 3. First electrode; 4. Second electrode; 5. Infrared sensitive layer; 6. Second hard mask layer; 7. First mask pattern layer; 8. Second mask pattern layer; 9. Isolation trench; 10. Passivation layer; 11. Interconnect structure; 12. First bump; 13. Readout circuit; 14. Common electrode. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0041] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0042] like Figure 1 As shown, this embodiment provides a dual-platform infrared focal plane pixel structure, including a pixel boss 1. The pixel boss 1 has a pixel platform 101, a bottom surface 102, and a sidewall 103 connecting the pixel platform 101 and the bottom surface 102. A contact layer 2 is provided on the bottom surface 102, and a recess 104 is provided on the sidewall 103. The recess 104 extends from the pixel platform 101 to the contact layer 2 and forms a contact platform 105 on the contact layer 2. A first electrode 3 is provided on the pixel platform 101, and a second electrode 4 is provided on the contact platform 105.

[0043] In this embodiment, a recessed portion 104 is provided on the side wall 103 of the pixel protrusion 1 and extends from the pixel mesa 101 to the contact layer 2, and a contact mesa 105 is formed on the contact layer 2, thereby forming a single-pixel double-mesa structure with a pixel mesa 101 and a contact mesa 105. A first electrode 3 and a second electrode 4 are respectively provided on the pixel mesa 101 and the contact mesa 105, so that a single pixel forms an independent electrical circuit, which completely solves the problem of uneven opening caused by the contact resistance difference of large-area array chips.

[0044] In some embodiments, the second electrode 4 includes a main body portion and an extension portion. The main body portion is disposed on the contact platform 105. One end of the extension portion is connected to the main body portion, and the other end extends through the recess 104 to the pixel platform 101 and is electrically isolated from the first electrode 3. In this embodiment, by adding an extension portion to the main body portion of the second electrode 4 and extending it to the pixel platform 101 through the recess 104 on the pixel boss 1, it facilitates flip-soldering interconnection with the readout circuit 13.

[0045] Furthermore, the inner wall of the recess 104 is inclined, and the inclination direction is consistent with the inclination direction of the side wall 103; the extended portion extends along the inner wall of the recess 104 to the pixel platform 101. Figure 1 As shown, the inner wall of the recess 104 slopes outward from the outer edge of the pixel platform 101 to the inner edge of the contact platform 105, so that the extended portion can smoothly transition to the pixel platform 101 along the inclined inner wall of the recess 104, avoiding the metal layer from breaking or becoming significantly thinner at the corner.

[0046] Furthermore, a passivation layer 10 is provided on the side of the contact layer 2, as well as on the pixel platform 101 and the sidewall 103 of the pixel protrusion 1. A first contact hole and a second contact hole are respectively provided on the passivation layer 10 at positions corresponding to the pixel platform 101 and the contact platform 105. The first electrode 3 is electrically connected to the pixel platform 101 through the first contact hole, and the main body of the second electrode 4 is electrically connected to the contact layer 2 through the second contact hole. By providing the passivation layer 10, the pixel protrusion 1 and the contact layer 2 can be protected. Simultaneously, by providing the first and second contact holes on the passivation layer 10, reliable electrical connections can be achieved between the first electrode 3 and the pixel platform 101, and between the main body of the second electrode 4 and the contact layer 2, while ensuring effective isolation between the first electrode 3 and the second electrode 4, thus avoiding the risk of short circuits.

[0047] In this embodiment, the pixel protrusion 1 can be columnar, preferably frustum or truncated cone. When the pixel protrusion 1 is truncated cone, the recess 104 can be located at the connection between two adjacent sides of the pixel protrusion 1; when the pixel protrusion 1 is frustum or columnar, the recess 104 can be located at any position on the side wall 103 of the pixel protrusion 1.

[0048] like Figure 2As shown, this embodiment also provides an isolation type chip, including a readout circuit 13 and an infrared focal plane array flip-soldered on the readout circuit 13. The infrared focal plane array includes a plurality of pixel structures arranged in an array. At least some of the pixel structures adopt the dual-mesa infrared focal plane pixel structure described in any of the above embodiments, and an isolation groove 9 is provided between adjacent pixel protrusions 1. The isolation groove 9 penetrates the contact layer 2. The first electrode 3 and the second electrode 4 are respectively flip-soldered to the readout circuit 13 through an interconnection structure 11.

[0049] In this embodiment, by extending the isolation groove 9 between the pixel protrusions 1 through the contact layer 2, the dual-platform infrared focal plane pixel structures are completely physically isolated. This not only effectively solves the problem of electrical crosstalk between pixels, but also releases the internal stress of the large-area array chip, effectively solving the problem of performance degradation and poor reliability caused by the accumulation of internal stress in large-area and ultra-large-area infrared focal plane chips.

[0050] Furthermore, the readout circuit 13 is provided with a common circuit electrode 14 and circuit pixels corresponding one-to-one with the dual-mesa infrared focal plane pixel structure. Each circuit pixel is provided with a third electrode. Each first electrode 3 is connected to the corresponding third electrode through an interconnection structure 11, and each second electrode 4 is connected to the common electrode 14 through an interconnection structure 11. The third electrode enables independent transmission of pixel signals to the readout circuit 13, avoiding crosstalk between channels; the common electrode 14 enables all pixels to share a unified reference potential, ensuring the reference consistency of the entire array signal readout.

[0051] Furthermore, each of the interconnect structures 11 includes a first bump 12 disposed on the first electrode 3 or the second electrode 4 and a second bump disposed on the readout circuit 13. The first bump 12 corresponds one-to-one with the second bump, and the first bump 12 is welded to the corresponding second bump. By welding the first bump 12 and the second bump to form the interconnect structure 11, precise alignment and reliable welding of the pixel structure and the readout circuit 13 are achieved. The first bump 12 and the second bump can both be made of indium pillars, etc. The third electrode is the signal input electrode of the circuit pixel. The second bump corresponding to the first bump 12 on the first electrode 3 is connected to the signal input electrode, and the second bump corresponding to the first bump 12 on the second electrode 4 is connected to the common electrode 14 via metal leads on the circuit surface or inside.

[0052] This embodiment also provides a method for fabricating the isolation chip described in any one of the above claims, comprising the following steps:

[0053] An epitaxial material is provided, the epitaxial material comprising a substrate, a contact layer 2 and an infrared sensitive layer 5 stacked sequentially;

[0054] The epitaxial material is etched to obtain the infrared focal plane array;

[0055] The infrared focal plane array is flip-soldered to the readout circuit 13 for interconnection.

[0056] Encapsulating adhesive is filled between the infrared focal plane array and the readout circuit 13;

[0057] Remove the substrate.

[0058] In this embodiment, an infrared focal plane array containing dual-mesa infrared focal plane pixel structures is first fabricated on a substrate using an etching process. Then, the infrared focal plane array is interconnected with the readout circuit 13 by flip-soldering, and encapsulant is filled between the two. After that, the substrate is removed, so that the dual-mesa infrared focal plane pixel structures are completely physically isolated from each other, thus completely cutting off the crosstalk path that may be formed between pixels through the substrate or contact layer 2, which significantly improves the spatial resolution, signal-to-noise ratio and imaging quality of the infrared focal plane array.

[0059] The epitaxial materials include, but are not limited to, mercury cadmium telluride, indium antimonide, and type II superlattice epitaxial materials; when the infrared focal plane array and the readout circuit 13 are interconnected by flip-wire bonding, the first electrode 3 and the second electrode 4 of the dual-mesa infrared focal plane pixel structure are interconnected with the readout circuit 13 through the interconnection structure 11, respectively; the methods for removing the substrate include, but are not limited to, thinning + chemical mechanical polishing, substrate etching wet etching, and dry etching processes.

[0060] In some embodiments, etching the epitaxial material to obtain the infrared focal plane array includes:

[0061] A hard mask layer is grown and patterned on the surface of the infrared sensitive layer 5 to obtain a mask pattern layer that defines the isolation groove 9 and the recess 104.

[0062] Dry etching is used to remove the infrared sensitive layer 5 and the contact layer 2 at the location of the isolation trench 9 to obtain the isolation trench 9. At the same time, the infrared sensitive layer 5, the mask pattern layer and the mask pattern layer on the pixel mesa 101 at the location of the recess 104 are removed to obtain the contact mesa 105 and the pixel mesa 101 respectively, thereby obtaining the structure of each pixel.

[0063] A first electrode 3 and a second electrode 4 are respectively fabricated on the pixel platform 101 and the contact platform 105.

[0064] In this embodiment, the etching depth between the pixel structures is deep etching to ensure that the infrared sensitive layer 5 and passivation layer 10 of the chip are not damaged after the substrate on the back of the chip is removed. Specifically, the isolation trench 9 between the pixel structures penetrates through the infrared sensitive layer 5 and the contact layer 2, so that the pixel structures are physically isolated from each other after the substrate is removed.

[0065] In some embodiments, growing and patterning a hard mask layer on the surface of the infrared sensitive layer 5 to obtain a mask pattern layer defining the isolation groove 9 and the recess 104 includes:

[0066] A second hard mask layer 6 and a first hard mask layer are sequentially grown on the surface of the infrared sensitive layer 5 to complete the fabrication of the hard mask layer;

[0067] Photolithography is performed on the first hard mask layer to define the isolation groove 9 between the pixel protrusions 1 and the recess 104 of the pixel protrusion 1, and the first hard mask layer at the location of the isolation groove 9 and the recess 104 is etched away to form the first mask pattern layer 7.

[0068] Photolithography is performed on the second hard mask layer 6 to define the isolation grooves 9 between the pixel protrusions 1, and the second hard mask layer 6 at the location of the isolation grooves 9 is etched away to form the second mask pattern layer 8, thus completing the preparation of the mask pattern layer.

[0069] In this embodiment, the first mask pattern layer 7 covers the pixel platform 101 (excluding the recessed portion 104) area of ​​the pixel boss 1, and the second mask pattern layer 8 covers the pixel platform 101 and the recessed portion 104 area of ​​the pixel boss 1. Based on the depth of the dual-mesa infrared focal plane pixel structure, the depth of the contact mesa 105, and the etching selectivity, the thicknesses of the first hard mask layer and the second hard mask layer 6 are designed. By utilizing the difference in coverage area and thickness of the two hard mask layers, step etching of the material is achieved. When the hard mask layer in the recessed area 104 is exhausted, the pixel mesa 101 area is still covered by the hard mask layer. Since the etching rate of the hard mask layer is different from that of the infrared sensitive layer 5 and the contact layer 2, etching continues. When the contact layer 2 is etched to form the contact mesa 105 in the recessed area 104, the contact layer 2 in the isolation trench 9 area is etched completely, and the remaining hard mask layer in the pixel mesa 101 area is also etched completely. At this point, etching is stopped, and a dual mesa is formed on the pixel structure.

[0070] Specifically, the first hard mask layer and the second hard mask layer 6 can be made of SiO2, Si3N4 or other films, and the first hard mask layer and the second hard mask layer 6 can be made of the same material or different materials.

[0071] In some embodiments, the fabrication of the first electrode 3 and the second electrode 4 on the pixel mesa 101 and the contact mesa 105, respectively, includes:

[0072] A passivation layer 10 is deposited on the surface of the multiple pixel protrusions 1 with pixel mesa 101 and contact mesa 105.

[0073] The passivation layer 10 is photolithographically and etched to form a first contact hole and a second contact hole on the pixel mesa 101 and the contact mesa 105, respectively.

[0074] A metal layer is deposited on the surface of the passivation layer 10, in the first contact hole, and in the second contact hole;

[0075] The metal layer outside the regions of the first electrode 3 and the second electrode 4 is removed by photolithography and etching, and the first electrode 3 and the second electrode 4 are formed on the pixel mesa 101 and the contact mesa 105, respectively.

[0076] The passivation layer 10 can be a film such as ZnS.

[0077] The preparation method of the present invention will be described in detail below through a specific embodiment.

[0078] like Figure 3 As shown, a method for fabricating a barrier-type infrared focal plane array chip includes the following steps:

[0079] (1) A substrate is provided, on which a contact layer 2 and an infrared sensitive layer 5 are sequentially stacked;

[0080] (2) A second hard mask layer 6 and a first hard mask layer are sequentially grown on the surface of the infrared sensitive layer 5. The first hard mask layer and the second hard mask layer 6 together constitute a hard mask layer.

[0081] (3) A first photoresist layer is formed by coating photoresist on the surface of the first hard mask. The isolation groove 9 between the pixel protrusions 1 and the recess 104 of the pixel protrusion 1 are defined by exposure. Then, the first photoresist layer in the isolation groove 9 area and the recess 104 area is removed by development to obtain a patterned first photoresist layer. Then, the first hard mask layer is etched using the patterned first photoresist layer as a mask to remove the first hard mask layer in the isolation groove 9 area and the recess 104 area to form a first mask patterned layer 7. Then, the first photoresist layer is removed.

[0082] (4) A second photoresist layer is formed by coating the surface of the structure obtained in step (3). An isolation trench 9 between the pixel protrusions 1 is defined by exposure. Then, the second photoresist layer in the isolation trench 9 area is removed by development to obtain a patterned second photoresist layer that completely covers the first mask pattern layer 7. Then, the patterned second photoresist layer is used as a mask to etch the second hard mask layer 6 to completely remove the second hard mask layer 6 in the isolation trench 9 area, exposing the infrared sensitive layer 5 to form the second mask pattern layer 8. Then, the second photoresist layer is removed. The first mask pattern layer 7 and the second mask pattern layer 8 together constitute the mask pattern layer.

[0083] (5) Dry etching is performed on the structure obtained in step (4). Taking advantage of the thickness difference between the first hard mask layer and the second hard mask layer 6 and the difference in etching rate of the hard mask layer, infrared sensitive layer 5 and contact layer 2 by dry etching, after the second hard mask layer 6 in the recessed area 104 is completely etched, the exposed infrared sensitive layer 5 in the recessed area 104 is etched until the contact layer 2 is etched to form the contact mesa 105. At this time, the contact layer 2 is etched away in the isolation groove 9 area, and the mask pattern layer is just etched away. Thus, the mask pattern layer, the infrared sensitive layer 5 at the position of the isolation groove 9 and the contact layer 2, and the infrared sensitive layer 5 at the position of the recessed area 104 are all etched away to form a double mesa infrared focal plane pixel structure with pixel mesa 101 and contact mesa 105.

[0084] (6) A passivation layer 10 is deposited on the surface of the structure obtained in step (5). The passivation layer 10 covers the surface of the pixel boss 1 and the contact layer 2. Then, a third photoresist layer is coated on the surface of the passivation layer 10. The first contact hole and the second contact hole are defined by exposure. Then, the third photoresist layer in the area of ​​the first contact hole and the second contact hole is removed by development to obtain a patterned third photoresist layer. Using the patterned third photoresist layer as a mask, the passivation layer 10 is etched to remove the passivation layer 10 in the area of ​​the first contact hole and the second contact hole. The first contact hole and the second contact hole are formed on the pixel mesa 101 and the contact mesa 105, respectively. Then, a metal layer is deposited on the surface of the passivation layer 10, in the first contact hole and the second contact hole. Then, the metal layer other than the first electrode 3 and the second electrode 4 is removed by photolithography and etching. The first electrode 3 and the second electrode 4 are formed on the pixel mesa 101 and the contact mesa 105, respectively. The extension of the second electrode 4 climbs from the contact mesa 105 to the pixel mesa 101 to complete the fabrication of the infrared focal plane array.

[0085] (7) A first bump 12 is prepared on the first electrode 3 and the second electrode 4 of the infrared focal plane array, and a second bump is prepared on the third electrode and the common electrode 14 of the readout circuit 13.

[0086] (8) The infrared focal plane array and the readout circuit 13 are flip-soldered together, so that the first electrode 3 and the second electrode 4 of the dual-mesa infrared focal plane pixel structure are flip-soldered together with the readout circuit 13 through the interconnection structure 11 respectively.

[0087] (9) Fill the space between the infrared focal plane array and the readout circuit 13 with encapsulating adhesive;

[0088] (10) The back of the chip is removed by a substrate removal process, and the removal depth is extended to expose the isolation groove 9 between the dual-mesa infrared focal plane pixel structures, thereby completely physically isolating the pixel structures.

[0089] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dual-platform infrared focal plane pixel structure, comprising a pixel boss, the pixel boss having a pixel platform, a bottom surface, and a sidewall connecting the pixel platform and the bottom surface, characterized in that: A contact layer is provided on the bottom surface, and a recess is provided on the side wall. The recess extends from the pixel platform to the contact layer and forms a contact platform on the contact layer. A first electrode is provided on the pixel platform, and a second electrode is provided on the contact platform.

2. The dual-platform infrared focal plane pixel structure as described in claim 1, characterized in that: The second electrode includes a main body portion and an extension portion, wherein the main body portion is disposed on the contact platform surface; One end of the extension is connected to the main body, and the other end extends through the recess to the pixel platform and is electrically isolated from the first electrode.

3. The dual-platform infrared focal plane pixel structure as described in claim 2, characterized in that: The inner wall of the recess is inclined, and the inclination direction is consistent with the inclination direction of the side wall; the extension extends along the inner wall of the recess to the pixel platform.

4. The dual-platform infrared focal plane pixel structure as described in claim 1, characterized in that: A passivation layer is provided on the side of the contact layer, the pixel platform and the side wall of the pixel boss. A first contact hole and a second contact hole are respectively provided on the passivation layer at the positions corresponding to the pixel platform and the contact platform. The first electrode is electrically connected to the pixel platform through the first contact hole, and the main body of the second electrode is electrically connected to the contact layer through the second contact hole.

5. A blocking chip, comprising a readout circuit and an infrared focal plane array flip-soldered onto the readout circuit, the infrared focal plane array comprising a plurality of pixel structures arranged in an array, characterized in that: At least a portion of the pixel structure adopts the dual-platform infrared focal plane pixel structure of any one of claims 1-4, and an isolation groove is provided between adjacent pixel protrusions, the isolation groove penetrating the contact layer; the first electrode and the second electrode are respectively interconnected with the readout circuit by flip-soldering through an interconnect structure.

6. The isolation chip as described in claim 5, characterized in that: The readout circuit is provided with a common circuit electrode and circuit pixels that correspond one-to-one with the dual-mesa infrared focal plane pixel structure. Each circuit pixel is provided with a third electrode. Each first electrode is connected to the corresponding third electrode through an interconnection structure. Each second electrode is connected to the common electrode through an interconnection structure.

7. A method for fabricating a barrier-type chip as described in claim 5 or 6, characterized in that, Includes the following steps: An epitaxial material is provided, the epitaxial material comprising a substrate, a contact layer and an infrared sensitive layer sequentially stacked; The epitaxial material is etched to obtain the infrared focal plane array; The infrared focal plane array is flip-soldered to the readout circuit for interconnection. Encapsulating adhesive is filled between the infrared focal plane array and the readout circuit; Remove the substrate.

8. The preparation method according to claim 7, characterized in that, The etching of the epitaxial material to obtain the infrared focal plane array includes: A hard mask layer is grown and patterned on the surface of the infrared sensitive layer to obtain a mask pattern layer that defines the isolation grooves and recesses. Dry etching is used to remove the infrared sensitive layer and the contact layer at the location of the isolation trench to obtain the isolation trench. At the same time, the infrared sensitive layer and the mask pattern layer at the location of the recess and the mask pattern layer on the pixel mesa are removed to obtain the contact mesa and the pixel mesa, thereby obtaining the structure of each pixel. A first electrode and a second electrode are respectively fabricated on the pixel platform and the contact platform.

9. The preparation method according to claim 8, characterized in that, The process of growing and patterning a hard mask layer on the surface of the infrared sensitive layer to obtain a mask pattern layer defining isolation grooves and recesses includes: A second hard mask layer and a first hard mask layer are sequentially grown on the surface of the infrared sensitive layer to complete the fabrication of the hard mask layer; Photolithography is performed on the first hard mask layer to define the isolation groove between the pixel protrusions and the recessed portion of the pixel protrusion, and the first hard mask layer at the location of the isolation groove and the recessed portion is etched away to form a first mask pattern layer. Photolithography is performed on the second hard mask layer to define the isolation grooves between the pixel protrusions, and the second hard mask layer at the location of the isolation grooves is etched away to form the second mask pattern layer, thus completing the fabrication of the mask pattern layer.

10. The preparation method according to claim 8, characterized in that: The step of fabricating a first electrode and a second electrode on the pixel mesa and the contact mesa, respectively, includes: A passivation layer is deposited on the surface of multiple pixel bosses with pixel mezzanines and contact mezzanines. The passivation layer is photolithographically and etched to form a first contact hole and a second contact hole on the pixel mesa and the contact mesa, respectively. A metal layer is deposited on the surface of the passivation layer, in the first contact hole, and in the second contact hole; The metal layer outside the first electrode and second electrode regions is removed by photolithography and etching, and the first electrode and the second electrode are formed on the pixel mesa and the contact mesa, respectively.

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