Semiconductor device and method of manufacturing a vertical rigid-flex package optical module

Abstract

A semiconductor device includes a flexible cable and a substrate attached to the flexible cable. A first semiconductor die and a photonic semiconductor die are disposed on the flexible cable opposite to the substrate. The flexible cable is deformed to attach it to a side surface of the photonic semiconductor die. A second semiconductor die is disposed on the substrate opposite to the flexible cable. A sealant is deposited on the second semiconductor die, the substrate, and the flexible cable. One end of the flexible cable extends from the sealant.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for manufacturing vertical rigid-flex co-packaged optical (CPO) modules. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Photonic semiconductor devices capable of transmitting or receiving signals via light are becoming increasingly common. Compared to electrical signals, device-to-device transmission via light offers numerous advantages, particularly avoiding losses due to wire resistance and reducing the effects of electromagnetic interference (EMI). However, to date, the options for packaging photonic semiconductor devices have been limited and unsatisfactory in many respects. Therefore, there is a need for improved co-packaged optical (CPO) modules and methods for manufacturing them. Attached Figure Description

[0004] Figures 1a-1c A semiconductor wafer with multiple semiconductor dies separated by saw marks is shown; Figures 2a-2j The process of forming a rigid-flexible co-packaged optical module using semiconductor dies is shown; Figures 3a-3d An embodiment of an optional cover is shown; Figure 4a and Figure 4b Additional electrical interconnection options are shown; and Figure 5a and Figure 5b An electronic device with a co-packaged optical module is shown. Detailed Implementation

[0005] Referring to the figures, the invention is described in one or more embodiments in the following description, wherein similar reference numerals denote the same or similar elements. While the invention has been described in accordance with the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents (which are supported by the following disclosure and the figures). Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between the voltage and current necessary to perform the circuit's function.

[0007] Back-end manufacturing refers to the process of dicing or dicing finished wafers into individual semiconductor dies and encapsulating these dies for structural support, electrical interconnection, and environmental isolation. To dice semiconductor dies, the wafer is scribbled and broken along non-functional areas (called serrations or cuts). This dicing is performed using laser cutting tools or saw blades. After dicing, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor die are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited on top of the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, making the semiconductor device functional for use with other system components.

[0008] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, silicon nitride, lithium niobate (LiNbO3), or other bulk material for structural support. Multiple semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active, inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to cut the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or passive surface 108 and an active surface 110, which contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed on or within the die, and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, power devices, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed on the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads for circuitry electrically connected to the active surface 110.

[0011] Conductive bump material is deposited over conductive layer 112 using evaporation, electrolytic plating, electroless plating, drop balling, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, and optionally, a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflow soldered by heating it above its melting point to form balls or bumps 114. In one embodiment, bumps 114 are formed over under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 can also be compression bonded or thermo-pressed bonded to conductive layer 112. Bumps 114 represent a type of interconnect structure that can be formed over conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0012] exist Figure 1cIn this process, a saw blade or laser cutting tool 118 is used to cut the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) or known good cells (KGU) after cutting.

[0013] Figures 2a-2j The formation of a rigid-flexible co-packaged optical module with semiconductor die 104 is shown. Figure 2a Substrate 120 is shown. Substrate 120 is a multilayer interconnect substrate including a conductive layer 122 and an insulating layer 124. The conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 may be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnects across substrate 120 and vertical electrical interconnects between the top and bottom surfaces. Depending on the design and function of the formed package or module, portions of the conductive layer 122 may be electrically shared or electrically isolated.

[0014] The insulating layer 124 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, PI, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layer 124 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, thermal oxidation, or another suitable process. The insulating layer 124 provides isolation between the conductive layers 122. Any number of conductive layers 122 and insulating layers 124 can be interleaved on top of each other to form the substrate 120.

[0015] In other embodiments, any other suitable type of packaging substrate or lead frame may be used for substrate 120. For example, substrate 120 may be a laminated interposer, PCB, wafer-form, strip interposer, lead frame, or another suitable substrate. Substrate 120 may comprise one or more laminates of pre-impregnated (prepreg) polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3 combined with phenolic cotton paper, epoxy resin, resin, woven glass, frosted glass, polyester, and other reinforcing fibers or fabrics.

[0016] Substrate 120 is formed on or attached to flexible cable 130. Flexible cable 130 is a flexible cable having multiple conductive traces extending parallel within an insulating film. Flexible cable 130 can be any type of ribbon cable, flexible flat cable (FFC), or flexible printed circuit (FPC). The insulating film can be polyimide, polyester, or another suitable insulating material (e.g., the material mentioned above for insulating layer 124). The inner conductor can be copper, steel, aluminum, gold, or another suitable conductive material. Flexible cable 130 is flexible, allowing it to bend and electrically connect to connectors that are not fully aligned with substrate 120. End 130a of flexible cable 130 has exposed contacts that the connector electrically connects to when the end of the flexible cable is inserted into a connector. In other embodiments, board-to-board or other types of connectors are mounted to end 130a for subsequent electrical interconnection.

[0017] The conductor of the flexible cable 130 can be screen-printed onto an insulating film or patterned using photolithography. The patterned conductor can be laminated between two insulating films, having a thermosetting adhesive coating activated by the lamination process. The flexible cable 130 can be formed as a flexible cable with an internal conductor using any suitable process. The flexible cable 130 can be attached to the substrate 120 using a conductive adhesive. In other embodiments, the substrate 120 is formed directly on the flexible cable 130 by directly constructing the insulating layer 124 and the conductive layer 122 onto the flexible cable using thin-film deposition techniques. Even in embodiments where the substrate is formed directly on the flexible cable, the substrate 120 is considered attached to the flexible cable 130. The resulting CPO module is referred to as a rigid-flexible package because the flexible cable 130 remains rigid in the area where the substrate 120 is attached and flexible elsewhere.

[0018] exist Figure 2b In the process, a conventional electronic semiconductor die 104a and a photonic semiconductor die 140 are disposed on and mounted to the flexible cable 130. The semiconductor die 104a is derived from... Figure 1c The semiconductor die 104, or another semiconductor die similarly formed and functioning. The photonic semiconductor die 140 is similar to... Figures 1a-1c The semiconductor die 104 is formed in such a way that an optically sensitive region or photonic region 142 is fabricated on the back surface 108. The photonic region 142 is formed of a material that can be or otherwise configured to convert external optical signals or light signals received in the photonic region into electrical signals within the photonic semiconductor die 140, which can then be processed by circuitry on the active surface 110 or the back surface 108.

[0019] Reference numerals 104, 104a, and 104b refer to semiconductor dies with purely electronic functions. Reference numeral 140 refers to a semiconductor die with photonic functions. Although two conventional semiconductor dies 104 and a single photonic semiconductor die 140 are shown in the illustrated embodiment, any number of dies and combinations of dies can be used, including more than one photonic semiconductor die in a single package or module.

[0020] In some embodiments, the photonic semiconductor die 140 is a photonic integrated circuit (PIC) containing photonic components that form functional circuitry capable of detecting, generating, transmitting, or processing light. The semiconductor die 140 may be formed of indium phosphide (InP), which allows for the integration of various active and passive optical functions on the same chip. The photonic region 142 is configured to receive optical signals directly from the air or via an attached fiber optic cable into the photonic circuitry of the semiconductor die 140.

[0021] In some embodiments, the photonic region 142 has a physical structure suitable for accommodating fiber optic cables or receiving signals (e.g., a grating coupler), and optionally has a separate connector mounted to the surface of the photonic semiconductor die 140. In other embodiments, the semiconductor die 140 is configured to emit light from the photonic region 142. The semiconductor die 140 may have multiple photonic regions 142, for example, one or more for receiving optical signals and one or more for transmitting optical signals.

[0022] Semiconductor dies 140 and 104a are both picked up and placed on flexible cable 130, with solder bumps 114 oriented toward the flexible cable. Solder bumps 114 are aligned with exposed contact pads of flexible cable 130. Solder bumps 114 are reflow soldered to physically and electrically connect semiconductor dies 140 and 104a to conductive traces embedded in flexible cable 130. Optionally, underfill is used under semiconductor dies 104a and 140 to physically support the solder connection. A portion of adhesive 146 is applied to flexible cable 130 adjacent to photonic semiconductor die 140 by, for example, inkjet printing. The size and shape of adhesive 146 are configured to correspond to the side surface of photonic semiconductor die 140 when flexible cable 130 is folded upwards in a later manufacturing stage.

[0023] exist Figure 2cIn this design, a heat sink 150 is disposed above and downwards on the rear surfaces 108 of semiconductor dies 104a and 140. The heat sink 150 is a solid material, such as steel, aluminum, copper, their alloys, or another thermally conductive material. The heat sink 150 can be cut from a single piece of material. A thermal interface material (TIM) 152 is disposed on the surface of the heat sink 150 oriented towards the semiconductor dies 104a and 140. The TIM 152 can be any suitable type of thermal material, such as thermal paste, thermal adhesive, or thermal pads. During subsequent manufacturing steps, the heat sink 150 can be adhered to the semiconductor dies 104a and 140 using thermal adhesive. The heat sink 150 absorbs heat generated by the semiconductor dies 104a and 140 and presents a smooth surface on the exterior of the package being formed. If necessary, the outer surface of the heat sink 150 may have fins attached to it to more effectively dissipate heat to the surrounding air. TIM 152 improves heat transfer between the semiconductor die and the heat sink 150.

[0024] exist Figure 2d In this embodiment, a heat sink 150 is mounted on the back surface 108 of semiconductor dies 104a and 140. The photonic region 142 remains exposed from the heat sink 150. In some embodiments, the heat sink 150 is rectangular and positioned outside the coverage area of ​​the photonic region 142. In other embodiments, the heat sink 150 may have a recess in a plan view, in which the photonic region 142 is located, such that the heat sink extends to the left edge of the photonic semiconductor die 140 in other cross-sections. In one embodiment, the heat sink 150 has an internal opening to accommodate the photonic region 142.

[0025] The flexible cable 130 is folded upwards or otherwise deformed as indicated by arrow 153, so that the adhesive 146 contacts it. Figure 2e The side surface of the photonic semiconductor die 140 is shown. Folding the flexible cable 130 creates a rounded or rounded corner 155. The radius of the corner 155 can be as large as possible to allow the flexible cable 130 to be folded without damage. In some embodiments, the internal conductor of the flexible cable 130 does not extend beyond the coverage area of ​​the semiconductor die 140 to the corner 155, allowing the flexible cable to be folded without bending the conductor. In this case, only the laminated insulating film needs to be bent, allowing for a smaller radius of the corner 155. Adhesive 146 passes through the corner 155 at a right angle to hold the flexible cable 130 in place.

[0026] The length of the flexible cable 130 on the left side of the photonic semiconductor die 140 is chosen such that, after folding at corner 155, the end 130b of the flexible cable approximately reaches the height of the top surface of the heat sink 150. In other embodiments, the end 130b of the flexible cable 130 may be cut after folding to be flush with the top surface of the heat sink 150. A channel or groove 154 is formed in the area between the end 130b of the flexible cable 130 and the heat sink 150 above the photonic region 142. The folded portion of the flexible cable 130 operates as a sidewall for the groove 154. The groove 154 may extend across the entire width of the photonic semiconductor die 140 (in and out). Figure 2e (See the page). In other embodiments, the heat sink 150 extends in other cross-sections to the vertical portion of the flexible cable 130, defining a recess 154 on three sides, while a fourth side is defined by the flexible cable. In embodiments where the heat sink extends in other cross-sections to the left edge of the photonic semiconductor die 140, the adhesive 146 may optionally extend higher until the flexible cable 130 is coupled to the heat sink 150.

[0027] exist Figure 2f In this process, a temporary protective layer 156 is formed over the photonic region 142. The protective layer 156 fills the groove 154. The protective layer 156 can be deposited as a liquid, inserted as a preformed plug, constructed using thin-film deposition techniques, or using any other suitable process. The protective layer 156 can be formed from photoresist materials, epoxy resin, or any of the methods and materials mentioned above or below for insulating layers or sealants. The top surface of the protective layer 156 is made coplanar with the end 130b of the flexible cable 130 and the top surface of the heat sink 150 by depositing the material for the protective layer to this height or by back-side grinding.

[0028] exist Figure 2g In this configuration, a temporary carrier or reinforcement 160 is disposed on the combined top surface of the heat sink 150, protective layer 156, and flexible cable 130, with an adhesive or release layer 162. The carrier 160 can be any suitable material, such as glass, metal, semiconductor, or polymer. The adhesive layer 162 is a heat-, UV-, or other type of releasable adhesive or double-sided tape, allowing the carrier 160 to be removed later.

[0029] exist Figure 2h In this process, the flexible cable 130 is flipped over, exposing the substrate 120 for further processing. The semiconductor die 104b, along with any other desired electronic components 164, is mounted onto the substrate 120. The semiconductor die 104b is from... Figure 1cOne of the semiconductor dies 104, or another semiconductor die with different functions but formed in a similar manner. Semiconductor dies 104a and 104b can be identical or have complementary functions; for example, one can be a processor and the second a memory chip. Semiconductor dies 104a, 104b and 140 are electrically coupled to each other via flexible cable 130 and substrate 120.

[0030] Electrical component 164 may be a discrete active or passive electrical device, such as a diode, transistor, resistor, capacitor, or inductor. Electrical component 164 may include additional semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete active or passive electrical devices, and may include integrated passive devices (IPDs). Component 164 is electrically and physically coupled to substrate 120 by reflowing solder paste 166 between terminals 168 and contact pads of conductive layer 124, while solder bumps 114 are reflow soldered to attach semiconductor die 104b. Underfill may optionally be used under any of the mounted components, as desired.

[0031] exist Figure 2i In this process, a sealant or molding compound 170 is deposited on the flexible cable 130, the substrate 120, and the semiconductor dies 104a, 104b, and 140 to complete the co-packaged optical (CPO) module 172. The sealant 170 is deposited using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 170 can be a liquid or particulate polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without fillers. The sealant 170 is non-conductive, provides structural support, and environmentally protects the embedded electrical components from external elements and contaminants.

[0032] A sealant 170 is deposited in a mold, with the end 130a of the flexible cable 130 extending outside the mold, such that the sealant does not completely cover the flexible cable. The sealant 170 fills the space between the flexible cable 130, the semiconductor die 104a, and the photonic semiconductor die 140, in addition to covering the semiconductor die 104b and the electrical component 164. The CPO module 172 has two common electronic semiconductor dies 104a and 104b co-packaged with the optical or photonic semiconductor die 140. The end 130a of the flexible cable 130 extends from the sealant 170 for subsequent electrical interconnection with external systems.

[0033] exist Figure 2jIn this process, the carrier 160 is removed by releasing the release layer 162. The protective layer 156 is removed by chemical etching, mechanical etching, physical stretching, laser ablation, or other suitable means to clear the groove 154 and expose the photonic region 142. The CPO module 172 is complete, having a flexible cable 130 for external electrical interconnection and a photonic region 142 for external optical interconnection. The CPO module 172 is referred to as a rigid-flexible CPO module because the flexible cable 130 is combined with a rigid substrate 120 or has a region that is kept rigid by being encapsulated in a sealant 170. In some embodiments, the CPO module 172 is formed as part of a panel or unit strip and is cut into individual pieces before or after the carrier 160 is removed.

[0034] The vertical portion of the flexible cable 130 near its end 130b is folded or deformed to serve as a sidewall, thus preparing for coupler protection. A heat sink 150 is mounted as a second sidewall opposite the flexible cable 130, and optionally a third or fourth sidewall, to form a channel or peripheral barrier for masking protection of the photon region 142. The heat sink 150 helps dissipate heat generated from the module, improving the lifespan and reliability of the CPO module 172.

[0035] Figures 3a-3d An embodiment in which fiber optic cable 176 is added to CPO module 172 is shown. Figure 3a CPO module 172a is shown, wherein a recess 154 is covered by a cover 180a, which has a flat top and vertical or elongated sidewalls. The cover 180a is a transparent cap formed of any suitable material, such as glass or plastic. The cover 180a is formed by injection molding or other suitable means and is then picked up and placed over the recess 154. Before installing the cover, adhesive 182 may be applied to the bottom of the cover 180a or the top of the CPO module 172. The cover 180a is attached to the radiator 150 and sealant 170 by a sealant, epoxy resin, or adhesive 182. Adhesive 182 may be applied as an adhesive bead completely surrounding the recess 154, two rows of adhesive on two opposite sides of the recess, or multiple discrete points.

[0036] The cover 180a has an opening 184 formed through the top of the cover. A fiber optic cable 176 can be inserted through the opening 184 for mounting on the photonic region 142. The fiber optic cable 176 can be attached to the photonic region 142 using adhesive, a coupler pre-installed or formed within a recess 154, or any other suitable means. The fiber optic cable 176 extends from the photonic region 142 to another device or coupler remote from the CPO module 172a, to which the CPO module can communicate via the fiber optic cable.

[0037] Figure 3bA CPO module 172b with a U-shaped cap 180b is shown. The cap 180b has a horizontally oriented flat flange 185 for attaching the cap to the CPO module 172b using adhesive 182. The flange 185 may extend linearly along two opposite sides of the cap 180b, or extend completely around all sides of the recess 154. A central portion 186 of the cap 180b extends downward into the recess 154. In some embodiments, the width of the central portion 186 is approximately equal to or slightly less than the width of the recess 154, such that the sidewalls of the recess 154 contact the sidewalls of the cap 180b to keep the cap aligned. Except for the change in shape, the cap 180b operates and forms in the same manner as the cap 180a.

[0038] Figure 3c CPO module 172c is shown, which has a cover 180c with a convex bulb 187 extending upward above a flange 185. The bulb 187 is circular in shape, extending in an arc or partially spherical shape away from the groove 154. Figure 3d A CPO module 172d with a cover 180d is shown, the cover 180d having a concave spherical shape 188 extending downward relative to the flange 185. The spherical shape 188 is circular in an arcuate or partially spherical shape extending downward to the groove 154. The formation and operation of the two covers 180c and 180d are as described above for cover 180a.

[0039] Figure 4a and Figure 4b Additional electrical interconnection options are shown. Figure 4a In the middle, the CPO module 200 has a PCB unit or e-Bar 201, in Figure 2hDuring the steps of mounting the semiconductor die 104b and assembly 164, a PCB cell or e-Bar 201 is disposed on the substrate 120. The PCB cell 201 may be picked up and placed onto the substrate 120 and coupled to the conductive layer 122 using a thin layer of solder paste or any other suitable means. The PCB cell 201 includes a substrate insulating material 202 and conductive vias 204 formed through the insulating material. The insulating material 202 can generally be any suitable material described above for sealant or insulating layer. The PCB cell 201 is pre-shaped and then disposed on the substrate 120. In one embodiment, the PCB cell 201 is constructed as part of a process for forming the substrate 120. In some embodiments, the PCB cell 201 includes additional conductive layers, RDLs, or contact pads formed over one or both ends of the conductive vias 204. A sealant 170 is deposited on the PCB cell 201. The sealant 170 may be deposited coplanar with the PCB cell 201, or optionally back-mounted to expose the PCB cell. Solder bump 206 is formed on PCB unit 201 (as described above for solder bump 114) and is typically formed at the end of the manufacturing process.

[0040] Figure 4b A CPO module 210 is shown, having a conductive via 212 formed through a sealant 170. The conductive via 212 may be a pre-formed post disposed on a substrate 120 prior to sealing, or a conductive via formed in a hole drilled into the sealant 170. The via can be formed through the sealant 170 using chemical etching, laser drilling, mechanical drilling, or any other suitable means to expose the contact pads of the conductive layer 122. Any suitable conductive material is deposited into the opening using any suitable metal deposition technique. As described above with respect to solder bump 114, solder bump 216 is formed on the conductive via 212. In some embodiments, contact pads, under-bump metallization, conductive traces, or other conductive structures are formed on the surfaces of the sealant 170 and the conductive via 212 prior to solder ball attachment.

[0041] The conductive via 212 and PCB unit 201 are vertically interconnected to provide an alternative or complementary electrical connection mechanism together with the flexible cable 130. CPO modules 200 and 210 can be mounted on a PCB and electrically connected to the PCB via solder bumps 206 or 216, while the flexible cable 130 provides electrical connections to another PCB or to another package on the same PCB.

[0042] Figure 5a and Figure 5b The illustration shows the integration of the aforementioned semiconductor package (e.g., CPO module 172) into a larger electronic device 300. Figure 5aThe illustration shows a partial cross-section of a CPO module 172 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. An adhesive or underfill layer is used to attach the CPO module 172 to the PCB 302. A flexible cable 130 is routed such that its end 130a extends into a connector 306. The connector 306 is soldered to a conductive layer 304 of the PCB 302 and has internal electrical contacts that apply pressure to the exposed contacts of the flexible cable 130 for electrical connection.

[0043] Semiconductor dies 104a, 104b, and 140 are electrically coupled to conductive layer 304 via substrate 120, flexible cable 130, and connector 306. Optical fiber 176 is attached to photonic region 142 to provide optical functionality to device 300. Electronic device 300 uses photonic semiconductor die 140 to transmit or receive optical signals via optical fiber, or to perform any other suitable optical function. In another embodiment, photonic region 142 is exposed to detect ambient light incident on CPO module 172.

[0044] Figure 5b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, on the surface of which multiple semiconductor packages, including a CPO module 172, are disposed. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0045] Electronic device 300 may be a standalone system performing one or more electrical functions using a semiconductor package. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for a product to be accepted by the market. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 may have a more irregular shape to facilitate assembly into more ergonomic and smaller device housings.

[0046] exist Figure 5bIn this design, PCB 302 provides a common substrate for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Trace 304 also provides power and ground connections to each semiconductor package.

[0047] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically disposed directly on the PCB.

[0048] For illustrative purposes, several types of first-level packages are shown on PCB 302, including wire-bonded packages 346 and flip chips 348. Additionally, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, linear grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, square flat no-lead package (QFN) 360, square flat package 362, and embedded wafer-level ball grid array (eWLB) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0049] Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level packaging styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, resulting in lower costs for consumers.

[0050] Although one or more embodiments of the invention have been illustrated in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide flexible cables; Attach the substrate to the flexible cable; The first semiconductor die and the photonic semiconductor die are mounted on a flexible cable opposite to the substrate; The flexible cable is deformed to attach it to the side surface of the photonic semiconductor die; The second semiconductor die is placed on a substrate opposite to that of the flexible cable; and A sealant is deposited on a second semiconductor die, a substrate, and a flexible cable, wherein one end of the flexible cable remains extended from the sealant.

2. The method according to claim 1 further includes a heat sink disposed on the first semiconductor die and the photonic semiconductor die.

3. The method of claim 1 further comprises forming a protective layer on the photonic region of the photonic semiconductor die prior to depositing the sealant.

4. The method of claim 3, further comprising: Remove the protective layer; and Attach fiber optic cables to the photonic region.

5. The method of claim 1, further comprising providing a cap including an opening on the photonic region of the photonic semiconductor die.

6. The method of claim 1, further comprising disposing a vertical interconnect structure on the substrate and extending through the sealant.

7. A method for manufacturing a semiconductor device, comprising: Provide flexible cables; Attach the substrate to the flexible cable; The photonic semiconductor die is placed on a flexible cable opposite to the substrate; The flexible cable is deformed to attach it to the side surface of the photonic semiconductor die; and A sealant is deposited on a flexible cable and a photonic semiconductor die, wherein one end of the flexible cable remains extended from the sealant.

8. The method of claim 7 further comprises forming a protective layer on the photonic region of the photonic semiconductor die prior to depositing the sealant.

9. The method of claim 8, further comprising: Remove the protective layer; and Attach fiber optic cables to the photonic region.

10. A semiconductor device, comprising: Flexible cables; Substrate attached to flexible cables; The first semiconductor die and the photonic semiconductor die are disposed on a flexible cable opposite to the substrate, wherein the flexible cable is deformed to attach to the side surface of the photonic semiconductor die. The second semiconductor die is disposed on a substrate opposite to that of the flexible cable; and A sealant is deposited on the second semiconductor die, the substrate, and the flexible cable, wherein one end of the flexible cable remains extended from the sealant.

11. The semiconductor device according to claim 10, further comprising a heat sink disposed on the first semiconductor die and the photonic semiconductor die.

12. The semiconductor device of claim 10, further comprising a protective layer formed on the photonic region of the photonic semiconductor die.

13. The semiconductor device of claim 10 further includes an optical fiber cable attached to the photonic region of the photonic semiconductor die.

14. The semiconductor device of claim 10, further comprising a cover, the cover including an opening disposed over a photonic region of the photonic semiconductor die.

15. The semiconductor device of claim 10, further comprising a vertical interconnect structure disposed on the substrate and extending through the sealant.

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