Semiconductor device and method of manufacturing a rigid-flex co-packaged optical module having an enclosure

Abstract

A semiconductor device and a method for fabricating a rigid-flexible co-packaged optical module with a housing. A semiconductor device has a flexible cable. A substrate is attached to the flexible cable. A first semiconductor die and a photonic semiconductor die are disposed above the flexible cable opposite the substrate. A housing is disposed on the flexible cable above the first semiconductor die and the photonic semiconductor die. A second semiconductor die is disposed above the substrate opposite the flexible cable. A sealant is deposited on the second semiconductor die and the substrate.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating rigid-flexible co-packaged optical (CPO) modules with housings. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Photonic semiconductor devices capable of transmitting or receiving signals via light are becoming increasingly common. Device-to-device transmission via light offers numerous advantages over electrical signals, particularly avoiding losses due to wire resistance and reducing the effects of electromagnetic interference (EMI). However, to date, the options for packaging photonic semiconductor devices have been limited and unsatisfactory in many ways. Therefore, there is a need for improved co-packaged optical (CPO) modules and their fabrication methods. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw tracks; Figures 2a-2j The diagram illustrates the process of forming a rigid-flexible co-packaged optical module using a semiconductor die; Figure 3a and Figure 3b The first housing embodiment is illustrated; Figure 4a and Figure 4b The second housing embodiment is illustrated; Figure 5a and Figure 5b The diagram illustrates additional electrical interconnection options; and Figure 6a and Figure 6b The illustration shows an electronic device with a co-packaged optical module. Detailed Implementation

[0005] In the following description with reference to the figures, the invention is described in one or more embodiments, wherein similar numerals denote the same or similar elements. While the invention has been described in relation to the best mode for carrying out its objectives, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the figures. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are generally manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between the voltage and current necessary for the circuit to function.

[0007] Back-end manufacturing refers to the process of dicing or dicing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To dice a semiconductor die, the wafer is scribed and broken along non-functional areas (referred to as serrations or saw marks). Dicing is performed using laser cutting tools or saw blades. After dicing, the individual semiconductor dies are placed on a packaging substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the semiconductor device functional and available to other system components.

[0008] Figure 1aA semiconductor wafer 100 with a base substrate material 102 is shown. The base substrate material 102 may be such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, silicon nitride, lithium niobate (LiNbO3), or other bulk materials used for structural support. Multiple semiconductor dies or electrical components 104 are formed on the wafer 100, separated by passive inter-die regions or saw tracks 106. The saw tracks 106 provide dicing areas to cut the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or passive surface 108 and an active surface 110. The active surface 110 contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed above or within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, power devices, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed over the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connection to circuitry on the active surface 110.

[0011] Conductive bump material is deposited over conductive layer 112 using processes such as evaporation, electrolytic plating, electroless plating, droplet deposition, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), copper, solder, combinations thereof, and optionally, flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 114. In one embodiment, bumps 114 are formed over an under-bump metallization (UBM) layer having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 can also be compression bonded or thermo-pressed to conductive layer 112. Bumps 114 represent a type of interconnect structure that can be formed over conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0012] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to cut the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. The individual semiconductor dies 104 can be inspected and electrically tested for the purpose of identifying known good dies (KGD) or known good cells (KGU) after cutting.

[0013] Figures 2a-2j The illustration shows the formation of a rigid-flexible co-packaged optical module using a semiconductor die 104. Figure 2a Substrate 120 is shown. Substrate 120 is a multilayer interconnect substrate including a conductive layer 122 and an insulating layer 124. The conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 may be formed using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnects across substrate 120 and vertical electrical interconnects between the top and bottom surfaces. Depending on the design and function of the formed package or module, portions of the conductive layer 122 may be electrically shared or electrically isolated.

[0014] The insulating layer 124 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, PI, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layer 124 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, thermal oxidation, or another suitable process. The insulating layer 124 provides isolation between the conductive layers 122. Any number of conductive layers 122 and insulating layers 124 can be interleaved over each other to form the substrate 120.

[0015] In other embodiments, any other suitable type of packaging substrate or lead frame may be used for substrate 120. For example, substrate 120 may be a laminated interposer, PCB, wafer form, strip interposer, lead frame, or another suitable substrate. Substrate 120 may comprise one or more laminates of pre-impregnated polytetrafluoroethylene (prepreg), FR-4, FR-1, CEM-1, or CEM-3 combined with phenolic cotton paper, epoxy resin, resin, woven glass, frosted glass, polyester, and other reinforcing fibers or fabrics.

[0016] Substrate 120 is formed on or attached to flexible cable 130. Flexible cable 130 is a flexible cable having multiple conductive traces extending in parallel within an insulating film. Flexible cable 130 can be a ribbon cable, flexible flat cable (FFC), flexible printed circuit (FPC), or another similar device. The insulating film can be polyimide, polyester, or another suitable insulating material, such as those mentioned above for insulating layer 124. The inner conductor can be copper, steel, aluminum, gold, or another suitable conductive material. Flexible cable 130 is flexible, allowing it to bend and electrically connect to connectors that are not perfectly aligned with substrate 120. End 130a of flexible cable 130 has exposed contacts that the connector electrically connects to when the end of the flexible cable is inserted into the connector. In other embodiments, board-to-board or other types of connectors are mounted or soldered to end 130a for mating with compatible connectors on another PCB.

[0017] The conductor of the flexible cable 130 can be screen-printed onto an insulating film or patterned using photolithography. The patterned conductor can be laminated between two insulating films using a thermosetting adhesive coating activated through a lamination process. The flexible cable 130 can be formed as a flexible cable with an internal conductor using any suitable process. The flexible cable 130 can be attached to the substrate 120 using solder or conductive adhesive. In other embodiments, the substrate 120 is formed directly on the flexible cable 130 by directly building the insulating layer 124 and the conductive layer 122 onto the flexible cable using thin-film deposition techniques. Even in embodiments where the substrate is formed directly on the flexible cable, the substrate 120 is considered attached to the flexible cable 130.

[0018] The resulting CPO module is referred to as a rigid-flexible package because the flexible cable 130 remains rigid in the area where the substrate 120 is attached, and flexible elsewhere. In one embodiment, the flexible cable 130 and the substrate 120 have a common extending coverage area in a plan view, rather than the end 130a extending beyond the coverage area of ​​the substrate 120 for subsequent electrical interconnection. Either the substrate 120 or the flexible cable 130 may have a portion extending beyond the coverage area of ​​the other at any given area of ​​the device.

[0019] exist Figure 2b In this process, a conventional electronic semiconductor die 104a and a photonic semiconductor die 140 are disposed above and mounted on the flexible cable 130. The semiconductor die 104a is from... Figure 1c The semiconductor die 104, or another semiconductor die similarly formed and functioning. The photonic semiconductor die 140 is similar to... Figures 1a-1c The semiconductor die 104 is formed in such a way that, except that an optically sensitive or photonic region 142 is fabricated on the back surface 108, the photonic region 142 is formed of a material that can be or otherwise configured to convert external optical signals or light signals received at the photonic region into electrical signals within the photonic semiconductor die 140, which can then be processed by circuitry on the active surface 110 or the back surface 108.

[0020] Reference numerals 104, 104a, and 104b refer to semiconductor dies with purely electronic functionality. Reference numeral 140 refers to a semiconductor die with photonic functionality. Although two conventional semiconductor dies 104 and a single photonic semiconductor die 140 are shown in the illustrated embodiment, any number and combination of dies can be used, including more than one photonic semiconductor die in a single package or module.

[0021] In some embodiments, the photonic semiconductor die 140 is a photonic integrated circuit (PIC) containing photonic components that form functional circuitry capable of detecting, generating, transporting, or processing light. The semiconductor die 140 may be formed of indium phosphide (InP), which allows for the integration of various active and passive optical functions on the same chip. The photonic region 142 is configured to receive optical signals into the photonic circuitry of the semiconductor die 140 either directly from the air or via an attached fiber optic cable.

[0022] In some embodiments, photonic region 142 has a physical structure adapted to receive fiber optic cables or signals, such as a grating coupler, and optionally has a discrete connector mounted to the surface of photonic semiconductor die 140. In other embodiments, semiconductor die 140 is configured to emit light from photonic region 142. Semiconductor die 140 may have multiple photonic regions 142, for example, one or more for receiving optical signals and one or more for transmitting optical signals. A single photonic region 142 may also have multiple fiber optic cables coupled to the same region.

[0023] As illustrated, the photonic region 142 can be formed offset from the edge of the photonic semiconductor die 140. In this case, the resulting CPO module would be suitable for use in a vertical fiber coupler. In other embodiments, such as Figure 2c As shown in the diagram, Figure 2b In an alternative configuration as shown, the photonic region 142 can be formed at the edge of the photonic semiconductor die 140. Having the photonic region 142' at the edge of the photonic semiconductor die 140 makes the CPO module more suitable for use as an edge coupler.

[0024] Both semiconductor dies 140 and 104a are picked up and placed over the flexible cable 130, with solder bumps 114 oriented toward the flexible cable. Solder bumps 114 are aligned with the exposed contact pads of the flexible cable 130. Solder bumps 114 are reflowed to physically and electrically connect semiconductor dies 140 and 104a to conductive traces embedded in the flexible cable 130. Optionally, underfill is used beneath semiconductor dies 104a and 140 to physically support the solder connection.

[0025] exist Figure 2d In this process, a temporary carrier or reinforcement 150 is disposed on the surface 108 of semiconductor dies 104a and 140, wherein an adhesive or release layer 152 is used to attach the reinforcement to the die. The carrier 150 can be any suitable material, such as glass, metal, semiconductor, or polymer. The adhesive layer 162 is a heat-, UV-, or other type of releasable adhesive or double-sided tape that allows the carrier 150 to be removed later.

[0026] A temporary protective layer 154 is formed over the carrier 150 and the release layer 152. When the carrier 150 is installed... Figure 2e When the semiconductor dies 104a and 140 are applied, the top of the semiconductor die is embedded in a protective layer 154. The protective layer 154 completely covers any exposed surface of the photonic region 142 for protection during subsequent processing steps. The protective layer 154 can be any suitable mask, photoresist, epoxy resin, molding compound, or insulating material sufficient to protect the photonic region 142.

[0027] exist Figure 2f In this process, the flexible cable 130 is flipped over, exposing the substrate 120 for further processing. The semiconductor die 104b, along with any other desired electrical components 164, is mounted onto the substrate 120. The semiconductor die 104b is from... Figure 1c One of the semiconductor dies 104, or another semiconductor die with different functionalities but formed in a similar manner. Semiconductor dies 104a and 104b can be identical or have complementary functionalities; for example, one might be a processor, while the second is a memory chip. Semiconductor dies 104a, 104b, and 140 are electrically coupled to each other via flexible cable 130 and substrate 120.

[0028] Electrical component 164 may be a discrete active or passive electrical device, such as a diode, transistor, resistor, capacitor, or inductor. Electrical component 164 may include additional semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete active or passive electrical devices, and may include integrated passive devices (IPDs). Component 164 is electrically and physically coupled to substrate 120 by reflowing solder paste 166 between terminals 168 and contact pads of conductive layer 124, while solder bumps 114 are reflowed to attach semiconductor die 104b. Underfill may optionally be used beneath any of the mounted components, as desired.

[0029] exist Figure 2g In this process, a sealant or molding compound 170 is deposited over a substrate 120, a semiconductor die 104b, and an electrical component 164. The sealant 170 is deposited using solder paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 170 can be a liquid or particulate polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without fillers. The sealant 170 is non-conductive, provides structural support, and environmentally protects the embedded electrical component from external elements and contaminants. The sealant 170 is deposited in a mold that holds the sealant just above the substrate 120. The end 130a of the flexible cable 130 is not covered by the sealant 170 to allow the flexible cable to continue operating.

[0030] exist Figure 2h In this process, the carrier 150 is removed by releasing the release layer 152. When the carrier 150 is released, the protective layer 154 is removed, or by a separation step such as cleaning, chemical etching, mechanical etching, physical stretching, laser ablation or another suitable means.

[0031] exist Figure 2iIn this package, a heat sink 180 is positioned above and downwards on the back surfaces 108 of semiconductor dies 104a and 140. The heat sink 180 is a block of solid material, such as steel, aluminum, copper, their alloys, or another thermally conductive material. The heat sink 180 can be cut from a sheet of material. A thermal interface material (TIM) 182 is disposed on the surface of the heat sink 180 oriented towards the semiconductor dies 104a and 140. The TIM 182 can be any suitable type of thermal material, such as thermal paste, thermal adhesive, or thermal pads. In subsequent manufacturing steps, the heat sink 180 can be bonded to the semiconductor dies 104a and 140 using thermal adhesive. The heat sink 180 absorbs heat generated by the semiconductor dies 104a and 140 and presents a smooth surface on the exterior of the formed package. If necessary, the outer surface of the heat sink 180 can have a heat sink attached thereto for more efficient heat dissipation to the surrounding air. TIM 182 improves heat transfer between the semiconductor die and the heat sink 180.

[0032] exist Figure 2j In this configuration, heat sink 180 has been mounted onto the back surface 108 of semiconductor dies 104a and 140 to complete CPO module 190. Photonic region 142 remains exposed from heat sink 180. In some embodiments, heat sink 180 is rectangular and positioned outside the coverage area of ​​photonic region 142. In other embodiments, heat sink 180 may have a recess in plan view, in which photonic region 142 is located, such that the heat sink extends to the left edge of photonic semiconductor die 140 in other cross-sections. In one embodiment, heat sink 180 has an internal opening to accommodate photonic region 142.

[0033] CPO module 190 is completed, featuring a flexible cable 130 for external electrical interconnection and a photonic region 142 for external optical interconnection. CPO module 190 is referred to as a rigid-flexible CPO module because the flexible cable 130 is combined with a rigid substrate 120. In some embodiments, CPO module 190 is formed as a portion of a panel or cell strip and is slit after mounting a heat sink 180. CPO module 190 has two common electronic semiconductor dies 104a and 104b co-packaged with an optical or photonic semiconductor die 140. The end 130a of the flexible cable 130 extends from the substrate 120 for subsequent electrical interconnection with external systems. Heat sink 180 assists in dissipating heat generated from the module to enhance the lifespan and reliability of CPO module 190.

[0034] Figure 3a and Figure 3b The diagram illustrates the information from... Figure 2j The CPO module 190 is equipped with an additional housing, cover, or cap 202 for the CPO module 200. Figure 3a A cross-sectional view is shown, while Figure 3b A plan view is shown. In some embodiments, the housing 202 is formed of a transparent or translucent material, such as glass or plastic. The housing 202 may be formed by injection molding or another suitable process. The housing 202 is picked up and placed over semiconductor dies 104a and 140, and then attached to a flexible cable 130 over substrate 120 using adhesive 204.

[0035] The housing 202 has an opening 206 formed above the heat sink 180. The opening 206 is formed during the injection molding of the housing 202, or after molding by cutting, laser ablation, stamping, or another suitable process. The opening 206 exposes the heat sink 180 to allow heat dissipation from the CPO module 200, or for subsequent attachment of the heat sink to the heat sink. The opening 206 can be formed to any suitable size and shape, but will generally be made as large as possible while allowing the housing 202 to overhang the coverage area of ​​the heat sink 180, sufficiently allowing beads of adhesive 208 to attach the housing to the heat sink. Adhesive 208 can be the same adhesive as adhesive 204 and is applied simultaneously with adhesive 204.

[0036] Housing 202 includes openings or slots 210 and 212 configured to route fiber optic cables through the slots. Slot 210 is formed through the top of housing 202 above photonic area 142 for use with a vertical coupler. Slot 212 is formed through one side of housing adjacent to photonic area 142 for use with an edge coupler. Fiber optic cable 216 is mounted through slot 210 or 212, whichever is more convenient for any given configuration, and is either directly attached to photonic area 142 or attached to a coupler previously formed or mounted on the photonic area. Fiber optic cable 216 can be a single fiber or multiple parallel fibers bundled together and connected in parallel to photonic area 142. Photonic area 142 can have multiple optical transmitters and / or receivers as desired.

[0037] Figure 4a and Figure 4b The diagram illustrates the information from... Figure 2j The CPO module 190 is equipped with an additional housing, cover, or cap 222 for the CPO module 220. Figure 4a A cross-sectional view is shown, while Figure 4bA plan view is shown. Housing 222 is formed and operates similarly to housing 202. Relative to housing 202, housing 222 is modified by being beveled due to an inclined surface 224 above photon region 142. The inclined surface 224 extends from the top of housing 222 to its side. An opening or slot 230 is formed through the inclined surface 224, and a slot 232 is formed through the side of the housing. Slot 230 is generally used in vertical connectors, while slot 232 is generally used in edge connectors; however, either slot 230 or 232 can be used in any embodiment, depending on which is more convenient in a particular use case.

[0038] Figure 5a and Figure 5b The diagram illustrates additional electrical interconnection options. Figure 5a In the middle, CPO module 240 has a PCB unit or e-Bar 241, in Figure 2f During the steps of mounting the semiconductor die 104b and assembly 164, a PCB cell or e-bar 241 is disposed on the substrate 120. The PCB cell 241 can be picked up and placed onto the substrate 120 and coupled to the conductive layer 122 using a thin layer of solder paste or any other suitable means. The PCB cell 241 includes a base insulating material 242 and conductive vias 244 formed through the insulating material. The insulating material 242 can generally be any suitable material described above for sealant or insulating layer. The PCB cell 241 is pre-formed and then disposed on the substrate 120. In one embodiment, the PCB cell 241 is constructed as part of the process of forming the substrate 120. In some embodiments, the PCB cell 241 includes additional conductive layers, RDLs, or contact pads formed above one or both ends of the conductive vias 244. A sealant 170 is deposited over the PCB cell 241. The sealant 170 can be deposited coplanar with the PCB cell 241, or optionally back-mounted to expose the PCB cell. Solder bumps 246 are formed on PCB unit 241, as described above for solder bumps 114, typically at the end of the manufacturing process.

[0039] Figure 5bA CPO module 250 with a conductive via 252 formed through sealant 170 is shown. The conductive via 252 may be a pre-formed pillar disposed on substrate 120 prior to encapsulation, or a conductive via formed in a hole drilled into sealant 170. The via may be formed through sealant 170 using chemical etching, laser drilling, mechanical drilling, or any other suitable means to expose the contact pads of conductive layer 122. Any suitable conductive material may be deposited into the opening using any suitable metal deposition technique. Solder bump 256 is formed on conductive via 252 as described above with respect to solder bump 114. In some embodiments, contact pads, under-bump metallization, conductive traces, or other conductive structures are formed on the surfaces of sealant 170 and conductive via 252 prior to solder ball attachment.

[0040] The conductive via 252 and PCB unit 241 are vertically interconnected to provide alternative or supplementary electrical connection mechanisms together with the flexible cable 130. CPO modules 240 and 250 can be mounted on a PCB and electrically connected to the PCB via solder bumps 246 or 256, while the flexible cable 130 provides electrical connections to another PCB or another package on the same PCB.

[0041] Figure 5a and Figure 5b The illustration shows the integration of the aforementioned semiconductor package (e.g., CPO module 200) into a larger electronic device 300. Figure 5a The illustration shows a partial cross-section of a CPO module 172, mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302. An adhesive or underfill layer is used to attach the CPO module 200 to the PCB 302. A flexible cable 130 is routed such that its end 130a extends into a connector 306. The connector 306 is soldered to a conductive layer 304 of the PCB 302 and has internal electrical contacts that apply pressure against the exposed contacts of the flexible cable 130 for electrical connection.

[0042] Semiconductor dies 104a, 104b, and 140 are electrically coupled to conductive layer 304 via substrate 120, flexible cable 130, and connector 306. Optical fiber 216 is attached to photonic region 142 to provide optical functionality to device 300. Photonic semiconductor die 140 is used by electronic device 300 to transmit or receive optical signals via optical fiber, or to perform any other suitable optical function. In another embodiment, photonic region 142 is exposed to detect ambient light incident on CPO module 200.

[0043] Figure 5bThe illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, wherein multiple semiconductor packages, including a CPO module 200, are disposed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0044] Electronic device 300 can be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 can be a sub-component of a larger system. For example, electronic device 300 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 can have more irregular shapes to easily fit into more ergonomic and smaller device housings.

[0045] exist Figure 5b In this PCB 302, a general-purpose substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed above or within layers of the PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Trace 304 also provides power and ground connections to each of the semiconductor packages.

[0046] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically disposed directly on the PCB.

[0047] For illustrative purposes, several types of first-level packages, including wire-bonded packages 346 and flip-chip packages 348, are illustrated on PCB 302. Furthermore, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, pad gate array (LGA) 356, multi-chip module (MCM) or SIP module 358, square flat no-lead package (QFN) 360, square flat package 362, and embedded die-level ball grid array (eWLB) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out die-level package (Fo-WLP) or a fan-in die-level package (Fi-WLP).

[0048] Depending on system requirements, any combination of semiconductor packages configured with first-level and second-level packaging styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages encompass complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, leading to lower costs for consumers.

[0049] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide flexible cables; Attach the substrate to the flexible cable; The first semiconductor die and the photonic semiconductor die are positioned above the flexible cable opposite the substrate; The housing is mounted on a flexible cable above the first semiconductor die and the photonic semiconductor die; The second semiconductor die is positioned above the substrate opposite the flexible cable; and The sealant is deposited over the second semiconductor die and the substrate.

2. The method of claim 1, wherein the housing includes an opening above the photonic region of the photonic semiconductor die.

3. The method of claim 2, wherein the housing includes an inclined surface above the photon region, and wherein an opening is formed in the inclined surface.

4. The method of claim 1, further comprising placing a heat sink above the first semiconductor die and the photonic semiconductor die.

5. The method of claim 4, wherein the housing includes an opening above the heat sink.

6. The method of claim 1, further comprising disposing a vertical interconnect structure above the substrate and extending through the sealant.

7. A method for manufacturing a semiconductor device, comprising: Provide flexible cables; Attach the substrate to the flexible cable; The photonic semiconductor die is positioned above the flexible cable opposite the substrate; and The housing is mounted on a flexible cable above the photonic semiconductor die.

8. The method of claim 7, wherein the housing includes an opening above the photonic region of the photonic semiconductor die.

9. The method of claim 7, further comprising: Extend the fiber optic cable through the opening in the housing; and Optical fiber cables are coupled to photonic semiconductor chips.

10. A semiconductor device, comprising: Flexible cables; The substrate is attached to the flexible cable; The first semiconductor die and the photonic semiconductor die are positioned above the flexible cable opposite the substrate; The outer casing is mounted on a flexible cable above the first semiconductor die and the photonic semiconductor die; The second semiconductor die is disposed above the substrate opposite the flexible cable; and A sealant is deposited over the second semiconductor die and the substrate.

11. The semiconductor device of claim 10, wherein the housing includes an opening above the photonic region of the photonic semiconductor die.

12. The semiconductor device of claim 11, wherein the housing includes an inclined surface above the photonic region, and wherein an opening is formed in the inclined surface.

13. The semiconductor device of claim 10, further comprising a heat sink disposed above the first semiconductor die and the photonic semiconductor die.

14. The semiconductor device of claim 13, wherein the housing includes an opening above the heat sink.

15. The semiconductor device of claim 10, further comprising a vertical interconnect structure disposed above the substrate and extending through the sealant.

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