Battery structure

Abstract

This application relates to the field of crystalline silicon photovoltaic cells, and in particular to a cell structure. The cell includes a base layer; a PN junction layer connected to the back side of the base layer; and an electrode layer comprising multiple main grids and multiple fine grids, each fine grid including a first conductive portion and a second conductive portion connected to both ends of the first conductive portion. The multiple main grids and multiple fine grids are all connected to the side of the PN junction layer opposite to the base layer. The multiple main grids are spaced apart, and multiple fine grids are spaced apart between adjacent main grids. The second conductive portions at both ends of the first conductive portion are respectively connected to adjacent main grids, and the cross-sectional area of ​​the first conductive portion is smaller than the cross-sectional area of ​​the second conductive portion. This cell structure can meet the requirements of high current convergence and transmission, and reduces the overall amount of electrode conductive material used while ensuring normal current conduction capability, thus preventing excessive material waste.

Description

Technical Field

[0001] This application relates to the field of crystalline silicon photovoltaic cells, and more particularly to a cell structure. Background Technology

[0002] Solar cells utilize the photoelectric effect to directly convert sunlight into electrical energy. They are clean and renewable, and are widely used in the field of photovoltaic power generation.

[0003] In related technologies, the cell structure of a solar cell includes a base layer, a PN junction layer, and an electrode layer. The PN junction layer is connected to the back of the base layer. Along the direction away from the base layer, the PN junction layer and the electrode layer are arranged sequentially. The base layer and the PN junction layer cooperate to generate and separate photogenerated carriers. The electrode layer includes multiple main grids and multiple fine grids. The main grids and fine grids are arranged perpendicularly and intersectingly. The fine grids are used to collect photogenerated carriers generated in the base layer and PN junction layer regions, while the main grids are used to collect current and transmit the current to the outside.

[0004] However, all photogenerated carriers generated throughout the battery converge towards the main grid through the fine grid. On a single fine grid, the current collected at various locations along the way continuously superimposes and accumulates, resulting in a higher current density near the root of the main grid and a lower current density at the end far from the main grid. To meet the high current transmission requirements near the main grid, the fine grid as a whole needs to have a large cross-sectional area, which leads to a waste of electrode material. Summary of the Invention

[0005] This application provides a battery structure to solve the technical problem in related technologies where a large cross-sectional area of ​​the fine grid is required to meet the high current transmission demand near the main grid, resulting in a waste of electrode material.

[0006] This application provides a battery structure, including:

[0007] grassroots level;

[0008] The PN junction layer is connected to the back of the substrate;

[0009] The electrode layer includes multiple main gates and multiple fine gates, each fine gate including a first conductive portion and a second conductive portion connected to both ends of the first conductive portion;

[0010] Multiple main grids and multiple fine grids are connected to the side of the PN junction layer away from the base layer. The multiple main grids are spaced apart, and multiple fine grids are spaced apart between adjacent main grids.

[0011] The second conductive parts at both ends of the first conductive part are respectively connected to the adjacent main grid, and the cross-sectional area of ​​the first conductive part is smaller than the cross-sectional area of ​​the second conductive part.

[0012] In some embodiments, the cross-sectional area of ​​the second conductive portion is a, where 150 μm² ≥ a ≥ 120 μm², and / or the cross-sectional area of ​​the first conductive portion is b, where 100 μm² ≥ b ≥ 80 μm².

[0013] In some embodiments, the main gate includes multiple conductive segments, all of which are located on the same straight line and are spaced apart from each other.

[0014] In some embodiments, each of the conductive segments includes an aluminum-based conductive layer and a nano-silver coating layer, wherein the nano-silver coating layer is coated on the outside of the aluminum-based conductive layer;

[0015] The second conductive part is connected to the corresponding main gate's nano-silver coating layer.

[0016] In some embodiments, the aluminum-based conductive layer is internally doped with carbon nanotubes.

[0017] In some embodiments, including the battery structure provided above, the PN junction layer includes a plurality of P regions and a plurality of N regions, which are arranged sequentially at intervals.

[0018] In some embodiments, the doping concentration of the P-region and N-region gradually decreases along the direction closer to the substrate.

[0019] In some embodiments, the concentration on the side of region P furthest from the substrate is 1 × 10⁻⁶. 20 cm -3 The concentration on the side of zone P closest to the base layer is 5 × 10⁻⁶. 18 cm -3 And / or, the concentration on the side of zone N furthest from the base layer is 8 × 10⁻⁶. 19 cm -3 The concentration on the side of zone N closest to the base layer is 3×10⁻⁶. 18 cm -3 .

[0020] In some embodiments, the battery structure provided above further includes a silicon dioxide layer and a hydrogenated amorphous silicon layer, wherein the silicon dioxide layer is connected to the side of the PN junction layer away from the substrate, the hydrogenated amorphous silicon layer is connected to the side of the silicon dioxide layer away from the substrate, and the electrode layer is connected to the side of the hydrogenated amorphous silicon layer away from the substrate.

[0021] In some embodiments, the battery structure provided above further includes a silicon oxynitride layer connected to the side of the plurality of main grids and the plurality of fine grids away from the base layer.

[0022] This application provides a battery structure in which a PN junction layer is formed on the back of a substrate, and multiple main grids and multiple fine grids are located on the side of the PN junction layer facing away from the substrate. Adjacent main grids are connected by a first conductive portion and a second conductive portion, forming a current conduction path. The cross-sectional area of ​​the first conductive portion is smaller than that of the second conductive portion. Therefore, near the main grids, a strong current carrying capacity and low contact resistance are maintained, while away from the main grids, unnecessary conductive material accumulation and obstruction area are reduced. This makes the current transmission path in the fine grids more closely match the actual current density distribution, thereby reducing local resistance loss and current congestion. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] Figure 1 This is a schematic diagram of the battery structure provided in this application;

[0025] Figure 2 A schematic diagram of the electrode layer of the battery structure provided in this application;

[0026] Figure 3 This is a schematic diagram of the conductive segment of the battery structure provided in this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 100. Grassroots level;

[0029] 200, PN junction layer; 210, P-region; 220, N-region;

[0030] 300, Electrode layer; 310, Main grid; 311, Conductive segment; 312, Aluminum-based conductive layer; 313, Nano-silver coating layer;

[0031] 320. Fine grid; 321. First conductive part; 322. Second conductive part;

[0032] 400, silicon dioxide layer;

[0033] 500, Hydrogenated amorphous silicon layer;

[0034] 600, silicon oxynitride layer;

[0035] 700, Anti-reflection layer.

[0036] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0038] BC cells are an important type of crystalline silicon photovoltaic cells, primarily used in the manufacturing and integration of high-efficiency solar power generation modules. They are particularly suitable for applications requiring high conversion efficiency and long-term reliability, such as distributed rooftop photovoltaic power stations, large-scale ground-mounted power stations, and building-integrated photovoltaic systems. These cells typically employ a back-contact structure, placing the PN junction layer and electrode layer on the back of the substrate. This prevents the wiring on the front of the substrate from blocking incident light, thereby improving light utilization and output power. In related technologies, the cell structure of a solar cell includes a substrate, a PN junction layer, and an electrode layer. The PN junction layer is connected to the back of the substrate. Along the direction away from the substrate, the PN junction layer and electrode layer are arranged sequentially. The substrate and PN junction layer work together to generate and separate photogenerated carriers. The electrode layer includes multiple main grids and multiple fine grids, arranged perpendicularly and intersecting each other. The fine grids collect photogenerated carriers generated in the substrate and PN junction layer regions, while the main grids collect current and conduct it outwards.

[0039] However, all photogenerated carriers generated by light across the entire solar cell must be collected by the fine grid before being conducted to the main grid. The current continuously accumulates during conduction within the fine grid. Each fine grid collects photogenerated carriers from its corresponding lower region along its length, and all carriers converge and flow towards the main grid. This results in the fine grid near the root of the main grid collecting all the conduction current, leading to a high current density. Conversely, the ends farther from the main grid only collect carriers in localized areas, resulting in relatively low current flow and density. To meet the requirements of high-current, efficient transmission and reduced Joule heat loss at the main grid connection point, related technologies require a uniformly large cross-sectional area for the entire fine grid. This design cannot accommodate the differentiated current distribution characteristics on the fine grid, leading to severe redundancy in the grid line cross-section in low-current regions, resulting in significant waste of electrode material. Furthermore, the wider grid structure increases the surface shading area, encroaching on the light-receiving area of ​​the silicon wafer and further affecting the cell's photoelectric conversion efficiency.

[0040] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0041] Combination Figure 1 , Figure 2 and Figure 3 This application provides a battery structure including a base layer 100, a PN junction layer 200 and an electrode layer 300. The PN junction layer 200 is connected to the back side of the base layer 100. The electrode layer 300 includes a plurality of main grids 310 and a plurality of fine grids 320. Each fine grid 320 includes a first conductive portion 321 and a second conductive portion 322 connected to both ends of the first conductive portion 321.

[0042] Multiple main grids 310 and multiple fine grids 320 are all connected to the side of the PN junction layer 200 away from the base layer 100. The multiple main grids 310 are spaced apart, and multiple fine grids 320 are spaced apart between adjacent main grids 310.

[0043] The second conductive portions 322 at both ends of the first conductive portion 321 are respectively connected to the adjacent main gate 310, and the cross-sectional area of ​​the first conductive portion 321 is smaller than the cross-sectional area of ​​the second conductive portion 322.

[0044] In this embodiment, the substrate 100 uses an N-type single-crystal silicon substrate with a silicon wafer thickness of 150 μm and a resistivity greater than or equal to 1.5 Ω•cm and less than or equal to 2 Ω•cm; the front side of the silicon wafer is texturized with alkali and then SiN is deposited. x The anti-reflection layer 700 has a thickness greater than or equal to 70 nm and less than or equal to 80 nm, preferably 75 nm. The back side of the silicon wafer is polished and cleaned. In some embodiments, the base layer 100 can also be a silicon material with a passivation pretreatment layer on its surface. It can be in the shape of a square, round, or irregularly shaped slice, and its thickness is usually greater than the thickness of the functional layer formed on it, so as to stably support the PN junction layer 200 and the electrode layer 300, and adapt to subsequent packaging and interconnection processes.

[0045] In some embodiments, the electrode layer 300 can be formed by screen printing, inkjet printing, electroplating or laser-induced deposition. The main gate 310 is used to collect the current of the fine gate 320 and transmit the current to the external interconnect structure. The cross-section of the main gate 310 can be rectangular, rounded rectangle or trapezoidal, and the width and thickness of the main gate 310 are set according to the current capacity and packaging requirements to form the main low-resistance conductive channel. The fine gate 320 is used to collect the current generated in the local area of ​​the PN junction layer 200 and transmit it to the adjacent main gate 310. The first conductive part 321 and the second conductive part 322 make the fine gate 320 form a continuous conductive path across the two main gates 310. The material of the fine gate 320 can be silver, aluminum, copper, silver-clad aluminum, silver-clad copper or conductive composite paste.

[0046] Based on the above analysis, it can be seen that during operation, after the incident light enters the base layer 100 through the front of the battery, photogenerated carriers are generated and separated under the action of the built-in electric field formed by the PN junction layer 200. The separated carriers migrate to the back side and enter the coupling region between the PN junction layer 200 and the electrode layer 300. Multiple fine grids 320 on the side of the PN junction layer 200 away from the base layer 100 first collect the current in the local area, and then collect the current in segments to the adjacent main grid 310 through the continuous bridging path formed by the first conductive part 321 and the second conductive part 322. Since the fine grid 320 does not use a fixed conductive path with a uniform cross-section throughout, but the cross-sectional area of ​​the first conductive part 321 is smaller than that of the second conductive part 322, it can retain a strong current carrying capacity and a low contact resistance near the main grid 310, and reduce unnecessary conductive material accumulation and blocking area far from the main grid 310. This makes the current transmission path in the fine grid 320 more matched with the actual current density distribution, thereby reducing local resistance loss and current congestion.

[0047] Meanwhile, multiple main grids 310 are distributed between adjacent fine grids 320, which re-collect currents from different fine grids 320 and output them to the external interconnect structure, so that the entire electrode layer 300 forms a hierarchical current collection network. Through this hierarchical conductive cooperation between the main grids 310 and the fine grids 320, and the cross-sectional area design of the first conductive part 321 and the second conductive part 322 of the fine grids 320, the uniformity of current distribution can be improved while ensuring the overall conductive continuity of the back contact battery, reducing the local load near the main grids 310, reducing the energy loss caused by series resistance, and helping to reduce the amount of conductive material used and local thermal stress concentration, thereby improving the electrical performance, stability and long-term service reliability of the battery structure.

[0048] The cross-sectional area of ​​the second conductive part 322 is a, 150μm²≥a≥120μm², and / or the cross-sectional area of ​​the first conductive part 321 is b, 100μm²≥b≥80μm².

[0049] In this embodiment, the cross-sectional area of ​​the second conductive part 322 is a, 150μm²≥a≥120μm², and the cross-sectional area of ​​the first conductive part 321 is b, 100μm²≥b≥80μm².

[0050] In this application, the structure with an end cross-sectional area of ​​a or b is defined to characterize the conductivity of the first conductive part 321 and the second conductive part 322. The cross-sectional areas of the first conductive part 321 and the second conductive part 322 are essentially the equivalent current-carrying areas of the fine gate 320 at corresponding positions. Its function is to enable the fine gate 320 to maintain a large current carrying capacity near the main gate 310, and to complete the current collection with a smaller cross-sectional area far from the main gate 310, thereby reducing the consumption of metal materials and reducing local resistance loss while ensuring the continuity of conductivity.

[0051] In some embodiments, the end cross-sectional areas a and b can be understood as the equivalent area formed by the linewidth and thickness of the fine grid 320 at the corresponding positions, or can be determined by the porosity, composite filling rate, or local thickening structure. For example, when the fine grid 320 is formed using silver paste, silver-aluminum composite paste, copper-based conductive paste, or multilayer composite metal plating, the cross-sectional area range can be achieved by changing the printing linewidth, screen aperture, sintered metal layer thickness, or local deposition morphology. The end closer to the main grid 310 can correspond to a wider or thicker conductive cross-section to obtain lower contact resistance and smaller current congestion effect, while the end farther from the main grid 310 can correspond to a narrower or thinner conductive cross-section to reduce material usage and reduce the heat load caused by redundant metal.

[0052] For embodiments under different process conditions, the ratio of a to b can vary between approximately 1.2 and 1.9 times to achieve a balance between conductivity, process feasibility, and metal consumption. It should be understood that the above examples are merely illustrative and not limiting.

[0053] The main gate 310 includes multiple conductive segments 311, all of which are located on the same straight line and are spaced apart from each other.

[0054] In this embodiment, the length of each conductive segment 311 is greater than or equal to 8 mm and less than or equal to 12 mm, preferably 10 mm. The interval between adjacent conductive segments 311 is greater than or equal to 0.5 mm and less than or equal to 1 mm. In some embodiments, the multiple conductive segments 311 may be in the form of short strips, segmented long strips, or locally thickened straight segments. The length of a single conductive segment 311 may be on the order of millimeters, and the multiple conductive segments 311 may be arranged at equal or non-equal intervals along the same straight line to adapt to the layout design of solar cells of different sizes.

[0055] In this embodiment, the segmented fabrication process of the main grid 310 is as follows: after completing the overall replication, multiple conductive segments 311 are formed by segmented cutting. In some embodiments, the main grid 310 can also be formed by screen printing, inkjet printing, laser transfer printing or electroplating deposition, or obtained by intermittent exposure or selective removal processes. In different implementations, the spacing width, segment length and segment thickness between adjacent conductive segments 311 can be adjusted according to the cell size, operating current and packaging requirements, usually satisfying the structural constraints that do not significantly increase the series resistance and provide sufficient space for thermal stress release. It should be understood that the above materials, shapes and dimensions are only illustrative and not limiting.

[0056] In this application, the reserved interval between adjacent conductive segments 311 allows the main grid 310 to release some mechanical stress in discontinuous areas when affected by light-induced heating, changes in ambient temperature, or differences in thermal expansion between component layers. This reduces the stress accumulation phenomenon commonly seen in continuous metal busbars, thereby reducing peeling, cracking, or microcrack propagation between the conductive layer and the base layer 100. Since the main grid 310 is not a completely continuous strip but is composed of multiple conductive segments 311, it can reduce the area of ​​metal material laid while maintaining the necessary current collection capacity, reducing shading, heat absorption, and material consumption, and making the thermal load more evenly distributed among the conductive segments 311. Based on the above working principle, it can be seen that the segmented linear main grid 310 structure can improve the current collection stability and enhance the structural reliability and service life of the battery under long-term high temperature, high humidity, and cyclic load conditions.

[0057] Each conductive segment 311 includes an aluminum-based conductive layer 312 and a nano-silver coating layer 313, with the nano-silver coating layer 313 covering the outside of the aluminum-based conductive layer 312; the second conductive part 322 is connected to the nano-silver coating layer 313 of the corresponding main gate 310.

[0058] In this application, the aluminum-based conductive layer 312 is the conductive framework constituting the internal current path of the main gate 310. Its main function is to carry and transmit the current collected from the fine gate 320 and to provide necessary mechanical support for the main gate 310. The nano-silver coating layer 313 is a highly conductive contact layer covering the outer surface of the aluminum-based conductive layer 312. Its function is to reduce the contact resistance of the main gate 310 surface and improve the electrical connection stability with the fine gate 320. The ends of the first conductive portion 321 and the second conductive portion 322 are respectively connected to the corresponding main gate 310. The 10 nano-silver coating layer 313 forms an electrical contact, allowing the charge carriers collected by the fine gate 320 to enter the main gate 310 via the nano-silver coating layer 313. The aluminum-based conductive layer 312 then completes the low-loss current transfer. Since the nano-silver coating layer 313 is located at the external contact interface, its connection interface with the fine gate 320 is more likely to form a stable low-impedance conduction path. At the same time, it can isolate the aluminum-based conductive layer 312 from the oxidation risk caused by direct exposure to the external environment, thereby improving the conductivity consistency and durability of the electrode under long-term operation.

[0059] In this embodiment, the thickness of the aluminum-based conductive layer 312 is greater than or equal to 5 μm and less than or equal to 8 μm, preferably 7 μm; the thickness of the nano-silver coating layer 313 is greater than or equal to 0.5 μm and less than or equal to 1 μm, preferably 0.8 μm; in some embodiments, the aluminum-based conductive layer 312 can be formed by aluminum paste sintering, that is, after forming an aluminum-based pattern on the surface of the PN junction layer 200 by screen printing or spraying, it is sintered to form a firm bond with the underlying functional layer; it can also be formed by aluminum alloy extrusion layer, that is, aluminum alloy material is made into strips and then compositely disposed on the back of the battery; it can also be formed by aluminum metal deposition layer, that is, a continuous aluminum layer is constructed in a predetermined area by vacuum evaporation, magnetron sputtering or electrodeposition.

[0060] In some embodiments, the nano-silver coating layer 313 can be implemented by any one or more of the following methods: a sintered layer of nano-silver particles, a layer of silver nanowires, or an ultrathin silver plating layer. The sintered layer of nano-silver particles can be formed into a porous but continuous conductive film on the outside of the aluminum-based conductive layer 312 by low-temperature sintering. The silver nanowire layer can be coated or transferred to cover the outer surface of the aluminum-based conductive layer 312 to form a flexible conductive network. The ultrathin silver plating layer can be formed into a dense metal coating on the surface of the aluminum layer by chemical plating, electroplating, or physical vapor deposition.

[0061] In some embodiments, the main grid 310 can be a coaxial composite strip with a core aluminum core and an outer silver coating, a layered composite metal strip, or a partially coated composite segment structure to adapt to different battery layouts and metallization processes. The aluminum-based conductive layer 312 has a thickness in the micrometer range to ensure the main current carrying capacity and structural strength, while the nano-silver coating layer 313 has a thickness in the submicrometer to micrometer range, significantly less than the thickness of the aluminum-based conductive layer 312, thereby reducing the amount of precious metals used while ensuring contact conductivity. It should be understood that the above material morphology and preparation method are exemplary descriptions, and can be adjusted according to sintering temperature, surface roughness, and process compatibility in actual applications, and are not limited thereto.

[0062] The aluminum-based conductive layer 312 is doped with carbon nanotubes.

[0063] In this embodiment, the aluminum-based conductive layer 312 is doped with carbon nanotubes at a mass ratio of 5%. In this application, the doping of carbon nanotubes into the aluminum-based conductive layer 312 refers to introducing a nanoscale carbon material reinforcing phase dispersed within the aluminum matrix into the layered structure with aluminum as the main conductive matrix, forming an aluminum-based composite conductive layer. This improves the continuous current transmission capability within the conductive layer without increasing its overall thickness, and enhances its crack resistance and structural stability under thermal cycling, mechanical loads, and welding or sintering stresses, thereby reducing the risk of microcrack propagation caused by localized stress concentration.

[0064] In some embodiments, carbon nanotubes can be single-walled carbon nanotubes, multi-walled carbon nanotubes, or carbon nanotubes that have undergone surface functionalization treatment with carboxyl, hydroxyl, amino groups, etc. Single-walled carbon nanotubes are suitable for constructing microscopic conductive channels with high mobility, multi-walled carbon nanotubes are suitable for improving structural strength and resistance to deformation, and surface functionalized carbon nanotubes are beneficial for improving the interfacial bonding state between them and the aluminum matrix.

[0065] In some embodiments, carbon nanotubes can be introduced by mechanical mixing, ultrasonic dispersion, slurry blending, or in-situ growth. Mechanical mixing is suitable for uniformly introducing carbon nanotubes into the aluminum-based system during the powder metallurgy or slurry preparation stage. Ultrasonic dispersion is suitable for breaking up agglomerates to improve dispersion uniformity. Slurry blending is suitable for synergistic implementation with printing or coating processes. In-situ growth can simultaneously construct a carbon nanotube network during the formation of the aluminum matrix.

[0066] In some embodiments, carbon nanotubes can be uniformly dispersed within the aluminum-based conductive layer 312, or oriented along the extension direction of the main gate 310, and can also form an enhancement network in local high current density regions to achieve a match between conductivity and enhancement functions in different working regions. In terms of size, the diameter of the carbon nanotubes is typically in the nanometer range, preferably several nanometers to tens of nanometers, and the length can be in the micrometer range, so as to form conductive bridging pathways across grains or intergranular spaces with a low addition amount; the doping amount is generally a very low proportion of the mass of the aluminum-based conductive layer 312, usually controlled within a range that does not significantly degrade the overall resistivity, in order to balance conductivity, processability, and enhancement effect.

[0067] It should be understood that the above examples are for demonstration purposes only and are not limiting. Without departing from the technical concept of this application, graphene, carbon nanofibers, metal nanowires or other nano-reinforced materials can be used to replace carbon nanotubes, and their dispersion mode, orientation state and addition ratio can be adjusted accordingly according to different preparation processes.

[0068] The PN junction layer 200 includes multiple P regions 210 and multiple N regions 220, which are arranged alternately in sequence.

[0069] In this embodiment, multiple P-regions 210 and multiple N-regions 220 constitute alternating doped functional regions on the back side, wherein the P-regions 210 are used to form acceptor-doped hole collection regions, and the N-regions 220 are used to form donor-doped electron collection regions.

[0070] In this embodiment, P region 210 is formed by boron doping and N region 220 is formed by phosphorus doping. In some embodiments, P region 210 can also be formed by acceptor element doping such as aluminum or gallium, and N region 220 can be formed by phosphorus doping or donor element doping such as arsenic or antimony. It can also be replaced by local selective emitter, local high and low doping region or heterojunction functional region according to the device design.

[0071] In this embodiment, multiple P-regions 210 and multiple N-regions 220 are arranged in an alternating finger-like pattern. The width of each P-region 210 and N-region 220 is greater than or equal to 80 μm and less than or equal to 120 μm, and the spacing between them is greater than or equal to 150 μm and less than or equal to 250 μm. The edges of the P-regions 210 and N-regions 220 adopt a rounded transition structure with a radius of 20 μm or greater and less than or equal to 30 μm, which can effectively alleviate the phenomenon of edge electric field concentration and reduce carrier recombination loss. In some embodiments, the multiple P-regions 210 and multiple N-regions 220 can be arranged in a strip, grid, or array pattern. The fabric is arranged along the back of the base layer 100 at a predetermined cycle to adapt to the wiring pattern of the main gate 310 and the fine gate 320; the spacing between adjacent P regions 210 and N regions 220 can be set according to the minority carrier diffusion length, contact opening size and passivation layer coverage. Typically, the width of a single region, the spacing width and the repetition cycle can be in the range of micrometers to hundreds of micrometers, so as to suppress series resistance and parasitic recombination while ensuring current collection efficiency. The thickness of P regions 210 and N regions 220 can also be controlled in combination with diffusion depth, laser doping depth or ion implantation depth to obtain sufficient junction depth and stable contact window.

[0072] Because the P-region 210 and N-region 220 are arranged alternately, charge carriers at different locations on the back of the battery can enter the corresponding selective collection region nearby, and then be transported to the main grid 310 and external circuits via the corresponding electrode layer 300, thereby reducing the lateral migration distance and lowering the recombination probability. At the same time, this alternating arrangement can make the potential distribution on the back more uniform. In conjunction with the aforementioned main grid 310, fine grid 320 and their cross-sectional area structure, it can further alleviate local current congestion, reduce contact resistance and series resistance, and improve the current collection uniformity and output stability of the entire battery.

[0073] Along the direction close to the base layer 100, the doping concentration of P region 210 and N region 220 gradually decreases.

[0074] In this application, the gradual decrease in doping concentration of P-region 210 and N-region 220 along the direction close to the substrate 100 refers to the gradient doping structure formed inside the PN junction layer 200 along the thickness direction of the battery. The P-region 210 and N-region 220 on the side away from the substrate 100 have relatively high doping concentrations, while the doping concentrations of P-region 210 and N-region 220 on the side close to the substrate 100 decrease sequentially. This results in a continuous transition in electrical distribution in the depth direction of the corresponding regions. The function of this structure is to reduce the recombination probability of photogenerated carriers during migration by adjusting the electric field distribution and carrier diffusion conditions, and to reduce the local junction resistance and interface loss, so that holes and electrons can be collected and output more effectively to the back electrode side.

[0075] In this application, the structure with gradually decreasing concentration results in a lower doping level on the side near the base layer 100, thereby preventing lattice damage, increased impurity recombination centers, and tunnel recombination enhancement caused by excessive doping. It also helps to form a more suitable built-in electric field distribution when the battery is working, so that photogenerated carriers can obtain a smoother migration path before diffusing to the back electrode.

[0076] In some embodiments, the gradual reduction can be achieved through linear, exponential, or piecewise reduction. The P-region 210 and N-region 220 can also employ different reduction rates to match the differences in mobility, diffusion length, and recombination sensitivity between holes and electrons. Morphologically, the doped region can exhibit a continuous concentration gradient layer, a multi-level diffusion layer formed by multiple transition layers, or an approximate gradient structure formed by stepwise concentration changes. The gradient transition thickness is typically on the micrometer scale, enabling continuous electrical connection with the upper electrode contact area and the lower substrate 100. The aforementioned gradient doping can also be achieved through processes such as bimodal doping, pulsed diffusion doping, or ion implantation followed by annealing diffusion. Process parameters are used to control the distribution of doped atoms at different depths to obtain a stable and repeatable concentration decay curve. It should be understood that the above examples are merely illustrative and not limiting.

[0077] In some embodiments, the specific material systems of P-region 210 and N-region 220 can be selected according to the type of substrate silicon wafer and process conditions. The doping source may include one or more of boron, phosphorus, arsenic, or antimony. The formation of the concentration gradient can be controlled by diffusion time, temperature profile, implantation dose, and annealing conditions to achieve the desired concentration distribution while maintaining junction depth consistency. In terms of size, the effective depth of a single gradient region can be from several micrometers to tens of micrometers. The gradient change can occur continuously throughout the entire thickness of the doped layer, or a gradually changing tail can be formed near the end of the substrate 100 to reduce electrical abrupt changes with the substrate 100 material.

[0078] The concentration of P zone 210 on the side 100 units away from the base layer is 1×10⁻⁶. 20 cm -3 The concentration of P210 on the side closest to the base layer 100 is 5×10⁻⁶. 18 cm -3 And / or, the concentration on the side of N zone 220 away from the base layer by 100 is 8 × 10⁻⁶. 19 cm -3 The concentration of N zone 220 on the side closest to the base layer 100 is 3×10⁻⁶. 18 cm -3 .

[0079] In this embodiment, the concentration of P region 210 on the side furthest from the base layer 100 is 1×10⁻⁶. 20 cm -3The concentration of P210 on the side closest to the base layer 100 is 5×10⁻⁶. 18 cm -3 The concentration of N region 220 on the side 100 away from the base layer is 8 × 10⁻⁶. 19 cm -3 The concentration of N zone 220 on the side closest to the base layer 100 is 3×10⁻⁶. 18 cm -3 This is to create a linear gradient doping in the P region 210 along the direction close to the substrate 100, and an exponential gradient doping in the N region 220 along the direction close to the substrate 100.

[0080] By adopting the above technical solutions, the P-region 210 uses linear gradient doping, which can make the impurity concentration decrease uniformly and gradually, effectively widening the drift range of photogenerated minority carriers, optimizing the interface electric field distribution, and taking into account the good junction characteristics brought by high surface doping and the improved minority carrier lifetime brought by low bulk doping. The N-region 220 uses exponential gradient doping, and the doping concentration decreases rapidly with increasing depth, which can reduce the bulk resistance of the base region and weaken the minority carrier recombination effect. The differentiated gradient doping of the P-region 210 and the N-region 220 work together to smooth the overall band bending degree, reduce the photogenerated carrier recombination loss, and improve the open-circuit voltage and photoelectric conversion efficiency of the battery.

[0081] In this embodiment, P-region 210 employs a low-temperature boron diffusion process with a diffusion temperature greater than or equal to 920°C and less than or equal to 950°C. Combined with an in-situ BSG mask, linear gradient doping is achieved through stepwise heating and atmosphere control. N-region 220 employs a phosphorus diffusion process with a diffusion temperature greater than or equal to 880°C and less than or equal to 910°C. Combined with plasma-enhanced doping, exponential gradient doping is achieved through power gradient adjustment. After doping, rapid thermal annealing is performed at a temperature of 750°C for 30 seconds to repair lattice defects generated during the diffusion process.

[0082] The battery structure also includes a silicon dioxide layer 400 and a hydrogenated amorphous silicon layer 500. The silicon dioxide layer 400 is connected to the side of the PN junction layer 200 away from the base layer 100, the hydrogenated amorphous silicon layer 500 is connected to the side of the silicon dioxide layer 400 away from the base layer 100, and the electrode layer 300 is connected to the side of the hydrogenated amorphous silicon layer 500 away from the base layer 100.

[0083] In this application, the silicon dioxide layer 400 and the hydrogenated amorphous silicon layer 500 together constitute a double-layer interface structure disposed between the PN junction layer 200 and the electrode layer 300. The silicon dioxide layer 400 can be understood as an insulating or semi-insulating passivation film formed on the silicon substrate surface, used to saturate the surface dangling bonds on the side of the PN junction layer 200 away from the base layer 100, thereby reducing the surface recombination rate and suppressing carrier loss at the interface. The hydrogenated amorphous silicon layer 500 is a hydrogen-containing amorphous silicon thin film covering the outside of the silicon dioxide layer 400, which can further passivate interface defects and provide a buffer transition for the subsequent contact of the electrode layer 300.

[0084] In this embodiment, the silicon dioxide layer 400 has a thickness of ≥10nm and ≤15nm, the hydrogenated amorphous silicon layer 500 has a thickness of ≥5nm and ≤8nm, and the overall surface recombination rate is less than 5cm / s, exhibiting excellent interface passivation effect. In some embodiments, the silicon dioxide layer 400 can also be achieved by thermal oxidation of silicon dioxide, chemical oxidation of silicon dioxide, or deposition of silicon dioxide layer 400, with its thickness preferably ranging from nanometers to several nanometers, to balance passivation effect and carrier tunneling transport capability. In this embodiment, the hydrogenated amorphous silicon layer 500 is preferably an intrinsic a-Si:H layer, a doped a-Si:H layer, or an interface layer formed by multiple a-Si:H composites, with its thickness ranging from several nanometers to tens of nanometers, and can be locally covered or patterned according to the electrode contact area, so as to form the required contact window for the electrode layer 300 while ensuring passivation effect.

[0085] The electrode layer 300 is connected to the side of the hydrogenated amorphous silicon layer 500 away from the base layer 100, so that the electrode layer 300 can achieve electrical connection and interface coupling with the PN junction layer 200 through this double-layer structure. The main gate 310 and the fine gate 320 in the electrode layer 300 can make local contact with the corresponding position of the hydrogenated amorphous silicon layer 500 or make contact through the reserved window, thereby completing the current extraction without increasing the interface recombination.

[0086] The silicon dioxide layer 400 mainly serves as the first layer for interface passivation and charge selectivity regulation. After it comes into direct contact with the PN junction layer 200, it can reduce the surface state density through chemical bonding and fill the micro-rough areas that may exist on the back of the battery, thereby improving the deposition uniformity of the subsequent hydrogenated amorphous silicon layer 500. The hydrogenated amorphous silicon layer 500 is located outside the silicon dioxide layer 400 and serves as the second layer for interface regulation. It can reduce recombination losses caused by direct metal contact when the electrode layer 300 is connected, and further passivate local defects through its hydrogen-containing structure.

[0087] In some embodiments, the silicon dioxide layer 400 can be configured to continuously cover the entire side of the PN junction layer 200 away from the base layer 100, or it can be formed only in the corresponding electrode contact area. It can also be in a patterned form with windows opened at the positions of the main gate 310 and the fine gate 320, so that the non-contact area maintains a strong passivation capability while the contact area maintains the necessary conduction conditions. In terms of material implementation, the silicon dioxide layer 400 can be dense silicon dioxide, loose silicon dioxide, or a silicon dioxide layer modified by post-treatment.

[0088] In some embodiments, the hydrogenated amorphous silicon layer 500 can be an intrinsic state, an n-type doped type, a p-type doped type, or a multilayer composite layer formed by stacking an intrinsic layer and a doped layer. In terms of thickness, the silicon dioxide layer 400 is typically controlled between about 0.5 nm and 10 nm to form a sufficient passivation barrier without excessively hindering carrier transport. The hydrogenated amorphous silicon layer 500 can be controlled between about 1 nm and 20 nm to achieve a balance between interface passivation, carrier selectivity, and subsequent electrode attachment.

[0089] In this embodiment, a PECVD deposition process is used to sequentially deposit a silicon dioxide layer 400 and a hydrogenated amorphous silicon layer 500. The deposition temperature is controlled to be greater than or equal to 200°C and less than or equal to 250°C, and the pressure is greater than or equal to 50Pa and less than or equal to 80Pa. In this embodiment, picosecond ultrafast laser etching is used to open electrode contact windows corresponding to P-region 210 and N-region 220. The laser process parameters are a power greater than or equal to 10W and less than or equal to 15W, a frequency greater than or equal to 50kHz and less than or equal to 80kHz, and an etching accuracy of ±2μm. This method is consumable-free, has high processing efficiency, and does not damage the substrate.

[0090] The battery structure also includes a silicon oxynitride layer 600, which is connected to the side of the plurality of main grids 310 and the plurality of fine grids 320 away from the base layer 100.

[0091] In this embodiment, the silicon oxynitride layer 600 is a dielectric protective layer disposed on the outside of the electrode layer 300. It is mainly composed of silicon, nitrogen, and oxygen, such as SiNxOy. The thickness of the silicon oxynitride layer 600 is greater than or equal to 2 μm and less than or equal to 3 μm, preferably 2.5 μm. The silicon oxynitride layer 600 is used to form a continuous or partial covering structure on the outer surface of the multiple main gates 310 and multiple fine gates 320. In terms of structural arrangement, the silicon oxynitride layer 600 is connected to the side of the multiple main gates 310 and multiple fine gates 320 away from the base layer 100. It is usually located on the outermost layer of the electrode layer 300, and is in direct contact with the main gates 310 and fine gates 320 or is stacked with them through an extremely thin transition interface layer, thereby protecting the entire electrode network.

[0092] The function of the silicon oxynitride layer 600 is to provide weather protection, chemical isolation and a certain degree of insulation buffer for the electrode layer 300, so as to reduce the corrosion of the metal electrode by the external humid and hot environment, ultraviolet radiation and corrosive media, while inhibiting the outward diffusion of metal elements or adverse reactions with the surrounding encapsulation materials, thereby improving the electrical stability and mechanical reliability of the battery structure during long-term service.

[0093] In some embodiments, the silicon oxynitride layer 600 can be fabricated as a dense SiN layer. x Oᵧ thin film, SiN with gradient refractive index x O3 thin film, or a protective film composed of multiple layers of oxide-nitrogen composite; in terms of morphology, it can be adopted as a continuous overall coverage, or it can be set as a partial coating layer or a patterned protective layer according to the spacing of the main grid 310, the distribution of the fine grid 320, and the local stress conditions, so as to balance the protective effect and the functional requirements of the battery surface. The material composition of this layer can be adjusted by adjusting the ratio of silicon source, nitrogen source, and oxygen source to form thin films with different densities and stress states, thereby adapting to different encapsulation systems.

[0094] In some embodiments, a silicon nitride layer, a silicon oxide layer, an aluminum oxide layer, or a multilayer composite passivation protective layer may be used instead to achieve a barrier and protective function similar to that of the silicon oxynitride layer 600. In terms of size, the thickness of the silicon oxynitride layer 600 can be adjusted to the submicron to micron range, for example, from tens of nanometers to hundreds of nanometers, or further thickened to approximately 1 μm under specific packaging conditions, to ensure that it covers the electrode surface without significantly affecting subsequent packaging. It should be understood that the above examples are merely illustrative and not limiting.

[0095] In this embodiment, a silicon oxynitride layer 600 is prepared by PECVD deposition process at a deposition temperature greater than or equal to 180°C and less than or equal to 220°C. After all electrodes are formed, the whole structure is sintered at high temperature at a temperature greater than or equal to 550°C and less than or equal to 600°C for 10 minutes to complete the preparation of the silicon oxynitride layer 600. Subsequent electrical performance testing and product sorting are carried out.

[0096] In the battery structure provided in this application, sunlight enters from the front of the substrate 100. After the anti-reflection layer 700 reduces light reflection loss, the light enters the interior of the substrate 100 and excites photogenerated electron-hole pairs. P-regions 210 and N-regions 220 arranged alternately on the back of the substrate 100 form differentiated built-in electric fields. The separated photogenerated holes and electrons converge towards the corresponding P-regions 210 and N-regions 220 on the back, respectively. The silicon dioxide layer 400 and the hydrogenated amorphous silicon layer 500 on the outer sides of the P-regions 210 and N-regions 220 reduce dangling bond defects on the silicon surface. Subsequently, the charge carriers are conducted to the electrode layer 300, the first conductive part 321, and the first conductive part 32... The second conductive parts 322 at both ends are connected between adjacent main gates 310. The cross-sectional area of ​​the first conductive part 321 is smaller than that of the second conductive part 322. The cross-sectional distribution and the current density distribution are precisely matched, which not only meets the high current conduction requirements at the connection and reduces the transmission Joule heat loss, but also reduces redundant metal materials and light-shielding losses. The current bridging and converging is transmitted to multiple conductive segments 311 of the main gate 310. The outermost silicon oxynitride layer 600 isolates the external environment from corrosion and blocks the diffusion of aluminum atoms, ensuring the long-term stable operation of the electrodes. Finally, the current after multi-stage convergence is led out through the external interconnection structure to form a complete circuit, realizing stable and efficient photoelectric energy conversion.

[0097] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A battery structure, characterized in that, include: Grassroots level (100); A PN junction layer (200) is connected to the back side of the base layer (100); An electrode layer (300) includes a plurality of main gates (310) and a plurality of fine gates (320), each of the fine gates (320) including a first conductive portion (321) and a second conductive portion (322) connected to both ends of the first conductive portion (321); The multiple main gates (310) and the multiple fine gates (320) are all connected to the side of the PN junction layer (200) away from the base layer (100). The multiple main gates (310) are spaced apart, and multiple fine gates (320) are spaced apart between adjacent main gates (310). The second conductive portions (322) at both ends of the first conductive portion (321) are respectively connected to the adjacent main gate (310), and the cross-sectional area of ​​the first conductive portion (321) is smaller than the cross-sectional area of ​​the second conductive portion (322).

2. The battery structure according to claim 1, characterized in that, The cross-sectional area of ​​the second conductive part (322) is a, 150μm²≥a≥120μm², and / or the cross-sectional area of ​​the first conductive part (321) is b, 100μm²≥b≥80μm².

3. The battery structure according to claim 1, characterized in that, The main gate (310) includes multiple conductive segments (311), all of which are located on the same straight line and are spaced apart from each other.

4. The battery structure according to claim 3, characterized in that, Each of the conductive segments (311) includes an aluminum-based conductive layer (312) and a nano-silver coating layer (313), wherein the nano-silver coating layer (313) covers the outside of the aluminum-based conductive layer (312); The second conductive part (322) is connected to the nano-silver coating layer (313) of the corresponding main gate (310).

5. The battery structure according to claim 4, characterized in that, The aluminum-based conductive layer (312) is doped with carbon nanotubes.

6. The battery structure according to any one of claims 1-5, characterized in that, The PN junction layer (200) includes a plurality of P regions (210) and a plurality of N regions (220), which are arranged sequentially at intervals.

7. The battery structure according to claim 6, characterized in that, Along the direction close to the base layer (100), the doping concentration of the P region (210) and the N region (220) gradually decreases.

8. The battery structure according to claim 7, characterized in that, The concentration on the side of the P zone (210) away from the base layer (100) is 1×10⁻⁶. 20 cm -3 The concentration of the P region (210) on the side closest to the base layer (100) is 5 × 10⁻⁶. 18 cm -3 And / or, the concentration on the side of the N region (220) away from the base layer (100) is 8 × 10⁻⁶. 19 cm -3 The concentration in the N region (220) near the base layer (100) is 3 × 10⁻⁶. 18 cm -3 .

9. The battery structure according to any one of claims 1-5, characterized in that, It also includes a silicon dioxide layer (400) and a hydrogenated amorphous silicon layer (500), wherein the silicon dioxide layer (400) is connected to the side of the PN junction layer (200) away from the base layer (100), the hydrogenated amorphous silicon layer (500) is connected to the side of the silicon dioxide layer (400) away from the base layer (100), and the electrode layer (300) is connected to the side of the hydrogenated amorphous silicon layer (500) away from the base layer (100).

10. The battery structure according to any one of claims 1-5, characterized in that, It also includes a silicon oxynitride layer (600) connected to the side of the plurality of main gates (310) and the plurality of fine gates (320) away from the base layer (100).

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