Back contact cells, methods of making and using the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-11
- Publication Date
- 2026-08-11
Smart Images
Figure CN122555286A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and in particular to a back-contact cell, its preparation method, and its application. Background Technology
[0002] Traditional contact passivation type back contact solar cells (BC cells) mainly include TBC cells, which are primarily passivated by tunneling layers and polycrystalline silicon layers, and HBC cells, which are primarily passivated by heterojunctions. Among them, TBC cells are mainly limited by their phosphorus-doped polycrystalline silicon (p-poly) structure. Due to the need to fabricate at temperatures above 940℃ and the characteristics of the doped silicon making the etching process difficult, the cell yield is low and efficiency improvement is limited. HBC cells are mainly limited by the low tolerance of the thin amorphous silicon layer to lasers. They can only be fabricated by repeatedly using expensive equipment such as masks and photolithography, and cannot be effectively mass-produced using the laser equipment currently used in large-scale photovoltaics. This results in high cell manufacturing costs. Moreover, when multiple layers of amorphous silicon are arranged in an interlaced manner, the inability to achieve effective lateral and vertical isolation leads to a large leakage current.
[0003] In summary, the passivation performance of the P-region in TBC cells requires a novel passivation structure to further improve. Meanwhile, while HTBC and HBC cells have high efficiency potential, they are not resistant to high temperatures. If their N-region and P-region are isolated, subsequent passivation of the isolation region cannot be performed using high-temperature deposition of passivation materials, but without isolation, leakage current is high. Therefore, it is necessary to develop a solar cell that can simultaneously improve both P-region passivation performance and high-temperature resistance. Summary of the Invention
[0004] Based on this, it is necessary to provide a back contact battery, its preparation method, and its application to address the above problems; the back contact battery has high passivation efficiency and good heat resistance in the P region, giving the battery advantages such as high yield, high conversion efficiency, and low cost.
[0005] A back contact battery includes a silicon substrate, the back side of which includes a P region, an N region, and an isolation region disposed between the P region and the N region;
[0006] The P region includes a first tunneling oxide layer, an intrinsic hydrogenation layer, at least one doped hydrogenation layer, a first passivation layer, and a first electrode stacked on the surface of the silicon substrate. The intrinsic hydrogenation layer includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenation layer includes at least microcrystalline silicon and polycrystalline silicon.
[0007] The N region includes a second tunneling oxide layer, a doped polysilicon layer, a second passivation layer, and a second electrode stacked on the surface of the silicon substrate.
[0008] In one embodiment, the intrinsic hydrogenation layer and the doped hydrogenation layer each independently satisfy at least one of the following conditions:
[0009] (1) Hydrogen content greater than or equal to 10^17 cm -3 ;
[0010] (2) The crystallization rate of the intrinsic hydrogenation layer is greater than or equal to 10%;
[0011] (3) The crystallinity of the doped hydrogenated layer is greater than or equal to 15%;
[0012] (4) The grain size of the microcrystals on the side near the silicon substrate is less than or equal to the grain size of the polycrystals on the side near the first passivation layer.
[0013] In one embodiment, the doped hydrogenated layer further satisfies at least one of the following conditions:
[0014] (1) When at least two doped hydrogenation layers are provided, the doping concentration of two adjacent doped hydrogenation layers decreases along the direction from the first passivation layer to the silicon substrate.
[0015] (2) The doping concentration of the hydrogenated layer near the silicon substrate is greater than 10^17 cm. -3 ;
[0016] (3) The doping concentration of the doped hydrogen layer near the first passivation layer is greater than 10^20 cm⁻¹ -3 ;
[0017] (4) The thickness of each doped hydrogenated layer is independently selected from 3 nm or more;
[0018] (5) When at least two doped hydrogenated layers are provided, the thickness of two adjacent doped hydrogenated layers decreases along the direction from the first passivation layer to the silicon substrate.
[0019] (6) The total doping concentration of all doped hydrogenated layers is greater than 10^19 cm. -3 .
[0020] In one embodiment, at least one third tunneling oxide layer is further included between the intrinsic hydrogenation layer and the first passivation layer, the third tunneling oxide layer being spaced apart from the doped hydrogenation layer, and the third tunneling oxide layer being disposed on the surface of the intrinsic hydrogenation layer.
[0021] In one embodiment, both the third tunneling oxide layer and the doped hydrogenation layer are three layers.
[0022] In one embodiment, the thickness of the third tunneling oxide layer is 0.5 nm to 2 nm.
[0023] In one embodiment, the silicon substrate thickness projected under the P-region is less than or equal to the silicon substrate thickness projected under the N-region.
[0024] In one embodiment, the thickness difference between the silicon substrate projected in the P region and the silicon substrate projected in the N region is 2 μm-10 μm.
[0025] A method for preparing a back contact battery as described above includes the following steps:
[0026] A second tunneling oxide layer and a polycrystalline silicon layer are sequentially deposited on one surface of a silicon substrate, and a doped polycrystalline silicon layer is formed by diffusion of doping elements.
[0027] A first patterning process is performed on the surface of the doped polysilicon layer to remove the second tunneling oxide layer and the doped polysilicon layer in the P-region and the isolation region.
[0028] After the first patterning process, a first tunneling oxide layer, an intrinsic hydrogenated amorphous silicon layer, at least one doped hydrogenated amorphous silicon layer, and a fourth tunneling oxide layer are sequentially deposited on the surface.
[0029] A second patterning process is performed on the surface of the fourth tunneling oxide layer to remove the fourth tunneling oxide layer in the N region and the isolation region.
[0030] The isolation region and the other surface of the silicon substrate are texturized to expose the silicon substrate on the surface of the isolation region. The fourth tunneling oxide layer on the surface of the P region and the first tunneling oxide layer, the intrinsic hydrogenated amorphous silicon layer, and the doped hydrogenated amorphous silicon layer on the surface of the N region are removed by wet etching.
[0031] Passivation layers are deposited on two surfaces of a silicon substrate, while an intrinsic hydrogenated amorphous silicon layer and a doped hydrogenated amorphous silicon layer are formed to form an intrinsic hydrogenated layer and a doped hydrogenated layer, respectively. The intrinsic hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon.
[0032] The first electrode and the second electrode are fabricated in the P region and the N region, respectively, to obtain the back contact battery.
[0033] In one embodiment, at least one third tunneling oxide layer is deposited between the deposition of the intrinsic hydrogenated amorphous silicon layer and the deposition of the fourth tunneling oxide layer.
[0034] In one embodiment, after depositing an intrinsic hydrogenated amorphous silicon layer, a third tunneling oxide layer and a doped hydrogenated amorphous silicon layer are deposited alternately in sequence.
[0035] A photovoltaic module, comprising a back-contact cell as described above.
[0036] The back contact battery described in this invention, through the synergistic effect of the first tunneling oxide layer, the intrinsic hydrogenation layer, and the doped hydrogenation layer in the P-region, improves the heat resistance of the P-region, preventing degradation issues caused by hydrogen overflow during passivation layer fabrication, thereby increasing the yield of the back contact battery. Furthermore, it not only effectively improves contact but also prevents doped atoms from diffusing into the undoped layer at high temperatures, ensuring passivation and thus improving the conversion efficiency of the back contact battery. In addition, this invention provides a method for fabricating a back contact battery that is simple, easy to operate, and highly efficient, offering advantages such as low cost compared to traditional technologies. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a cross-sectional structural diagram of a back-contact battery according to one embodiment of the present invention.
[0039] Wherein, 10 is a silicon substrate; 11 is a P-region; 111 is a first tunneling oxide layer; 112 is an intrinsic hydrogenation layer; 113 is a third tunneling oxide layer; 114 is a doped hydrogenation layer; 115 is a first passivation layer; 116 is a first electrode; 12 is an N-region; 121 is a second tunneling oxide layer; 122 is a doped polysilicon layer; 123 is a second passivation layer; 124 is a second electrode; 13 is a third passivation layer; and 14 is a fourth passivation layer. Detailed Implementation
[0040] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. In this invention, when referring to numerical ranges, unless otherwise specified, such ranges are considered continuous and include the minimum and maximum values of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, it includes every integer between the minimum and maximum values of the range. Furthermore, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included.
[0042] Combination Figure 1 As shown, a back contact battery provided by the present invention includes a silicon substrate 10. The back side of the silicon substrate 10 includes a P-region 11, an N-region 12, and an isolation region disposed between the P-region 11 and the N-region 12. The P-region 11 includes a first tunneling oxide layer 111, an intrinsic hydrogenation layer 112, at least one doped hydrogenation layer 114, a first passivation layer 115, and a first electrode 116 stacked on the surface of the silicon substrate 10. The intrinsic hydrogenation layer 112 includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenation layer 114 includes at least microcrystalline silicon and polycrystalline silicon. The N-region 12 includes a second tunneling oxide layer 121, a doped polycrystalline silicon layer 122, a second passivation layer 123, and a second electrode 124 stacked on the surface of the silicon substrate 10.
[0043] The back contact battery of the present invention, through the synergistic effect of the first tunneling oxide layer 111, the intrinsic hydrogenation layer 112, and the doped hydrogenation layer 114 in the P region 11, on the one hand, helps to improve the heat resistance of the P region 11 and avoids the degradation problem caused by hydrogen overflow during the preparation of the passivation layer, thereby improving the yield of the back contact battery; on the other hand, it can not only effectively improve the contact, but also prevent the doped atoms from diffusing into the undoped layer during the high temperature process, thereby ensuring the passivation effect and improving the conversion efficiency of the back contact battery.
[0044] In one embodiment, the intrinsic hydrogenation layer 112 has a hydrogen content greater than or equal to 10^17 cm³. -3 including but not limited to 10^17 cm -3 10^18cm -3 10^19cm -3 Any point value in the range or any range between two values.
[0045] In one embodiment, the intrinsic hydrogenation layer 112 has a crystallinity greater than or equal to 10%, including but not limited to any one of 10%, 15%, 16%, 20%, 25%, 30%, or any range between two of these values.
[0046] It should be noted that crystallization rate refers to the proportion of crystalline portion in the total material. In this invention, the crystalline portion includes microcrystals and polycrystals.
[0047] In one embodiment, the grain size of the microcrystals in the intrinsic hydrogenation layer 112 near the silicon substrate 10 is less than or equal to the grain size of the polycrystals near the first passivation layer 115.
[0048] In one embodiment, the hydrogen content of the doped hydrogenated layer 114 is greater than or equal to 10^17 cm^2. -3 including but not limited to 10^17 cm -3 10^18cm -3 10^19cm -3 Any point value in the range or any range between two values.
[0049] In one embodiment, the hydrogen content of the intrinsic hydrogenation layer 112 is greater than or equal to the hydrogen content of the doped hydrogenation layer 114.
[0050] In one embodiment, the crystallinity of the doped hydrogenated layer 114 is greater than or equal to 15%, including but not limited to any one of 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, or any range between two of them.
[0051] In one embodiment, the crystallinity of the intrinsic hydrogenation layer 112 is less than or equal to the crystallinity of the doped hydrogenation layer 114. More preferably, the crystallinity of the intrinsic hydrogenation layer 112 is less than the crystallinity of the doped hydrogenation layer 114.
[0052] In one embodiment, the sum of the crystallinity of the intrinsic hydrogenation layer 112 and the crystallinity of the doped hydrogenation layer 114 is less than or equal to 80%.
[0053] In one embodiment, the grain size of the microcrystals in the side of the doped hydrogenated layer 114 near the silicon substrate 10 is less than or equal to the grain size of the polycrystals in the side near the first passivation layer 115.
[0054] In one embodiment, when at least two doped hydrogenation layers 114 are provided, the doping concentration of adjacent doped hydrogenation layers 114 decreases along the direction from the first passivation layer 115 to the silicon substrate 10. For example, when there are two doped hydrogenation layers 114, and along the direction from the first passivation layer 115 to the silicon substrate 10, they are sequentially a first doped hydrogenation layer 114 and a second doped hydrogenation layer 114, then the doping concentration of the first doped hydrogenation layer 114 is greater than the doping concentration of the second doped hydrogenation layer 114.
[0055] By designing the doping concentration of the hydrogenated layer 114 to have a gradient, the doping concentration on the side in contact with the first passivation layer 115 is higher, which can make the contact effect between the doped hydrogenated layer 114 and the first passivation layer 115 better; the doping concentration on the side in contact with the intrinsic hydrogenated layer 112 is higher, which can avoid doping diffusion and help protect the intrinsic passivation effect.
[0056] It is understood that "adjacent" refers to two layers that are adjacent to another layer. Adjacent layers can be in direct contact with each other, or there can be an intervening layer. There is no blank space between adjacent layers. Doping concentration refers to the number of doped atoms in a unit area of matrix. This invention does not limit the doped atoms, including but not limited to phosphorus atoms.
[0057] In one embodiment, the doping concentration of the hydrogenated layer 114 near the silicon substrate 10 is greater than 10^17 cm^-3. -3 Including but not limited to 10^18 cm -3 10^19cm -3 10^20cm -3 Any point value in the range or any range between two values.
[0058] In one embodiment, the doping concentration of the doped hydrogenation layer 114 near the first passivation layer 115 is greater than 10^20 cm⁻¹. -3 , including but not limited to 10^21 cm -3 10^22cm -3 10^23cm -3 Any point value in the range or any range between two values.
[0059] In one embodiment, the thickness of each doped hydrogenation layer 114 is independently selected from 3 nm or more. It is understood that the thickness of each doped hydrogenation layer 114 can be the same or different, and the present invention does not limit this.
[0060] In one embodiment, when at least two doped hydrogenation layers 114 are provided, the thickness of adjacent doped hydrogenation layers 114 decreases along the direction from the first passivation layer 115 to the silicon substrate 10. For example, when there are two doped hydrogenation layers 114, and along the direction from the first passivation layer 115 to the silicon substrate 10, they are sequentially a first doped hydrogenation layer 114 and a second doped hydrogenation layer 114, then the thickness of the first doped hydrogenation layer 114 is greater than the thickness of the second doped hydrogenation layer 114.
[0061] In one embodiment, the total doping concentration of all the doped hydrogenated layers 114 is greater than 10^19 cm^-1. -3 .
[0062] By designing the doping concentration in the hydrogenated layer 114 to have a gradient distribution and satisfying a certain relationship between doping concentration and thickness, it is beneficial to control the diffusion rate and further prevent doped atoms from diffusing into the undoped layer during high-temperature processes, thereby ensuring the passivation effect.
[0063] Considering that although hydrogenated intrinsic amorphous silicon has excellent passivation performance, hydrogen will diffuse into the material it contacts at high temperatures, and hydrogenated amorphous silicon will form epitaxial growth at the silicon interface at high temperatures, resulting in a poor passivation effect, as a preferred option, a third tunneling oxide layer 113 is provided between the intrinsic hydrogenated layer 112 and the doped hydrogenated layer 114. In other words, the third tunneling oxide layer 113 is provided on the surface of the intrinsic hydrogenated layer 112.
[0064] In one embodiment, at least one third tunneling oxide layer 113 is further included between the intrinsic hydrogenation layer 112 and the first passivation layer 115. The third tunneling oxide layer 113 is disposed at a distance from the doped hydrogenation layer 114, and the third tunneling oxide layer 113 is disposed on the surface of the intrinsic hydrogenation layer 112.
[0065] By setting a third tunneling oxide layer 113 between adjacent doped hydrogenated layers 114, it is not only beneficial to further adjust the doping concentration distribution in each layer, ensure a step-like distribution of doping concentration, block effective diffusion paths, and reduce the influence of temperature on diffusion, thereby further improving heat resistance, but also, considering the different migration rates of hydrogen in the tunneling layer and microcrystals or polycrystals, the presence of the third tunneling oxide layer 113 can further effectively slow down the hydrogen escape rate and improve the battery yield.
[0066] More preferably, both the third tunneling oxide layer 113 and the doped hydrogenation layer 114 are three layers, that is, from the intrinsic hydrogenation layer 112 to the first passivation layer 115, they sequentially include a first third tunneling oxide layer 113, a first doped hydrogenation layer 114, a second third tunneling oxide layer 113, a second doped hydrogenation layer 114, a third third tunneling oxide layer 113, and a third doped hydrogenation layer 114.
[0067] In one embodiment, the thickness of the third tunneling oxide layer 113 is 0.5nm-2nm, including but not limited to any one of 0.5nm, 1nm, 1.5nm, 2nm or any range between two of them.
[0068] In one embodiment, the thickness of the silicon substrate 10 projected under the P region 11 is less than or equal to the thickness of the silicon substrate 10 projected under the N region 12.
[0069] In one embodiment, the thickness difference between the silicon substrate 10 projected under the P region 11 and the silicon substrate 10 projected under the N region 12 is 2μm-10μm, including but not limited to any one of 2μm, 4μm, 6μm, 8μm, 10μm or any range between the two.
[0070] In one embodiment, the first passivation layer 115 and the second passivation layer 123 each independently comprise AlO. x Layer, SiO x Layer, SiN x Layer, SiON x At least one of the layers, preferably, the first passivation layer 115 and the second passivation layer 123 are both selected from AlO. x Layer, SiO x Layer, SiN x Layers and SiON x The layers are stacked, that is, AlO is sequentially stacked on the surface of the hydrogenated layer 114. x Layer, SiO x Layer, SiN x Layers and SiON x Layer; AlO is sequentially stacked on the surface of the doped polycrystalline silicon layer 122. x Layer, SiO x Layer, SiN x Layers and SiON x layer.
[0071] It should be noted that the present invention does not limit the specific materials of the first tunneling oxide layer 111, the second tunneling oxide layer 121, the doped polysilicon layer 122, and the first electrode 116 and the second electrode 124. Selection can be made according to conventional techniques. For example, the first tunneling oxide layer 111 and the second tunneling oxide layer 121 are independently selected from silicon oxide, silicon oxynitride, or aluminum oxide layers, respectively; the doped polysilicon layer 122 includes a phosphorus-doped polysilicon layer. The present invention does not limit the isolation region and the front structure of the silicon substrate 10. For example, as shown... Figure 1 As shown, the isolation region includes a third passivation layer 13 with a textured surface; the front side of the silicon substrate 10 includes a fourth passivation layer 14 with a textured surface.
[0072] This invention provides a method for preparing the back contact battery as described above, comprising the following steps:
[0073] S1, a second tunneling oxide layer and a polycrystalline silicon layer are sequentially deposited on one surface of a silicon substrate, and a doped polycrystalline silicon layer is formed by diffusion of doping elements;
[0074] S2, perform a first patterning process on the surface of the doped polysilicon layer to remove the second tunneling oxide layer and the doped polysilicon layer of the P region and the isolation region.
[0075] S3, a first tunneling oxide layer, an intrinsic hydrogenated amorphous silicon layer, at least one doped hydrogenated amorphous silicon layer and a fourth tunneling oxide layer are sequentially deposited on the surface after the first patterning process.
[0076] S4, perform a second patterning process on the surface of the fourth tunneling oxide layer to remove the fourth tunneling oxide layer in the N region and the isolation region;
[0077] S5, texturing is performed on the isolation region and the other surface of the silicon substrate to make the surface of the isolation region a bare silicon substrate. The fourth tunneling oxide layer on the surface of the P region and the first tunneling oxide layer, intrinsic hydrogenated amorphous silicon layer and doped hydrogenated amorphous silicon layer on the surface of the N region are removed by wet etching.
[0078] S6, passivation layers are deposited on two surfaces of a silicon substrate, while an intrinsic hydrogenated amorphous silicon layer and a doped hydrogenated amorphous silicon layer are formed to form an intrinsic hydrogenated layer and a doped hydrogenated layer, respectively. The intrinsic hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon.
[0079] S7, the first electrode and the second electrode are fabricated in the P region and the N region respectively to obtain the back contact battery.
[0080] In step S1, the present invention does not limit the deposition method of the second tunneling oxide layer and the polycrystalline silicon layer, nor the diffusion method of the dopant elements; existing deposition and diffusion processes can be used. It should be noted that, before deposition, it is preferable to use a wet tank equipment to pre-clean, double-sided polish, and post-clean the silicon substrate to remove surface impurities.
[0081] In step S2, the present invention does not limit the method of the first patterning process, and any existing process can be used, such as laser or wet etching.
[0082] In one embodiment, when removing the second tunneling oxide layer and the doped polysilicon layer of the P-region and the isolation region, the layers can be further extended into the silicon substrate, so that the thickness of the silicon substrate corresponding to the P-region and the isolation region is smaller than that of the silicon substrate corresponding to the N-region.
[0083] After the first patterning process, a patterned groove is formed on the surface of the silicon substrate. Preferably, the depth of the groove is 2μm-10μm, including but not limited to any point value of 2μm, 4μm, 6μm, 8μm, 10μm or any range between two.
[0084] It is understandable that during the diffusion process in step S1, a doped glass layer (such as a PSG layer) is also formed on the surface of the doped polysilicon layer. In the first patterning process in step S2, the doped glass layer of the P region and the isolation region is first patterned to remove the doped glass layer. Then, through further etching, the second tunneling oxide layer and the doped polysilicon layer of the P region and the isolation region are removed, and the doped glass layer on the surface of the doped polysilicon layer is also removed.
[0085] In step S3, the present invention does not limit the deposition method of the first tunneling oxide layer, the intrinsic hydrogenated amorphous silicon layer, the doped hydrogenated amorphous silicon layer and the fourth tunneling oxide layer, and any existing process can be used, such as plasma enhanced chemical vapor deposition (PECVD).
[0086] In one embodiment, between depositing the intrinsic hydrogenated amorphous silicon layer and depositing the fourth tunneling oxide layer, at least one third tunneling oxide layer is also deposited.
[0087] In one embodiment, after depositing an intrinsic hydrogenated amorphous silicon layer, a third tunneling oxide layer and a doped hydrogenated amorphous silicon layer are deposited alternately in sequence.
[0088] In steps S4 to S5, the fourth tunneling oxide layer of the N region and the isolation region is removed first, and the fourth tunneling oxide layer on the surface of the P region is used as a protective layer to ensure that the hydrogen-doped amorphous silicon layer is not removed or modified during the texturing process.
[0089] It should be noted that the present invention does not limit the method of the second patterning process, and any existing process can be used, such as laser or wet etching.
[0090] In one embodiment, a combination of chain acid etching and wet plating is preferably used, wherein acid etching removes the plating around the front surface on one side, and the wet plating process is used to texturize the other surface and remove the GAP area texturing, as well as remove the first tunneling oxide layer, the intrinsic hydrogenated amorphous silicon layer, and the doped hydrogenated amorphous silicon layer from the N-region surface.
[0091] In step S6, the thermal process generated by the deposition of the passivation layer causes the amorphous material to gradually crystallize after being heated, and the microcrystals to gradually grow after being heated. This results in the formation of an intrinsic hydrogenated amorphous silicon layer and a doped hydrogenated amorphous silicon layer, respectively, consisting of at least microcrystalline silicon and polycrystalline silicon. At the same time, based on the P-region structure designed in step S3, the heat resistance of the P-region is improved, effectively avoiding the degradation problem caused by hydrogen overflow during the preparation of the passivation layer, and preventing doped atoms from diffusing into the undoped layer at high temperatures, thereby improving the yield and conversion efficiency of the back contact cell.
[0092] It should be noted that the present invention does not limit the deposition method of the passivation layer, and any existing process can be used. It is preferred to use a deposition process with heating conditions, and the heating conditions are preferably 300℃-500℃.
[0093] In step S7, the present invention does not limit the preparation method of the first and second electrodes; any existing process can be used. It is understood that after electrode preparation, processes such as photoinjection or dark annealing may be included, which will not be elaborated upon in this invention.
[0094] Therefore, the preparation method provided by the present invention is not only simple and easy to operate with high production efficiency, but also has advantages such as low cost compared with traditional technology.
[0095] The present invention also provides a photovoltaic module, including the back contact battery as described above. The photovoltaic module can be widely used in various fields such as power generation, outdoor lighting, mobile power supplies, and aerospace, and the present invention does not limit its applications.
[0096] The following specific embodiments will further illustrate the back contact battery, its preparation method, and its application. However, those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified, specific conditions in the embodiments are performed under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.
[0097] Example 1
[0098] The N-type silicon wafers are pre-cleaned, double-sided polished, and post-cleaned using a wet tank process. A second tunneling oxide layer and a polycrystalline silicon layer are sequentially deposited on the back side of the N-type silicon wafer using an LP process, followed by phosphorus diffusion using a high-temperature tubular process to form a doped polycrystalline silicon layer.
[0099] The first patterning process is performed on the surface of the doped polysilicon layer using a laser device to remove the PSG layer on the surface of the P region and the isolation region. Then, a wet polishing process is used to remove the PSG layer on the surface of the N region, as well as the second tunneling oxide layer and the doped polysilicon layer in the P region and the isolation region, so that the depth of the patterned groove is about 2 μm.
[0100] A first tunneling oxide layer, an intrinsic hydrogenated amorphous silicon layer, a first third tunneling oxide layer, a first doped hydrogenated amorphous silicon layer, a second third tunneling oxide layer, a second doped hydrogenated amorphous silicon layer, a third third tunneling oxide layer, a third doped hydrogenated amorphous silicon layer, and a fourth tunneling oxide layer are sequentially deposited on the surface after the first patterning process using a plate-type PECVD equipment.
[0101] A second patterning process was performed on the surface of the fourth tunneling oxide layer using a laser device to remove the fourth tunneling oxide layer in the N region and the isolation region.
[0102] A combination of chain-type acid etching and wet etching equipment is used. Acid etching removes the front surface coating on one side, while wet etching equipment texturizes the front side and isolation area of the N-type silicon wafer, making the isolation area surface a bare silicon substrate. At the same time, the fourth tunneling oxide layer on the surface of the P-region and the first tunneling oxide layer, intrinsic hydrogenated amorphous silicon layer, three-layer doped hydrogenated amorphous silicon layer and three-layer third tunneling oxide layer on the surface of the N-region are removed.
[0103] Al2O3 layers and SiN layers were sequentially deposited on both the front and back sides using a PECVD apparatus. x Layer, SiON x Layers and SiO x The thermal process during deposition causes the intrinsic hydrogenated amorphous silicon layer and the three-layer doped hydrogenated amorphous silicon layer to crystallize, forming the intrinsic hydrogenated layer and the three-layer doped hydrogenated layer.
[0104] Metal grid lines are printed on the N and P regions using screen printing, and after sintering, they are subjected to light injection or dark annealing to obtain a back contact battery.
[0105] Examples 2-4
[0106] Different back-contact batteries were prepared using the same method as in Example 1, and the differences are shown in Table 1.
[0107] Table 1
[0108]
[0109]
[0110] Example 5
[0111] The difference between Example 5 and Example 1 is that the second third tunneling oxide layer, the second doped hydrogenated amorphous silicon layer, the third third tunneling oxide layer, and the third doped hydrogenated amorphous silicon layer were not prepared.
[0112] Example 6
[0113] The difference between Example 6 and Example 1 is that the depth of the patterned groove is approximately 0.2 μm.
[0114] The back-contact batteries prepared in Examples 1-6 were tested, and the results are shown in Table 2. Test methods: yield was tested using EL and PL, conversion efficiency was tested using IV, and heat resistance was verified using Suns-VOC to observe the IVOC performance of its symmetrical structure at different temperatures.
[0115] Table 2
[0116] Yield (%) Conversion efficiency (%) Heat resistance (°C) Example 1 95.1 26.55 290 Example 2 95.5 26.61 330 Example 3 96.1 26.73 360 Example 4 96.8 26.85 420 Example 5 90.0 25.50 200 Example 6 85.0 25.80 270
[0117] As can be seen from Tables 1 and 2, in the back contact battery provided by the present invention, the passivation of the P region is improved from the conventional 725mV to 735mV-750mV, resulting in high conversion efficiency. Furthermore, the back contact battery also has high yield and excellent heat resistance.
[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0119] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A back-contact battery, comprising a silicon substrate, wherein the back side of the silicon substrate includes a P-region, an N-region, and an isolation region disposed between the P-region and the N-region, characterized in that: The P region includes a first tunneling oxide layer, an intrinsic hydrogenation layer, at least one doped hydrogenation layer, a first passivation layer, and a first electrode stacked on the surface of the silicon substrate. The intrinsic hydrogenation layer includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenation layer includes at least microcrystalline silicon and polycrystalline silicon. The N region includes a second tunneling oxide layer, a doped polysilicon layer, a second passivation layer, and a second electrode stacked on the surface of the silicon substrate.
2. The back contact cell of claim 1, wherein, The intrinsic hydrogenation layer and the doped hydrogenation layer each independently satisfy at least one of the following conditions: (1) hydrogen content greater than or equal to 10^17 cm -3 ; (2) The crystallization rate of the intrinsic hydrogenation layer is greater than or equal to 10%; (3) The crystallinity of the doped hydrogenated layer is greater than or equal to 15%; (4) The grain size of the microcrystals on the side near the silicon substrate is less than or equal to the grain size of the polycrystals on the side near the first passivation layer.
3. The back contact cell according to claim 1 or 2, characterized in that The doped hydrogenated layer also satisfies at least one of the following conditions: (1) When at least two doped hydrogenation layers are provided, the doping concentration of two adjacent doped hydrogenation layers decreases along the direction from the first passivation layer to the silicon substrate. (2) the doped concentration of the doped hydrogenated layer near the silicon substrate is greater than 10^17 cm -3 ; (3) the doped concentration of the doped hydrogenated layer close to the first passivation layer is greater than 10^20 cm -3 ; (4) The thickness of each doped hydrogenated layer is independently selected from 3 nm or more; (5) When at least two doped hydrogenated layers are provided, the thickness of two adjacent doped hydrogenated layers decreases along the direction from the first passivation layer to the silicon substrate. (6) The total doping concentration of all doped hydrogenated layers is greater than 10^19 cm. -3 .
4. The back contact cell of claim 1, wherein, At least one third tunneling oxide layer is further included between the intrinsic hydrogenation layer and the first passivation layer. The third tunneling oxide layer is disposed at an interval from the doped hydrogenation layer and is disposed on the surface of the intrinsic hydrogenation layer.
5. The back contact cell of claim 4, wherein, Both the third tunneling oxide layer and the doped hydrogenated layer are three-layered.
6. The back contact cell of claim 4, wherein, The thickness of the third tunneling oxide layer is 0.5 nm to 2 nm.
7. The back contact battery according to claim 1, characterized in that, The thickness of the silicon substrate projected under the P region is less than or equal to the thickness of the silicon substrate projected under the N region.
8. The back contact battery according to claim 7, characterized in that, The thickness difference between the silicon substrate projected in the P region and the silicon substrate projected in the N region is 2μm-10μm.
9. A method for preparing a back contact battery as described in any one of claims 1-8, characterized in that, Includes the following steps: A second tunneling oxide layer and a polycrystalline silicon layer are sequentially deposited on one surface of a silicon substrate, and a doped polycrystalline silicon layer is formed by diffusion of doping elements. The surface of the doped polysilicon layer is first patterned to remove the second tunneling oxide layer and the doped polysilicon layer in the P-region and the isolation region. After the first patterning process, a first tunneling oxide layer, an intrinsic hydrogenated amorphous silicon layer, at least one doped hydrogenated amorphous silicon layer, and a fourth tunneling oxide layer are sequentially deposited on the surface. A second patterning process is performed on the surface of the fourth tunneling oxide layer to remove the fourth tunneling oxide layer in the N region and the isolation region. The isolation region and the other surface of the silicon substrate are texturized to expose the silicon substrate on the surface of the isolation region. The fourth tunneling oxide layer on the surface of the P region and the first tunneling oxide layer, the intrinsic hydrogenated amorphous silicon layer, and the doped hydrogenated amorphous silicon layer on the surface of the N region are removed by wet etching. Passivation layers are deposited on two surfaces of a silicon substrate, while an intrinsic hydrogenated amorphous silicon layer and a doped hydrogenated amorphous silicon layer are formed to form an intrinsic hydrogenated layer and a doped hydrogenated layer, respectively. The intrinsic hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon, and the doped hydrogenated layer includes at least microcrystalline silicon and polycrystalline silicon. The first electrode and the second electrode are fabricated in the P region and the N region, respectively, to obtain the back contact battery.
10. The method for preparing a back contact battery according to claim 9, characterized in that, Between the deposition of the intrinsic hydrogenated amorphous silicon layer and the deposition of the fourth tunneling oxide layer, at least one third tunneling oxide layer is also deposited.
11. The method for preparing a back contact battery according to claim 10, characterized in that, After depositing the intrinsic hydrogenated amorphous silicon layer, the third tunneling oxide layer and the doped hydrogenated amorphous silicon layer are deposited alternately in sequence.
12. A photovoltaic module, characterized in that, Includes the back contact battery as described in any one of claims 1-8.